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ath79: ag71xx: remove PHY reset
[openwrt/staging/wigyori.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
60 {
61 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
62 ag->dev->name, label, intr,
63 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
64 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
65 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
66 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
67 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
68 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
69 }
70
71 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
72 {
73 struct ag71xx_ring *ring = &ag->tx_ring;
74 struct net_device *dev = ag->dev;
75 int ring_mask = BIT(ring->order) - 1;
76 u32 bytes_compl = 0, pkts_compl = 0;
77
78 while (ring->curr != ring->dirty) {
79 struct ag71xx_desc *desc;
80 u32 i = ring->dirty & ring_mask;
81
82 desc = ag71xx_ring_desc(ring, i);
83 if (!ag71xx_desc_empty(desc)) {
84 desc->ctrl = 0;
85 dev->stats.tx_errors++;
86 }
87
88 if (ring->buf[i].skb) {
89 bytes_compl += ring->buf[i].len;
90 pkts_compl++;
91 dev_kfree_skb_any(ring->buf[i].skb);
92 }
93 ring->buf[i].skb = NULL;
94 ring->dirty++;
95 }
96
97 /* flush descriptors */
98 wmb();
99
100 netdev_completed_queue(dev, pkts_compl, bytes_compl);
101 }
102
103 static void ag71xx_ring_tx_init(struct ag71xx *ag)
104 {
105 struct ag71xx_ring *ring = &ag->tx_ring;
106 int ring_size = BIT(ring->order);
107 int ring_mask = ring_size - 1;
108 int i;
109
110 for (i = 0; i < ring_size; i++) {
111 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
112
113 desc->next = (u32) (ring->descs_dma +
114 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
115
116 desc->ctrl = DESC_EMPTY;
117 ring->buf[i].skb = NULL;
118 }
119
120 /* flush descriptors */
121 wmb();
122
123 ring->curr = 0;
124 ring->dirty = 0;
125 netdev_reset_queue(ag->dev);
126 }
127
128 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
129 {
130 struct ag71xx_ring *ring = &ag->rx_ring;
131 int ring_size = BIT(ring->order);
132 int i;
133
134 if (!ring->buf)
135 return;
136
137 for (i = 0; i < ring_size; i++)
138 if (ring->buf[i].rx_buf) {
139 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
140 ag->rx_buf_size, DMA_FROM_DEVICE);
141 skb_free_frag(ring->buf[i].rx_buf);
142 }
143 }
144
145 static int ag71xx_buffer_size(struct ag71xx *ag)
146 {
147 return ag->rx_buf_size +
148 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
149 }
150
151 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
152 int offset,
153 void *(*alloc)(unsigned int size))
154 {
155 struct ag71xx_ring *ring = &ag->rx_ring;
156 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
157 void *data;
158
159 data = alloc(ag71xx_buffer_size(ag));
160 if (!data)
161 return false;
162
163 buf->rx_buf = data;
164 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
165 DMA_FROM_DEVICE);
166 desc->data = (u32) buf->dma_addr + offset;
167 return true;
168 }
169
170 static int ag71xx_ring_rx_init(struct ag71xx *ag)
171 {
172 struct ag71xx_ring *ring = &ag->rx_ring;
173 int ring_size = BIT(ring->order);
174 int ring_mask = BIT(ring->order) - 1;
175 unsigned int i;
176 int ret;
177
178 ret = 0;
179 for (i = 0; i < ring_size; i++) {
180 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
181
182 desc->next = (u32) (ring->descs_dma +
183 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
184
185 DBG("ag71xx: RX desc at %p, next is %08x\n",
186 desc, desc->next);
187 }
188
189 for (i = 0; i < ring_size; i++) {
190 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
191
192 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
193 netdev_alloc_frag)) {
194 ret = -ENOMEM;
195 break;
196 }
197
198 desc->ctrl = DESC_EMPTY;
199 }
200
201 /* flush descriptors */
202 wmb();
203
204 ring->curr = 0;
205 ring->dirty = 0;
206
207 return ret;
208 }
209
210 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
211 {
212 struct ag71xx_ring *ring = &ag->rx_ring;
213 int ring_mask = BIT(ring->order) - 1;
214 unsigned int count;
215 int offset = ag->rx_buf_offset;
216
217 count = 0;
218 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
219 struct ag71xx_desc *desc;
220 unsigned int i;
221
222 i = ring->dirty & ring_mask;
223 desc = ag71xx_ring_desc(ring, i);
224
225 if (!ring->buf[i].rx_buf &&
226 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
227 napi_alloc_frag))
228 break;
229
230 desc->ctrl = DESC_EMPTY;
231 count++;
232 }
233
234 /* flush descriptors */
235 wmb();
236
237 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
238
239 return count;
240 }
241
242 static int ag71xx_rings_init(struct ag71xx *ag)
243 {
244 struct ag71xx_ring *tx = &ag->tx_ring;
245 struct ag71xx_ring *rx = &ag->rx_ring;
246 int ring_size = BIT(tx->order) + BIT(rx->order);
247 int tx_size = BIT(tx->order);
248
249 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
250 if (!tx->buf)
251 return -ENOMEM;
252
253 tx->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
254 &tx->descs_dma, GFP_ATOMIC);
255 if (!tx->descs_cpu) {
256 kfree(tx->buf);
257 tx->buf = NULL;
258 return -ENOMEM;
259 }
260
261 rx->buf = &tx->buf[BIT(tx->order)];
262 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
263 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
264
265 ag71xx_ring_tx_init(ag);
266 return ag71xx_ring_rx_init(ag);
267 }
268
269 static void ag71xx_rings_free(struct ag71xx *ag)
270 {
271 struct ag71xx_ring *tx = &ag->tx_ring;
272 struct ag71xx_ring *rx = &ag->rx_ring;
273 int ring_size = BIT(tx->order) + BIT(rx->order);
274
275 if (tx->descs_cpu)
276 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
277 tx->descs_cpu, tx->descs_dma);
278
279 kfree(tx->buf);
280
281 tx->descs_cpu = NULL;
282 rx->descs_cpu = NULL;
283 tx->buf = NULL;
284 rx->buf = NULL;
285 }
286
287 static void ag71xx_rings_cleanup(struct ag71xx *ag)
288 {
289 ag71xx_ring_rx_clean(ag);
290 ag71xx_ring_tx_clean(ag);
291 ag71xx_rings_free(ag);
292
293 netdev_reset_queue(ag->dev);
294 }
295
296 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
297 {
298 switch (ag->speed) {
299 case SPEED_1000:
300 return "1000";
301 case SPEED_100:
302 return "100";
303 case SPEED_10:
304 return "10";
305 }
306
307 return "?";
308 }
309
310 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
311 {
312 u32 t;
313
314 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
315 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
316
317 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
318
319 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
320 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
321 }
322
323 static void ag71xx_dma_reset(struct ag71xx *ag)
324 {
325 u32 val;
326 int i;
327
328 ag71xx_dump_dma_regs(ag);
329
330 /* stop RX and TX */
331 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
332 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
333
334 /*
335 * give the hardware some time to really stop all rx/tx activity
336 * clearing the descriptors too early causes random memory corruption
337 */
338 mdelay(1);
339
340 /* clear descriptor addresses */
341 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
342 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
343
344 /* clear pending RX/TX interrupts */
345 for (i = 0; i < 256; i++) {
346 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
347 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
348 }
349
350 /* clear pending errors */
351 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
352 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
353
354 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
355 if (val)
356 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
357 ag->dev->name, val);
358
359 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
360
361 /* mask out reserved bits */
362 val &= ~0xff000000;
363
364 if (val)
365 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
366 ag->dev->name, val);
367
368 ag71xx_dump_dma_regs(ag);
369 }
370
371 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
372 MAC_CFG1_SRX | MAC_CFG1_STX)
373
374 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
375
376 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
377 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
378 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
379 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
380 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
381 FIFO_CFG4_VT)
382
383 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
384 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
385 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
386 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
387 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
388 FIFO_CFG5_17 | FIFO_CFG5_SF)
389
390 static void ag71xx_hw_stop(struct ag71xx *ag)
391 {
392 /* disable all interrupts and stop the rx/tx engine */
393 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
394 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
395 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
396 }
397
398 static void ag71xx_hw_setup(struct ag71xx *ag)
399 {
400 struct device_node *np = ag->pdev->dev.of_node;
401 u32 init = MAC_CFG1_INIT;
402
403 /* setup MAC configuration registers */
404 if (of_property_read_bool(np, "flow-control"))
405 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
406 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
407
408 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
409 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
410
411 /* setup max frame length to zero */
412 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
413
414 /* setup FIFO configuration registers */
415 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
416 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
417 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
418 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
419 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
420 }
421
422 static void ag71xx_hw_init(struct ag71xx *ag)
423 {
424 ag71xx_hw_stop(ag);
425
426 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
427 udelay(20);
428
429 reset_control_assert(ag->mac_reset);
430 msleep(100);
431 reset_control_deassert(ag->mac_reset);
432 msleep(200);
433
434 ag71xx_hw_setup(ag);
435
436 ag71xx_dma_reset(ag);
437 }
438
439 static void ag71xx_fast_reset(struct ag71xx *ag)
440 {
441 struct net_device *dev = ag->dev;
442 u32 rx_ds;
443 u32 mii_reg;
444
445 ag71xx_hw_stop(ag);
446 wmb();
447
448 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
449 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
450
451 ag71xx_tx_packets(ag, true);
452
453 reset_control_assert(ag->mac_reset);
454 udelay(10);
455 reset_control_deassert(ag->mac_reset);
456 udelay(10);
457
458 ag71xx_dma_reset(ag);
459 ag71xx_hw_setup(ag);
460 ag->tx_ring.curr = 0;
461 ag->tx_ring.dirty = 0;
462 netdev_reset_queue(ag->dev);
463
464 /* setup max frame length */
465 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
466 ag71xx_max_frame_len(ag->dev->mtu));
467
468 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
469 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
470 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
471
472 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
473 }
474
475 static void ag71xx_hw_start(struct ag71xx *ag)
476 {
477 /* start RX engine */
478 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
479
480 /* enable interrupts */
481 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
482
483 netif_wake_queue(ag->dev);
484 }
485
486 static void ath79_set_pllval(struct ag71xx *ag)
487 {
488 u32 pll_reg = ag->pllreg[1];
489 u32 pll_val;
490
491 if (!ag->pllregmap)
492 return;
493
494 switch (ag->speed) {
495 case SPEED_10:
496 pll_val = ag->plldata[2];
497 break;
498 case SPEED_100:
499 pll_val = ag->plldata[1];
500 break;
501 case SPEED_1000:
502 pll_val = ag->plldata[0];
503 break;
504 default:
505 BUG();
506 }
507
508 if (pll_val)
509 regmap_write(ag->pllregmap, pll_reg, pll_val);
510 }
511
512 static void ath79_set_pll(struct ag71xx *ag)
513 {
514 u32 pll_cfg = ag->pllreg[0];
515 u32 pll_shift = ag->pllreg[2];
516
517 if (!ag->pllregmap)
518 return;
519
520 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
521 udelay(100);
522
523 ath79_set_pllval(ag);
524
525 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
526 udelay(100);
527
528 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
529 udelay(100);
530 }
531
532 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
533 {
534 unsigned int mii_speed;
535 u32 t;
536
537 if (!ag->mii_base)
538 return;
539
540 switch (ag->speed) {
541 case SPEED_10:
542 mii_speed = AR71XX_MII_CTRL_SPEED_10;
543 break;
544 case SPEED_100:
545 mii_speed = AR71XX_MII_CTRL_SPEED_100;
546 break;
547 case SPEED_1000:
548 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
549 break;
550 default:
551 BUG();
552 }
553
554 t = __raw_readl(ag->mii_base);
555 t &= ~(AR71XX_MII_CTRL_IF_MASK);
556 t |= (mii_speed & AR71XX_MII_CTRL_IF_MASK);
557 __raw_writel(t, ag->mii_base);
558 }
559
560 static void
561 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
562 {
563 struct device_node *np = ag->pdev->dev.of_node;
564 u32 cfg2;
565 u32 ifctl;
566 u32 fifo5;
567
568 if (!ag->link && update) {
569 ag71xx_hw_stop(ag);
570 netif_carrier_off(ag->dev);
571 if (netif_msg_link(ag))
572 pr_info("%s: link down\n", ag->dev->name);
573 return;
574 }
575
576 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
577 !of_device_is_compatible(np, "qca,ar7100-eth"))
578 ag71xx_fast_reset(ag);
579
580 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
581 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
582 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
583
584 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
585 ifctl &= ~(MAC_IFCTL_SPEED);
586
587 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
588 fifo5 &= ~FIFO_CFG5_BM;
589
590 switch (ag->speed) {
591 case SPEED_1000:
592 cfg2 |= MAC_CFG2_IF_1000;
593 fifo5 |= FIFO_CFG5_BM;
594 break;
595 case SPEED_100:
596 cfg2 |= MAC_CFG2_IF_10_100;
597 ifctl |= MAC_IFCTL_SPEED;
598 break;
599 case SPEED_10:
600 cfg2 |= MAC_CFG2_IF_10_100;
601 break;
602 default:
603 BUG();
604 return;
605 }
606
607 if (ag->tx_ring.desc_split) {
608 ag->fifodata[2] &= 0xffff;
609 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
610 }
611
612 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
613
614 if (update) {
615 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
616 of_device_is_compatible(np, "qca,ar9130-eth")) {
617 ath79_set_pll(ag);
618 ath79_mii_ctrl_set_speed(ag);
619 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
620 of_device_is_compatible(np, "qca,ar9340-eth") ||
621 of_device_is_compatible(np, "qca,qca9550-eth") ||
622 of_device_is_compatible(np, "qca,qca9560-eth")) {
623 ath79_set_pllval(ag);
624 }
625 }
626
627 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
628 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
629 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
630
631 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
632 of_device_is_compatible(np, "qca,qca9560-eth")) {
633 /*
634 * The rx ring buffer can stall on small packets on QCA953x and
635 * QCA956x. Disabling the inline checksum engine fixes the stall.
636 * The wr, rr functions cannot be used since this hidden register
637 * is outside of the normal ag71xx register block.
638 */
639 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
640 if (dam) {
641 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
642 (void)__raw_readl(dam);
643 iounmap(dam);
644 }
645 }
646
647 ag71xx_hw_start(ag);
648
649 netif_carrier_on(ag->dev);
650 if (update && netif_msg_link(ag))
651 pr_info("%s: link up (%sMbps/%s duplex)\n",
652 ag->dev->name,
653 ag71xx_speed_str(ag),
654 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
655
656 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
657 ag->dev->name,
658 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
659 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
660 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
661
662 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
663 ag->dev->name,
664 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
665 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
666 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
667
668 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
669 ag->dev->name,
670 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
671 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
672 }
673
674 void ag71xx_link_adjust(struct ag71xx *ag)
675 {
676 __ag71xx_link_adjust(ag, true);
677 }
678
679 static int ag71xx_hw_enable(struct ag71xx *ag)
680 {
681 int ret;
682
683 ret = ag71xx_rings_init(ag);
684 if (ret)
685 return ret;
686
687 napi_enable(&ag->napi);
688 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
689 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
690 netif_start_queue(ag->dev);
691
692 return 0;
693 }
694
695 static void ag71xx_hw_disable(struct ag71xx *ag)
696 {
697 unsigned long flags;
698
699 spin_lock_irqsave(&ag->lock, flags);
700
701 netif_stop_queue(ag->dev);
702
703 ag71xx_hw_stop(ag);
704 ag71xx_dma_reset(ag);
705
706 napi_disable(&ag->napi);
707 del_timer_sync(&ag->oom_timer);
708
709 spin_unlock_irqrestore(&ag->lock, flags);
710
711 ag71xx_rings_cleanup(ag);
712 }
713
714 static int ag71xx_open(struct net_device *dev)
715 {
716 struct ag71xx *ag = netdev_priv(dev);
717 unsigned int max_frame_len;
718 int ret;
719
720 netif_carrier_off(dev);
721 max_frame_len = ag71xx_max_frame_len(dev->mtu);
722 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
723
724 /* setup max frame length */
725 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
726 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
727
728 ret = ag71xx_hw_enable(ag);
729 if (ret)
730 goto err;
731
732 phy_start(ag->phy_dev);
733
734 return 0;
735
736 err:
737 ag71xx_rings_cleanup(ag);
738 return ret;
739 }
740
741 static int ag71xx_stop(struct net_device *dev)
742 {
743 struct ag71xx *ag = netdev_priv(dev);
744
745 netif_carrier_off(dev);
746 phy_stop(ag->phy_dev);
747 ag71xx_hw_disable(ag);
748
749 return 0;
750 }
751
752 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
753 {
754 int i;
755 struct ag71xx_desc *desc;
756 int ring_mask = BIT(ring->order) - 1;
757 int ndesc = 0;
758 int split = ring->desc_split;
759
760 if (!split)
761 split = len;
762
763 while (len > 0) {
764 unsigned int cur_len = len;
765
766 i = (ring->curr + ndesc) & ring_mask;
767 desc = ag71xx_ring_desc(ring, i);
768
769 if (!ag71xx_desc_empty(desc))
770 return -1;
771
772 if (cur_len > split) {
773 cur_len = split;
774
775 /*
776 * TX will hang if DMA transfers <= 4 bytes,
777 * make sure next segment is more than 4 bytes long.
778 */
779 if (len <= split + 4)
780 cur_len -= 4;
781 }
782
783 desc->data = addr;
784 addr += cur_len;
785 len -= cur_len;
786
787 if (len > 0)
788 cur_len |= DESC_MORE;
789
790 /* prevent early tx attempt of this descriptor */
791 if (!ndesc)
792 cur_len |= DESC_EMPTY;
793
794 desc->ctrl = cur_len;
795 ndesc++;
796 }
797
798 return ndesc;
799 }
800
801 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
802 struct net_device *dev)
803 {
804 struct ag71xx *ag = netdev_priv(dev);
805 struct ag71xx_ring *ring = &ag->tx_ring;
806 int ring_mask = BIT(ring->order) - 1;
807 int ring_size = BIT(ring->order);
808 struct ag71xx_desc *desc;
809 dma_addr_t dma_addr;
810 int i, n, ring_min;
811
812 if (skb->len <= 4) {
813 DBG("%s: packet len is too small\n", ag->dev->name);
814 goto err_drop;
815 }
816
817 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
818 DMA_TO_DEVICE);
819
820 i = ring->curr & ring_mask;
821 desc = ag71xx_ring_desc(ring, i);
822
823 /* setup descriptor fields */
824 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
825 if (n < 0)
826 goto err_drop_unmap;
827
828 i = (ring->curr + n - 1) & ring_mask;
829 ring->buf[i].len = skb->len;
830 ring->buf[i].skb = skb;
831
832 netdev_sent_queue(dev, skb->len);
833
834 skb_tx_timestamp(skb);
835
836 desc->ctrl &= ~DESC_EMPTY;
837 ring->curr += n;
838
839 /* flush descriptor */
840 wmb();
841
842 ring_min = 2;
843 if (ring->desc_split)
844 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
845
846 if (ring->curr - ring->dirty >= ring_size - ring_min) {
847 DBG("%s: tx queue full\n", dev->name);
848 netif_stop_queue(dev);
849 }
850
851 DBG("%s: packet injected into TX queue\n", ag->dev->name);
852
853 /* enable TX engine */
854 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
855
856 return NETDEV_TX_OK;
857
858 err_drop_unmap:
859 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
860
861 err_drop:
862 dev->stats.tx_dropped++;
863
864 dev_kfree_skb(skb);
865 return NETDEV_TX_OK;
866 }
867
868 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
869 {
870 struct ag71xx *ag = netdev_priv(dev);
871 int ret;
872
873 switch (cmd) {
874 case SIOCETHTOOL:
875 if (ag->phy_dev == NULL)
876 break;
877
878 spin_lock_irq(&ag->lock);
879 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
880 spin_unlock_irq(&ag->lock);
881 return ret;
882
883 case SIOCSIFHWADDR:
884 if (copy_from_user
885 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
886 return -EFAULT;
887 return 0;
888
889 case SIOCGIFHWADDR:
890 if (copy_to_user
891 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
892 return -EFAULT;
893 return 0;
894
895 case SIOCGMIIPHY:
896 case SIOCGMIIREG:
897 case SIOCSMIIREG:
898 if (ag->phy_dev == NULL)
899 break;
900
901 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
902
903 default:
904 break;
905 }
906
907 return -EOPNOTSUPP;
908 }
909
910 static void ag71xx_oom_timer_handler(unsigned long data)
911 {
912 struct net_device *dev = (struct net_device *) data;
913 struct ag71xx *ag = netdev_priv(dev);
914
915 napi_schedule(&ag->napi);
916 }
917
918 static void ag71xx_tx_timeout(struct net_device *dev)
919 {
920 struct ag71xx *ag = netdev_priv(dev);
921
922 if (netif_msg_tx_err(ag))
923 pr_info("%s: tx timeout\n", ag->dev->name);
924
925 schedule_delayed_work(&ag->restart_work, 1);
926 }
927
928 static void ag71xx_restart_work_func(struct work_struct *work)
929 {
930 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
931
932 rtnl_lock();
933 ag71xx_hw_disable(ag);
934 ag71xx_hw_enable(ag);
935 if (ag->link)
936 __ag71xx_link_adjust(ag, false);
937 rtnl_unlock();
938 }
939
940 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
941 {
942 unsigned long timestamp;
943 u32 rx_sm, tx_sm, rx_fd;
944
945 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
946 if (likely(time_before(jiffies, timestamp + HZ/10)))
947 return false;
948
949 if (!netif_carrier_ok(ag->dev))
950 return false;
951
952 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
953 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
954 return true;
955
956 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
957 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
958 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
959 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
960 return true;
961
962 return false;
963 }
964
965 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
966 {
967 struct ag71xx_ring *ring = &ag->tx_ring;
968 bool dma_stuck = false;
969 int ring_mask = BIT(ring->order) - 1;
970 int ring_size = BIT(ring->order);
971 int sent = 0;
972 int bytes_compl = 0;
973 int n = 0;
974
975 DBG("%s: processing TX ring\n", ag->dev->name);
976
977 while (ring->dirty + n != ring->curr) {
978 unsigned int i = (ring->dirty + n) & ring_mask;
979 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
980 struct sk_buff *skb = ring->buf[i].skb;
981
982 if (!flush && !ag71xx_desc_empty(desc)) {
983 if (ag->tx_hang_workaround &&
984 ag71xx_check_dma_stuck(ag)) {
985 schedule_delayed_work(&ag->restart_work, HZ / 2);
986 dma_stuck = true;
987 }
988 break;
989 }
990
991 if (flush)
992 desc->ctrl |= DESC_EMPTY;
993
994 n++;
995 if (!skb)
996 continue;
997
998 dev_kfree_skb_any(skb);
999 ring->buf[i].skb = NULL;
1000
1001 bytes_compl += ring->buf[i].len;
1002
1003 sent++;
1004 ring->dirty += n;
1005
1006 while (n > 0) {
1007 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1008 n--;
1009 }
1010 }
1011
1012 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1013
1014 if (!sent)
1015 return 0;
1016
1017 ag->dev->stats.tx_bytes += bytes_compl;
1018 ag->dev->stats.tx_packets += sent;
1019
1020 netdev_completed_queue(ag->dev, sent, bytes_compl);
1021 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1022 netif_wake_queue(ag->dev);
1023
1024 if (!dma_stuck)
1025 cancel_delayed_work(&ag->restart_work);
1026
1027 return sent;
1028 }
1029
1030 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1031 {
1032 struct net_device *dev = ag->dev;
1033 struct ag71xx_ring *ring = &ag->rx_ring;
1034 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1035 unsigned int offset = ag->rx_buf_offset;
1036 int ring_mask = BIT(ring->order) - 1;
1037 int ring_size = BIT(ring->order);
1038 struct sk_buff_head queue;
1039 struct sk_buff *skb;
1040 int done = 0;
1041
1042 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1043 dev->name, limit, ring->curr, ring->dirty);
1044
1045 skb_queue_head_init(&queue);
1046
1047 while (done < limit) {
1048 unsigned int i = ring->curr & ring_mask;
1049 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1050 int pktlen;
1051 int err = 0;
1052
1053 if (ag71xx_desc_empty(desc))
1054 break;
1055
1056 if ((ring->dirty + ring_size) == ring->curr) {
1057 ag71xx_assert(0);
1058 break;
1059 }
1060
1061 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1062
1063 pktlen = desc->ctrl & pktlen_mask;
1064 pktlen -= ETH_FCS_LEN;
1065
1066 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1067 ag->rx_buf_size, DMA_FROM_DEVICE);
1068
1069 dev->stats.rx_packets++;
1070 dev->stats.rx_bytes += pktlen;
1071
1072 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1073 if (!skb) {
1074 skb_free_frag(ring->buf[i].rx_buf);
1075 goto next;
1076 }
1077
1078 skb_reserve(skb, offset);
1079 skb_put(skb, pktlen);
1080
1081 if (err) {
1082 dev->stats.rx_dropped++;
1083 kfree_skb(skb);
1084 } else {
1085 skb->dev = dev;
1086 skb->ip_summed = CHECKSUM_NONE;
1087 __skb_queue_tail(&queue, skb);
1088 }
1089
1090 next:
1091 ring->buf[i].rx_buf = NULL;
1092 done++;
1093
1094 ring->curr++;
1095 }
1096
1097 ag71xx_ring_rx_refill(ag);
1098
1099 while ((skb = __skb_dequeue(&queue)) != NULL) {
1100 skb->protocol = eth_type_trans(skb, dev);
1101 netif_receive_skb(skb);
1102 }
1103
1104 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1105 dev->name, ring->curr, ring->dirty, done);
1106
1107 return done;
1108 }
1109
1110 static int ag71xx_poll(struct napi_struct *napi, int limit)
1111 {
1112 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1113 struct net_device *dev = ag->dev;
1114 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1115 int rx_ring_size = BIT(rx_ring->order);
1116 unsigned long flags;
1117 u32 status;
1118 int tx_done;
1119 int rx_done;
1120
1121 tx_done = ag71xx_tx_packets(ag, false);
1122
1123 DBG("%s: processing RX ring\n", dev->name);
1124 rx_done = ag71xx_rx_packets(ag, limit);
1125
1126 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1127
1128 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1129 goto oom;
1130
1131 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1132 if (unlikely(status & RX_STATUS_OF)) {
1133 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1134 dev->stats.rx_fifo_errors++;
1135
1136 /* restart RX */
1137 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1138 }
1139
1140 if (rx_done < limit) {
1141 if (status & RX_STATUS_PR)
1142 goto more;
1143
1144 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1145 if (status & TX_STATUS_PS)
1146 goto more;
1147
1148 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1149 dev->name, rx_done, tx_done, limit);
1150
1151 napi_complete(napi);
1152
1153 /* enable interrupts */
1154 spin_lock_irqsave(&ag->lock, flags);
1155 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1156 spin_unlock_irqrestore(&ag->lock, flags);
1157 return rx_done;
1158 }
1159
1160 more:
1161 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1162 dev->name, rx_done, tx_done, limit);
1163 return limit;
1164
1165 oom:
1166 if (netif_msg_rx_err(ag))
1167 pr_info("%s: out of memory\n", dev->name);
1168
1169 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1170 napi_complete(napi);
1171 return 0;
1172 }
1173
1174 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1175 {
1176 struct net_device *dev = dev_id;
1177 struct ag71xx *ag = netdev_priv(dev);
1178 u32 status;
1179
1180 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1181 ag71xx_dump_intr(ag, "raw", status);
1182
1183 if (unlikely(!status))
1184 return IRQ_NONE;
1185
1186 if (unlikely(status & AG71XX_INT_ERR)) {
1187 if (status & AG71XX_INT_TX_BE) {
1188 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1189 dev_err(&dev->dev, "TX BUS error\n");
1190 }
1191 if (status & AG71XX_INT_RX_BE) {
1192 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1193 dev_err(&dev->dev, "RX BUS error\n");
1194 }
1195 }
1196
1197 if (likely(status & AG71XX_INT_POLL)) {
1198 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1199 DBG("%s: enable polling mode\n", dev->name);
1200 napi_schedule(&ag->napi);
1201 }
1202
1203 ag71xx_debugfs_update_int_stats(ag, status);
1204
1205 return IRQ_HANDLED;
1206 }
1207
1208 #ifdef CONFIG_NET_POLL_CONTROLLER
1209 /*
1210 * Polling 'interrupt' - used by things like netconsole to send skbs
1211 * without having to re-enable interrupts. It's not called while
1212 * the interrupt routine is executing.
1213 */
1214 static void ag71xx_netpoll(struct net_device *dev)
1215 {
1216 disable_irq(dev->irq);
1217 ag71xx_interrupt(dev->irq, dev);
1218 enable_irq(dev->irq);
1219 }
1220 #endif
1221
1222 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1223 {
1224 struct ag71xx *ag = netdev_priv(dev);
1225
1226 dev->mtu = new_mtu;
1227 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1228 ag71xx_max_frame_len(dev->mtu));
1229
1230 return 0;
1231 }
1232
1233 static const struct net_device_ops ag71xx_netdev_ops = {
1234 .ndo_open = ag71xx_open,
1235 .ndo_stop = ag71xx_stop,
1236 .ndo_start_xmit = ag71xx_hard_start_xmit,
1237 .ndo_do_ioctl = ag71xx_do_ioctl,
1238 .ndo_tx_timeout = ag71xx_tx_timeout,
1239 .ndo_change_mtu = ag71xx_change_mtu,
1240 .ndo_set_mac_address = eth_mac_addr,
1241 .ndo_validate_addr = eth_validate_addr,
1242 #ifdef CONFIG_NET_POLL_CONTROLLER
1243 .ndo_poll_controller = ag71xx_netpoll,
1244 #endif
1245 };
1246
1247 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1248 {
1249 switch (mode) {
1250 case PHY_INTERFACE_MODE_MII:
1251 return "MII";
1252 case PHY_INTERFACE_MODE_GMII:
1253 return "GMII";
1254 case PHY_INTERFACE_MODE_RMII:
1255 return "RMII";
1256 case PHY_INTERFACE_MODE_RGMII:
1257 return "RGMII";
1258 case PHY_INTERFACE_MODE_SGMII:
1259 return "SGMII";
1260 default:
1261 break;
1262 }
1263
1264 return "unknown";
1265 }
1266
1267 static int ag71xx_probe(struct platform_device *pdev)
1268 {
1269 struct device_node *np = pdev->dev.of_node;
1270 struct device_node *mdio_node;
1271 struct net_device *dev;
1272 struct resource *res;
1273 struct ag71xx *ag;
1274 const void *mac_addr;
1275 u32 max_frame_len;
1276 int tx_size, err;
1277
1278 if (!np)
1279 return -ENODEV;
1280
1281 dev = alloc_etherdev(sizeof(*ag));
1282 if (!dev)
1283 return -ENOMEM;
1284
1285 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1286 if (!res)
1287 return -EINVAL;
1288
1289 err = ag71xx_setup_gmac(np);
1290 if (err)
1291 return err;
1292
1293 SET_NETDEV_DEV(dev, &pdev->dev);
1294
1295 ag = netdev_priv(dev);
1296 ag->pdev = pdev;
1297 ag->dev = dev;
1298 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1299 AG71XX_DEFAULT_MSG_ENABLE);
1300 spin_lock_init(&ag->lock);
1301
1302 ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac");
1303 if (IS_ERR(ag->mac_reset)) {
1304 dev_err(&pdev->dev, "missing mac reset\n");
1305 err = PTR_ERR(ag->mac_reset);
1306 goto err_free;
1307 }
1308
1309 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1310 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1311 of_device_is_compatible(np, "qca,ar7100-eth")) {
1312 ag->fifodata[0] = 0x0fff0000;
1313 ag->fifodata[1] = 0x00001fff;
1314 } else {
1315 ag->fifodata[0] = 0x0010ffff;
1316 ag->fifodata[1] = 0x015500aa;
1317 ag->fifodata[2] = 0x01f00140;
1318 }
1319 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1320 ag->fifodata[2] = 0x00780fff;
1321 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1322 ag->fifodata[2] = 0x008001ff;
1323 }
1324
1325 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1326 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1327
1328 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1329 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1330
1331 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1332 if (IS_ERR(ag->pllregmap)) {
1333 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1334 ag->pllregmap = NULL;
1335 }
1336
1337 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1338 res->end - res->start + 1);
1339 if (!ag->mac_base) {
1340 err = -ENOMEM;
1341 goto err_free;
1342 }
1343 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1344 if (res) {
1345 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1346 res->end - res->start + 1);
1347 if (!ag->mii_base) {
1348 err = -ENOMEM;
1349 goto err_free;
1350 }
1351 }
1352
1353 dev->irq = platform_get_irq(pdev, 0);
1354 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1355 0x0, dev_name(&pdev->dev), dev);
1356 if (err) {
1357 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1358 goto err_free;
1359 }
1360
1361 dev->netdev_ops = &ag71xx_netdev_ops;
1362 dev->ethtool_ops = &ag71xx_ethtool_ops;
1363
1364 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1365
1366 init_timer(&ag->oom_timer);
1367 ag->oom_timer.data = (unsigned long) dev;
1368 ag->oom_timer.function = ag71xx_oom_timer_handler;
1369
1370 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1371 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1372
1373 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1374 of_device_is_compatible(np, "qca,qca9530-eth") ||
1375 of_device_is_compatible(np, "qca,qca9550-eth") ||
1376 of_device_is_compatible(np, "qca,qca9560-eth"))
1377 ag->desc_pktlen_mask = SZ_16K - 1;
1378 else
1379 ag->desc_pktlen_mask = SZ_4K - 1;
1380
1381 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1382 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1383 !of_device_is_compatible(np, "qca,qca9560-eth"))
1384 max_frame_len = ag->desc_pktlen_mask;
1385 else
1386 max_frame_len = 1540;
1387
1388 dev->min_mtu = 68;
1389 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1390
1391 if (of_device_is_compatible(np, "qca,ar7240-eth"))
1392 ag->tx_hang_workaround = 1;
1393
1394 ag->rx_buf_offset = NET_SKB_PAD;
1395 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1396 !of_device_is_compatible(np, "qca,ar9130-eth"))
1397 ag->rx_buf_offset += NET_IP_ALIGN;
1398
1399 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1400 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1401 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1402 }
1403 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1404
1405 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1406 sizeof(struct ag71xx_desc),
1407 &ag->stop_desc_dma, GFP_KERNEL);
1408 if (!ag->stop_desc)
1409 goto err_free;
1410
1411 ag->stop_desc->data = 0;
1412 ag->stop_desc->ctrl = 0;
1413 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1414
1415 mac_addr = of_get_mac_address(np);
1416 if (mac_addr)
1417 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1418 if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1419 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1420 eth_random_addr(dev->dev_addr);
1421 }
1422
1423 ag->phy_if_mode = of_get_phy_mode(np);
1424 if (ag->phy_if_mode < 0) {
1425 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1426 err = ag->phy_if_mode;
1427 goto err_free;
1428 }
1429
1430 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1431
1432 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1433 ag71xx_hw_init(ag);
1434
1435 if(!of_device_is_compatible(np, "simple-mfd")) {
1436 mdio_node = of_get_child_by_name(np, "mdio-bus");
1437 if(!IS_ERR(mdio_node))
1438 of_platform_device_create(mdio_node, NULL, NULL);
1439 }
1440
1441 err = ag71xx_phy_connect(ag);
1442 if (err)
1443 goto err_free;
1444
1445 err = ag71xx_debugfs_init(ag);
1446 if (err)
1447 goto err_phy_disconnect;
1448
1449 platform_set_drvdata(pdev, dev);
1450
1451 err = register_netdev(dev);
1452 if (err) {
1453 dev_err(&pdev->dev, "unable to register net device\n");
1454 platform_set_drvdata(pdev, NULL);
1455 ag71xx_debugfs_exit(ag);
1456 goto err_phy_disconnect;
1457 }
1458
1459 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1460 dev->name, (unsigned long) ag->mac_base, dev->irq,
1461 ag71xx_get_phy_if_mode_name(ag->phy_if_mode));
1462
1463 return 0;
1464
1465 err_phy_disconnect:
1466 ag71xx_phy_disconnect(ag);
1467 err_free:
1468 free_netdev(dev);
1469 return err;
1470 }
1471
1472 static int ag71xx_remove(struct platform_device *pdev)
1473 {
1474 struct net_device *dev = platform_get_drvdata(pdev);
1475 struct ag71xx *ag;
1476
1477 if (!dev)
1478 return 0;
1479
1480 ag = netdev_priv(dev);
1481 ag71xx_debugfs_exit(ag);
1482 ag71xx_phy_disconnect(ag);
1483 unregister_netdev(dev);
1484 free_irq(dev->irq, dev);
1485 iounmap(ag->mac_base);
1486 kfree(dev);
1487 platform_set_drvdata(pdev, NULL);
1488
1489 return 0;
1490 }
1491
1492 static const struct of_device_id ag71xx_match[] = {
1493 { .compatible = "qca,ar7100-eth" },
1494 { .compatible = "qca,ar7240-eth" },
1495 { .compatible = "qca,ar7241-eth" },
1496 { .compatible = "qca,ar7242-eth" },
1497 { .compatible = "qca,ar9130-eth" },
1498 { .compatible = "qca,ar9330-eth" },
1499 { .compatible = "qca,ar9340-eth" },
1500 { .compatible = "qca,qca9530-eth" },
1501 { .compatible = "qca,qca9550-eth" },
1502 { .compatible = "qca,qca9560-eth" },
1503 {}
1504 };
1505
1506 static struct platform_driver ag71xx_driver = {
1507 .probe = ag71xx_probe,
1508 .remove = ag71xx_remove,
1509 .driver = {
1510 .name = AG71XX_DRV_NAME,
1511 .of_match_table = ag71xx_match,
1512 }
1513 };
1514
1515 static int __init ag71xx_module_init(void)
1516 {
1517 int ret;
1518
1519 ret = ag71xx_debugfs_root_init();
1520 if (ret)
1521 goto err_out;
1522
1523 ret = platform_driver_register(&ag71xx_driver);
1524 if (ret)
1525 goto err_debugfs_exit;
1526
1527 return 0;
1528
1529 err_debugfs_exit:
1530 ag71xx_debugfs_root_exit();
1531 err_out:
1532 return ret;
1533 }
1534
1535 static void __exit ag71xx_module_exit(void)
1536 {
1537 platform_driver_unregister(&ag71xx_driver);
1538 ag71xx_debugfs_root_exit();
1539 }
1540
1541 module_init(ag71xx_module_init);
1542 module_exit(ag71xx_module_exit);
1543
1544 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1545 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1546 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1547 MODULE_LICENSE("GPL v2");
1548 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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