target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_mdio.c

   1 /*
   2  *  Atheros AR71xx built-in ethernet mac driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Based on Atheros' AG7100 driver
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/of_mdio.h>
  16 #include "ag71xx.h"
  17
  18 #define AG71XX_MDIO_RETRY       1000
  19 #define AG71XX_MDIO_DELAY       5
  20
  21 static int bus_count;
  22
  23 static int ag71xx_mdio_wait_busy(struct ag71xx *ag)
  24 {
  25         int i;
  26
  27         for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
  28                 u32 busy;
  29
  30                 udelay(AG71XX_MDIO_DELAY);
  31
  32                 regmap_read(ag->mii_regmap, AG71XX_REG_MII_IND, &busy);
  33                 if (!busy)
  34                         return 0;
  35
  36                 udelay(AG71XX_MDIO_DELAY);
  37         }
  38
  39         pr_err("%s: MDIO operation timed out\n", ag->mii_bus->name);
  40
  41         return -ETIMEDOUT;
  42 }
  43
  44 int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
  45 {
  46         struct ag71xx *ag = bus->priv;
  47         int err;
  48         int ret;
  49
  50         err = ag71xx_mdio_wait_busy(ag);
  51         if (err)
  52                 return 0xffff;
  53
  54         regmap_write(ag->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  55         regmap_write(ag->mii_regmap, AG71XX_REG_MII_ADDR,
  56                         ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  57         regmap_write(ag->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_READ);
  58
  59         err = ag71xx_mdio_wait_busy(ag);
  60         if (err)
  61                 return 0xffff;
  62
  63         regmap_read(ag->mii_regmap, AG71XX_REG_MII_STATUS, &ret);
  64         ret &= 0xffff;
  65         regmap_write(ag->mii_regmap, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
  66
  67         DBG("mii_read: addr=%04x, reg=%04x, value=%04x\n", addr, reg, ret);
  68
  69         return ret;
  70 }
  71
  72 int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
  73 {
  74         struct ag71xx *ag = bus->priv;
  75
  76         DBG("mii_write: addr=%04x, reg=%04x, value=%04x\n", addr, reg, val);
  77
  78         regmap_write(ag->mii_regmap, AG71XX_REG_MII_ADDR,
  79                         ((addr & 0xff) << MII_ADDR_SHIFT) | (reg & 0xff));
  80         regmap_write(ag->mii_regmap, AG71XX_REG_MII_CTRL, val);
  81
  82         ag71xx_mdio_wait_busy(ag);
  83
  84         return 0;
  85 }
  86
  87 static int ar934x_mdio_clock_div(unsigned int rate)
  88 {
  89         if (rate == 100 * 1000 * 1000)
  90                 return 6; /* 100 MHz clock divided by 20 => 5 MHz */
  91         else if (rate == 25 * 1000 * 1000)
  92                 return 0; /* 25 MHz clock divided by 4 => 6.25 MHz */
  93         else
  94                 return 3; /* 40 MHz clock divided by 8 => 5 MHz */
  95 }
  96
  97 static int ag71xx_mdio_reset(struct mii_bus *bus)
  98 {
  99         struct device_node *np = bus->dev.of_node;
 100         struct ag71xx *ag = bus->priv;
 101         struct device_node *np_ag = ag->pdev->dev.of_node;
 102         bool builtin_switch;
 103         u32 t;
 104
 105         builtin_switch = of_property_read_bool(np, "builtin-switch");
 106
 107         if (of_device_is_compatible(np_ag, "qca,ar7240-eth"))
 108                 t = MII_CFG_CLK_DIV_6;
 109         else if (of_device_is_compatible(np_ag, "qca,ar9340-eth"))
 110                 t = MII_CFG_CLK_DIV_58;
 111         else if (builtin_switch)
 112                 t = MII_CFG_CLK_DIV_10;
 113         else
 114                 t = MII_CFG_CLK_DIV_28;
 115
 116         if (builtin_switch && of_device_is_compatible(np_ag, "qca,ar9340-eth")) {
 117                 struct clk *ref_clk = of_clk_get(np, 0);
 118                 int clock_rate;
 119
 120                 if (WARN_ON_ONCE(!ref_clk))
 121                         clock_rate = 40 * 1000 * 1000;
 122                 else
 123                         clock_rate = clk_get_rate(ref_clk);
 124
 125                 t = ar934x_mdio_clock_div(clock_rate);
 126                 clk_put(ref_clk);
 127         }
 128
 129         regmap_write(ag->mii_regmap, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
 130         udelay(100);
 131
 132         regmap_write(ag->mii_regmap, AG71XX_REG_MII_CFG, t);
 133         udelay(100);
 134
 135         return 0;
 136 }
 137
 138 int ag71xx_mdio_init(struct ag71xx *ag)
 139 {
 140         struct device *parent = &ag->pdev->dev;
 141         struct device_node *np;
 142         struct mii_bus *mii_bus;
 143         bool builtin_switch;
 144         int i, err;
 145
 146         np = of_get_child_by_name(parent->of_node, "mdio-bus");
 147         if (!np)
 148                 return -ENODEV;
 149
 150         if (!of_device_is_available(np)) {
 151                 err = 0;
 152                 goto err_out;
 153         }
 154
 155         ag->mii_regmap = syscon_regmap_lookup_by_phandle(np, "regmap");
 156         if (!ag->mii_regmap)
 157                 return -ENOENT;
 158
 159         mii_bus = devm_mdiobus_alloc(parent);
 160         if (!mii_bus) {
 161                 err = -ENOMEM;
 162                 goto err_out;
 163         }
 164
 165         ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio");
 166         builtin_switch = of_property_read_bool(np, "builtin-switch");
 167
 168         mii_bus->name = "mdio";
 169         if (builtin_switch) {
 170                 mii_bus->read = ar7240sw_phy_read;
 171                 mii_bus->write = ar7240sw_phy_write;
 172         } else {
 173                 mii_bus->read = ag71xx_mdio_mii_read;
 174                 mii_bus->write = ag71xx_mdio_mii_write;
 175         }
 176         mii_bus->reset = ag71xx_mdio_reset;
 177         mii_bus->priv = ag;
 178         mii_bus->parent = parent;
 179         snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, bus_count++);
 180
 181         if (!builtin_switch &&
 182             of_property_read_u32(np, "phy-mask", &mii_bus->phy_mask))
 183                 mii_bus->phy_mask = 0;
 184
 185         for (i = 0; i < PHY_MAX_ADDR; i++)
 186                 mii_bus->irq[i] = PHY_POLL;
 187
 188         if (!IS_ERR(ag->mdio_reset)) {
 189                 reset_control_assert(ag->mdio_reset);
 190                 msleep(100);
 191                 reset_control_deassert(ag->mdio_reset);
 192                 msleep(200);
 193         }
 194
 195         err = of_mdiobus_register(mii_bus, np);
 196         if (err)
 197                 goto err_out;
 198
 199         ag->mii_bus = mii_bus;
 200
 201         if (builtin_switch)
 202                 ag71xx_ar7240_init(ag, np);
 203
 204         return 0;
 205
 206 err_out:
 207         of_node_put(np);
 208         return err;
 209 }
 210
 211 void ag71xx_mdio_cleanup(struct ag71xx *ag)
 212 {
 213         if (!ag->mii_bus)
 214                 return;
 215
 216         ag71xx_ar7240_cleanup(ag);
 217         mdiobus_unregister(ag->mii_bus);
 218 }