target/linux/atheros/files/arch/mips/atheros/ar531x.h

   1 #ifndef __AR531X_H
   2 #define __AR531X_H
   3
   4 #include <asm/cpu-info.h>
   5 #include <ar531x_platform.h>
   6 #include "ar5312/ar5312.h"
   7 #include "ar5315/ar5315.h"
   8
   9
  10 /*
  11  * C access to CLZ instruction
  12  * (count leading zeroes).
  13  */
  14 static inline int clz(unsigned long val)
  15 {
  16         int ret;
  17
  18         __asm__ volatile (
  19                 ".set\tnoreorder\n\t"
  20                 ".set\tnoat\n\t"
  21                 ".set\tmips32\n\t"
  22                 "clz\t%0,%1\n\t"
  23                 ".set\tmips0\n\t"
  24                 ".set\tat\n\t"
  25                 ".set\treorder"
  26                 : "=r" (ret)
  27                 : "r" (val)
  28         );
  29
  30         return ret;
  31 }
  32
  33 /*
  34  * Atheros CPUs before the AR2315 are using MIPS 4Kc core, later designs are
  35  * using MIPS 4KEc R2 core. This makes it easy to determine the board at runtime.
  36  */
  37 #ifdef CONFIG_ATHEROS_AR5312
  38 #define DO_AR5312(...) \
  39         if (current_cpu_data.cputype != CPU_4KEC) { \
  40                 __VA_ARGS__ \
  41         }
  42 #else
  43 #define DO_AR5312(...)
  44 #endif
  45 #ifdef CONFIG_ATHEROS_AR5315
  46 #define DO_AR5315(...) \
  47         if (current_cpu_data.cputype == CPU_4KEC) { \
  48                 __VA_ARGS__ \
  49         }
  50 #else
  51 #define DO_AR5315(...)
  52 #endif
  53
  54 #define AR531X_MISC_IRQ_BASE            0x20
  55 #define AR531X_GPIO_IRQ_BASE            0x30
  56
  57 /* Software's idea of interrupts handled by "CPU Interrupt Controller" */
  58 #define AR531X_IRQ_NONE         MIPS_CPU_IRQ_BASE+0
  59 #define AR531X_IRQ_CPU_CLOCK    MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
  60
  61 /* Miscellaneous interrupts, which share IP6 */
  62 #define AR531X_MISC_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
  63 #define AR531X_MISC_IRQ_TIMER           AR531X_MISC_IRQ_BASE+1
  64 #define AR531X_MISC_IRQ_AHB_PROC        AR531X_MISC_IRQ_BASE+2
  65 #define AR531X_MISC_IRQ_AHB_DMA         AR531X_MISC_IRQ_BASE+3
  66 #define AR531X_MISC_IRQ_GPIO            AR531X_MISC_IRQ_BASE+4
  67 #define AR531X_MISC_IRQ_UART0           AR531X_MISC_IRQ_BASE+5
  68 #define AR531X_MISC_IRQ_UART0_DMA       AR531X_MISC_IRQ_BASE+6
  69 #define AR531X_MISC_IRQ_WATCHDOG        AR531X_MISC_IRQ_BASE+7
  70 #define AR531X_MISC_IRQ_LOCAL           AR531X_MISC_IRQ_BASE+8
  71 #define AR531X_MISC_IRQ_SPI             AR531X_MISC_IRQ_BASE+9
  72 #define AR531X_MISC_IRQ_COUNT           10
  73
  74 /* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
  75 #define AR531X_GPIO_IRQ_NONE            AR531X_MISC_IRQ_BASE+0
  76 #define AR531X_GPIO_IRQ(n)              AR531X_MISC_IRQ_BASE+(n)+1
  77 #define AR531X_GPIO_IRQ_COUNT           22
  78
  79 #define sysRegRead(phys)        \
  80         (*(volatile u32 *)KSEG1ADDR(phys))
  81
  82 #define sysRegWrite(phys, val)  \
  83         ((*(volatile u32 *)KSEG1ADDR(phys)) = (val))
  84
  85 /*
  86  * This is board-specific data that is stored in a "fixed" location in flash.
  87  * It is shared across operating systems, so it should not be changed lightly.
  88  * The main reason we need it is in order to extract the ethernet MAC
  89  * address(es).
  90  */
  91 struct ar531x_boarddata {
  92     u32 magic;                       /* board data is valid */
  93 #define AR531X_BD_MAGIC 0x35333131   /* "5311", for all 531x platforms */
  94     u16 cksum;                       /* checksum (starting with BD_REV 2) */
  95     u16 rev;                         /* revision of this struct */
  96 #define BD_REV  4
  97     char   boardName[64];            /* Name of board */
  98     u16 major;                       /* Board major number */
  99     u16 minor;                       /* Board minor number */
 100     u32 config;                      /* Board configuration */
 101 #define BD_ENET0        0x00000001   /* ENET0 is stuffed */
 102 #define BD_ENET1        0x00000002   /* ENET1 is stuffed */
 103 #define BD_UART1        0x00000004   /* UART1 is stuffed */
 104 #define BD_UART0        0x00000008   /* UART0 is stuffed (dma) */
 105 #define BD_RSTFACTORY   0x00000010   /* Reset factory defaults stuffed */
 106 #define BD_SYSLED       0x00000020   /* System LED stuffed */
 107 #define BD_EXTUARTCLK   0x00000040   /* External UART clock */
 108 #define BD_CPUFREQ      0x00000080   /* cpu freq is valid in nvram */
 109 #define BD_SYSFREQ      0x00000100   /* sys freq is set in nvram */
 110 #define BD_WLAN0        0x00000200   /* Enable WLAN0 */
 111 #define BD_MEMCAP       0x00000400   /* CAP SDRAM @ memCap for testing */
 112 #define BD_DISWATCHDOG  0x00000800   /* disable system watchdog */
 113 #define BD_WLAN1        0x00001000   /* Enable WLAN1 (ar5212) */
 114 #define BD_ISCASPER     0x00002000   /* FLAG for AR2312 */
 115 #define BD_WLAN0_2G_EN  0x00004000   /* FLAG for radio0_2G */
 116 #define BD_WLAN0_5G_EN  0x00008000   /* FLAG for radio0_2G */
 117 #define BD_WLAN1_2G_EN  0x00020000   /* FLAG for radio0_2G */
 118 #define BD_WLAN1_5G_EN  0x00040000   /* FLAG for radio0_2G */
 119     u16 resetConfigGpio;             /* Reset factory GPIO pin */
 120     u16 sysLedGpio;                  /* System LED GPIO pin */
 121
 122     u32 cpuFreq;                     /* CPU core frequency in Hz */
 123     u32 sysFreq;                     /* System frequency in Hz */
 124     u32 cntFreq;                     /* Calculated C0_COUNT frequency */
 125
 126     u8  wlan0Mac[6];
 127     u8  enet0Mac[6];
 128     u8  enet1Mac[6];
 129
 130     u16 pciId;                       /* Pseudo PCIID for common code */
 131     u16 memCap;                      /* cap bank1 in MB */
 132
 133     /* version 3 */
 134     u8  wlan1Mac[6];                 /* (ar5212) */
 135 };
 136
 137 #define BOARD_CONFIG_BUFSZ              0x1000
 138
 139 extern char *board_config, *radio_config;
 140 extern void serial_setup(unsigned long mapbase, unsigned int uartclk);
 141 extern int ar531x_find_config(char *flash_limit);
 142
 143 extern void ar5312_prom_init(void);
 144 extern void ar5312_misc_intr_init(int irq_base);
 145 extern void ar5312_plat_setup(void);
 146 extern asmlinkage void ar5312_irq_dispatch(void);
 147
 148 extern void ar5315_prom_init(void);
 149 extern void ar5315_misc_intr_init(int irq_base);
 150 extern void ar5315_plat_setup(void);
 151 extern asmlinkage void ar5315_irq_dispatch(void);
 152 extern void ar5315_pci_irq(int irq);
 153 static inline u32 sysRegMask(u32 phys, u32 mask, u32 value)
 154 {
 155         u32 reg;
 156
 157         reg = sysRegRead(phys);
 158         reg &= ~mask;
 159         reg |= value & mask;
 160         sysRegWrite(phys, reg);
 161         reg = sysRegRead(phys); /* flush write to the hardware */
 162
 163         return reg;
 164 }
 165
 166 #endif