1 From ce3d899b0ed284a6e901fb6f4a459fdcf003cadb Mon Sep 17 00:00:00 2001
2 From: Florian Meier <florian.meier@koalo.de>
3 Date: Fri, 22 Nov 2013 14:22:53 +0100
4 Subject: [PATCH 029/114] dmaengine: Add support for BCM2708
6 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
7 Currently it only supports cyclic DMA.
9 Signed-off-by: Florian Meier <florian.meier@koalo.de>
11 dmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels
13 DMA: fix cyclic LITE length overflow bug
15 arch/arm/mach-bcm2708/dma.c | 2 +
16 arch/arm/mach-bcm2708/include/mach/dma.h | 6 +-
17 drivers/dma/Kconfig | 6 +
18 drivers/dma/Makefile | 1 +
19 drivers/dma/bcm2708-dmaengine.c | 1052 ++++++++++++++++++++++++++++++
20 5 files changed, 1066 insertions(+), 1 deletion(-)
21 create mode 100644 drivers/dma/bcm2708-dmaengine.c
23 diff --git a/arch/arm/mach-bcm2708/dma.c b/arch/arm/mach-bcm2708/dma.c
24 index 1da2413..a5e58d1 100644
25 --- a/arch/arm/mach-bcm2708/dma.c
26 +++ b/arch/arm/mach-bcm2708/dma.c
27 @@ -156,6 +156,8 @@ static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
28 dmaman->chan_available = chans_available;
29 dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
30 dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
31 + dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */
32 + dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */
35 static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
36 diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h
37 index a4aac4c..d03e7b5 100644
38 --- a/arch/arm/mach-bcm2708/include/mach/dma.h
39 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
40 @@ -77,9 +77,13 @@ extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
41 those with higher priority smaller ordinal numbers */
42 #define BCM_DMA_FEATURE_FAST_ORD 0
43 #define BCM_DMA_FEATURE_BULK_ORD 1
44 +#define BCM_DMA_FEATURE_NORMAL_ORD 2
45 +#define BCM_DMA_FEATURE_LITE_ORD 3
46 #define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
47 #define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
48 -#define BCM_DMA_FEATURE_COUNT 2
49 +#define BCM_DMA_FEATURE_NORMAL (1<<BCM_DMA_FEATURE_NORMAL_ORD)
50 +#define BCM_DMA_FEATURE_LITE (1<<BCM_DMA_FEATURE_LITE_ORD)
51 +#define BCM_DMA_FEATURE_COUNT 4
53 /* return channel no or -ve error */
54 extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
55 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
56 index de46982..c9b8eb5 100644
57 --- a/drivers/dma/Kconfig
58 +++ b/drivers/dma/Kconfig
59 @@ -330,6 +330,12 @@ config DMA_BCM2835
61 select DMA_VIRTUAL_CHANNELS
64 + tristate "BCM2708 DMA engine support"
65 + depends on MACH_BCM2708
67 + select DMA_VIRTUAL_CHANNELS
70 tristate "AM33xx CPPI41 DMA support"
72 diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
73 index cb626c1..d3c4a82 100644
74 --- a/drivers/dma/Makefile
75 +++ b/drivers/dma/Makefile
76 @@ -38,6 +38,7 @@ obj-$(CONFIG_DMA_SA11X0) += sa11x0-dma.o
77 obj-$(CONFIG_MMP_TDMA) += mmp_tdma.o
78 obj-$(CONFIG_DMA_OMAP) += omap-dma.o
79 obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
80 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
81 obj-$(CONFIG_MMP_PDMA) += mmp_pdma.o
82 obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
83 obj-$(CONFIG_TI_CPPI41) += cppi41.o
84 diff --git a/drivers/dma/bcm2708-dmaengine.c b/drivers/dma/bcm2708-dmaengine.c
86 index 0000000..10463db
88 +++ b/drivers/dma/bcm2708-dmaengine.c
91 + * BCM2835 DMA engine support
93 + * This driver supports cyclic and scatter/gather DMA transfers.
95 + * Author: Florian Meier <florian.meier@koalo.de>
96 + * Gellert Weisz <gellert@raspberrypi.org>
97 + * Copyright 2013-2014
100 + * OMAP DMAengine support by Russell King
102 + * BCM2708 DMA Driver
103 + * Copyright (C) 2010 Broadcom
105 + * Raspberry Pi PCM I2S ALSA Driver
106 + * Copyright (c) by Phil Poole 2013
108 + * MARVELL MMP Peripheral DMA Driver
109 + * Copyright 2012 Marvell International Ltd.
111 + * This program is free software; you can redistribute it and/or modify
112 + * it under the terms of the GNU General Public License as published by
113 + * the Free Software Foundation; either version 2 of the License, or
114 + * (at your option) any later version.
116 + * This program is distributed in the hope that it will be useful,
117 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
118 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
119 + * GNU General Public License for more details.
122 +#include <linux/dmaengine.h>
123 +#include <linux/dma-mapping.h>
124 +#include <linux/err.h>
125 +#include <linux/init.h>
126 +#include <linux/interrupt.h>
127 +#include <linux/list.h>
128 +#include <linux/module.h>
129 +#include <linux/platform_device.h>
130 +#include <linux/slab.h>
131 +#include <linux/io.h>
132 +#include <linux/spinlock.h>
137 +#include <mach/dma.h>
139 +//#define DMA_COMPLETE DMA_SUCCESS
143 +#include <linux/of.h>
144 +#include <linux/of_dma.h>
146 +#include "virt-dma.h"
149 +struct bcm2835_dmadev {
150 + struct dma_device ddev;
152 + void __iomem *base;
153 + struct device_dma_parameters dma_parms;
156 +struct bcm2835_dma_cb {
166 +struct bcm2835_chan {
167 + struct virt_dma_chan vc;
168 + struct list_head node;
170 + struct dma_slave_config cfg;
174 + struct bcm2835_desc *desc;
176 + void __iomem *chan_base;
182 +struct bcm2835_desc {
183 + struct virt_dma_desc vd;
184 + enum dma_transfer_direction dir;
186 + unsigned int control_block_size;
187 + struct bcm2835_dma_cb *control_block_base;
188 + dma_addr_t control_block_base_phys;
190 + unsigned int frames;
194 +#define BCM2835_DMA_CS 0x00
195 +#define BCM2835_DMA_ADDR 0x04
196 +#define BCM2835_DMA_SOURCE_AD 0x0c
197 +#define BCM2835_DMA_DEST_AD 0x10
198 +#define BCM2835_DMA_NEXTCB 0x1C
200 +/* DMA CS Control and Status bits */
201 +#define BCM2835_DMA_ACTIVE BIT(0)
202 +#define BCM2835_DMA_INT BIT(2)
203 +#define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
204 +#define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
205 +#define BCM2835_DMA_ERR BIT(8)
206 +#define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
207 +#define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
209 +#define BCM2835_DMA_INT_EN BIT(0)
210 +#define BCM2835_DMA_WAIT_RESP BIT(3)
211 +#define BCM2835_DMA_D_INC BIT(4)
212 +#define BCM2835_DMA_D_WIDTH BIT(5)
213 +#define BCM2835_DMA_D_DREQ BIT(6)
214 +#define BCM2835_DMA_S_INC BIT(8)
215 +#define BCM2835_DMA_S_WIDTH BIT(9)
216 +#define BCM2835_DMA_S_DREQ BIT(10)
218 +#define BCM2835_DMA_PER_MAP(x) ((x) << 16)
219 +#define BCM2835_DMA_WAITS(x) (((x)&0x1f) << 21)
221 +#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
223 +#define BCM2835_DMA_DATA_TYPE_S8 1
224 +#define BCM2835_DMA_DATA_TYPE_S16 2
225 +#define BCM2835_DMA_DATA_TYPE_S32 4
226 +#define BCM2835_DMA_DATA_TYPE_S128 16
228 +#define BCM2835_DMA_BULK_MASK BIT(0)
229 +#define BCM2835_DMA_FIQ_MASK (BIT(2) | BIT(3))
232 +/* Valid only for channels 0 - 14, 15 has its own base address */
233 +#define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
234 +#define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
236 +#define MAX_LITE_TRANSFER 32768
237 +#define MAX_NORMAL_TRANSFER 1073741824
239 +static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
241 + return container_of(d, struct bcm2835_dmadev, ddev);
244 +static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
246 + return container_of(c, struct bcm2835_chan, vc.chan);
249 +static inline struct bcm2835_desc *to_bcm2835_dma_desc(
250 + struct dma_async_tx_descriptor *t)
252 + return container_of(t, struct bcm2835_desc, vd.tx);
255 +static void dma_dumpregs(struct bcm2835_chan *c)
257 + pr_debug("-------------DMA DUMPREGS-------------\n");
258 + pr_debug("CS= %u\n",
259 + readl(c->chan_base + BCM2835_DMA_CS));
260 + pr_debug("ADDR= %u\n",
261 + readl(c->chan_base + BCM2835_DMA_ADDR));
262 + pr_debug("SOURCE_ADDR= %u\n",
263 + readl(c->chan_base + BCM2835_DMA_SOURCE_AD));
264 + pr_debug("DEST_AD= %u\n",
265 + readl(c->chan_base + BCM2835_DMA_DEST_AD));
266 + pr_debug("NEXTCB= %u\n",
267 + readl(c->chan_base + BCM2835_DMA_NEXTCB));
268 + pr_debug("--------------------------------------\n");
271 +static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
273 + struct bcm2835_desc *desc = container_of(vd, struct bcm2835_desc, vd);
274 + dma_free_coherent(desc->vd.tx.chan->device->dev,
275 + desc->control_block_size,
276 + desc->control_block_base,
277 + desc->control_block_base_phys);
281 +static int bcm2835_dma_abort(void __iomem *chan_base)
284 + long int timeout = 10000;
286 + cs = readl(chan_base + BCM2835_DMA_CS);
287 + if (!(cs & BCM2835_DMA_ACTIVE))
290 + /* Write 0 to the active bit - Pause the DMA */
291 + writel(0, chan_base + BCM2835_DMA_CS);
293 + /* Wait for any current AXI transfer to complete */
294 + while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) {
296 + cs = readl(chan_base + BCM2835_DMA_CS);
299 + /* We'll un-pause when we set of our next DMA */
303 + if (!(cs & BCM2835_DMA_ACTIVE))
306 + /* Terminate the control block chain */
307 + writel(0, chan_base + BCM2835_DMA_NEXTCB);
309 + /* Abort the whole DMA */
310 + writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE,
311 + chan_base + BCM2835_DMA_CS);
317 +static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
319 + struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
320 + struct bcm2835_desc *d;
327 + list_del(&vd->node);
329 + c->desc = d = to_bcm2835_dma_desc(&vd->tx);
331 + writel(d->control_block_base_phys, c->chan_base + BCM2835_DMA_ADDR);
332 + writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
336 +static irqreturn_t bcm2835_dma_callback(int irq, void *data)
338 + struct bcm2835_chan *c = data;
339 + struct bcm2835_desc *d;
340 + unsigned long flags;
342 + spin_lock_irqsave(&c->vc.lock, flags);
344 + /* Acknowledge interrupt */
345 + writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS);
351 + vchan_cyclic_callback(&d->vd);
353 + /* Keep the DMA engine running */
354 + writel(BCM2835_DMA_ACTIVE,
355 + c->chan_base + BCM2835_DMA_CS);
358 + vchan_cookie_complete(&c->desc->vd);
359 + bcm2835_dma_start_desc(c);
363 + spin_unlock_irqrestore(&c->vc.lock, flags);
365 + return IRQ_HANDLED;
368 +static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
370 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
373 + dev_dbg(c->vc.chan.device->dev,
374 + "Allocating DMA channel %d\n", c->ch);
376 + ret = request_irq(c->irq_number,
377 + bcm2835_dma_callback, 0, "DMA IRQ", c);
382 +static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
384 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
386 + vchan_free_chan_resources(&c->vc);
387 + free_irq(c->irq_number, c);
389 + dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
392 +static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
397 +static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
402 + for (size = i = 0; i < d->frames; i++) {
403 + struct bcm2835_dma_cb *control_block =
404 + &d->control_block_base[i];
405 + size_t this_size = control_block->length;
408 + if (d->dir == DMA_DEV_TO_MEM)
409 + dma = control_block->dst;
411 + dma = control_block->src;
415 + else if (addr >= dma && addr < dma + this_size)
416 + size += dma + this_size - addr;
422 +static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
423 + dma_cookie_t cookie, struct dma_tx_state *txstate)
425 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
426 + struct bcm2835_desc *d;
427 + struct virt_dma_desc *vd;
428 + enum dma_status ret;
429 + unsigned long flags;
432 + ret = dma_cookie_status(chan, cookie, txstate);
433 + if (ret == DMA_COMPLETE || !txstate)
436 + spin_lock_irqsave(&c->vc.lock, flags);
437 + vd = vchan_find_desc(&c->vc, cookie);
440 + bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
441 + } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
444 + if (d->dir == DMA_MEM_TO_DEV)
445 + pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
446 + else if (d->dir == DMA_DEV_TO_MEM)
447 + pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
451 + txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
453 + txstate->residue = 0;
456 + spin_unlock_irqrestore(&c->vc.lock, flags);
461 +static void bcm2835_dma_issue_pending(struct dma_chan *chan)
463 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
464 + unsigned long flags;
466 + spin_lock_irqsave(&c->vc.lock, flags);
467 + if (vchan_issue_pending(&c->vc) && !c->desc)
468 + bcm2835_dma_start_desc(c);
470 + spin_unlock_irqrestore(&c->vc.lock, flags);
473 +static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
474 + struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
475 + size_t period_len, enum dma_transfer_direction direction,
476 + unsigned long flags)
478 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
479 + enum dma_slave_buswidth dev_width;
480 + struct bcm2835_desc *d;
481 + dma_addr_t dev_addr;
482 + unsigned int es, sync_type;
483 + unsigned int frame, max_size;
485 + /* Grab configuration */
486 + if (!is_slave_direction(direction)) {
487 + dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
491 + if (direction == DMA_DEV_TO_MEM) {
492 + dev_addr = c->cfg.src_addr;
493 + dev_width = c->cfg.src_addr_width;
494 + sync_type = BCM2835_DMA_S_DREQ;
496 + dev_addr = c->cfg.dst_addr;
497 + dev_width = c->cfg.dst_addr_width;
498 + sync_type = BCM2835_DMA_D_DREQ;
501 + /* Bus width translates to the element size (ES) */
502 + switch (dev_width) {
503 + case DMA_SLAVE_BUSWIDTH_4_BYTES:
504 + es = BCM2835_DMA_DATA_TYPE_S32;
510 + /* Now allocate and setup the descriptor. */
511 + d = kzalloc(sizeof(*d), GFP_NOWAIT);
515 + d->dir = direction;
517 + if (c->ch >= 8) /* we have a LITE channel */
518 + max_size = MAX_LITE_TRANSFER;
520 + max_size = MAX_NORMAL_TRANSFER;
521 + period_len = min(period_len, max_size);
523 + d->frames = (buf_len-1) / period_len + 1;
525 + /* Allocate memory for control blocks */
526 + d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
527 + d->control_block_base = dma_zalloc_coherent(chan->device->dev,
528 + d->control_block_size, &d->control_block_base_phys,
531 + if (!d->control_block_base) {
537 + * Iterate over all frames, create a control block
538 + * for each frame and link them together.
540 + for (frame = 0; frame < d->frames; frame++) {
541 + struct bcm2835_dma_cb *control_block =
542 + &d->control_block_base[frame];
544 + /* Setup adresses */
545 + if (d->dir == DMA_DEV_TO_MEM) {
546 + control_block->info = BCM2835_DMA_D_INC;
547 + control_block->src = dev_addr;
548 + control_block->dst = buf_addr + frame * period_len;
550 + control_block->info = BCM2835_DMA_S_INC;
551 + control_block->src = buf_addr + frame * period_len;
552 + control_block->dst = dev_addr;
555 + /* Enable interrupt */
556 + control_block->info |= BCM2835_DMA_INT_EN;
558 + /* Setup synchronization */
559 + if (sync_type != 0)
560 + control_block->info |= sync_type;
562 + /* Setup DREQ channel */
563 + if (c->cfg.slave_id != 0)
564 + control_block->info |=
565 + BCM2835_DMA_PER_MAP(c->cfg.slave_id);
567 + /* Length of a frame */
568 + if (frame != d->frames-1)
569 + control_block->length = period_len;
571 + control_block->length = buf_len - (d->frames - 1) * period_len;
573 + d->size += control_block->length;
576 + * Next block is the next frame.
577 + * This function is called on cyclic DMA transfers.
578 + * Therefore, wrap around at number of frames.
580 + control_block->next = d->control_block_base_phys +
581 + sizeof(struct bcm2835_dma_cb)
582 + * ((frame + 1) % d->frames);
587 + return vchan_tx_prep(&c->vc, &d->vd, flags);
591 +static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
592 + struct dma_chan *chan, struct scatterlist *sgl,
593 + unsigned int sg_len, enum dma_transfer_direction direction,
594 + unsigned long flags, void *context)
596 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
597 + enum dma_slave_buswidth dev_width;
598 + struct bcm2835_desc *d;
599 + dma_addr_t dev_addr;
600 + struct scatterlist *sgent;
601 + unsigned int es, sync_type;
602 + unsigned int i, j, splitct, max_size;
604 + if (!is_slave_direction(direction)) {
605 + dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
609 + if (direction == DMA_DEV_TO_MEM) {
610 + dev_addr = c->cfg.src_addr;
611 + dev_width = c->cfg.src_addr_width;
612 + sync_type = BCM2835_DMA_S_DREQ;
614 + dev_addr = c->cfg.dst_addr;
615 + dev_width = c->cfg.dst_addr_width;
616 + sync_type = BCM2835_DMA_D_DREQ;
619 + /* Bus width translates to the element size (ES) */
620 + switch (dev_width) {
621 + case DMA_SLAVE_BUSWIDTH_4_BYTES:
622 + es = BCM2835_DMA_DATA_TYPE_S32;
628 + /* Now allocate and setup the descriptor. */
629 + d = kzalloc(sizeof(*d), GFP_NOWAIT);
633 + d->dir = direction;
635 + if (c->ch >= 8) /* we have a LITE channel */
636 + max_size = MAX_LITE_TRANSFER;
638 + max_size = MAX_NORMAL_TRANSFER;
640 + /* We store the length of the SG list in d->frames
641 + taking care to account for splitting up transfers
642 + too large for a LITE channel */
645 + for_each_sg(sgl, sgent, sg_len, i) {
646 + uint32_t len = sg_dma_len(sgent);
647 + d->frames += 1 + len / max_size;
650 + /* Allocate memory for control blocks */
651 + d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
652 + d->control_block_base = dma_zalloc_coherent(chan->device->dev,
653 + d->control_block_size, &d->control_block_base_phys,
656 + if (!d->control_block_base) {
662 + * Iterate over all SG entries, create a control block
663 + * for each frame and link them together.
666 + /* we count the number of times an SG entry had to be splitct
667 + as a result of using a LITE channel */
670 + for_each_sg(sgl, sgent, sg_len, i) {
671 + dma_addr_t addr = sg_dma_address(sgent);
672 + uint32_t len = sg_dma_len(sgent);
674 + for (j = 0; j < len; j += max_size) {
675 + struct bcm2835_dma_cb *control_block =
676 + &d->control_block_base[i+splitct];
678 + /* Setup adresses */
679 + if (d->dir == DMA_DEV_TO_MEM) {
680 + control_block->info = BCM2835_DMA_D_INC |
681 + BCM2835_DMA_D_WIDTH | BCM2835_DMA_S_DREQ;
682 + control_block->src = dev_addr;
683 + control_block->dst = addr + (dma_addr_t)j;
685 + control_block->info = BCM2835_DMA_S_INC |
686 + BCM2835_DMA_S_WIDTH | BCM2835_DMA_D_DREQ;
687 + control_block->src = addr + (dma_addr_t)j;
688 + control_block->dst = dev_addr;
692 + control_block->info |= BCM2835_DMA_WAITS(SDHCI_BCM_DMA_WAITS);
693 + control_block->info |= BCM2835_DMA_WAIT_RESP;
696 + if (i == sg_len-1 && len-j <= max_size)
697 + control_block->info |= BCM2835_DMA_INT_EN;
699 + /* Setup synchronization */
700 + if (sync_type != 0)
701 + control_block->info |= sync_type;
703 + /* Setup DREQ channel */
704 + c->dreq = c->cfg.slave_id; /* DREQ loaded from config */
707 + control_block->info |=
708 + BCM2835_DMA_PER_MAP(c->dreq);
710 + /* Length of a frame */
711 + control_block->length = min(len-j, max_size);
712 + d->size += control_block->length;
715 + * Next block is the next frame.
717 + if (i < sg_len-1 || len-j > max_size) {
718 + /* next block is the next frame. */
719 + control_block->next = d->control_block_base_phys +
720 + sizeof(struct bcm2835_dma_cb) * (i + splitct + 1);
722 + /* next block is empty. */
723 + control_block->next = 0;
726 + if (len-j > max_size)
733 + return vchan_tx_prep(&c->vc, &d->vd, flags);
736 +static int bcm2835_dma_slave_config(struct bcm2835_chan *c,
737 + struct dma_slave_config *cfg)
739 + if ((cfg->direction == DMA_DEV_TO_MEM &&
740 + cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
741 + (cfg->direction == DMA_MEM_TO_DEV &&
742 + cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) ||
743 + !is_slave_direction(cfg->direction)) {
752 +static int bcm2835_dma_terminate_all(struct bcm2835_chan *c)
754 + struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device);
755 + unsigned long flags;
756 + int timeout = 10000;
759 + spin_lock_irqsave(&c->vc.lock, flags);
761 + /* Prevent this channel being scheduled */
762 + spin_lock(&d->lock);
763 + list_del_init(&c->node);
764 + spin_unlock(&d->lock);
767 + * Stop DMA activity: we assume the callback will not be called
768 + * after bcm_dma_abort() returns (even if it does, it will see
769 + * c->desc is NULL and exit.)
773 + bcm2835_dma_abort(c->chan_base);
775 + /* Wait for stopping */
776 + while (--timeout) {
777 + if (!(readl(c->chan_base + BCM2835_DMA_CS) &
778 + BCM2835_DMA_ACTIVE))
785 + dev_err(d->ddev.dev, "DMA transfer could not be terminated\n");
788 + vchan_get_all_descriptors(&c->vc, &head);
789 + spin_unlock_irqrestore(&c->vc.lock, flags);
790 + vchan_dma_desc_free_list(&c->vc, &head);
795 +static int bcm2835_dma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
798 + struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
801 + case DMA_SLAVE_CONFIG:
802 + return bcm2835_dma_slave_config(c,
803 + (struct dma_slave_config *)arg);
805 + case DMA_TERMINATE_ALL:
806 + return bcm2835_dma_terminate_all(c);
814 +static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, int irq)
816 + struct bcm2835_chan *c;
818 + c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
822 + c->vc.desc_free = bcm2835_dma_desc_free;
823 + vchan_init(&c->vc, &d->ddev);
824 + INIT_LIST_HEAD(&c->node);
828 + c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
830 + c->irq_number = irq;
836 +static int bcm2708_dma_chan_init(struct bcm2835_dmadev *d,
837 + void __iomem *chan_base, int chan_id, int irq)
839 + struct bcm2835_chan *c;
841 + c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
845 + c->vc.desc_free = bcm2835_dma_desc_free;
846 + vchan_init(&c->vc, &d->ddev);
847 + INIT_LIST_HEAD(&c->node);
851 + c->chan_base = chan_base;
853 + c->irq_number = irq;
859 +static void bcm2835_dma_free(struct bcm2835_dmadev *od)
861 + struct bcm2835_chan *c, *next;
863 + list_for_each_entry_safe(c, next, &od->ddev.channels,
864 + vc.chan.device_node) {
865 + list_del(&c->vc.chan.device_node);
866 + tasklet_kill(&c->vc.task);
870 +static const struct of_device_id bcm2835_dma_of_match[] = {
871 + { .compatible = "brcm,bcm2835-dma", },
874 +MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
877 +static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
878 + struct of_dma *ofdma)
880 + struct bcm2835_dmadev *d = ofdma->of_dma_data;
881 + struct dma_chan *chan;
883 + chan = dma_get_any_slave_channel(&d->ddev);
887 + /* Set DREQ from param */
888 + to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
894 +static int bcm2835_dma_device_slave_caps(struct dma_chan *dchan,
895 + struct dma_slave_caps *caps)
897 + caps->src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
898 + caps->dstn_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
899 + caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
900 + caps->cmd_pause = false;
901 + caps->cmd_terminate = true;
906 +static int bcm2835_dma_probe(struct platform_device *pdev)
908 + struct bcm2835_dmadev *od;
910 + struct resource *res;
911 + void __iomem *base;
912 + uint32_t chans_available;
919 + if (!pdev->dev.dma_mask)
920 + pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
922 + /* If CONFIG_OF is selected, device tree is used */
923 + /* hence the difference between probing */
927 + rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
930 + dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
933 + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
937 + pdev->dev.dma_parms = &od->dma_parms;
938 + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
941 + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
942 + dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
943 + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
944 + od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
945 + od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
946 + od->ddev.device_tx_status = bcm2835_dma_tx_status;
947 + od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
948 + od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
949 + od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
950 + od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
951 + od->ddev.device_control = bcm2835_dma_control;
952 + od->ddev.dev = &pdev->dev;
953 + INIT_LIST_HEAD(&od->ddev.channels);
954 + spin_lock_init(&od->lock);
956 + platform_set_drvdata(pdev, od);
958 + for (i = 0; i < 5; i++) {
959 + void __iomem *chan_base;
962 + chan_id = bcm_dma_chan_alloc(BCM_DMA_FEATURE_LITE,
969 + rc = bcm2708_dma_chan_init(od, chan_base, chan_id, irq);
974 + rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
979 + od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
983 + pdev->dev.dma_parms = &od->dma_parms;
984 + dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
987 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
988 + base = devm_ioremap_resource(&pdev->dev, res);
990 + return PTR_ERR(base);
995 + dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
996 + dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
997 + dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
998 + od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
999 + od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
1000 + od->ddev.device_tx_status = bcm2835_dma_tx_status;
1001 + od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
1002 + od->ddev.device_slave_caps = bcm2835_dma_device_slave_caps;
1003 + od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
1004 + od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
1005 + od->ddev.device_control = bcm2835_dma_control;
1006 + od->ddev.dev = &pdev->dev;
1007 + INIT_LIST_HEAD(&od->ddev.channels);
1008 + spin_lock_init(&od->lock);
1010 + platform_set_drvdata(pdev, od);
1013 + /* Request DMA channel mask from device tree */
1014 + if (of_property_read_u32(pdev->dev.of_node,
1015 + "brcm,dma-channel-mask",
1016 + &chans_available)) {
1017 + dev_err(&pdev->dev, "Failed to get channel mask\n");
1024 + * Do not use the FIQ and BULK channels,
1025 + * because they are used by the GPU.
1027 + chans_available &= ~(BCM2835_DMA_FIQ_MASK | BCM2835_DMA_BULK_MASK);
1030 + for (i = 0; i < pdev->num_resources; i++) {
1031 + irq = platform_get_irq(pdev, i);
1035 + if (chans_available & (1 << i)) {
1036 + rc = bcm2835_dma_chan_init(od, i, irq);
1042 + dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
1044 + /* Device-tree DMA controller registration */
1045 + rc = of_dma_controller_register(pdev->dev.of_node,
1046 + bcm2835_dma_xlate, od);
1048 + dev_err(&pdev->dev, "Failed to register DMA controller\n");
1053 + rc = dma_async_device_register(&od->ddev);
1055 + dev_err(&pdev->dev,
1056 + "Failed to register slave DMA engine device: %d\n", rc);
1060 + dev_info(&pdev->dev, "Load BCM2835 DMA engine driver\n");
1065 + bcm2835_dma_free(od);
1069 +static int bcm2835_dma_remove(struct platform_device *pdev)
1071 + struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
1073 + dma_async_device_unregister(&od->ddev);
1074 + bcm2835_dma_free(od);
1082 +static struct platform_driver bcm2835_dma_driver = {
1083 + .probe = bcm2835_dma_probe,
1084 + .remove = bcm2835_dma_remove,
1086 + .name = "bcm2708-dmaengine",
1087 + .owner = THIS_MODULE,
1091 +static struct platform_device *pdev;
1093 +static const struct platform_device_info bcm2835_dma_dev_info = {
1094 + .name = "bcm2708-dmaengine",
1098 +static int bcm2835_dma_init(void)
1100 + int rc = platform_driver_register(&bcm2835_dma_driver);
1103 + pdev = platform_device_register_full(&bcm2835_dma_dev_info);
1104 + if (IS_ERR(pdev)) {
1105 + platform_driver_unregister(&bcm2835_dma_driver);
1106 + rc = PTR_ERR(pdev);
1112 +module_init(bcm2835_dma_init); /* preferable to subsys_initcall */
1114 +static void __exit bcm2835_dma_exit(void)
1116 + platform_device_unregister(pdev);
1117 + platform_driver_unregister(&bcm2835_dma_driver);
1119 +module_exit(bcm2835_dma_exit);
1123 +static struct platform_driver bcm2835_dma_driver = {
1124 + .probe = bcm2835_dma_probe,
1125 + .remove = bcm2835_dma_remove,
1127 + .name = "bcm2835-dma",
1128 + .owner = THIS_MODULE,
1129 + .of_match_table = of_match_ptr(bcm2835_dma_of_match),
1133 +module_platform_driver(bcm2835_dma_driver);
1137 +MODULE_ALIAS("platform:bcm2835-dma");
1138 +MODULE_DESCRIPTION("BCM2835 DMA engine driver");
1139 +MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
1140 +MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
1141 +MODULE_LICENSE("GPL v2");