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[openwrt/staging/wigyori.git] / target / linux / brcm2708 / patches-4.4 / 0027-Main-bcm2708-bcm2709-linux-port.patch
1 From 20ae9d488adbe06ef257b7920fab756063e2cf38 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH] Main bcm2708/bcm2709 linux port
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 Signed-off-by: popcornmix <popcornmix@gmail.com>
10 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
11 ---
12 arch/arm/Kconfig | 49 +++
13 arch/arm/Kconfig.debug | 8 +
14 arch/arm/Makefile | 2 +
15 arch/arm/kernel/head.S | 8 +
16 arch/arm/kernel/process.c | 10 +
17 arch/arm/mach-bcm2708/Kconfig | 23 ++
18 arch/arm/mach-bcm2708/Makefile | 5 +
19 arch/arm/mach-bcm2708/Makefile.boot | 3 +
20 arch/arm/mach-bcm2708/bcm2708.c | 231 ++++++++++++
21 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 ++
22 arch/arm/mach-bcm2708/include/mach/io.h | 27 ++
23 arch/arm/mach-bcm2708/include/mach/memory.h | 57 +++
24 arch/arm/mach-bcm2708/include/mach/platform.h | 112 ++++++
25 arch/arm/mach-bcm2708/include/mach/system.h | 37 ++
26 arch/arm/mach-bcm2708/include/mach/uncompress.h | 84 +++++
27 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 ++
28 arch/arm/mach-bcm2709/Kconfig | 16 +
29 arch/arm/mach-bcm2709/Makefile | 5 +
30 arch/arm/mach-bcm2709/Makefile.boot | 3 +
31 arch/arm/mach-bcm2709/bcm2709.c | 380 ++++++++++++++++++++
32 arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 ++
33 arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 +++++++
34 arch/arm/mach-bcm2709/include/mach/io.h | 27 ++
35 arch/arm/mach-bcm2709/include/mach/memory.h | 57 +++
36 arch/arm/mach-bcm2709/include/mach/platform.h | 188 ++++++++++
37 arch/arm/mach-bcm2709/include/mach/system.h | 37 ++
38 arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 +++++
39 arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 ++
40 arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 ++
41 arch/arm/mach-bcm2709/vc_mem.c | 431 +++++++++++++++++++++++
42 arch/arm/mm/Kconfig | 2 +-
43 arch/arm/mm/proc-v6.S | 15 +-
44 arch/arm/mm/proc-v7.S | 1 +
45 arch/arm/tools/mach-types | 2 +
46 drivers/clocksource/Makefile | 2 +-
47 drivers/irqchip/Makefile | 3 +
48 include/linux/mmc/host.h | 1 +
49 37 files changed, 2147 insertions(+), 5 deletions(-)
50 create mode 100644 arch/arm/mach-bcm2708/Kconfig
51 create mode 100644 arch/arm/mach-bcm2708/Makefile
52 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
53 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
54 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
55 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
56 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
57 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
58 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
59 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
60 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
61 create mode 100644 arch/arm/mach-bcm2709/Kconfig
62 create mode 100644 arch/arm/mach-bcm2709/Makefile
63 create mode 100644 arch/arm/mach-bcm2709/Makefile.boot
64 create mode 100644 arch/arm/mach-bcm2709/bcm2709.c
65 create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S
66 create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S
67 create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h
68 create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h
69 create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h
70 create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h
71 create mode 100644 arch/arm/mach-bcm2709/include/mach/uncompress.h
72 create mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h
73 create mode 100644 arch/arm/mach-bcm2709/include/mach/vmalloc.h
74 create mode 100644 arch/arm/mach-bcm2709/vc_mem.c
75
76 --- a/arch/arm/Kconfig
77 +++ b/arch/arm/Kconfig
78 @@ -318,6 +318,52 @@ choice
79 default ARCH_VERSATILE if !MMU
80 default ARCH_MULTIPLATFORM if MMU
81
82 +config ARCH_BCM2708
83 + bool "Broadcom BCM2708 family"
84 + select CPU_V6
85 + select ARM_AMBA
86 + select CLKSRC_MMIO
87 + select CLKSRC_OF if OF
88 + select HAVE_SCHED_CLOCK
89 + select NEED_MACH_GPIO_H
90 + select NEED_MACH_MEMORY_H
91 + select COMMON_CLK
92 + select ARCH_HAS_CPUFREQ
93 + select GENERIC_CLOCKEVENTS
94 + select ARM_ERRATA_411920
95 + select MACH_BCM2708
96 + select MULTI_IRQ_HANDLER
97 + select SPARSE_IRQ
98 + select VC4
99 + select FIQ
100 + help
101 + This enables support for Broadcom BCM2708 boards.
102 +
103 +config ARCH_BCM2709
104 + bool "Broadcom BCM2709 family"
105 + select CPU_V7
106 + select HAVE_SMP
107 + select ARM_AMBA
108 + select MIGHT_HAVE_CACHE_L2X0
109 + select HAVE_SCHED_CLOCK
110 + select NEED_MACH_MEMORY_H
111 + select NEED_MACH_IO_H
112 + select COMMON_CLK
113 + select ARCH_HAS_CPUFREQ
114 + select GENERIC_CLOCKEVENTS
115 + select MACH_BCM2709
116 + select MULTI_IRQ_HANDLER
117 + select SPARSE_IRQ
118 + select MFD_SYSCON
119 + select VC4
120 + select FIQ
121 + select USE_OF
122 + select ARCH_REQUIRE_GPIOLIB
123 + select PINCTRL
124 + select PINCTRL_BCM2835
125 + help
126 + This enables support for Broadcom BCM2709 boards.
127 +
128 config ARCH_MULTIPLATFORM
129 bool "Allow multiple platforms to be selected"
130 depends on MMU
131 @@ -809,6 +855,9 @@ config ARCH_VIRT
132 # Kconfigs may be included either alphabetically (according to the
133 # plat- suffix) or along side the corresponding mach-* source.
134 #
135 +source "arch/arm/mach-bcm2708/Kconfig"
136 +source "arch/arm/mach-bcm2709/Kconfig"
137 +
138 source "arch/arm/mach-mvebu/Kconfig"
139
140 source "arch/arm/mach-alpine/Kconfig"
141 --- a/arch/arm/Kconfig.debug
142 +++ b/arch/arm/Kconfig.debug
143 @@ -1240,6 +1240,14 @@ choice
144 options; the platform specific options are deprecated
145 and will be soon removed.
146
147 + config DEBUG_BCM2708_UART0
148 + bool "Broadcom BCM270X UART0 (PL011)"
149 + depends on ARCH_BCM2708 || ARCH_BCM2709
150 + help
151 + Say Y here if you want the debug print routines to direct
152 + their output to UART 0. The port must have been initialised
153 + by the boot-loader before use.
154 +
155 endchoice
156
157 config DEBUG_EXYNOS_UART
158 --- a/arch/arm/Makefile
159 +++ b/arch/arm/Makefile
160 @@ -159,6 +159,8 @@ textofs-$(CONFIG_ARCH_AXXIA) := 0x003080
161
162 # Machine directory name. This list is sorted alphanumerically
163 # by CONFIG_* macro name.
164 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
165 +machine-$(CONFIG_ARCH_BCM2709) += bcm2709
166 machine-$(CONFIG_ARCH_ALPINE) += alpine
167 machine-$(CONFIG_ARCH_AT91) += at91
168 machine-$(CONFIG_ARCH_AXXIA) += axxia
169 --- a/arch/arm/kernel/head.S
170 +++ b/arch/arm/kernel/head.S
171 @@ -700,6 +700,14 @@ ARM_BE8(rev16 ip, ip)
172 ldrcc r7, [r4], #4 @ use branch for delay slot
173 bcc 1b
174 ret lr
175 + nop
176 + nop
177 + nop
178 + nop
179 + nop
180 + nop
181 + nop
182 + nop
183 #endif
184 ENDPROC(__fixup_a_pv_table)
185
186 --- a/arch/arm/kernel/process.c
187 +++ b/arch/arm/kernel/process.c
188 @@ -91,6 +91,16 @@ void arch_cpu_idle_exit(void)
189 ledtrig_cpu(CPU_LED_IDLE_END);
190 }
191
192 +char bcm2708_reboot_mode = 'h';
193 +
194 +int __init reboot_setup(char *str)
195 +{
196 + bcm2708_reboot_mode = str[0];
197 + return 1;
198 +}
199 +
200 +__setup("reboot=", reboot_setup);
201 +
202 void __show_regs(struct pt_regs *regs)
203 {
204 unsigned long flags;
205 --- /dev/null
206 +++ b/arch/arm/mach-bcm2708/Kconfig
207 @@ -0,0 +1,23 @@
208 +menu "Broadcom BCM2708 Implementations"
209 + depends on ARCH_BCM2708
210 +
211 +config MACH_BCM2708
212 + bool "Broadcom BCM2708 Development Platform"
213 + select NEED_MACH_MEMORY_H
214 + select NEED_MACH_IO_H
215 + select CPU_V6
216 + select USE_OF
217 + select ARCH_REQUIRE_GPIOLIB
218 + select PINCTRL
219 + select PINCTRL_BCM2835
220 + help
221 + Include support for the Broadcom(R) BCM2708 platform.
222 +
223 +config BCM2708_NOL2CACHE
224 + bool "Videocore L2 cache disable"
225 + depends on MACH_BCM2708
226 + default n
227 + help
228 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
229 +
230 +endmenu
231 --- /dev/null
232 +++ b/arch/arm/mach-bcm2708/Makefile
233 @@ -0,0 +1,5 @@
234 +#
235 +# Makefile for the linux kernel.
236 +#
237 +
238 +obj-$(CONFIG_MACH_BCM2708) += bcm2708.o
239 --- /dev/null
240 +++ b/arch/arm/mach-bcm2708/Makefile.boot
241 @@ -0,0 +1,3 @@
242 + zreladdr-y := 0x00008000
243 +params_phys-y := 0x00000100
244 +initrd_phys-y := 0x00800000
245 --- /dev/null
246 +++ b/arch/arm/mach-bcm2708/bcm2708.c
247 @@ -0,0 +1,231 @@
248 +/*
249 + * linux/arch/arm/mach-bcm2708/bcm2708.c
250 + *
251 + * Copyright (C) 2010 Broadcom
252 + *
253 + * This program is free software; you can redistribute it and/or modify
254 + * it under the terms of the GNU General Public License as published by
255 + * the Free Software Foundation; either version 2 of the License, or
256 + * (at your option) any later version.
257 + *
258 + * This program is distributed in the hope that it will be useful,
259 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
260 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
261 + * GNU General Public License for more details.
262 + *
263 + * You should have received a copy of the GNU General Public License
264 + * along with this program; if not, write to the Free Software
265 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
266 + */
267 +
268 +#include <linux/init.h>
269 +#include <linux/dma-mapping.h>
270 +#include <linux/module.h>
271 +#include <linux/of_platform.h>
272 +#include <asm/system_info.h>
273 +#include <asm/mach-types.h>
274 +#include <asm/mach/arch.h>
275 +#include <asm/mach/map.h>
276 +
277 +#include <mach/system.h>
278 +
279 +#include <linux/broadcom/vc_cma.h>
280 +
281 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
282 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
283 + * represent this window by setting our dmamasks to 26 bits but, in fact
284 + * we're not going to use addresses outside this range (they're not in real
285 + * memory) so we don't bother.
286 + *
287 + * In the future we might include code to use this IOMMU to remap other
288 + * physical addresses onto VideoCore memory then the use of 32-bits would be
289 + * more legitimate.
290 + */
291 +
292 +/* command line parameters */
293 +static unsigned boardrev, serial;
294 +static unsigned reboot_part = 0;
295 +
296 +static struct map_desc bcm2708_io_desc[] __initdata = {
297 + {
298 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
299 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
300 + .length = SZ_4K,
301 + .type = MT_DEVICE},
302 + {
303 + .virtual = IO_ADDRESS(UART0_BASE),
304 + .pfn = __phys_to_pfn(UART0_BASE),
305 + .length = SZ_4K,
306 + .type = MT_DEVICE},
307 + {
308 + .virtual = IO_ADDRESS(UART1_BASE),
309 + .pfn = __phys_to_pfn(UART1_BASE),
310 + .length = SZ_4K,
311 + .type = MT_DEVICE},
312 + {
313 + .virtual = IO_ADDRESS(DMA_BASE),
314 + .pfn = __phys_to_pfn(DMA_BASE),
315 + .length = SZ_4K,
316 + .type = MT_DEVICE},
317 + {
318 + .virtual = IO_ADDRESS(MCORE_BASE),
319 + .pfn = __phys_to_pfn(MCORE_BASE),
320 + .length = SZ_4K,
321 + .type = MT_DEVICE},
322 + {
323 + .virtual = IO_ADDRESS(ST_BASE),
324 + .pfn = __phys_to_pfn(ST_BASE),
325 + .length = SZ_4K,
326 + .type = MT_DEVICE},
327 + {
328 + .virtual = IO_ADDRESS(USB_BASE),
329 + .pfn = __phys_to_pfn(USB_BASE),
330 + .length = SZ_128K,
331 + .type = MT_DEVICE},
332 + {
333 + .virtual = IO_ADDRESS(PM_BASE),
334 + .pfn = __phys_to_pfn(PM_BASE),
335 + .length = SZ_4K,
336 + .type = MT_DEVICE},
337 + {
338 + .virtual = IO_ADDRESS(GPIO_BASE),
339 + .pfn = __phys_to_pfn(GPIO_BASE),
340 + .length = SZ_4K,
341 + .type = MT_DEVICE}
342 +};
343 +
344 +void __init bcm2708_map_io(void)
345 +{
346 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
347 +}
348 +
349 +int calc_rsts(int partition)
350 +{
351 + return PM_PASSWORD |
352 + ((partition & (1 << 0)) << 0) |
353 + ((partition & (1 << 1)) << 1) |
354 + ((partition & (1 << 2)) << 2) |
355 + ((partition & (1 << 3)) << 3) |
356 + ((partition & (1 << 4)) << 4) |
357 + ((partition & (1 << 5)) << 5);
358 +}
359 +
360 +static void bcm2708_restart(enum reboot_mode mode, const char *cmd)
361 +{
362 + extern char bcm2708_reboot_mode;
363 + uint32_t pm_rstc, pm_wdog;
364 + uint32_t timeout = 10;
365 + uint32_t pm_rsts = 0;
366 +
367 + if(bcm2708_reboot_mode == 'q')
368 + {
369 + // NOOBS < 1.3 booting with reboot=q
370 + pm_rsts = readl(__io_address(PM_RSTS));
371 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
372 + }
373 + else if(bcm2708_reboot_mode == 'p')
374 + {
375 + // NOOBS < 1.3 halting
376 + pm_rsts = readl(__io_address(PM_RSTS));
377 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
378 + }
379 + else
380 + {
381 + pm_rsts = calc_rsts(reboot_part);
382 + }
383 +
384 + writel(pm_rsts, __io_address(PM_RSTS));
385 +
386 + /* Setup watchdog for reset */
387 + pm_rstc = readl(__io_address(PM_RSTC));
388 +
389 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
390 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
391 +
392 + writel(pm_wdog, __io_address(PM_WDOG));
393 + writel(pm_rstc, __io_address(PM_RSTC));
394 +}
395 +
396 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
397 +static void bcm2708_power_off(void)
398 +{
399 + extern char bcm2708_reboot_mode;
400 + if(bcm2708_reboot_mode == 'q')
401 + {
402 + // NOOBS < v1.3
403 + bcm2708_restart('p', "");
404 + }
405 + else
406 + {
407 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
408 + reboot_part = 63;
409 + /* continue with normal reset mechanism */
410 + bcm2708_restart(0, "");
411 + }
412 +}
413 +
414 +static void __init bcm2708_init_uart1(void)
415 +{
416 + struct device_node *np;
417 +
418 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
419 + if (of_device_is_available(np)) {
420 + pr_info("bcm2708: Mini UART enabled\n");
421 + writel(1, __io_address(UART1_BASE + 0x4));
422 + }
423 +}
424 +
425 +void __init bcm2708_init(void)
426 +{
427 + int ret;
428 +
429 + vc_cma_early_init();
430 +
431 + pm_power_off = bcm2708_power_off;
432 +
433 + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
434 + NULL);
435 + if (ret) {
436 + pr_err("of_platform_populate failed: %d\n", ret);
437 + BUG();
438 + }
439 +
440 + bcm2708_init_uart1();
441 +
442 + system_rev = boardrev;
443 + system_serial_low = serial;
444 +}
445 +
446 +void __init bcm2708_init_early(void)
447 +{
448 + /*
449 + * Some devices allocate their coherent buffers from atomic
450 + * context. Increase size of atomic coherent pool to make sure such
451 + * the allocations won't fail.
452 + */
453 + init_dma_coherent_pool_size(SZ_4M);
454 +}
455 +
456 +static void __init board_reserve(void)
457 +{
458 + vc_cma_reserve();
459 +}
460 +
461 +static const char * const bcm2708_compat[] = {
462 + "brcm,bcm2708",
463 + NULL
464 +};
465 +
466 +MACHINE_START(BCM2708, "BCM2708")
467 + /* Maintainer: Broadcom Europe Ltd. */
468 + .map_io = bcm2708_map_io,
469 + .init_machine = bcm2708_init,
470 + .init_early = bcm2708_init_early,
471 + .reserve = board_reserve,
472 + .restart = bcm2708_restart,
473 + .dt_compat = bcm2708_compat,
474 +MACHINE_END
475 +
476 +module_param(boardrev, uint, 0644);
477 +module_param(serial, uint, 0644);
478 +module_param(reboot_part, uint, 0644);
479 --- /dev/null
480 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
481 @@ -0,0 +1,22 @@
482 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
483 + *
484 + * Debugging macro include header
485 + *
486 + * Copyright (C) 2010 Broadcom
487 + * Copyright (C) 1994-1999 Russell King
488 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
489 + *
490 + * This program is free software; you can redistribute it and/or modify
491 + * it under the terms of the GNU General Public License version 2 as
492 + * published by the Free Software Foundation.
493 + *
494 +*/
495 +
496 +#include <mach/platform.h>
497 +
498 + .macro addruart, rp, rv, tmp
499 + ldr \rp, =UART0_BASE
500 + ldr \rv, =IO_ADDRESS(UART0_BASE)
501 + .endm
502 +
503 +#include <debug/pl01x.S>
504 --- /dev/null
505 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
506 @@ -0,0 +1,27 @@
507 +/*
508 + * arch/arm/mach-bcm2708/include/mach/io.h
509 + *
510 + * Copyright (C) 2003 ARM Limited
511 + *
512 + * This program is free software; you can redistribute it and/or modify
513 + * it under the terms of the GNU General Public License as published by
514 + * the Free Software Foundation; either version 2 of the License, or
515 + * (at your option) any later version.
516 + *
517 + * This program is distributed in the hope that it will be useful,
518 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
519 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
520 + * GNU General Public License for more details.
521 + *
522 + * You should have received a copy of the GNU General Public License
523 + * along with this program; if not, write to the Free Software
524 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
525 + */
526 +#ifndef __ASM_ARM_ARCH_IO_H
527 +#define __ASM_ARM_ARCH_IO_H
528 +
529 +#define IO_SPACE_LIMIT 0xffffffff
530 +
531 +#define __io(a) __typesafe_io(a)
532 +
533 +#endif
534 --- /dev/null
535 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
536 @@ -0,0 +1,57 @@
537 +/*
538 + * arch/arm/mach-bcm2708/include/mach/memory.h
539 + *
540 + * Copyright (C) 2010 Broadcom
541 + *
542 + * This program is free software; you can redistribute it and/or modify
543 + * it under the terms of the GNU General Public License as published by
544 + * the Free Software Foundation; either version 2 of the License, or
545 + * (at your option) any later version.
546 + *
547 + * This program is distributed in the hope that it will be useful,
548 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
549 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
550 + * GNU General Public License for more details.
551 + *
552 + * You should have received a copy of the GNU General Public License
553 + * along with this program; if not, write to the Free Software
554 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
555 + */
556 +#ifndef __ASM_ARCH_MEMORY_H
557 +#define __ASM_ARCH_MEMORY_H
558 +
559 +/* Memory overview:
560 +
561 + [ARMcore] <--virtual addr-->
562 + [ARMmmu] <--physical addr-->
563 + [GERTmap] <--bus add-->
564 + [VCperiph]
565 +
566 +*/
567 +
568 +/*
569 + * Physical DRAM offset.
570 + */
571 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
572 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
573 +
574 +#ifdef CONFIG_BCM2708_NOL2CACHE
575 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
576 +#else
577 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
578 +#endif
579 +
580 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
581 + * will provide the offset into this area as well as setting the bits that
582 + * stop the L1 and L2 cache from being used
583 + *
584 + * WARNING: this only works because the ARM is given memory at a fixed location
585 + * (ARMMEM_OFFSET)
586 + */
587 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
588 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
589 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
590 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
591 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
592 +
593 +#endif
594 --- /dev/null
595 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
596 @@ -0,0 +1,112 @@
597 +/*
598 + * arch/arm/mach-bcm2708/include/mach/platform.h
599 + *
600 + * Copyright (C) 2010 Broadcom
601 + *
602 + * This program is free software; you can redistribute it and/or modify
603 + * it under the terms of the GNU General Public License as published by
604 + * the Free Software Foundation; either version 2 of the License, or
605 + * (at your option) any later version.
606 + *
607 + * This program is distributed in the hope that it will be useful,
608 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
609 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
610 + * GNU General Public License for more details.
611 + *
612 + * You should have received a copy of the GNU General Public License
613 + * along with this program; if not, write to the Free Software
614 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
615 + */
616 +
617 +#ifndef _BCM2708_PLATFORM_H
618 +#define _BCM2708_PLATFORM_H
619 +
620 +
621 +/* macros to get at IO space when running virtually */
622 +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
623 +
624 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
625 +
626 +
627 +/*
628 + * SDRAM
629 + */
630 +#define BCM2708_SDRAM_BASE 0x00000000
631 +
632 +/*
633 + * Logic expansion modules
634 + *
635 + */
636 +
637 +
638 +/* ------------------------------------------------------------------------
639 + * BCM2708 ARMCTRL Registers
640 + * ------------------------------------------------------------------------
641 + */
642 +
643 +#define HW_REGISTER_RW(addr) (addr)
644 +#define HW_REGISTER_RO(addr) (addr)
645 +
646 +/*
647 + * Definitions and addresses for the ARM CONTROL logic
648 + * This file is manually generated.
649 + */
650 +
651 +#define BCM2708_PERI_BASE 0x20000000
652 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
653 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
654 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
655 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
656 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
657 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
658 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
659 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
660 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
661 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
662 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
663 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
664 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
665 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
666 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
667 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
668 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
669 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
670 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
671 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
672 +
673 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
674 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
675 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
676 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
677 +
678 +/*
679 + * Watchdog
680 + */
681 +#define PM_RSTC (PM_BASE+0x1c)
682 +#define PM_RSTS (PM_BASE+0x20)
683 +#define PM_WDOG (PM_BASE+0x24)
684 +
685 +#define PM_WDOG_RESET 0000000000
686 +#define PM_PASSWORD 0x5a000000
687 +#define PM_WDOG_TIME_SET 0x000fffff
688 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
689 +#define PM_RSTC_WRCFG_SET 0x00000030
690 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
691 +#define PM_RSTC_RESET 0x00000102
692 +
693 +#define PM_RSTS_HADPOR_SET 0x00001000
694 +#define PM_RSTS_HADSRH_SET 0x00000400
695 +#define PM_RSTS_HADSRF_SET 0x00000200
696 +#define PM_RSTS_HADSRQ_SET 0x00000100
697 +#define PM_RSTS_HADWRH_SET 0x00000040
698 +#define PM_RSTS_HADWRF_SET 0x00000020
699 +#define PM_RSTS_HADWRQ_SET 0x00000010
700 +#define PM_RSTS_HADDRH_SET 0x00000004
701 +#define PM_RSTS_HADDRF_SET 0x00000002
702 +#define PM_RSTS_HADDRQ_SET 0x00000001
703 +
704 +#define UART0_CLOCK 3000000
705 +
706 +#endif
707 +
708 +/* END */
709 --- /dev/null
710 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
711 @@ -0,0 +1,37 @@
712 +/*
713 + * arch/arm/mach-bcm2708/include/mach/system.h
714 + *
715 + * Copyright (C) 2010 Broadcom
716 + * Copyright (C) 2003 ARM Limited
717 + * Copyright (C) 2000 Deep Blue Solutions Ltd
718 + *
719 + * This program is free software; you can redistribute it and/or modify
720 + * it under the terms of the GNU General Public License as published by
721 + * the Free Software Foundation; either version 2 of the License, or
722 + * (at your option) any later version.
723 + *
724 + * This program is distributed in the hope that it will be useful,
725 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
726 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
727 + * GNU General Public License for more details.
728 + *
729 + * You should have received a copy of the GNU General Public License
730 + * along with this program; if not, write to the Free Software
731 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
732 + */
733 +#ifndef __ASM_ARCH_SYSTEM_H
734 +#define __ASM_ARCH_SYSTEM_H
735 +
736 +#include <linux/io.h>
737 +#include <mach/platform.h>
738 +
739 +static inline void arch_idle(void)
740 +{
741 + /*
742 + * This should do all the clock switching
743 + * and wait for interrupt tricks
744 + */
745 + cpu_do_idle();
746 +}
747 +
748 +#endif
749 --- /dev/null
750 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
751 @@ -0,0 +1,84 @@
752 +/*
753 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
754 + *
755 + * Copyright (C) 2010 Broadcom
756 + * Copyright (C) 2003 ARM Limited
757 + *
758 + * This program is free software; you can redistribute it and/or modify
759 + * it under the terms of the GNU General Public License as published by
760 + * the Free Software Foundation; either version 2 of the License, or
761 + * (at your option) any later version.
762 + *
763 + * This program is distributed in the hope that it will be useful,
764 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
765 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
766 + * GNU General Public License for more details.
767 + *
768 + * You should have received a copy of the GNU General Public License
769 + * along with this program; if not, write to the Free Software
770 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
771 + */
772 +
773 +#include <linux/io.h>
774 +#include <linux/amba/serial.h>
775 +#include <mach/platform.h>
776 +
777 +#define UART_BAUD 115200
778 +
779 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
780 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
781 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
782 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
783 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
784 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
785 +
786 +/*
787 + * This does not append a newline
788 + */
789 +static inline void putc(int c)
790 +{
791 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
792 + barrier();
793 +
794 + __raw_writel(c, BCM2708_UART_DR);
795 +}
796 +
797 +static inline void flush(void)
798 +{
799 + int fr;
800 +
801 + do {
802 + fr = __raw_readl(BCM2708_UART_FR);
803 + barrier();
804 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
805 +}
806 +
807 +static inline void arch_decomp_setup(void)
808 +{
809 + int temp, div, rem, frac;
810 +
811 + temp = 16 * UART_BAUD;
812 + div = UART0_CLOCK / temp;
813 + rem = UART0_CLOCK % temp;
814 + temp = (8 * rem) / UART_BAUD;
815 + frac = (temp >> 1) + (temp & 1);
816 +
817 + /* Make sure the UART is disabled before we start */
818 + __raw_writel(0, BCM2708_UART_CR);
819 +
820 + /* Set the baud rate */
821 + __raw_writel(div, BCM2708_UART_IBRD);
822 + __raw_writel(frac, BCM2708_UART_FBRD);
823 +
824 + /* Set the UART to 8n1, FIFO enabled */
825 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
826 +
827 + /* Enable the UART */
828 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
829 + BCM2708_UART_CR);
830 +}
831 +
832 +/*
833 + * nothing to do
834 + */
835 +#define arch_decomp_wdog()
836 --- /dev/null
837 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
838 @@ -0,0 +1,20 @@
839 +/*
840 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
841 + *
842 + * Copyright (C) 2010 Broadcom
843 + *
844 + * This program is free software; you can redistribute it and/or modify
845 + * it under the terms of the GNU General Public License as published by
846 + * the Free Software Foundation; either version 2 of the License, or
847 + * (at your option) any later version.
848 + *
849 + * This program is distributed in the hope that it will be useful,
850 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
851 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
852 + * GNU General Public License for more details.
853 + *
854 + * You should have received a copy of the GNU General Public License
855 + * along with this program; if not, write to the Free Software
856 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
857 + */
858 +#define VMALLOC_END (0xe8000000)
859 --- /dev/null
860 +++ b/arch/arm/mach-bcm2709/Kconfig
861 @@ -0,0 +1,16 @@
862 +menu "Broadcom BCM2709 Implementations"
863 + depends on ARCH_BCM2709
864 +
865 +config MACH_BCM2709
866 + bool "Broadcom BCM2709 Development Platform"
867 + help
868 + Include support for the Broadcom(R) BCM2709 platform.
869 +
870 +config BCM2708_NOL2CACHE
871 + bool "Videocore L2 cache disable"
872 + depends on MACH_BCM2709
873 + default y
874 + help
875 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
876 +
877 +endmenu
878 --- /dev/null
879 +++ b/arch/arm/mach-bcm2709/Makefile
880 @@ -0,0 +1,5 @@
881 +#
882 +# Makefile for the linux kernel.
883 +#
884 +
885 +obj-$(CONFIG_MACH_BCM2709) += bcm2709.o
886 --- /dev/null
887 +++ b/arch/arm/mach-bcm2709/Makefile.boot
888 @@ -0,0 +1,3 @@
889 + zreladdr-y := 0x00008000
890 +params_phys-y := 0x00000100
891 +initrd_phys-y := 0x00800000
892 --- /dev/null
893 +++ b/arch/arm/mach-bcm2709/bcm2709.c
894 @@ -0,0 +1,380 @@
895 +/*
896 + * linux/arch/arm/mach-bcm2709/bcm2709.c
897 + *
898 + * Copyright (C) 2010 Broadcom
899 + *
900 + * This program is free software; you can redistribute it and/or modify
901 + * it under the terms of the GNU General Public License as published by
902 + * the Free Software Foundation; either version 2 of the License, or
903 + * (at your option) any later version.
904 + *
905 + * This program is distributed in the hope that it will be useful,
906 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
907 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
908 + * GNU General Public License for more details.
909 + *
910 + * You should have received a copy of the GNU General Public License
911 + * along with this program; if not, write to the Free Software
912 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
913 + */
914 +
915 +#include <linux/init.h>
916 +#include <linux/dma-mapping.h>
917 +#include <linux/interrupt.h>
918 +#include <linux/clk-provider.h>
919 +#include <linux/clocksource.h>
920 +#include <linux/io.h>
921 +#include <linux/module.h>
922 +#include <linux/of_platform.h>
923 +
924 +#include <asm/system_info.h>
925 +#include <asm/mach-types.h>
926 +#include <asm/cputype.h>
927 +
928 +#include <asm/mach/arch.h>
929 +#include <asm/mach/map.h>
930 +
931 +#include <mach/system.h>
932 +
933 +#include <linux/broadcom/vc_cma.h>
934 +
935 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
936 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
937 + * represent this window by setting our dmamasks to 26 bits but, in fact
938 + * we're not going to use addresses outside this range (they're not in real
939 + * memory) so we don't bother.
940 + *
941 + * In the future we might include code to use this IOMMU to remap other
942 + * physical addresses onto VideoCore memory then the use of 32-bits would be
943 + * more legitimate.
944 + */
945 +
946 +/* command line parameters */
947 +static unsigned boardrev, serial;
948 +static unsigned reboot_part = 0;
949 +
950 +static struct map_desc bcm2709_io_desc[] __initdata = {
951 + {
952 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
953 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
954 + .length = SZ_4K,
955 + .type = MT_DEVICE},
956 + {
957 + .virtual = IO_ADDRESS(UART0_BASE),
958 + .pfn = __phys_to_pfn(UART0_BASE),
959 + .length = SZ_4K,
960 + .type = MT_DEVICE},
961 + {
962 + .virtual = IO_ADDRESS(UART1_BASE),
963 + .pfn = __phys_to_pfn(UART1_BASE),
964 + .length = SZ_4K,
965 + .type = MT_DEVICE},
966 + {
967 + .virtual = IO_ADDRESS(DMA_BASE),
968 + .pfn = __phys_to_pfn(DMA_BASE),
969 + .length = SZ_4K,
970 + .type = MT_DEVICE},
971 + {
972 + .virtual = IO_ADDRESS(MCORE_BASE),
973 + .pfn = __phys_to_pfn(MCORE_BASE),
974 + .length = SZ_4K,
975 + .type = MT_DEVICE},
976 + {
977 + .virtual = IO_ADDRESS(ST_BASE),
978 + .pfn = __phys_to_pfn(ST_BASE),
979 + .length = SZ_4K,
980 + .type = MT_DEVICE},
981 + {
982 + .virtual = IO_ADDRESS(USB_BASE),
983 + .pfn = __phys_to_pfn(USB_BASE),
984 + .length = SZ_128K,
985 + .type = MT_DEVICE},
986 + {
987 + .virtual = IO_ADDRESS(PM_BASE),
988 + .pfn = __phys_to_pfn(PM_BASE),
989 + .length = SZ_4K,
990 + .type = MT_DEVICE},
991 + {
992 + .virtual = IO_ADDRESS(GPIO_BASE),
993 + .pfn = __phys_to_pfn(GPIO_BASE),
994 + .length = SZ_4K,
995 + .type = MT_DEVICE},
996 + {
997 + .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
998 + .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
999 + .length = SZ_4K,
1000 + .type = MT_DEVICE},
1001 +};
1002 +
1003 +void __init bcm2709_map_io(void)
1004 +{
1005 + iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
1006 +}
1007 +
1008 +int calc_rsts(int partition)
1009 +{
1010 + return PM_PASSWORD |
1011 + ((partition & (1 << 0)) << 0) |
1012 + ((partition & (1 << 1)) << 1) |
1013 + ((partition & (1 << 2)) << 2) |
1014 + ((partition & (1 << 3)) << 3) |
1015 + ((partition & (1 << 4)) << 4) |
1016 + ((partition & (1 << 5)) << 5);
1017 +}
1018 +
1019 +static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
1020 +{
1021 + extern char bcm2708_reboot_mode;
1022 + uint32_t pm_rstc, pm_wdog;
1023 + uint32_t timeout = 10;
1024 + uint32_t pm_rsts = 0;
1025 +
1026 + if(bcm2708_reboot_mode == 'q')
1027 + {
1028 + // NOOBS < 1.3 booting with reboot=q
1029 + pm_rsts = readl(__io_address(PM_RSTS));
1030 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
1031 + }
1032 + else if(bcm2708_reboot_mode == 'p')
1033 + {
1034 + // NOOBS < 1.3 halting
1035 + pm_rsts = readl(__io_address(PM_RSTS));
1036 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
1037 + }
1038 + else
1039 + {
1040 + pm_rsts = calc_rsts(reboot_part);
1041 + }
1042 +
1043 + writel(pm_rsts, __io_address(PM_RSTS));
1044 +
1045 + /* Setup watchdog for reset */
1046 + pm_rstc = readl(__io_address(PM_RSTC));
1047 +
1048 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
1049 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
1050 +
1051 + writel(pm_wdog, __io_address(PM_WDOG));
1052 + writel(pm_rstc, __io_address(PM_RSTC));
1053 +}
1054 +
1055 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
1056 +static void bcm2709_power_off(void)
1057 +{
1058 + extern char bcm2708_reboot_mode;
1059 + if(bcm2708_reboot_mode == 'q')
1060 + {
1061 + // NOOBS < v1.3
1062 + bcm2709_restart('p', "");
1063 + }
1064 + else
1065 + {
1066 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
1067 + reboot_part = 63;
1068 + /* continue with normal reset mechanism */
1069 + bcm2709_restart(0, "");
1070 + }
1071 +}
1072 +
1073 +static void __init bcm2709_init_uart1(void)
1074 +{
1075 + struct device_node *np;
1076 +
1077 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2835-aux-uart");
1078 + if (of_device_is_available(np)) {
1079 + pr_info("bcm2709: Mini UART enabled\n");
1080 + writel(1, __io_address(UART1_BASE + 0x4));
1081 + }
1082 +}
1083 +
1084 +void __init bcm2709_init(void)
1085 +{
1086 + int ret;
1087 +
1088 + vc_cma_early_init();
1089 +
1090 + pm_power_off = bcm2709_power_off;
1091 +
1092 + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL,
1093 + NULL);
1094 + if (ret) {
1095 + pr_err("of_platform_populate failed: %d\n", ret);
1096 + BUG();
1097 + }
1098 +
1099 + bcm2709_init_uart1();
1100 +
1101 + system_rev = boardrev;
1102 + system_serial_low = serial;
1103 +}
1104 +
1105 +static void __init bcm2709_timer_init(void)
1106 +{
1107 + // timer control
1108 + writel(0, __io_address(ARM_LOCAL_CONTROL));
1109 + // timer pre_scaler
1110 + writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
1111 + //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
1112 +
1113 + of_clk_init(NULL);
1114 + clocksource_probe();
1115 +}
1116 +
1117 +
1118 +void __init bcm2709_init_early(void)
1119 +{
1120 + /*
1121 + * Some devices allocate their coherent buffers from atomic
1122 + * context. Increase size of atomic coherent pool to make sure such
1123 + * the allocations won't fail.
1124 + */
1125 + init_dma_coherent_pool_size(SZ_4M);
1126 +}
1127 +
1128 +static void __init board_reserve(void)
1129 +{
1130 + vc_cma_reserve();
1131 +}
1132 +
1133 +
1134 +#ifdef CONFIG_SMP
1135 +#include <linux/smp.h>
1136 +
1137 +#include <asm/cacheflush.h>
1138 +#include <asm/smp_plat.h>
1139 +int dc4=0;
1140 +//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
1141 +void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
1142 +
1143 +static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
1144 +{
1145 + int cpu;
1146 + /*
1147 + * Ensure that stores to Normal memory are visible to the
1148 + * other CPUs before issuing the IPI.
1149 + */
1150 + dsb();
1151 +
1152 + /* Convert our logical CPU mask into a physical one. */
1153 + for_each_cpu(cpu, mask)
1154 + {
1155 + /* submit softirq */
1156 + writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
1157 + }
1158 +}
1159 +
1160 +void __init bcm2709_smp_init_cpus(void)
1161 +{
1162 + void secondary_startup(void);
1163 + unsigned int i, ncores;
1164 +
1165 + ncores = 4; // xxx scu_get_core_count(NULL);
1166 + printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
1167 + printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
1168 +
1169 + for (i = 0; i < ncores; i++) {
1170 + set_cpu_possible(i, true);
1171 + /* enable IRQ (not FIQ) */
1172 + writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
1173 + //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
1174 + }
1175 + set_smp_cross_call(bcm2835_send_doorbell);
1176 +}
1177 +
1178 +/*
1179 + * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
1180 + */
1181 +void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
1182 +{
1183 + //void __iomem *scu_base;
1184 +
1185 + printk("[%s] enter\n", __FUNCTION__);
1186 + //scu_base = scu_base_addr();
1187 + //scu_enable(scu_base);
1188 +}
1189 +
1190 +/*
1191 + * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
1192 + */
1193 +void __init bcm2709_secondary_init(unsigned int cpu)
1194 +{
1195 + printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
1196 + //gic_secondary_init(0);
1197 +}
1198 +
1199 +/*
1200 + * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
1201 + */
1202 +int __init bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
1203 +{
1204 + void secondary_startup(void);
1205 + void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
1206 + void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
1207 + unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
1208 + int timeout=20;
1209 + unsigned t = -1;
1210 + //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
1211 +
1212 + dsb();
1213 + BUG_ON(readl(mbox_clr) != 0);
1214 + writel(secondary_boot, mbox_set);
1215 +
1216 + while (--timeout > 0) {
1217 + t = readl(mbox_clr);
1218 + if (t == 0) break;
1219 + cpu_relax();
1220 + }
1221 + if (timeout==0)
1222 + printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
1223 + else
1224 + printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
1225 +
1226 + return 0;
1227 +}
1228 +
1229 +
1230 +struct smp_operations bcm2709_smp_ops __initdata = {
1231 + .smp_init_cpus = bcm2709_smp_init_cpus,
1232 + .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
1233 + .smp_secondary_init = bcm2709_secondary_init,
1234 + .smp_boot_secondary = bcm2709_boot_secondary,
1235 +};
1236 +#endif
1237 +
1238 +static const char * const bcm2709_compat[] = {
1239 + "brcm,bcm2709",
1240 + "brcm,bcm2708", /* Could use bcm2708 in a pinch */
1241 + NULL
1242 +};
1243 +
1244 +MACHINE_START(BCM2709, "BCM2709")
1245 + /* Maintainer: Broadcom Europe Ltd. */
1246 +#ifdef CONFIG_SMP
1247 + .smp = smp_ops(bcm2709_smp_ops),
1248 +#endif
1249 + .map_io = bcm2709_map_io,
1250 + .init_time = bcm2709_timer_init,
1251 + .init_machine = bcm2709_init,
1252 + .init_early = bcm2709_init_early,
1253 + .reserve = board_reserve,
1254 + .restart = bcm2709_restart,
1255 + .dt_compat = bcm2709_compat,
1256 +MACHINE_END
1257 +
1258 +MACHINE_START(BCM2708, "BCM2709")
1259 + /* Maintainer: Broadcom Europe Ltd. */
1260 +#ifdef CONFIG_SMP
1261 + .smp = smp_ops(bcm2709_smp_ops),
1262 +#endif
1263 + .map_io = bcm2709_map_io,
1264 + .init_time = bcm2709_timer_init,
1265 + .init_machine = bcm2709_init,
1266 + .init_early = bcm2709_init_early,
1267 + .reserve = board_reserve,
1268 + .restart = bcm2709_restart,
1269 + .dt_compat = bcm2709_compat,
1270 +MACHINE_END
1271 +
1272 +module_param(boardrev, uint, 0644);
1273 +module_param(serial, uint, 0644);
1274 +module_param(reboot_part, uint, 0644);
1275 --- /dev/null
1276 +++ b/arch/arm/mach-bcm2709/include/mach/debug-macro.S
1277 @@ -0,0 +1,22 @@
1278 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
1279 + *
1280 + * Debugging macro include header
1281 + *
1282 + * Copyright (C) 2010 Broadcom
1283 + * Copyright (C) 1994-1999 Russell King
1284 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
1285 + *
1286 + * This program is free software; you can redistribute it and/or modify
1287 + * it under the terms of the GNU General Public License version 2 as
1288 + * published by the Free Software Foundation.
1289 + *
1290 +*/
1291 +
1292 +#include <mach/platform.h>
1293 +
1294 + .macro addruart, rp, rv, tmp
1295 + ldr \rp, =UART0_BASE
1296 + ldr \rv, =IO_ADDRESS(UART0_BASE)
1297 + .endm
1298 +
1299 +#include <debug/pl01x.S>
1300 --- /dev/null
1301 +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
1302 @@ -0,0 +1,123 @@
1303 +/*
1304 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
1305 + *
1306 + * Low-level IRQ helper macros for BCM2708 platforms
1307 + *
1308 + * Copyright (C) 2010 Broadcom
1309 + *
1310 + * This program is free software; you can redistribute it and/or modify
1311 + * it under the terms of the GNU General Public License as published by
1312 + * the Free Software Foundation; either version 2 of the License, or
1313 + * (at your option) any later version.
1314 + *
1315 + * This program is distributed in the hope that it will be useful,
1316 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1317 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1318 + * GNU General Public License for more details.
1319 + *
1320 + * You should have received a copy of the GNU General Public License
1321 + * along with this program; if not, write to the Free Software
1322 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1323 + */
1324 +#include <mach/hardware.h>
1325 +#include <mach/irqs.h>
1326 +
1327 + .macro disable_fiq
1328 + .endm
1329 +
1330 + .macro get_irqnr_preamble, base, tmp
1331 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
1332 + .endm
1333 +
1334 + .macro arch_ret_to_user, tmp1, tmp2
1335 + .endm
1336 +
1337 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
1338 + /* get core number */
1339 + mrc p15, 0, \tmp, c0, c0, 5
1340 + ubfx \tmp, \tmp, #0, #2
1341 +
1342 + /* get core's local interrupt controller */
1343 + ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
1344 + add \irqstat, \irqstat, \tmp, lsl #2
1345 + ldr \tmp, [\irqstat]
1346 + /* ignore gpu interrupt */
1347 + bic \tmp, #0x100
1348 + /* ignore mailbox interrupts */
1349 + bics \tmp, #0xf0
1350 + beq 1005f
1351 +
1352 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
1353 + @ N.B. CLZ is an ARM5 instruction.
1354 + mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
1355 + sub \irqstat, \tmp, #1
1356 + eor \irqstat, \irqstat, \tmp
1357 + clz \tmp, \irqstat
1358 + sub \irqnr, \tmp
1359 + b 1020f
1360 +1005:
1361 + /* get core number */
1362 + mrc p15, 0, \tmp, c0, c0, 5
1363 + ubfx \tmp, \tmp, #0, #2
1364 +
1365 + cmp \tmp, #1
1366 + beq 1020f
1367 + cmp \tmp, #2
1368 + beq 1020f
1369 + cmp \tmp, #3
1370 + beq 1020f
1371 +
1372 + /* get masked status */
1373 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
1374 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
1375 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
1376 + /* clear bits 8 and 9, and test */
1377 + bics \irqstat, \irqstat, #0x300
1378 + bne 1010f
1379 +
1380 + tst \tmp, #0x100
1381 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
1382 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
1383 + @ Mask out the interrupts also present in PEND0 - see SW-5809
1384 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
1385 + bicne \irqstat, #((1<<18) | (1<<19))
1386 + bne 1010f
1387 +
1388 + tst \tmp, #0x200
1389 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
1390 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
1391 + @ Mask out the interrupts also present in PEND0 - see SW-5809
1392 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
1393 + bicne \irqstat, #((1<<30))
1394 + beq 1020f
1395 +
1396 +1010:
1397 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
1398 + @ N.B. CLZ is an ARM5 instruction.
1399 + sub \tmp, \irqstat, #1
1400 + eor \irqstat, \irqstat, \tmp
1401 + clz \tmp, \irqstat
1402 + sub \irqnr, \tmp
1403 +
1404 +1020: @ EQ will be set if no irqs pending
1405 +
1406 + .endm
1407 +
1408 + .macro test_for_ipi, irqnr, irqstat, base, tmp
1409 + /* get core number */
1410 + mrc p15, 0, \tmp, c0, c0, 5
1411 + ubfx \tmp, \tmp, #0, #2
1412 + /* get core's mailbox interrupt control */
1413 + ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
1414 + add \irqstat, \irqstat, \tmp, lsl #4
1415 + ldr \tmp, [\irqstat]
1416 + cmp \tmp, #0
1417 + beq 1030f
1418 + clz \tmp, \tmp
1419 + rsb \irqnr, \tmp, #31
1420 + mov \tmp, #1
1421 + lsl \tmp, \irqnr
1422 + str \tmp, [\irqstat] @ clear interrupt source
1423 + dsb
1424 +1030: @ EQ will be set if no irqs pending
1425 + .endm
1426 --- /dev/null
1427 +++ b/arch/arm/mach-bcm2709/include/mach/io.h
1428 @@ -0,0 +1,27 @@
1429 +/*
1430 + * arch/arm/mach-bcm2708/include/mach/io.h
1431 + *
1432 + * Copyright (C) 2003 ARM Limited
1433 + *
1434 + * This program is free software; you can redistribute it and/or modify
1435 + * it under the terms of the GNU General Public License as published by
1436 + * the Free Software Foundation; either version 2 of the License, or
1437 + * (at your option) any later version.
1438 + *
1439 + * This program is distributed in the hope that it will be useful,
1440 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1441 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1442 + * GNU General Public License for more details.
1443 + *
1444 + * You should have received a copy of the GNU General Public License
1445 + * along with this program; if not, write to the Free Software
1446 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1447 + */
1448 +#ifndef __ASM_ARM_ARCH_IO_H
1449 +#define __ASM_ARM_ARCH_IO_H
1450 +
1451 +#define IO_SPACE_LIMIT 0xffffffff
1452 +
1453 +#define __io(a) __typesafe_io(a)
1454 +
1455 +#endif
1456 --- /dev/null
1457 +++ b/arch/arm/mach-bcm2709/include/mach/memory.h
1458 @@ -0,0 +1,57 @@
1459 +/*
1460 + * arch/arm/mach-bcm2708/include/mach/memory.h
1461 + *
1462 + * Copyright (C) 2010 Broadcom
1463 + *
1464 + * This program is free software; you can redistribute it and/or modify
1465 + * it under the terms of the GNU General Public License as published by
1466 + * the Free Software Foundation; either version 2 of the License, or
1467 + * (at your option) any later version.
1468 + *
1469 + * This program is distributed in the hope that it will be useful,
1470 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1471 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1472 + * GNU General Public License for more details.
1473 + *
1474 + * You should have received a copy of the GNU General Public License
1475 + * along with this program; if not, write to the Free Software
1476 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1477 + */
1478 +#ifndef __ASM_ARCH_MEMORY_H
1479 +#define __ASM_ARCH_MEMORY_H
1480 +
1481 +/* Memory overview:
1482 +
1483 + [ARMcore] <--virtual addr-->
1484 + [ARMmmu] <--physical addr-->
1485 + [GERTmap] <--bus add-->
1486 + [VCperiph]
1487 +
1488 +*/
1489 +
1490 +/*
1491 + * Physical DRAM offset.
1492 + */
1493 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
1494 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
1495 +
1496 +#ifdef CONFIG_BCM2708_NOL2CACHE
1497 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
1498 +#else
1499 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
1500 +#endif
1501 +
1502 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
1503 + * will provide the offset into this area as well as setting the bits that
1504 + * stop the L1 and L2 cache from being used
1505 + *
1506 + * WARNING: this only works because the ARM is given memory at a fixed location
1507 + * (ARMMEM_OFFSET)
1508 + */
1509 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
1510 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
1511 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
1512 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
1513 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
1514 +
1515 +#endif
1516 --- /dev/null
1517 +++ b/arch/arm/mach-bcm2709/include/mach/platform.h
1518 @@ -0,0 +1,188 @@
1519 +/*
1520 + * arch/arm/mach-bcm2708/include/mach/platform.h
1521 + *
1522 + * Copyright (C) 2010 Broadcom
1523 + *
1524 + * This program is free software; you can redistribute it and/or modify
1525 + * it under the terms of the GNU General Public License as published by
1526 + * the Free Software Foundation; either version 2 of the License, or
1527 + * (at your option) any later version.
1528 + *
1529 + * This program is distributed in the hope that it will be useful,
1530 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1531 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1532 + * GNU General Public License for more details.
1533 + *
1534 + * You should have received a copy of the GNU General Public License
1535 + * along with this program; if not, write to the Free Software
1536 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1537 + */
1538 +
1539 +#ifndef _BCM2708_PLATFORM_H
1540 +#define _BCM2708_PLATFORM_H
1541 +
1542 +
1543 +/* macros to get at IO space when running virtually */
1544 +#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
1545 +
1546 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
1547 +
1548 +
1549 +/*
1550 + * SDRAM
1551 + */
1552 +#define BCM2708_SDRAM_BASE 0x00000000
1553 +
1554 +/*
1555 + * Logic expansion modules
1556 + *
1557 + */
1558 +
1559 +
1560 +/* ------------------------------------------------------------------------
1561 + * BCM2708 ARMCTRL Registers
1562 + * ------------------------------------------------------------------------
1563 + */
1564 +
1565 +#define HW_REGISTER_RW(addr) (addr)
1566 +#define HW_REGISTER_RO(addr) (addr)
1567 +
1568 +/*
1569 + * Definitions and addresses for the ARM CONTROL logic
1570 + * This file is manually generated.
1571 + */
1572 +
1573 +#define BCM2708_PERI_BASE 0x3F000000
1574 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
1575 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
1576 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
1577 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
1578 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
1579 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
1580 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
1581 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
1582 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
1583 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
1584 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
1585 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
1586 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
1587 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
1588 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
1589 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
1590 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
1591 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
1592 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
1593 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
1594 +
1595 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
1596 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
1597 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
1598 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
1599 +
1600 +/*
1601 + * Watchdog
1602 + */
1603 +#define PM_RSTC (PM_BASE+0x1c)
1604 +#define PM_RSTS (PM_BASE+0x20)
1605 +#define PM_WDOG (PM_BASE+0x24)
1606 +
1607 +#define PM_WDOG_RESET 0000000000
1608 +#define PM_PASSWORD 0x5a000000
1609 +#define PM_WDOG_TIME_SET 0x000fffff
1610 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
1611 +#define PM_RSTC_WRCFG_SET 0x00000030
1612 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
1613 +#define PM_RSTC_RESET 0x00000102
1614 +
1615 +#define PM_RSTS_HADPOR_SET 0x00001000
1616 +#define PM_RSTS_HADSRH_SET 0x00000400
1617 +#define PM_RSTS_HADSRF_SET 0x00000200
1618 +#define PM_RSTS_HADSRQ_SET 0x00000100
1619 +#define PM_RSTS_HADWRH_SET 0x00000040
1620 +#define PM_RSTS_HADWRF_SET 0x00000020
1621 +#define PM_RSTS_HADWRQ_SET 0x00000010
1622 +#define PM_RSTS_HADDRH_SET 0x00000004
1623 +#define PM_RSTS_HADDRF_SET 0x00000002
1624 +#define PM_RSTS_HADDRQ_SET 0x00000001
1625 +
1626 +#define UART0_CLOCK 3000000
1627 +
1628 +#define ARM_LOCAL_BASE 0x40000000
1629 +#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
1630 +
1631 +#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
1632 +#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
1633 +#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
1634 +#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
1635 +#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
1636 +#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
1637 +#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
1638 +#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
1639 +#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
1640 +#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
1641 +#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
1642 +#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
1643 +
1644 +#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
1645 +#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
1646 +#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
1647 +#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
1648 +
1649 +#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
1650 +#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
1651 +#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
1652 +#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
1653 +
1654 +#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
1655 +#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
1656 +#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
1657 +#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
1658 +
1659 +#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
1660 +#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
1661 +#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
1662 +#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
1663 +
1664 +#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
1665 +#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
1666 +#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
1667 +#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
1668 +
1669 +#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
1670 +#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
1671 +#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
1672 +#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
1673 +
1674 +#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
1675 +#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
1676 +#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
1677 +#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
1678 +
1679 +#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
1680 +#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
1681 +#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
1682 +#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
1683 +
1684 +#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
1685 +#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
1686 +#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
1687 +#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
1688 +
1689 +#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
1690 +#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
1691 +#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
1692 +#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
1693 +
1694 +#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
1695 +#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
1696 +#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
1697 +#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
1698 +
1699 +#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
1700 +#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
1701 +#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
1702 +#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
1703 +
1704 +#endif
1705 +
1706 +/* END */
1707 --- /dev/null
1708 +++ b/arch/arm/mach-bcm2709/include/mach/system.h
1709 @@ -0,0 +1,37 @@
1710 +/*
1711 + * arch/arm/mach-bcm2708/include/mach/system.h
1712 + *
1713 + * Copyright (C) 2010 Broadcom
1714 + * Copyright (C) 2003 ARM Limited
1715 + * Copyright (C) 2000 Deep Blue Solutions Ltd
1716 + *
1717 + * This program is free software; you can redistribute it and/or modify
1718 + * it under the terms of the GNU General Public License as published by
1719 + * the Free Software Foundation; either version 2 of the License, or
1720 + * (at your option) any later version.
1721 + *
1722 + * This program is distributed in the hope that it will be useful,
1723 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1724 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1725 + * GNU General Public License for more details.
1726 + *
1727 + * You should have received a copy of the GNU General Public License
1728 + * along with this program; if not, write to the Free Software
1729 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1730 + */
1731 +#ifndef __ASM_ARCH_SYSTEM_H
1732 +#define __ASM_ARCH_SYSTEM_H
1733 +
1734 +#include <linux/io.h>
1735 +#include <mach/platform.h>
1736 +
1737 +static inline void arch_idle(void)
1738 +{
1739 + /*
1740 + * This should do all the clock switching
1741 + * and wait for interrupt tricks
1742 + */
1743 + cpu_do_idle();
1744 +}
1745 +
1746 +#endif
1747 --- /dev/null
1748 +++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h
1749 @@ -0,0 +1,84 @@
1750 +/*
1751 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
1752 + *
1753 + * Copyright (C) 2010 Broadcom
1754 + * Copyright (C) 2003 ARM Limited
1755 + *
1756 + * This program is free software; you can redistribute it and/or modify
1757 + * it under the terms of the GNU General Public License as published by
1758 + * the Free Software Foundation; either version 2 of the License, or
1759 + * (at your option) any later version.
1760 + *
1761 + * This program is distributed in the hope that it will be useful,
1762 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1763 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1764 + * GNU General Public License for more details.
1765 + *
1766 + * You should have received a copy of the GNU General Public License
1767 + * along with this program; if not, write to the Free Software
1768 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1769 + */
1770 +
1771 +#include <linux/io.h>
1772 +#include <linux/amba/serial.h>
1773 +#include <mach/platform.h>
1774 +
1775 +#define UART_BAUD 115200
1776 +
1777 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
1778 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
1779 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
1780 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
1781 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
1782 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
1783 +
1784 +/*
1785 + * This does not append a newline
1786 + */
1787 +static inline void putc(int c)
1788 +{
1789 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
1790 + barrier();
1791 +
1792 + __raw_writel(c, BCM2708_UART_DR);
1793 +}
1794 +
1795 +static inline void flush(void)
1796 +{
1797 + int fr;
1798 +
1799 + do {
1800 + fr = __raw_readl(BCM2708_UART_FR);
1801 + barrier();
1802 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
1803 +}
1804 +
1805 +static inline void arch_decomp_setup(void)
1806 +{
1807 + int temp, div, rem, frac;
1808 +
1809 + temp = 16 * UART_BAUD;
1810 + div = UART0_CLOCK / temp;
1811 + rem = UART0_CLOCK % temp;
1812 + temp = (8 * rem) / UART_BAUD;
1813 + frac = (temp >> 1) + (temp & 1);
1814 +
1815 + /* Make sure the UART is disabled before we start */
1816 + __raw_writel(0, BCM2708_UART_CR);
1817 +
1818 + /* Set the baud rate */
1819 + __raw_writel(div, BCM2708_UART_IBRD);
1820 + __raw_writel(frac, BCM2708_UART_FBRD);
1821 +
1822 + /* Set the UART to 8n1, FIFO enabled */
1823 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
1824 +
1825 + /* Enable the UART */
1826 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
1827 + BCM2708_UART_CR);
1828 +}
1829 +
1830 +/*
1831 + * nothing to do
1832 + */
1833 +#define arch_decomp_wdog()
1834 --- /dev/null
1835 +++ b/arch/arm/mach-bcm2709/include/mach/vc_mem.h
1836 @@ -0,0 +1,35 @@
1837 +/*****************************************************************************
1838 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
1839 +*
1840 +* Unless you and Broadcom execute a separate written software license
1841 +* agreement governing use of this software, this software is licensed to you
1842 +* under the terms of the GNU General Public License version 2, available at
1843 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
1844 +*
1845 +* Notwithstanding the above, under no circumstances may you combine this
1846 +* software in any way with any other Broadcom software provided under a
1847 +* license other than the GPL, without Broadcom's express prior written
1848 +* consent.
1849 +*****************************************************************************/
1850 +
1851 +#if !defined( VC_MEM_H )
1852 +#define VC_MEM_H
1853 +
1854 +#include <linux/ioctl.h>
1855 +
1856 +#define VC_MEM_IOC_MAGIC 'v'
1857 +
1858 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
1859 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
1860 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
1861 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
1862 +
1863 +#if defined( __KERNEL__ )
1864 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
1865 +
1866 +extern unsigned long mm_vc_mem_phys_addr;
1867 +extern unsigned int mm_vc_mem_size;
1868 +extern int vc_mem_get_current_size( void );
1869 +#endif
1870 +
1871 +#endif /* VC_MEM_H */
1872 --- /dev/null
1873 +++ b/arch/arm/mach-bcm2709/include/mach/vmalloc.h
1874 @@ -0,0 +1,20 @@
1875 +/*
1876 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
1877 + *
1878 + * Copyright (C) 2010 Broadcom
1879 + *
1880 + * This program is free software; you can redistribute it and/or modify
1881 + * it under the terms of the GNU General Public License as published by
1882 + * the Free Software Foundation; either version 2 of the License, or
1883 + * (at your option) any later version.
1884 + *
1885 + * This program is distributed in the hope that it will be useful,
1886 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1887 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1888 + * GNU General Public License for more details.
1889 + *
1890 + * You should have received a copy of the GNU General Public License
1891 + * along with this program; if not, write to the Free Software
1892 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1893 + */
1894 +#define VMALLOC_END (0xff000000)
1895 --- /dev/null
1896 +++ b/arch/arm/mach-bcm2709/vc_mem.c
1897 @@ -0,0 +1,431 @@
1898 +/*****************************************************************************
1899 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
1900 +*
1901 +* Unless you and Broadcom execute a separate written software license
1902 +* agreement governing use of this software, this software is licensed to you
1903 +* under the terms of the GNU General Public License version 2, available at
1904 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
1905 +*
1906 +* Notwithstanding the above, under no circumstances may you combine this
1907 +* software in any way with any other Broadcom software provided under a
1908 +* license other than the GPL, without Broadcom's express prior written
1909 +* consent.
1910 +*****************************************************************************/
1911 +
1912 +#include <linux/kernel.h>
1913 +#include <linux/module.h>
1914 +#include <linux/fs.h>
1915 +#include <linux/device.h>
1916 +#include <linux/cdev.h>
1917 +#include <linux/mm.h>
1918 +#include <linux/slab.h>
1919 +#include <linux/debugfs.h>
1920 +#include <asm/uaccess.h>
1921 +#include <linux/dma-mapping.h>
1922 +#include <linux/platform_data/mailbox-bcm2708.h>
1923 +
1924 +#ifdef CONFIG_ARCH_KONA
1925 +#include <chal/chal_ipc.h>
1926 +#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
1927 +#else
1928 +#include <csp/chal_ipc.h>
1929 +#endif
1930 +
1931 +#include "mach/vc_mem.h"
1932 +
1933 +#define DRIVER_NAME "vc-mem"
1934 +
1935 +// Device (/dev) related variables
1936 +static dev_t vc_mem_devnum = 0;
1937 +static struct class *vc_mem_class = NULL;
1938 +static struct cdev vc_mem_cdev;
1939 +static int vc_mem_inited = 0;
1940 +
1941 +#ifdef CONFIG_DEBUG_FS
1942 +static struct dentry *vc_mem_debugfs_entry;
1943 +#endif
1944 +
1945 +/*
1946 + * Videocore memory addresses and size
1947 + *
1948 + * Drivers that wish to know the videocore memory addresses and sizes should
1949 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
1950 + * headers. This allows the other drivers to not be tied down to a a certain
1951 + * address/size at compile time.
1952 + *
1953 + * In the future, the goal is to have the videocore memory virtual address and
1954 + * size be calculated at boot time rather than at compile time. The decision of
1955 + * where the videocore memory resides and its size would be in the hands of the
1956 + * bootloader (and/or kernel). When that happens, the values of these variables
1957 + * would be calculated and assigned in the init function.
1958 + */
1959 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
1960 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
1961 +unsigned int mm_vc_mem_size = 0;
1962 +unsigned int mm_vc_mem_base = 0;
1963 +
1964 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
1965 +EXPORT_SYMBOL(mm_vc_mem_size);
1966 +EXPORT_SYMBOL(mm_vc_mem_base);
1967 +
1968 +static uint phys_addr = 0;
1969 +static uint mem_size = 0;
1970 +static uint mem_base = 0;
1971 +
1972 +
1973 +/****************************************************************************
1974 +*
1975 +* vc_mem_open
1976 +*
1977 +***************************************************************************/
1978 +
1979 +static int
1980 +vc_mem_open(struct inode *inode, struct file *file)
1981 +{
1982 + (void) inode;
1983 + (void) file;
1984 +
1985 + pr_debug("%s: called file = 0x%p\n", __func__, file);
1986 +
1987 + return 0;
1988 +}
1989 +
1990 +/****************************************************************************
1991 +*
1992 +* vc_mem_release
1993 +*
1994 +***************************************************************************/
1995 +
1996 +static int
1997 +vc_mem_release(struct inode *inode, struct file *file)
1998 +{
1999 + (void) inode;
2000 + (void) file;
2001 +
2002 + pr_debug("%s: called file = 0x%p\n", __func__, file);
2003 +
2004 + return 0;
2005 +}
2006 +
2007 +/****************************************************************************
2008 +*
2009 +* vc_mem_get_size
2010 +*
2011 +***************************************************************************/
2012 +
2013 +static void
2014 +vc_mem_get_size(void)
2015 +{
2016 +}
2017 +
2018 +/****************************************************************************
2019 +*
2020 +* vc_mem_get_base
2021 +*
2022 +***************************************************************************/
2023 +
2024 +static void
2025 +vc_mem_get_base(void)
2026 +{
2027 +}
2028 +
2029 +/****************************************************************************
2030 +*
2031 +* vc_mem_get_current_size
2032 +*
2033 +***************************************************************************/
2034 +
2035 +int
2036 +vc_mem_get_current_size(void)
2037 +{
2038 + return mm_vc_mem_size;
2039 +}
2040 +
2041 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
2042 +
2043 +/****************************************************************************
2044 +*
2045 +* vc_mem_ioctl
2046 +*
2047 +***************************************************************************/
2048 +
2049 +static long
2050 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
2051 +{
2052 + int rc = 0;
2053 +
2054 + (void) cmd;
2055 + (void) arg;
2056 +
2057 + pr_debug("%s: called file = 0x%p\n", __func__, file);
2058 +
2059 + switch (cmd) {
2060 + case VC_MEM_IOC_MEM_PHYS_ADDR:
2061 + {
2062 + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
2063 + __func__, (void *) mm_vc_mem_phys_addr);
2064 +
2065 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
2066 + sizeof (mm_vc_mem_phys_addr)) != 0) {
2067 + rc = -EFAULT;
2068 + }
2069 + break;
2070 + }
2071 + case VC_MEM_IOC_MEM_SIZE:
2072 + {
2073 + // Get the videocore memory size first
2074 + vc_mem_get_size();
2075 +
2076 + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
2077 + mm_vc_mem_size);
2078 +
2079 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
2080 + sizeof (mm_vc_mem_size)) != 0) {
2081 + rc = -EFAULT;
2082 + }
2083 + break;
2084 + }
2085 + case VC_MEM_IOC_MEM_BASE:
2086 + {
2087 + // Get the videocore memory base
2088 + vc_mem_get_base();
2089 +
2090 + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
2091 + mm_vc_mem_base);
2092 +
2093 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
2094 + sizeof (mm_vc_mem_base)) != 0) {
2095 + rc = -EFAULT;
2096 + }
2097 + break;
2098 + }
2099 + case VC_MEM_IOC_MEM_LOAD:
2100 + {
2101 + // Get the videocore memory base
2102 + vc_mem_get_base();
2103 +
2104 + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
2105 + mm_vc_mem_base);
2106 +
2107 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
2108 + sizeof (mm_vc_mem_base)) != 0) {
2109 + rc = -EFAULT;
2110 + }
2111 + break;
2112 + }
2113 + default:
2114 + {
2115 + return -ENOTTY;
2116 + }
2117 + }
2118 + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
2119 +
2120 + return rc;
2121 +}
2122 +
2123 +/****************************************************************************
2124 +*
2125 +* vc_mem_mmap
2126 +*
2127 +***************************************************************************/
2128 +
2129 +static int
2130 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
2131 +{
2132 + int rc = 0;
2133 + unsigned long length = vma->vm_end - vma->vm_start;
2134 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
2135 +
2136 + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
2137 + __func__, (long) vma->vm_start, (long) vma->vm_end,
2138 + (long) vma->vm_pgoff);
2139 +
2140 + if (offset + length > mm_vc_mem_size) {
2141 + pr_err("%s: length %ld is too big\n", __func__, length);
2142 + return -EINVAL;
2143 + }
2144 + // Do not cache the memory map
2145 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2146 +
2147 + rc = remap_pfn_range(vma, vma->vm_start,
2148 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
2149 + vma->vm_pgoff, length, vma->vm_page_prot);
2150 + if (rc != 0) {
2151 + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
2152 + }
2153 +
2154 + return rc;
2155 +}
2156 +
2157 +/****************************************************************************
2158 +*
2159 +* File Operations for the driver.
2160 +*
2161 +***************************************************************************/
2162 +
2163 +static const struct file_operations vc_mem_fops = {
2164 + .owner = THIS_MODULE,
2165 + .open = vc_mem_open,
2166 + .release = vc_mem_release,
2167 + .unlocked_ioctl = vc_mem_ioctl,
2168 + .mmap = vc_mem_mmap,
2169 +};
2170 +
2171 +#ifdef CONFIG_DEBUG_FS
2172 +static void vc_mem_debugfs_deinit(void)
2173 +{
2174 + debugfs_remove_recursive(vc_mem_debugfs_entry);
2175 + vc_mem_debugfs_entry = NULL;
2176 +}
2177 +
2178 +
2179 +static int vc_mem_debugfs_init(
2180 + struct device *dev)
2181 +{
2182 + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
2183 + if (!vc_mem_debugfs_entry) {
2184 + dev_warn(dev, "could not create debugfs entry\n");
2185 + return -EFAULT;
2186 + }
2187 +
2188 + if (!debugfs_create_x32("vc_mem_phys_addr",
2189 + 0444,
2190 + vc_mem_debugfs_entry,
2191 + (u32 *)&mm_vc_mem_phys_addr)) {
2192 + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
2193 + __func__);
2194 + goto fail;
2195 + }
2196 +
2197 + if (!debugfs_create_x32("vc_mem_size",
2198 + 0444,
2199 + vc_mem_debugfs_entry,
2200 + (u32 *)&mm_vc_mem_size)) {
2201 + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
2202 + __func__);
2203 + goto fail;
2204 + }
2205 +
2206 + if (!debugfs_create_x32("vc_mem_base",
2207 + 0444,
2208 + vc_mem_debugfs_entry,
2209 + (u32 *)&mm_vc_mem_base)) {
2210 + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
2211 + __func__);
2212 + goto fail;
2213 + }
2214 +
2215 + return 0;
2216 +
2217 +fail:
2218 + vc_mem_debugfs_deinit();
2219 + return -EFAULT;
2220 +}
2221 +
2222 +#endif /* CONFIG_DEBUG_FS */
2223 +
2224 +
2225 +/****************************************************************************
2226 +*
2227 +* vc_mem_init
2228 +*
2229 +***************************************************************************/
2230 +
2231 +static int __init
2232 +vc_mem_init(void)
2233 +{
2234 + int rc = -EFAULT;
2235 + struct device *dev;
2236 +
2237 + pr_debug("%s: called\n", __func__);
2238 +
2239 + mm_vc_mem_phys_addr = phys_addr;
2240 + mm_vc_mem_size = mem_size;
2241 + mm_vc_mem_base = mem_base;
2242 +
2243 + vc_mem_get_size();
2244 +
2245 + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
2246 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
2247 +
2248 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
2249 + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
2250 + __func__, rc);
2251 + goto out_err;
2252 + }
2253 +
2254 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
2255 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
2256 + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
2257 + goto out_unregister;
2258 + }
2259 +
2260 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
2261 + if (IS_ERR(vc_mem_class)) {
2262 + rc = PTR_ERR(vc_mem_class);
2263 + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
2264 + goto out_cdev_del;
2265 + }
2266 +
2267 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
2268 + DRIVER_NAME);
2269 + if (IS_ERR(dev)) {
2270 + rc = PTR_ERR(dev);
2271 + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
2272 + goto out_class_destroy;
2273 + }
2274 +
2275 +#ifdef CONFIG_DEBUG_FS
2276 + /* don't fail if the debug entries cannot be created */
2277 + vc_mem_debugfs_init(dev);
2278 +#endif
2279 +
2280 + vc_mem_inited = 1;
2281 + return 0;
2282 +
2283 + device_destroy(vc_mem_class, vc_mem_devnum);
2284 +
2285 + out_class_destroy:
2286 + class_destroy(vc_mem_class);
2287 + vc_mem_class = NULL;
2288 +
2289 + out_cdev_del:
2290 + cdev_del(&vc_mem_cdev);
2291 +
2292 + out_unregister:
2293 + unregister_chrdev_region(vc_mem_devnum, 1);
2294 +
2295 + out_err:
2296 + return -1;
2297 +}
2298 +
2299 +/****************************************************************************
2300 +*
2301 +* vc_mem_exit
2302 +*
2303 +***************************************************************************/
2304 +
2305 +static void __exit
2306 +vc_mem_exit(void)
2307 +{
2308 + pr_debug("%s: called\n", __func__);
2309 +
2310 + if (vc_mem_inited) {
2311 +#if CONFIG_DEBUG_FS
2312 + vc_mem_debugfs_deinit();
2313 +#endif
2314 + device_destroy(vc_mem_class, vc_mem_devnum);
2315 + class_destroy(vc_mem_class);
2316 + cdev_del(&vc_mem_cdev);
2317 + unregister_chrdev_region(vc_mem_devnum, 1);
2318 + }
2319 +}
2320 +
2321 +module_init(vc_mem_init);
2322 +module_exit(vc_mem_exit);
2323 +MODULE_LICENSE("GPL");
2324 +MODULE_AUTHOR("Broadcom Corporation");
2325 +
2326 +module_param(phys_addr, uint, 0644);
2327 +module_param(mem_size, uint, 0644);
2328 +module_param(mem_base, uint, 0644);
2329 --- a/arch/arm/mm/Kconfig
2330 +++ b/arch/arm/mm/Kconfig
2331 @@ -358,7 +358,7 @@ config CPU_PJ4B
2332
2333 # ARMv6
2334 config CPU_V6
2335 - bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
2336 + bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708)
2337 select CPU_32v6
2338 select CPU_ABRT_EV6
2339 select CPU_CACHE_V6
2340 --- a/arch/arm/mm/proc-v6.S
2341 +++ b/arch/arm/mm/proc-v6.S
2342 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
2343 *
2344 * IRQs are already disabled.
2345 */
2346 +
2347 +/* See jira SW-5991 for details of this workaround */
2348 ENTRY(cpu_v6_do_idle)
2349 - mov r1, #0
2350 - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
2351 - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
2352 + .align 5
2353 + mov r1, #2
2354 +1: subs r1, #1
2355 + nop
2356 + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
2357 + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
2358 + nop
2359 + nop
2360 + nop
2361 + bne 1b
2362 ret lr
2363
2364 ENTRY(cpu_v6_dcache_clean_area)
2365 --- a/arch/arm/mm/proc-v7.S
2366 +++ b/arch/arm/mm/proc-v7.S
2367 @@ -480,6 +480,7 @@ __errata_finish:
2368 orr r0, r0, r6 @ set them
2369 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
2370 ret lr @ return to head.S:__ret
2371 + .space 256
2372 ENDPROC(__v7_setup)
2373
2374 .align 2
2375 --- a/arch/arm/tools/mach-types
2376 +++ b/arch/arm/tools/mach-types
2377 @@ -522,6 +522,8 @@ torbreck MACH_TORBRECK TORBRECK 3090
2378 prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
2379 paz00 MACH_PAZ00 PAZ00 3128
2380 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
2381 +bcm2708 MACH_BCM2708 BCM2708 3138
2382 +bcm2709 MACH_BCM2709 BCM2709 3139
2383 ag5evm MACH_AG5EVM AG5EVM 3189
2384 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
2385 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
2386 --- a/drivers/clocksource/Makefile
2387 +++ b/drivers/clocksource/Makefile
2388 @@ -19,7 +19,7 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU) += noma
2389 obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
2390 obj-$(CONFIG_ARMADA_370_XP_TIMER) += time-armada-370-xp.o
2391 obj-$(CONFIG_ORION_TIMER) += time-orion.o
2392 -obj-$(CONFIG_ARCH_BCM2835) += bcm2835_timer.o
2393 +obj-$(CONFIG_ARCH_BCM2835)$(CONFIG_ARCH_BCM2708) += bcm2835_timer.o
2394 obj-$(CONFIG_ARCH_CLPS711X) += clps711x-timer.o
2395 obj-$(CONFIG_ARCH_ATLAS7) += timer-atlas7.o
2396 obj-$(CONFIG_ARCH_MOXART) += moxart_timer.o
2397 --- a/drivers/irqchip/Makefile
2398 +++ b/drivers/irqchip/Makefile
2399 @@ -2,6 +2,9 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
2400
2401 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
2402 obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
2403 +obj-$(CONFIG_ARCH_BCM2708) += irq-bcm2835.o
2404 +obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2835.o
2405 +obj-$(CONFIG_ARCH_BCM2709) += irq-bcm2836.o
2406 obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
2407 obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
2408 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
2409 --- a/include/linux/mmc/host.h
2410 +++ b/include/linux/mmc/host.h
2411 @@ -289,6 +289,7 @@ struct mmc_host {
2412 #define MMC_CAP2_HSX00_1_2V (MMC_CAP2_HS200_1_2V_SDR | MMC_CAP2_HS400_1_2V)
2413 #define MMC_CAP2_SDIO_IRQ_NOTHREAD (1 << 17)
2414 #define MMC_CAP2_NO_WRITE_PROTECT (1 << 18) /* No physical write protect pin, assume that card is always read-write */
2415 +#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 31) /* Always use multiblock transfers */
2416
2417 mmc_pm_flag_t pm_caps; /* supported pm features */
2418
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