target/linux/brcm2708/patches-4.4/0031-dmaengine-Add-support-for-BCM2708.patch

   1 From 659b118206dd29242abbb2d1f889b7b9788561f3 Mon Sep 17 00:00:00 2001
   2 From: Florian Meier <florian.meier@koalo.de>
   3 Date: Fri, 22 Nov 2013 14:22:53 +0100
   4 Subject: [PATCH] dmaengine: Add support for BCM2708
   5 MIME-Version: 1.0
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   7 Content-Transfer-Encoding: 8bit
   8
   9 Add support for DMA controller of BCM2708 as used in the Raspberry Pi.
  10 Currently it only supports cyclic DMA.
  11
  12 Signed-off-by: Florian Meier <florian.meier@koalo.de>
  13
  14 dmaengine: expand functionality by supporting scatter/gather transfers sdhci-bcm2708 and dma.c: fix for LITE channels
  15
  16 DMA: fix cyclic LITE length overflow bug
  17
  18 dmaengine: bcm2708: Remove chancnt affectations
  19
  20 Mirror bcm2835-dma.c commit 9eba5536a7434c69d8c185d4bd1c70734d92287d:
  21 chancnt is already filled by dma_async_device_register, which uses the channel
  22 list to know how much channels there is.
  23
  24 Since it's already filled, we can safely remove it from the drivers' probe
  25 function.
  26
  27 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  28
  29 dmaengine: bcm2708: overwrite dreq only if it is not set
  30
  31 dreq is set when the DMA channel is fetched from Device Tree.
  32 slave_id is set using dmaengine_slave_config().
  33 Only overwrite dreq with slave_id if it is not set.
  34
  35 dreq/slave_id in the cyclic DMA case is not touched, because I don't
  36 have hardware to test with.
  37
  38 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  39
  40 dmaengine: bcm2708: do device registration in the board file
  41
  42 Don't register the device in the driver. Do it in the board file.
  43
  44 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  45
  46 dmaengine: bcm2708: don't restrict DT support to ARCH_BCM2835
  47
  48 Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now.
  49 Add Device Tree support to the non ARCH_BCM2835 case.
  50 Use the same driver name regardless of architecture.
  51
  52 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  53
  54 BCM270x_DT: add bcm2835-dma entry
  55
  56 Add Device Tree entry for bcm2835-dma.
  57 The entry doesn't contain any resources since they are handled
  58 by the arch/arm/mach-bcm270x/dma.c driver.
  59 In non-DT mode, don't add the device in the board file.
  60
  61 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  62
  63 bcm2708-dmaengine: Add debug options
  64
  65 BCM270x: Add memory and irq resources to dmaengine device and DT
  66
  67 Prepare for merging of the legacy DMA API arch driver dma.c
  68 with bcm2708-dmaengine by adding memory and irq resources both
  69 to platform file device and Device Tree node.
  70 Don't use BCM_DMAMAN_DRIVER_NAME so we don't have to include mach/dma.h
  71
  72 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
  73
  74 dmaengine: bcm2708: Merge with arch dma.c driver and disable dma.c
  75
  76 Merge the legacy DMA API driver with bcm2708-dmaengine.
  77 This is done so we can use bcm2708_fb on ARCH_BCM2835 (mailbox
  78 driver is also needed).
  79
  80 Changes to the dma.c code:
  81 - Use BIT() macro.
  82 - Cutdown some comments to one line.
  83 - Add mutex to vc_dmaman and use this, since the dev lock is locked
  84   during probing of the engine part.
  85 - Add global g_dmaman variable since drvdata is used by the engine part.
  86 - Restructure for readability:
  87   vc_dmaman_chan_alloc()
  88   vc_dmaman_chan_free()
  89   bcm_dma_chan_free()
  90 - Restructure bcm_dma_chan_alloc() to simplify error handling.
  91 - Use device irq resources instead of hardcoded bcm_dma_irqs table.
  92 - Remove dev_dmaman_register() and code it directly.
  93 - Remove dev_dmaman_deregister() and code it directly.
  94 - Simplify bcm_dmaman_probe() using devm_* functions.
  95 - Get dmachans from DT if available.
  96 - Keep 'dma.dmachans' module argument name for backwards compatibility.
  97
  98 Make it available on ARCH_BCM2835 as well.
  99
 100 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 101
 102 dmaengine: bcm2708: set residue_granularity field
 103
 104 bcm2708-dmaengine supports residue reporting at burst level
 105 but didn't report this via the residue_granularity field.
 106
 107 Without this field set properly we get playback issues with I2S cards.
 108
 109 dmaengine: bcm2708-dmaengine: Fix memory leak when stopping a running transfer
 110
 111 bcm2708-dmaengine: Use more DMA channels (but not 12)
 112
 113 1) Only the bcm2708_fb drivers uses the legacy DMA API, and
 114 it requires a BULK-capable channel, so all other types
 115 (FAST, NORMAL and LITE) can be made available to the regular
 116 DMA API.
 117
 118 2) DMA channels 11-14 share an interrupt. The driver can't
 119 handle this, so don't use channels 12-14 (12 was used, probably
 120 because it appears to have an interrupt, but in reality that
 121 interrupt is for activity on ANY channel). This may explain
 122 a lockup encountered when running out of DMA channels.
 123
 124 The combined effect of this patch is to leave 7 DMA channels
 125 available + channel 0 for bcm2708_fb via the legacy API.
 126
 127 See: https://github.com/raspberrypi/linux/issues/1110
 128      https://github.com/raspberrypi/linux/issues/1108
 129
 130 dmaengine: bcm2708: Make legacy API available for bcm2835-dma
 131
 132 bcm2708_fb uses the legacy DMA API, so in order to start using
 133 bcm2835-dma, bcm2835-dma has to support the legacy API. Make this
 134 possible by exporting bcm_dmaman_probe() and bcm_dmaman_remove().
 135
 136 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 137
 138 dmaengine: bcm2708: Change DT compatible string
 139
 140 Both bcm2835-dma and bcm2708-dmaengine have the same compatible string.
 141 So change compatible to "brcm,bcm2708-dma".
 142
 143 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 144
 145 dmaengine: bcm2708: Remove driver but keep legacy API
 146
 147 Dropping non-DT support means we don't need this driver,
 148 but we still need the legacy DMA API.
 149
 150 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
 151 ---
 152  drivers/dma/Kconfig                       |   4 +
 153  drivers/dma/Makefile                      |   1 +
 154  drivers/dma/bcm2708-dmaengine.c           | 281 ++++++++++++++++++++++++++++++
 155  include/linux/platform_data/dma-bcm2708.h | 143 +++++++++++++++
 156  4 files changed, 429 insertions(+)
 157  create mode 100644 drivers/dma/bcm2708-dmaengine.c
 158  create mode 100644 include/linux/platform_data/dma-bcm2708.h
 159
 160 --- a/drivers/dma/Kconfig
 161 +++ b/drivers/dma/Kconfig
 162 @@ -470,6 +470,10 @@ config TIMB_DMA
 163         help
 164           Enable support for the Timberdale FPGA DMA engine.
 165
 166 +config DMA_BCM2708
 167 +       tristate "BCM2708 DMA legacy API support"
 168 +       depends on DMA_BCM2835
 169 +
 170  config TI_CPPI41
 171         tristate "AM33xx CPPI41 DMA support"
 172         depends on ARCH_OMAP
 173 --- a/drivers/dma/Makefile
 174 +++ b/drivers/dma/Makefile
 175 @@ -18,6 +18,7 @@ obj-$(CONFIG_AT_HDMAC) += at_hdmac.o
 176  obj-$(CONFIG_AT_XDMAC) += at_xdmac.o
 177  obj-$(CONFIG_AXI_DMAC) += dma-axi-dmac.o
 178  obj-$(CONFIG_COH901318) += coh901318.o coh901318_lli.o
 179 +obj-$(CONFIG_DMA_BCM2708) += bcm2708-dmaengine.o
 180  obj-$(CONFIG_DMA_BCM2835) += bcm2835-dma.o
 181  obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
 182  obj-$(CONFIG_DMA_JZ4780) += dma-jz4780.o
 183 --- /dev/null
 184 +++ b/drivers/dma/bcm2708-dmaengine.c
 185 @@ -0,0 +1,281 @@
 186 +/*
 187 + * BCM2708 legacy DMA API
 188 + *
 189 + * This program is free software; you can redistribute it and/or modify
 190 + * it under the terms of the GNU General Public License as published by
 191 + * the Free Software Foundation; either version 2 of the License, or
 192 + * (at your option) any later version.
 193 + *
 194 + * This program is distributed in the hope that it will be useful,
 195 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 196 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 197 + * GNU General Public License for more details.
 198 + */
 199 +
 200 +#include <linux/init.h>
 201 +#include <linux/interrupt.h>
 202 +#include <linux/list.h>
 203 +#include <linux/module.h>
 204 +#include <linux/platform_data/dma-bcm2708.h>
 205 +#include <linux/platform_device.h>
 206 +#include <linux/slab.h>
 207 +#include <linux/io.h>
 208 +#include <linux/spinlock.h>
 209 +
 210 +#include "virt-dma.h"
 211 +
 212 +#define CACHE_LINE_MASK 31
 213 +#define DEFAULT_DMACHAN_BITMAP 0x10  /* channel 4 only */
 214 +
 215 +/* valid only for channels 0 - 14, 15 has its own base address */
 216 +#define BCM2708_DMA_CHAN(n)    ((n) << 8) /* base address */
 217 +#define BCM2708_DMA_CHANIO(dma_base, n) \
 218 +       ((void __iomem *)((char *)(dma_base) + BCM2708_DMA_CHAN(n)))
 219 +
 220 +struct vc_dmaman {
 221 +       void __iomem *dma_base;
 222 +       u32 chan_available; /* bitmap of available channels */
 223 +       u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
 224 +       struct mutex lock;
 225 +};
 226 +
 227 +static struct device *dmaman_dev;      /* we assume there's only one! */
 228 +static struct vc_dmaman *g_dmaman;     /* DMA manager */
 229 +
 230 +/* DMA Auxiliary Functions */
 231 +
 232 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
 233 +   section inside the DMA buffer and another section outside it.
 234 +   Even if we flush DMA buffers from the cache there is always the chance that
 235 +   during a DMA someone will access the part of a cache line that is outside
 236 +   the DMA buffer - which will then bring in unwelcome data.
 237 +   Without being able to dictate our own buffer pools we must insist that
 238 +   DMA buffers consist of a whole number of cache lines.
 239 +*/
 240 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
 241 +{
 242 +       int i;
 243 +
 244 +       for (i = 0; i < sg_len; i++) {
 245 +               if (sg_ptr[i].offset & CACHE_LINE_MASK ||
 246 +                   sg_ptr[i].length & CACHE_LINE_MASK)
 247 +                       return 0;
 248 +       }
 249 +
 250 +       return 1;
 251 +}
 252 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
 253 +
 254 +extern void bcm_dma_start(void __iomem *dma_chan_base,
 255 +                         dma_addr_t control_block)
 256 +{
 257 +       dsb();  /* ARM data synchronization (push) operation */
 258 +
 259 +       writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
 260 +       writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
 261 +}
 262 +EXPORT_SYMBOL_GPL(bcm_dma_start);
 263 +
 264 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
 265 +{
 266 +       dsb();
 267 +
 268 +       /* ugly busy wait only option for now */
 269 +       while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
 270 +               cpu_relax();
 271 +}
 272 +EXPORT_SYMBOL_GPL(bcm_dma_wait_idle);
 273 +
 274 +extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
 275 +{
 276 +       dsb();
 277 +
 278 +       return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
 279 +}
 280 +EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
 281 +
 282 +/* Complete an ongoing DMA (assuming its results are to be ignored)
 283 +   Does nothing if there is no DMA in progress.
 284 +   This routine waits for the current AXI transfer to complete before
 285 +   terminating the current DMA. If the current transfer is hung on a DREQ used
 286 +   by an uncooperative peripheral the AXI transfer may never complete. In this
 287 +   case the routine times out and return a non-zero error code.
 288 +   Use of this routine doesn't guarantee that the ongoing or aborted DMA
 289 +   does not produce an interrupt.
 290 +*/
 291 +extern int bcm_dma_abort(void __iomem *dma_chan_base)
 292 +{
 293 +       unsigned long int cs;
 294 +       int rc = 0;
 295 +
 296 +       cs = readl(dma_chan_base + BCM2708_DMA_CS);
 297 +
 298 +       if (BCM2708_DMA_ACTIVE & cs) {
 299 +               long int timeout = 10000;
 300 +
 301 +               /* write 0 to the active bit - pause the DMA */
 302 +               writel(0, dma_chan_base + BCM2708_DMA_CS);
 303 +
 304 +               /* wait for any current AXI transfer to complete */
 305 +               while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
 306 +                       cs = readl(dma_chan_base + BCM2708_DMA_CS);
 307 +
 308 +               if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
 309 +                       /* we'll un-pause when we set of our next DMA */
 310 +                       rc = -ETIMEDOUT;
 311 +
 312 +               } else if (BCM2708_DMA_ACTIVE & cs) {
 313 +                       /* terminate the control block chain */
 314 +                       writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
 315 +
 316 +                       /* abort the whole DMA */
 317 +                       writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
 318 +                              dma_chan_base + BCM2708_DMA_CS);
 319 +               }
 320 +       }
 321 +
 322 +       return rc;
 323 +}
 324 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
 325 +
 326 + /* DMA Manager Device Methods */
 327 +
 328 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
 329 +                          u32 chans_available)
 330 +{
 331 +       dmaman->dma_base = dma_base;
 332 +       dmaman->chan_available = chans_available;
 333 +       dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c;  /* 2 & 3 */
 334 +       dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01;  /* 0 */
 335 +       dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe;  /* 1 to 7 */
 336 +       dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00;  /* 8 to 14 */
 337 +}
 338 +
 339 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
 340 +                               unsigned required_feature_set)
 341 +{
 342 +       u32 chans;
 343 +       int chan = 0;
 344 +       int feature;
 345 +
 346 +       chans = dmaman->chan_available;
 347 +       for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
 348 +               /* select the subset of available channels with the desired
 349 +                  features */
 350 +               if (required_feature_set & (1 << feature))
 351 +                       chans &= dmaman->has_feature[feature];
 352 +
 353 +       if (!chans)
 354 +               return -ENOENT;
 355 +
 356 +       /* return the ordinal of the first channel in the bitmap */
 357 +       while (chans != 0 && (chans & 1) == 0) {
 358 +               chans >>= 1;
 359 +               chan++;
 360 +       }
 361 +       /* claim the channel */
 362 +       dmaman->chan_available &= ~(1 << chan);
 363 +
 364 +       return chan;
 365 +}
 366 +
 367 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
 368 +{
 369 +       if (chan < 0)
 370 +               return -EINVAL;
 371 +
 372 +       if ((1 << chan) & dmaman->chan_available)
 373 +               return -EIDRM;
 374 +
 375 +       dmaman->chan_available |= (1 << chan);
 376 +
 377 +       return 0;
 378 +}
 379 +
 380 +/* DMA Manager Monitor */
 381 +
 382 +extern int bcm_dma_chan_alloc(unsigned required_feature_set,
 383 +                             void __iomem **out_dma_base, int *out_dma_irq)
 384 +{
 385 +       struct vc_dmaman *dmaman = g_dmaman;
 386 +       struct platform_device *pdev = to_platform_device(dmaman_dev);
 387 +       struct resource *r;
 388 +       int chan;
 389 +
 390 +       if (!dmaman_dev)
 391 +               return -ENODEV;
 392 +
 393 +       mutex_lock(&dmaman->lock);
 394 +       chan = vc_dmaman_chan_alloc(dmaman, required_feature_set);
 395 +       if (chan < 0)
 396 +               goto out;
 397 +
 398 +       r = platform_get_resource(pdev, IORESOURCE_IRQ, (unsigned int)chan);
 399 +       if (!r) {
 400 +               dev_err(dmaman_dev, "failed to get irq for DMA channel %d\n",
 401 +                       chan);
 402 +               vc_dmaman_chan_free(dmaman, chan);
 403 +               chan = -ENOENT;
 404 +               goto out;
 405 +       }
 406 +
 407 +       *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, chan);
 408 +       *out_dma_irq = r->start;
 409 +       dev_dbg(dmaman_dev,
 410 +               "Legacy API allocated channel=%d, base=%p, irq=%i\n",
 411 +               chan, *out_dma_base, *out_dma_irq);
 412 +
 413 +out:
 414 +       mutex_unlock(&dmaman->lock);
 415 +
 416 +       return chan;
 417 +}
 418 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
 419 +
 420 +extern int bcm_dma_chan_free(int channel)
 421 +{
 422 +       struct vc_dmaman *dmaman = g_dmaman;
 423 +       int rc;
 424 +
 425 +       if (!dmaman_dev)
 426 +               return -ENODEV;
 427 +
 428 +       mutex_lock(&dmaman->lock);
 429 +       rc = vc_dmaman_chan_free(dmaman, channel);
 430 +       mutex_unlock(&dmaman->lock);
 431 +
 432 +       return rc;
 433 +}
 434 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
 435 +
 436 +int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base,
 437 +                    u32 chans_available)
 438 +{
 439 +       struct device *dev = &pdev->dev;
 440 +       struct vc_dmaman *dmaman;
 441 +
 442 +       dmaman = devm_kzalloc(dev, sizeof(*dmaman), GFP_KERNEL);
 443 +       if (!dmaman)
 444 +               return -ENOMEM;
 445 +
 446 +       mutex_init(&dmaman->lock);
 447 +       vc_dmaman_init(dmaman, base, chans_available);
 448 +       g_dmaman = dmaman;
 449 +       dmaman_dev = dev;
 450 +
 451 +       dev_info(dev, "DMA legacy API manager at %p, dmachans=0x%x\n",
 452 +                base, chans_available);
 453 +
 454 +       return 0;
 455 +}
 456 +EXPORT_SYMBOL(bcm_dmaman_probe);
 457 +
 458 +int bcm_dmaman_remove(struct platform_device *pdev)
 459 +{
 460 +       dmaman_dev = NULL;
 461 +
 462 +       return 0;
 463 +}
 464 +EXPORT_SYMBOL(bcm_dmaman_remove);
 465 +
 466 +MODULE_LICENSE("GPL");
 467 --- /dev/null
 468 +++ b/include/linux/platform_data/dma-bcm2708.h
 469 @@ -0,0 +1,143 @@
 470 +/*
 471 + *  Copyright (C) 2010 Broadcom
 472 + *
 473 + * This program is free software; you can redistribute it and/or modify
 474 + * it under the terms of the GNU General Public License version 2 as
 475 + * published by the Free Software Foundation.
 476 + */
 477 +
 478 +#ifndef _PLAT_BCM2708_DMA_H
 479 +#define _PLAT_BCM2708_DMA_H
 480 +
 481 +/* DMA CS Control and Status bits */
 482 +#define BCM2708_DMA_ACTIVE     BIT(0)
 483 +#define BCM2708_DMA_INT                BIT(2)
 484 +#define BCM2708_DMA_ISPAUSED   BIT(4)  /* Pause requested or not active */
 485 +#define BCM2708_DMA_ISHELD     BIT(5)  /* Is held by DREQ flow control */
 486 +#define BCM2708_DMA_ERR                BIT(8)
 487 +#define BCM2708_DMA_ABORT      BIT(30) /* stop current CB, go to next, WO */
 488 +#define BCM2708_DMA_RESET      BIT(31) /* WO, self clearing */
 489 +
 490 +/* DMA control block "info" field bits */
 491 +#define BCM2708_DMA_INT_EN     BIT(0)
 492 +#define BCM2708_DMA_TDMODE     BIT(1)
 493 +#define BCM2708_DMA_WAIT_RESP  BIT(3)
 494 +#define BCM2708_DMA_D_INC      BIT(4)
 495 +#define BCM2708_DMA_D_WIDTH    BIT(5)
 496 +#define BCM2708_DMA_D_DREQ     BIT(6)
 497 +#define BCM2708_DMA_S_INC      BIT(8)
 498 +#define BCM2708_DMA_S_WIDTH    BIT(9)
 499 +#define BCM2708_DMA_S_DREQ     BIT(10)
 500 +
 501 +#define        BCM2708_DMA_BURST(x)    (((x) & 0xf) << 12)
 502 +#define        BCM2708_DMA_PER_MAP(x)  ((x) << 16)
 503 +#define        BCM2708_DMA_WAITS(x)    (((x) & 0x1f) << 21)
 504 +
 505 +#define BCM2708_DMA_DREQ_EMMC  11
 506 +#define BCM2708_DMA_DREQ_SDHOST        13
 507 +
 508 +#define BCM2708_DMA_CS         0x00 /* Control and Status */
 509 +#define BCM2708_DMA_ADDR       0x04
 510 +/* the current control block appears in the following registers - read only */
 511 +#define BCM2708_DMA_INFO       0x08
 512 +#define BCM2708_DMA_SOURCE_AD  0x0c
 513 +#define BCM2708_DMA_DEST_AD    0x10
 514 +#define BCM2708_DMA_NEXTCB     0x1C
 515 +#define BCM2708_DMA_DEBUG      0x20
 516 +
 517 +#define BCM2708_DMA4_CS                (BCM2708_DMA_CHAN(4) + BCM2708_DMA_CS)
 518 +#define BCM2708_DMA4_ADDR      (BCM2708_DMA_CHAN(4) + BCM2708_DMA_ADDR)
 519 +
 520 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
 521 +
 522 +/* When listing features we can ask for when allocating DMA channels give
 523 +   those with higher priority smaller ordinal numbers */
 524 +#define BCM_DMA_FEATURE_FAST_ORD       0
 525 +#define BCM_DMA_FEATURE_BULK_ORD       1
 526 +#define BCM_DMA_FEATURE_NORMAL_ORD     2
 527 +#define BCM_DMA_FEATURE_LITE_ORD       3
 528 +#define BCM_DMA_FEATURE_FAST           BIT(BCM_DMA_FEATURE_FAST_ORD)
 529 +#define BCM_DMA_FEATURE_BULK           BIT(BCM_DMA_FEATURE_BULK_ORD)
 530 +#define BCM_DMA_FEATURE_NORMAL         BIT(BCM_DMA_FEATURE_NORMAL_ORD)
 531 +#define BCM_DMA_FEATURE_LITE           BIT(BCM_DMA_FEATURE_LITE_ORD)
 532 +#define BCM_DMA_FEATURE_COUNT          4
 533 +
 534 +struct bcm2708_dma_cb {
 535 +       unsigned long info;
 536 +       unsigned long src;
 537 +       unsigned long dst;
 538 +       unsigned long length;
 539 +       unsigned long stride;
 540 +       unsigned long next;
 541 +       unsigned long pad[2];
 542 +};
 543 +
 544 +struct scatterlist;
 545 +struct platform_device;
 546 +
 547 +#ifdef CONFIG_DMA_BCM2708
 548 +
 549 +int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
 550 +void bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block);
 551 +void bcm_dma_wait_idle(void __iomem *dma_chan_base);
 552 +bool bcm_dma_is_busy(void __iomem *dma_chan_base);
 553 +int bcm_dma_abort(void __iomem *dma_chan_base);
 554 +
 555 +/* return channel no or -ve error */
 556 +int bcm_dma_chan_alloc(unsigned preferred_feature_set,
 557 +                      void __iomem **out_dma_base, int *out_dma_irq);
 558 +int bcm_dma_chan_free(int channel);
 559 +
 560 +int bcm_dmaman_probe(struct platform_device *pdev, void __iomem *base,
 561 +                    u32 chans_available);
 562 +int bcm_dmaman_remove(struct platform_device *pdev);
 563 +
 564 +#else /* CONFIG_DMA_BCM2708 */
 565 +
 566 +static inline int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr,
 567 +                                         int sg_len)
 568 +{
 569 +       return 0;
 570 +}
 571 +
 572 +static inline void bcm_dma_start(void __iomem *dma_chan_base,
 573 +                                dma_addr_t control_block) { }
 574 +
 575 +static inline void bcm_dma_wait_idle(void __iomem *dma_chan_base) { }
 576 +
 577 +static inline bool bcm_dma_is_busy(void __iomem *dma_chan_base)
 578 +{
 579 +       return false;
 580 +}
 581 +
 582 +static inline int bcm_dma_abort(void __iomem *dma_chan_base)
 583 +{
 584 +       return -EINVAL;
 585 +}
 586 +
 587 +static inline int bcm_dma_chan_alloc(unsigned preferred_feature_set,
 588 +                                    void __iomem **out_dma_base,
 589 +                                    int *out_dma_irq)
 590 +{
 591 +       return -EINVAL;
 592 +}
 593 +
 594 +static inline int bcm_dma_chan_free(int channel)
 595 +{
 596 +       return -EINVAL;
 597 +}
 598 +
 599 +static inline int bcm_dmaman_probe(struct platform_device *pdev,
 600 +                                  void __iomem *base, u32 chans_available)
 601 +{
 602 +       return 0;
 603 +}
 604 +
 605 +static inline int bcm_dmaman_remove(struct platform_device *pdev)
 606 +{
 607 +       return 0;
 608 +}
 609 +
 610 +#endif /* CONFIG_DMA_BCM2708 */
 611 +
 612 +#endif /* _PLAT_BCM2708_DMA_H */