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kernel: bump 4.9 to 4.9.96
[openwrt/staging/wigyori.git] / target / linux / brcm2708 / patches-4.9 / 950-0034-MMC-added-alternative-MMC-driver.patch
1 From 1620619c5fa6acae1e119d6461b5c9a2a9416e69 Mon Sep 17 00:00:00 2001
2 From: gellert <gellert@raspberrypi.org>
3 Date: Fri, 15 Aug 2014 16:35:06 +0100
4 Subject: [PATCH] MMC: added alternative MMC driver
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 mmc: Disable CMD23 transfers on all cards
10
11 Pending wire-level investigation of these types of transfers
12 and associated errors on bcm2835-mmc, disable for now. Fallback of
13 CMD18/CMD25 transfers will be used automatically by the MMC layer.
14
15 Reported/Tested-by: Gellert Weisz <gellert@raspberrypi.org>
16
17 mmc: bcm2835-mmc: enable DT support for all architectures
18
19 Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now.
20 Enable Device Tree support for all architectures.
21
22 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
23
24 mmc: bcm2835-mmc: fix probe error handling
25
26 Probe error handling is broken in several places.
27 Simplify error handling by using device managed functions.
28 Replace pr_{err,info} with dev_{err,info}.
29
30 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
31
32 bcm2835-mmc: Add locks when accessing sdhost registers
33
34 bcm2835-mmc: Add range of debug options for slowing things down
35
36 bcm2835-mmc: Add option to disable some delays
37
38 bcm2835-mmc: Add option to disable MMC_QUIRK_BLK_NO_CMD23
39
40 bcm2835-mmc: Default to disabling MMC_QUIRK_BLK_NO_CMD23
41
42 bcm2835-mmc: Adding overclocking option
43
44 Allow a different clock speed to be substitued for a requested 50MHz.
45 This option is exposed using the "overclock_50" DT parameter.
46 Note that the mmc interface is restricted to EVEN integer divisions of
47 250MHz, and the highest sensible option is 63 (250/4 = 62.5), the
48 next being 125 (250/2) which is much too high.
49
50 Use at your own risk.
51
52 bcm2835-mmc: Round up the overclock, so 62 works for 62.5Mhz
53
54 Also only warn once for each overclock setting.
55
56 mmc: bcm2835-mmc: Make available on ARCH_BCM2835
57
58 Make the bcm2835-mmc driver available for use on ARCH_BCM2835.
59
60 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
61
62 BCM270x_DT: add bcm2835-mmc entry
63
64 Add Device Tree entry for bcm2835-mmc.
65 In non-DT mode, don't add the device in the board file.
66
67 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
68
69 bcm2835-mmc: Don't overwrite MMC capabilities from DT
70
71 bcm2835-mmc: Don't override bus width capabilities from devicetree
72
73 Take out the force setting of the MMC_CAP_4_BIT_DATA host capability
74 so that the result read from devicetree via mmc_of_parse() is
75 preserved.
76
77 bcm2835-mmc: Only claim one DMA channel
78
79 With both MMC controllers enabled there are few DMA channels left. The
80 bcm2835-mmc driver only uses DMA in one direction at a time, so it
81 doesn't need to claim two channels.
82
83 See: https://github.com/raspberrypi/linux/issues/1327
84
85 Signed-off-by: Phil Elwell <phil@raspberrypi.org>
86 ---
87 drivers/mmc/core/quirks.c | 10 +
88 drivers/mmc/host/Kconfig | 29 +
89 drivers/mmc/host/Makefile | 1 +
90 drivers/mmc/host/bcm2835-mmc.c | 1574 ++++++++++++++++++++++++++++++++++++++++
91 4 files changed, 1614 insertions(+)
92 create mode 100644 drivers/mmc/host/bcm2835-mmc.c
93
94 --- a/drivers/mmc/core/quirks.c
95 +++ b/drivers/mmc/core/quirks.c
96 @@ -53,6 +53,9 @@ static const struct mmc_fixup mmc_fixup_
97
98 void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table)
99 {
100 +#ifdef CONFIG_MMC_BCM2835
101 + extern unsigned mmc_debug;
102 +#endif
103 const struct mmc_fixup *f;
104 u64 rev = cid_rev_card(card);
105
106 @@ -79,5 +82,12 @@ void mmc_fixup_device(struct mmc_card *c
107 f->vendor_fixup(card, f->data);
108 }
109 }
110 + /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail.
111 + * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers).
112 + */
113 +#ifdef CONFIG_MMC_BCM2835
114 + if (mmc_debug & (1<<13))
115 + card->quirks |= MMC_QUIRK_BLK_NO_CMD23;
116 +#endif
117 }
118 EXPORT_SYMBOL(mmc_fixup_device);
119 --- a/drivers/mmc/host/Kconfig
120 +++ b/drivers/mmc/host/Kconfig
121 @@ -4,6 +4,35 @@
122
123 comment "MMC/SD/SDIO Host Controller Drivers"
124
125 +config MMC_BCM2835
126 + tristate "MMC support on BCM2835"
127 + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
128 + help
129 + This selects the MMC Interface on BCM2835.
130 +
131 + If you have a controller with this interface, say Y or M here.
132 +
133 + If unsure, say N.
134 +
135 +config MMC_BCM2835_DMA
136 + bool "DMA support on BCM2835 Arasan controller"
137 + depends on MMC_BCM2835
138 + help
139 + Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
140 + based chips.
141 +
142 + If unsure, say N.
143 +
144 +config MMC_BCM2835_PIO_DMA_BARRIER
145 + int "Block count limit for PIO transfers"
146 + depends on MMC_BCM2835 && MMC_BCM2835_DMA
147 + range 0 256
148 + default 2
149 + help
150 + The inclusive limit in bytes under which PIO will be used instead of DMA
151 +
152 + If unsure, say 2 here.
153 +
154 config MMC_ARMMMCI
155 tristate "ARM AMBA Multimedia Card Interface support"
156 depends on ARM_AMBA
157 --- a/drivers/mmc/host/Makefile
158 +++ b/drivers/mmc/host/Makefile
159 @@ -18,6 +18,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c
160 obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
161 obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
162 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
163 +obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o
164 obj-$(CONFIG_MMC_WBSD) += wbsd.o
165 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
166 obj-$(CONFIG_MMC_MTK) += mtk-sd.o
167 --- /dev/null
168 +++ b/drivers/mmc/host/bcm2835-mmc.c
169 @@ -0,0 +1,1574 @@
170 +/*
171 + * BCM2835 MMC host driver.
172 + *
173 + * Author: Gellert Weisz <gellert@raspberrypi.org>
174 + * Copyright 2014
175 + *
176 + * Based on
177 + * sdhci-bcm2708.c by Broadcom
178 + * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
179 + * sdhci.c and sdhci-pci.c by Pierre Ossman
180 + *
181 + * This program is free software; you can redistribute it and/or modify it
182 + * under the terms and conditions of the GNU General Public License,
183 + * version 2, as published by the Free Software Foundation.
184 + *
185 + * This program is distributed in the hope it will be useful, but WITHOUT
186 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
187 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
188 + * more details.
189 + *
190 + * You should have received a copy of the GNU General Public License
191 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
192 + */
193 +
194 +#include <linux/delay.h>
195 +#include <linux/module.h>
196 +#include <linux/io.h>
197 +#include <linux/mmc/mmc.h>
198 +#include <linux/mmc/host.h>
199 +#include <linux/mmc/sd.h>
200 +#include <linux/scatterlist.h>
201 +#include <linux/of_address.h>
202 +#include <linux/of_irq.h>
203 +#include <linux/clk.h>
204 +#include <linux/platform_device.h>
205 +#include <linux/err.h>
206 +#include <linux/blkdev.h>
207 +#include <linux/dmaengine.h>
208 +#include <linux/dma-mapping.h>
209 +#include <linux/of_dma.h>
210 +
211 +#include "sdhci.h"
212 +
213 +
214 +#define DRIVER_NAME "mmc-bcm2835"
215 +
216 +#define DBG(f, x...) \
217 +pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
218 +
219 +#ifndef CONFIG_MMC_BCM2835_DMA
220 + #define FORCE_PIO
221 +#endif
222 +
223 +
224 +/* the inclusive limit in bytes under which PIO will be used instead of DMA */
225 +#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
226 +#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
227 +#else
228 +#define PIO_DMA_BARRIER 00
229 +#endif
230 +
231 +#define MIN_FREQ 400000
232 +#define TIMEOUT_VAL 0xE
233 +#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1)
234 +
235 +
236 +unsigned mmc_debug;
237 +unsigned mmc_debug2;
238 +
239 +struct bcm2835_host {
240 + spinlock_t lock;
241 +
242 + void __iomem *ioaddr;
243 + u32 bus_addr;
244 +
245 + struct mmc_host *mmc;
246 +
247 + u32 timeout;
248 +
249 + int clock; /* Current clock speed */
250 + u8 pwr; /* Current voltage */
251 +
252 + unsigned int max_clk; /* Max possible freq */
253 + unsigned int timeout_clk; /* Timeout freq (KHz) */
254 + unsigned int clk_mul; /* Clock Muliplier value */
255 +
256 + struct tasklet_struct finish_tasklet; /* Tasklet structures */
257 +
258 + struct timer_list timer; /* Timer for timeouts */
259 +
260 + struct sg_mapping_iter sg_miter; /* SG state for PIO */
261 + unsigned int blocks; /* remaining PIO blocks */
262 +
263 + int irq; /* Device IRQ */
264 +
265 +
266 + u32 ier; /* cached registers */
267 +
268 + struct mmc_request *mrq; /* Current request */
269 + struct mmc_command *cmd; /* Current command */
270 + struct mmc_data *data; /* Current data request */
271 + unsigned int data_early:1; /* Data finished before cmd */
272 +
273 + wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
274 +
275 + u32 thread_isr;
276 +
277 + u32 shadow;
278 +
279 + /*DMA part*/
280 + struct dma_chan *dma_chan_rxtx; /* DMA channel for reads and writes */
281 + struct dma_slave_config dma_cfg_rx;
282 + struct dma_slave_config dma_cfg_tx;
283 + struct dma_async_tx_descriptor *tx_desc; /* descriptor */
284 +
285 + bool have_dma;
286 + bool use_dma;
287 + /*end of DMA part*/
288 +
289 + int max_delay; /* maximum length of time spent waiting */
290 +
291 + int flags; /* Host attributes */
292 +#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
293 +#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
294 +#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
295 +#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
296 +#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
297 +
298 + u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
299 + u32 max_overclock; /* Highest reported */
300 +};
301 +
302 +
303 +static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from)
304 +{
305 + unsigned delay;
306 + lockdep_assert_held_once(&host->lock);
307 + writel(val, host->ioaddr + reg);
308 + udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));
309 +
310 + delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf);
311 + if (delay && !((1<<from) & mmc_debug2))
312 + udelay(delay);
313 +}
314 +
315 +static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)
316 +{
317 + unsigned delay;
318 + lockdep_assert_held_once(&host->lock);
319 + writel(val, host->ioaddr + reg);
320 +
321 + delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf);
322 + if (delay)
323 + udelay(delay);
324 +}
325 +
326 +static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)
327 +{
328 + lockdep_assert_held_once(&host->lock);
329 + return readl(host->ioaddr + reg);
330 +}
331 +
332 +static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)
333 +{
334 + u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :
335 + bcm2835_mmc_readl(host, reg & ~3);
336 + u32 word_num = (reg >> 1) & 1;
337 + u32 word_shift = word_num * 16;
338 + u32 mask = 0xffff << word_shift;
339 + u32 newval = (oldval & ~mask) | (val << word_shift);
340 +
341 + if (reg == SDHCI_TRANSFER_MODE)
342 + host->shadow = newval;
343 + else
344 + bcm2835_mmc_writel(host, newval, reg & ~3, 0);
345 +
346 +}
347 +
348 +static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)
349 +{
350 + u32 oldval = bcm2835_mmc_readl(host, reg & ~3);
351 + u32 byte_num = reg & 3;
352 + u32 byte_shift = byte_num * 8;
353 + u32 mask = 0xff << byte_shift;
354 + u32 newval = (oldval & ~mask) | (val << byte_shift);
355 +
356 + bcm2835_mmc_writel(host, newval, reg & ~3, 1);
357 +}
358 +
359 +
360 +static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)
361 +{
362 + u32 val = bcm2835_mmc_readl(host, (reg & ~3));
363 + u32 word_num = (reg >> 1) & 1;
364 + u32 word_shift = word_num * 16;
365 + u32 word = (val >> word_shift) & 0xffff;
366 +
367 + return word;
368 +}
369 +
370 +static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)
371 +{
372 + u32 val = bcm2835_mmc_readl(host, (reg & ~3));
373 + u32 byte_num = reg & 3;
374 + u32 byte_shift = byte_num * 8;
375 + u32 byte = (val >> byte_shift) & 0xff;
376 +
377 + return byte;
378 +}
379 +
380 +static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)
381 +{
382 + u32 ier;
383 +
384 + ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);
385 + ier &= ~clear;
386 + /* change which requests generate IRQs - makes no difference to
387 + the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
388 + bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2);
389 +}
390 +
391 +
392 +static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)
393 +{
394 + pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
395 + mmc_hostname(host->mmc));
396 +
397 + pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
398 + bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),
399 + bcm2835_mmc_readw(host, SDHCI_HOST_VERSION));
400 + pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
401 + bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),
402 + bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));
403 + pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
404 + bcm2835_mmc_readl(host, SDHCI_ARGUMENT),
405 + bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));
406 + pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
407 + bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),
408 + bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));
409 + pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
410 + bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),
411 + bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));
412 + pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
413 + bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),
414 + bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));
415 + pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
416 + bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),
417 + bcm2835_mmc_readl(host, SDHCI_INT_STATUS));
418 + pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
419 + bcm2835_mmc_readl(host, SDHCI_INT_ENABLE),
420 + bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));
421 + pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
422 + bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR),
423 + bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));
424 + pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
425 + bcm2835_mmc_readl(host, SDHCI_CAPABILITIES),
426 + bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));
427 + pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
428 + bcm2835_mmc_readw(host, SDHCI_COMMAND),
429 + bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));
430 + pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
431 + bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));
432 +
433 + pr_debug(DRIVER_NAME ": ===========================================\n");
434 +}
435 +
436 +
437 +static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)
438 +{
439 + unsigned long timeout;
440 + unsigned long flags;
441 +
442 + spin_lock_irqsave(&host->lock, flags);
443 + bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
444 +
445 + if (mask & SDHCI_RESET_ALL)
446 + host->clock = 0;
447 +
448 + /* Wait max 100 ms */
449 + timeout = 100;
450 +
451 + /* hw clears the bit when it's done */
452 + while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
453 + if (timeout == 0) {
454 + pr_err("%s: Reset 0x%x never completed.\n",
455 + mmc_hostname(host->mmc), (int)mask);
456 + bcm2835_mmc_dumpregs(host);
457 + return;
458 + }
459 + timeout--;
460 + spin_unlock_irqrestore(&host->lock, flags);
461 + mdelay(1);
462 + spin_lock_irqsave(&host->lock, flags);
463 + }
464 +
465 + if (100-timeout > 10 && 100-timeout > host->max_delay) {
466 + host->max_delay = 100-timeout;
467 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
468 + }
469 + spin_unlock_irqrestore(&host->lock, flags);
470 +}
471 +
472 +static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
473 +
474 +static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)
475 +{
476 + unsigned long flags;
477 + if (soft)
478 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
479 + else
480 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
481 +
482 + host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
483 + SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
484 + SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
485 + SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
486 + SDHCI_INT_RESPONSE;
487 +
488 + spin_lock_irqsave(&host->lock, flags);
489 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3);
490 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3);
491 + spin_unlock_irqrestore(&host->lock, flags);
492 +
493 + if (soft) {
494 + /* force clock reconfiguration */
495 + host->clock = 0;
496 + bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);
497 + }
498 +}
499 +
500 +
501 +
502 +static void bcm2835_mmc_finish_data(struct bcm2835_host *host);
503 +
504 +static void bcm2835_mmc_dma_complete(void *param)
505 +{
506 + struct bcm2835_host *host = param;
507 + struct dma_chan *dma_chan;
508 + unsigned long flags;
509 + u32 dir_data;
510 +
511 + spin_lock_irqsave(&host->lock, flags);
512 +
513 + if (host->data && !(host->data->flags & MMC_DATA_WRITE)) {
514 + /* otherwise handled in SDHCI IRQ */
515 + dma_chan = host->dma_chan_rxtx;
516 + dir_data = DMA_FROM_DEVICE;
517 +
518 + dma_unmap_sg(dma_chan->device->dev,
519 + host->data->sg, host->data->sg_len,
520 + dir_data);
521 +
522 + bcm2835_mmc_finish_data(host);
523 + }
524 +
525 + spin_unlock_irqrestore(&host->lock, flags);
526 +}
527 +
528 +static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)
529 +{
530 + unsigned long flags;
531 + size_t blksize, len, chunk;
532 +
533 + u32 uninitialized_var(scratch);
534 + u8 *buf;
535 +
536 + blksize = host->data->blksz;
537 + chunk = 0;
538 +
539 + local_irq_save(flags);
540 +
541 + while (blksize) {
542 + if (!sg_miter_next(&host->sg_miter))
543 + BUG();
544 +
545 + len = min(host->sg_miter.length, blksize);
546 +
547 + blksize -= len;
548 + host->sg_miter.consumed = len;
549 +
550 + buf = host->sg_miter.addr;
551 +
552 + while (len) {
553 + if (chunk == 0) {
554 + scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);
555 + chunk = 4;
556 + }
557 +
558 + *buf = scratch & 0xFF;
559 +
560 + buf++;
561 + scratch >>= 8;
562 + chunk--;
563 + len--;
564 + }
565 + }
566 +
567 + sg_miter_stop(&host->sg_miter);
568 +
569 + local_irq_restore(flags);
570 +}
571 +
572 +static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)
573 +{
574 + unsigned long flags;
575 + size_t blksize, len, chunk;
576 + u32 scratch;
577 + u8 *buf;
578 +
579 + blksize = host->data->blksz;
580 + chunk = 0;
581 + chunk = 0;
582 + scratch = 0;
583 +
584 + local_irq_save(flags);
585 +
586 + while (blksize) {
587 + if (!sg_miter_next(&host->sg_miter))
588 + BUG();
589 +
590 + len = min(host->sg_miter.length, blksize);
591 +
592 + blksize -= len;
593 + host->sg_miter.consumed = len;
594 +
595 + buf = host->sg_miter.addr;
596 +
597 + while (len) {
598 + scratch |= (u32)*buf << (chunk * 8);
599 +
600 + buf++;
601 + chunk++;
602 + len--;
603 +
604 + if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
605 + mmc_raw_writel(host, scratch, SDHCI_BUFFER);
606 + chunk = 0;
607 + scratch = 0;
608 + }
609 + }
610 + }
611 +
612 + sg_miter_stop(&host->sg_miter);
613 +
614 + local_irq_restore(flags);
615 +}
616 +
617 +
618 +static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)
619 +{
620 + u32 mask;
621 +
622 + BUG_ON(!host->data);
623 +
624 + if (host->blocks == 0)
625 + return;
626 +
627 + if (host->data->flags & MMC_DATA_READ)
628 + mask = SDHCI_DATA_AVAILABLE;
629 + else
630 + mask = SDHCI_SPACE_AVAILABLE;
631 +
632 + while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
633 +
634 + if (host->data->flags & MMC_DATA_READ)
635 + bcm2835_bcm2835_mmc_read_block_pio(host);
636 + else
637 + bcm2835_bcm2835_mmc_write_block_pio(host);
638 +
639 + host->blocks--;
640 +
641 + /* QUIRK used in sdhci.c removes the 'if' */
642 + /* but it seems this is unnecessary */
643 + if (host->blocks == 0)
644 + break;
645 +
646 +
647 + }
648 +}
649 +
650 +
651 +static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)
652 +{
653 + u32 len, dir_data, dir_slave;
654 + struct dma_async_tx_descriptor *desc = NULL;
655 + struct dma_chan *dma_chan;
656 +
657 +
658 + WARN_ON(!host->data);
659 +
660 + if (!host->data)
661 + return;
662 +
663 + if (host->blocks == 0)
664 + return;
665 +
666 + dma_chan = host->dma_chan_rxtx;
667 + if (host->data->flags & MMC_DATA_READ) {
668 + dir_data = DMA_FROM_DEVICE;
669 + dir_slave = DMA_DEV_TO_MEM;
670 + } else {
671 + dir_data = DMA_TO_DEVICE;
672 + dir_slave = DMA_MEM_TO_DEV;
673 + }
674 +
675 + /* The parameters have already been validated, so this will not fail */
676 + (void)dmaengine_slave_config(dma_chan,
677 + (dir_data == DMA_FROM_DEVICE) ?
678 + &host->dma_cfg_rx :
679 + &host->dma_cfg_tx);
680 +
681 + BUG_ON(!dma_chan->device);
682 + BUG_ON(!dma_chan->device->dev);
683 + BUG_ON(!host->data->sg);
684 +
685 + len = dma_map_sg(dma_chan->device->dev, host->data->sg,
686 + host->data->sg_len, dir_data);
687 + if (len > 0) {
688 + desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
689 + len, dir_slave,
690 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
691 + } else {
692 + dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
693 + }
694 + if (desc) {
695 + unsigned long flags;
696 + spin_lock_irqsave(&host->lock, flags);
697 + bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
698 + SDHCI_INT_SPACE_AVAIL);
699 + host->tx_desc = desc;
700 + desc->callback = bcm2835_mmc_dma_complete;
701 + desc->callback_param = host;
702 + spin_unlock_irqrestore(&host->lock, flags);
703 + dmaengine_submit(desc);
704 + dma_async_issue_pending(dma_chan);
705 + }
706 +
707 +}
708 +
709 +
710 +
711 +static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)
712 +{
713 + u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
714 + u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
715 +
716 + if (host->use_dma)
717 + host->ier = (host->ier & ~pio_irqs) | dma_irqs;
718 + else
719 + host->ier = (host->ier & ~dma_irqs) | pio_irqs;
720 +
721 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4);
722 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4);
723 +}
724 +
725 +
726 +static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
727 +{
728 + u8 count;
729 + struct mmc_data *data = cmd->data;
730 +
731 + WARN_ON(host->data);
732 +
733 + if (data || (cmd->flags & MMC_RSP_BUSY)) {
734 + count = TIMEOUT_VAL;
735 + bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
736 + }
737 +
738 + if (!data)
739 + return;
740 +
741 + /* Sanity checks */
742 + BUG_ON(data->blksz * data->blocks > 524288);
743 + BUG_ON(data->blksz > host->mmc->max_blk_size);
744 + BUG_ON(data->blocks > 65535);
745 +
746 + host->data = data;
747 + host->data_early = 0;
748 + host->data->bytes_xfered = 0;
749 +
750 +
751 + if (!(host->flags & SDHCI_REQ_USE_DMA)) {
752 + int flags;
753 +
754 + flags = SG_MITER_ATOMIC;
755 + if (host->data->flags & MMC_DATA_READ)
756 + flags |= SG_MITER_TO_SG;
757 + else
758 + flags |= SG_MITER_FROM_SG;
759 + sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
760 + host->blocks = data->blocks;
761 + }
762 +
763 + host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
764 +
765 + bcm2835_mmc_set_transfer_irqs(host);
766 +
767 + /* Set the DMA boundary value and block size */
768 + bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
769 + data->blksz), SDHCI_BLOCK_SIZE);
770 + bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
771 +
772 + BUG_ON(!host->data);
773 +}
774 +
775 +static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,
776 + struct mmc_command *cmd)
777 +{
778 + u16 mode;
779 + struct mmc_data *data = cmd->data;
780 +
781 + if (data == NULL) {
782 + /* clear Auto CMD settings for no data CMDs */
783 + mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);
784 + bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
785 + SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
786 + return;
787 + }
788 +
789 + WARN_ON(!host->data);
790 +
791 + mode = SDHCI_TRNS_BLK_CNT_EN;
792 +
793 + if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {
794 + mode |= SDHCI_TRNS_MULTI;
795 +
796 + /*
797 + * If we are sending CMD23, CMD12 never gets sent
798 + * on successful completion (so no Auto-CMD12).
799 + */
800 + if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
801 + mode |= SDHCI_TRNS_AUTO_CMD12;
802 + else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
803 + mode |= SDHCI_TRNS_AUTO_CMD23;
804 + bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5);
805 + }
806 + }
807 +
808 + if (data->flags & MMC_DATA_READ)
809 + mode |= SDHCI_TRNS_READ;
810 + if (host->flags & SDHCI_REQ_USE_DMA)
811 + mode |= SDHCI_TRNS_DMA;
812 +
813 + bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);
814 +}
815 +
816 +void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
817 +{
818 + int flags;
819 + u32 mask;
820 + unsigned long timeout;
821 +
822 + WARN_ON(host->cmd);
823 +
824 + /* Wait max 10 ms */
825 + timeout = 1000;
826 +
827 + mask = SDHCI_CMD_INHIBIT;
828 + if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
829 + mask |= SDHCI_DATA_INHIBIT;
830 +
831 + /* We shouldn't wait for data inihibit for stop commands, even
832 + though they might use busy signaling */
833 + if (host->mrq->data && (cmd == host->mrq->data->stop))
834 + mask &= ~SDHCI_DATA_INHIBIT;
835 +
836 + while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
837 + if (timeout == 0) {
838 + pr_err("%s: Controller never released inhibit bit(s).\n",
839 + mmc_hostname(host->mmc));
840 + bcm2835_mmc_dumpregs(host);
841 + cmd->error = -EIO;
842 + tasklet_schedule(&host->finish_tasklet);
843 + return;
844 + }
845 + timeout--;
846 + udelay(10);
847 + }
848 +
849 + if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
850 + host->max_delay = (1000-timeout)/100;
851 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
852 + }
853 +
854 + timeout = jiffies;
855 + if (!cmd->data && cmd->busy_timeout > 9000)
856 + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
857 + else
858 + timeout += 10 * HZ;
859 + mod_timer(&host->timer, timeout);
860 +
861 + host->cmd = cmd;
862 +
863 + bcm2835_mmc_prepare_data(host, cmd);
864 +
865 + bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6);
866 +
867 + bcm2835_mmc_set_transfer_mode(host, cmd);
868 +
869 + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
870 + pr_err("%s: Unsupported response type!\n",
871 + mmc_hostname(host->mmc));
872 + cmd->error = -EINVAL;
873 + tasklet_schedule(&host->finish_tasklet);
874 + return;
875 + }
876 +
877 + if (!(cmd->flags & MMC_RSP_PRESENT))
878 + flags = SDHCI_CMD_RESP_NONE;
879 + else if (cmd->flags & MMC_RSP_136)
880 + flags = SDHCI_CMD_RESP_LONG;
881 + else if (cmd->flags & MMC_RSP_BUSY)
882 + flags = SDHCI_CMD_RESP_SHORT_BUSY;
883 + else
884 + flags = SDHCI_CMD_RESP_SHORT;
885 +
886 + if (cmd->flags & MMC_RSP_CRC)
887 + flags |= SDHCI_CMD_CRC;
888 + if (cmd->flags & MMC_RSP_OPCODE)
889 + flags |= SDHCI_CMD_INDEX;
890 +
891 + if (cmd->data)
892 + flags |= SDHCI_CMD_DATA;
893 +
894 + bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
895 +}
896 +
897 +
898 +static void bcm2835_mmc_finish_data(struct bcm2835_host *host)
899 +{
900 + struct mmc_data *data;
901 +
902 + BUG_ON(!host->data);
903 +
904 + data = host->data;
905 + host->data = NULL;
906 +
907 + if (data->error)
908 + data->bytes_xfered = 0;
909 + else
910 + data->bytes_xfered = data->blksz * data->blocks;
911 +
912 + /*
913 + * Need to send CMD12 if -
914 + * a) open-ended multiblock transfer (no CMD23)
915 + * b) error in multiblock transfer
916 + */
917 + if (data->stop &&
918 + (data->error ||
919 + !host->mrq->sbc)) {
920 +
921 + /*
922 + * The controller needs a reset of internal state machines
923 + * upon error conditions.
924 + */
925 + if (data->error) {
926 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
927 + bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
928 + }
929 +
930 + bcm2835_mmc_send_command(host, data->stop);
931 + } else
932 + tasklet_schedule(&host->finish_tasklet);
933 +}
934 +
935 +static void bcm2835_mmc_finish_command(struct bcm2835_host *host)
936 +{
937 + int i;
938 +
939 + BUG_ON(host->cmd == NULL);
940 +
941 + if (host->cmd->flags & MMC_RSP_PRESENT) {
942 + if (host->cmd->flags & MMC_RSP_136) {
943 + /* CRC is stripped so we need to do some shifting. */
944 + for (i = 0; i < 4; i++) {
945 + host->cmd->resp[i] = bcm2835_mmc_readl(host,
946 + SDHCI_RESPONSE + (3-i)*4) << 8;
947 + if (i != 3)
948 + host->cmd->resp[i] |=
949 + bcm2835_mmc_readb(host,
950 + SDHCI_RESPONSE + (3-i)*4-1);
951 + }
952 + } else {
953 + host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);
954 + }
955 + }
956 +
957 + host->cmd->error = 0;
958 +
959 + /* Finished CMD23, now send actual command. */
960 + if (host->cmd == host->mrq->sbc) {
961 + host->cmd = NULL;
962 + bcm2835_mmc_send_command(host, host->mrq->cmd);
963 +
964 + if (host->mrq->cmd->data && host->use_dma) {
965 + /* DMA transfer starts now, PIO starts after interrupt */
966 + bcm2835_mmc_transfer_dma(host);
967 + }
968 + } else {
969 +
970 + /* Processed actual command. */
971 + if (host->data && host->data_early)
972 + bcm2835_mmc_finish_data(host);
973 +
974 + if (!host->cmd->data)
975 + tasklet_schedule(&host->finish_tasklet);
976 +
977 + host->cmd = NULL;
978 + }
979 +}
980 +
981 +
982 +static void bcm2835_mmc_timeout_timer(unsigned long data)
983 +{
984 + struct bcm2835_host *host;
985 + unsigned long flags;
986 +
987 + host = (struct bcm2835_host *)data;
988 +
989 + spin_lock_irqsave(&host->lock, flags);
990 +
991 + if (host->mrq) {
992 + pr_err("%s: Timeout waiting for hardware interrupt.\n",
993 + mmc_hostname(host->mmc));
994 + bcm2835_mmc_dumpregs(host);
995 +
996 + if (host->data) {
997 + host->data->error = -ETIMEDOUT;
998 + bcm2835_mmc_finish_data(host);
999 + } else {
1000 + if (host->cmd)
1001 + host->cmd->error = -ETIMEDOUT;
1002 + else
1003 + host->mrq->cmd->error = -ETIMEDOUT;
1004 +
1005 + tasklet_schedule(&host->finish_tasklet);
1006 + }
1007 + }
1008 +
1009 + mmiowb();
1010 + spin_unlock_irqrestore(&host->lock, flags);
1011 +}
1012 +
1013 +
1014 +static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
1015 +{
1016 + if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1017 + if (enable)
1018 + host->ier |= SDHCI_INT_CARD_INT;
1019 + else
1020 + host->ier &= ~SDHCI_INT_CARD_INT;
1021 +
1022 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7);
1023 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7);
1024 + mmiowb();
1025 + }
1026 +}
1027 +
1028 +static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1029 +{
1030 + struct bcm2835_host *host = mmc_priv(mmc);
1031 + unsigned long flags;
1032 +
1033 + spin_lock_irqsave(&host->lock, flags);
1034 + if (enable)
1035 + host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1036 + else
1037 + host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1038 +
1039 + bcm2835_mmc_enable_sdio_irq_nolock(host, enable);
1040 + spin_unlock_irqrestore(&host->lock, flags);
1041 +}
1042 +
1043 +static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)
1044 +{
1045 +
1046 + BUG_ON(intmask == 0);
1047 +
1048 + if (!host->cmd) {
1049 + pr_err("%s: Got command interrupt 0x%08x even "
1050 + "though no command operation was in progress.\n",
1051 + mmc_hostname(host->mmc), (unsigned)intmask);
1052 + bcm2835_mmc_dumpregs(host);
1053 + return;
1054 + }
1055 +
1056 + if (intmask & SDHCI_INT_TIMEOUT)
1057 + host->cmd->error = -ETIMEDOUT;
1058 + else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1059 + SDHCI_INT_INDEX)) {
1060 + host->cmd->error = -EILSEQ;
1061 + }
1062 +
1063 + if (host->cmd->error) {
1064 + tasklet_schedule(&host->finish_tasklet);
1065 + return;
1066 + }
1067 +
1068 + if (intmask & SDHCI_INT_RESPONSE)
1069 + bcm2835_mmc_finish_command(host);
1070 +
1071 +}
1072 +
1073 +static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)
1074 +{
1075 + struct dma_chan *dma_chan;
1076 + u32 dir_data;
1077 +
1078 + BUG_ON(intmask == 0);
1079 +
1080 + if (!host->data) {
1081 + /*
1082 + * The "data complete" interrupt is also used to
1083 + * indicate that a busy state has ended. See comment
1084 + * above in sdhci_cmd_irq().
1085 + */
1086 + if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1087 + if (intmask & SDHCI_INT_DATA_END) {
1088 + bcm2835_mmc_finish_command(host);
1089 + return;
1090 + }
1091 + }
1092 +
1093 + pr_debug("%s: Got data interrupt 0x%08x even "
1094 + "though no data operation was in progress.\n",
1095 + mmc_hostname(host->mmc), (unsigned)intmask);
1096 + bcm2835_mmc_dumpregs(host);
1097 +
1098 + return;
1099 + }
1100 +
1101 + if (intmask & SDHCI_INT_DATA_TIMEOUT)
1102 + host->data->error = -ETIMEDOUT;
1103 + else if (intmask & SDHCI_INT_DATA_END_BIT)
1104 + host->data->error = -EILSEQ;
1105 + else if ((intmask & SDHCI_INT_DATA_CRC) &&
1106 + SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))
1107 + != MMC_BUS_TEST_R)
1108 + host->data->error = -EILSEQ;
1109 +
1110 + if (host->use_dma) {
1111 + if (host->data->flags & MMC_DATA_WRITE) {
1112 + /* IRQ handled here */
1113 +
1114 + dma_chan = host->dma_chan_rxtx;
1115 + dir_data = DMA_TO_DEVICE;
1116 + dma_unmap_sg(dma_chan->device->dev,
1117 + host->data->sg, host->data->sg_len,
1118 + dir_data);
1119 +
1120 + bcm2835_mmc_finish_data(host);
1121 + }
1122 +
1123 + } else {
1124 + if (host->data->error)
1125 + bcm2835_mmc_finish_data(host);
1126 + else {
1127 + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1128 + bcm2835_mmc_transfer_pio(host);
1129 +
1130 + if (intmask & SDHCI_INT_DATA_END) {
1131 + if (host->cmd) {
1132 + /*
1133 + * Data managed to finish before the
1134 + * command completed. Make sure we do
1135 + * things in the proper order.
1136 + */
1137 + host->data_early = 1;
1138 + } else {
1139 + bcm2835_mmc_finish_data(host);
1140 + }
1141 + }
1142 + }
1143 + }
1144 +}
1145 +
1146 +
1147 +static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)
1148 +{
1149 + irqreturn_t result = IRQ_NONE;
1150 + struct bcm2835_host *host = dev_id;
1151 + u32 intmask, mask, unexpected = 0;
1152 + int max_loops = 16;
1153 +
1154 + spin_lock(&host->lock);
1155 +
1156 + intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1157 +
1158 + if (!intmask || intmask == 0xffffffff) {
1159 + result = IRQ_NONE;
1160 + goto out;
1161 + }
1162 +
1163 + do {
1164 + /* Clear selected interrupts. */
1165 + mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
1166 + SDHCI_INT_BUS_POWER);
1167 + bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8);
1168 +
1169 +
1170 + if (intmask & SDHCI_INT_CMD_MASK)
1171 + bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1172 +
1173 + if (intmask & SDHCI_INT_DATA_MASK)
1174 + bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1175 +
1176 + if (intmask & SDHCI_INT_BUS_POWER)
1177 + pr_err("%s: Card is consuming too much power!\n",
1178 + mmc_hostname(host->mmc));
1179 +
1180 + if (intmask & SDHCI_INT_CARD_INT) {
1181 + bcm2835_mmc_enable_sdio_irq_nolock(host, false);
1182 + host->thread_isr |= SDHCI_INT_CARD_INT;
1183 + result = IRQ_WAKE_THREAD;
1184 + }
1185 +
1186 + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
1187 + SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
1188 + SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
1189 + SDHCI_INT_CARD_INT);
1190 +
1191 + if (intmask) {
1192 + unexpected |= intmask;
1193 + bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9);
1194 + }
1195 +
1196 + if (result == IRQ_NONE)
1197 + result = IRQ_HANDLED;
1198 +
1199 + intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1200 + } while (intmask && --max_loops);
1201 +out:
1202 + spin_unlock(&host->lock);
1203 +
1204 + if (unexpected) {
1205 + pr_err("%s: Unexpected interrupt 0x%08x.\n",
1206 + mmc_hostname(host->mmc), unexpected);
1207 + bcm2835_mmc_dumpregs(host);
1208 + }
1209 +
1210 + return result;
1211 +}
1212 +
1213 +static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id)
1214 +{
1215 + struct bcm2835_host *host = dev_id;
1216 + unsigned long flags;
1217 + u32 isr;
1218 +
1219 + spin_lock_irqsave(&host->lock, flags);
1220 + isr = host->thread_isr;
1221 + host->thread_isr = 0;
1222 + spin_unlock_irqrestore(&host->lock, flags);
1223 +
1224 + if (isr & SDHCI_INT_CARD_INT) {
1225 + sdio_run_irqs(host->mmc);
1226 +
1227 + spin_lock_irqsave(&host->lock, flags);
1228 + if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
1229 + bcm2835_mmc_enable_sdio_irq_nolock(host, true);
1230 + spin_unlock_irqrestore(&host->lock, flags);
1231 + }
1232 +
1233 + return isr ? IRQ_HANDLED : IRQ_NONE;
1234 +}
1235 +
1236 +
1237 +
1238 +void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)
1239 +{
1240 + int div = 0; /* Initialized for compiler warning */
1241 + int real_div = div, clk_mul = 1;
1242 + u16 clk = 0;
1243 + unsigned long timeout;
1244 + unsigned int input_clock = clock;
1245 +
1246 + if (host->overclock_50 && (clock == 50000000))
1247 + clock = host->overclock_50 * 1000000 + 999999;
1248 +
1249 + host->mmc->actual_clock = 0;
1250 +
1251 + bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);
1252 +
1253 + if (clock == 0)
1254 + return;
1255 +
1256 + /* Version 3.00 divisors must be a multiple of 2. */
1257 + if (host->max_clk <= clock)
1258 + div = 1;
1259 + else {
1260 + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1261 + div += 2) {
1262 + if ((host->max_clk / div) <= clock)
1263 + break;
1264 + }
1265 + }
1266 +
1267 + real_div = div;
1268 + div >>= 1;
1269 +
1270 + if (real_div)
1271 + clock = (host->max_clk * clk_mul) / real_div;
1272 + host->mmc->actual_clock = clock;
1273 +
1274 + if ((clock > input_clock) && (clock > host->max_overclock)) {
1275 + pr_warn("%s: Overclocking to %dHz\n",
1276 + mmc_hostname(host->mmc), clock);
1277 + host->max_overclock = clock;
1278 + }
1279 +
1280 + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1281 + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1282 + << SDHCI_DIVIDER_HI_SHIFT;
1283 + clk |= SDHCI_CLOCK_INT_EN;
1284 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1285 +
1286 + /* Wait max 20 ms */
1287 + timeout = 20;
1288 + while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))
1289 + & SDHCI_CLOCK_INT_STABLE)) {
1290 + if (timeout == 0) {
1291 + pr_err("%s: Internal clock never "
1292 + "stabilised.\n", mmc_hostname(host->mmc));
1293 + bcm2835_mmc_dumpregs(host);
1294 + return;
1295 + }
1296 + timeout--;
1297 + mdelay(1);
1298 + }
1299 +
1300 + if (20-timeout > 10 && 20-timeout > host->max_delay) {
1301 + host->max_delay = 20-timeout;
1302 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
1303 + }
1304 +
1305 + clk |= SDHCI_CLOCK_CARD_EN;
1306 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1307 +}
1308 +
1309 +static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1310 +{
1311 + struct bcm2835_host *host;
1312 + unsigned long flags;
1313 +
1314 + host = mmc_priv(mmc);
1315 +
1316 + spin_lock_irqsave(&host->lock, flags);
1317 +
1318 + WARN_ON(host->mrq != NULL);
1319 +
1320 + host->mrq = mrq;
1321 +
1322 + if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1323 + bcm2835_mmc_send_command(host, mrq->sbc);
1324 + else
1325 + bcm2835_mmc_send_command(host, mrq->cmd);
1326 +
1327 + mmiowb();
1328 + spin_unlock_irqrestore(&host->lock, flags);
1329 +
1330 + if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) {
1331 + /* DMA transfer starts now, PIO starts after interrupt */
1332 + bcm2835_mmc_transfer_dma(host);
1333 + }
1334 +}
1335 +
1336 +
1337 +static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1338 +{
1339 +
1340 + struct bcm2835_host *host = mmc_priv(mmc);
1341 + unsigned long flags;
1342 + u8 ctrl;
1343 + u16 clk, ctrl_2;
1344 +
1345 + pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n",
1346 + ios->clock, ios->power_mode, ios->bus_width,
1347 + ios->timing, ios->signal_voltage, ios->drv_type);
1348 +
1349 + spin_lock_irqsave(&host->lock, flags);
1350 +
1351 + if (!ios->clock || ios->clock != host->clock) {
1352 + bcm2835_mmc_set_clock(host, ios->clock);
1353 + host->clock = ios->clock;
1354 + }
1355 +
1356 + if (host->pwr != SDHCI_POWER_330) {
1357 + host->pwr = SDHCI_POWER_330;
1358 + bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1359 + }
1360 +
1361 + ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);
1362 +
1363 + /* set bus width */
1364 + ctrl &= ~SDHCI_CTRL_8BITBUS;
1365 + if (ios->bus_width == MMC_BUS_WIDTH_4)
1366 + ctrl |= SDHCI_CTRL_4BITBUS;
1367 + else
1368 + ctrl &= ~SDHCI_CTRL_4BITBUS;
1369 +
1370 + ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */
1371 +
1372 +
1373 + bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1374 + /*
1375 + * We only need to set Driver Strength if the
1376 + * preset value enable is not set.
1377 + */
1378 + ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);
1379 + ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1380 + if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1381 + ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1382 + else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1383 + ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1384 +
1385 + bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1386 +
1387 + /* Reset SD Clock Enable */
1388 + clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);
1389 + clk &= ~SDHCI_CLOCK_CARD_EN;
1390 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1391 +
1392 + /* Re-enable SD Clock */
1393 + bcm2835_mmc_set_clock(host, host->clock);
1394 + bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1395 +
1396 + mmiowb();
1397 +
1398 + spin_unlock_irqrestore(&host->lock, flags);
1399 +}
1400 +
1401 +
1402 +static struct mmc_host_ops bcm2835_ops = {
1403 + .request = bcm2835_mmc_request,
1404 + .set_ios = bcm2835_mmc_set_ios,
1405 + .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,
1406 +};
1407 +
1408 +
1409 +static void bcm2835_mmc_tasklet_finish(unsigned long param)
1410 +{
1411 + struct bcm2835_host *host;
1412 + unsigned long flags;
1413 + struct mmc_request *mrq;
1414 +
1415 + host = (struct bcm2835_host *)param;
1416 +
1417 + spin_lock_irqsave(&host->lock, flags);
1418 +
1419 + /*
1420 + * If this tasklet gets rescheduled while running, it will
1421 + * be run again afterwards but without any active request.
1422 + */
1423 + if (!host->mrq) {
1424 + spin_unlock_irqrestore(&host->lock, flags);
1425 + return;
1426 + }
1427 +
1428 + del_timer(&host->timer);
1429 +
1430 + mrq = host->mrq;
1431 +
1432 + /*
1433 + * The controller needs a reset of internal state machines
1434 + * upon error conditions.
1435 + */
1436 + if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1437 + ((mrq->cmd && mrq->cmd->error) ||
1438 + (mrq->data && (mrq->data->error ||
1439 + (mrq->data->stop && mrq->data->stop->error))))) {
1440 +
1441 + spin_unlock_irqrestore(&host->lock, flags);
1442 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
1443 + bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
1444 + spin_lock_irqsave(&host->lock, flags);
1445 + }
1446 +
1447 + host->mrq = NULL;
1448 + host->cmd = NULL;
1449 + host->data = NULL;
1450 +
1451 + mmiowb();
1452 +
1453 + spin_unlock_irqrestore(&host->lock, flags);
1454 + mmc_request_done(host->mmc, mrq);
1455 +}
1456 +
1457 +
1458 +
1459 +static int bcm2835_mmc_add_host(struct bcm2835_host *host)
1460 +{
1461 + struct mmc_host *mmc = host->mmc;
1462 + struct device *dev = mmc->parent;
1463 +#ifndef FORCE_PIO
1464 + struct dma_slave_config cfg;
1465 +#endif
1466 + int ret;
1467 +
1468 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
1469 +
1470 + host->clk_mul = 0;
1471 +
1472 + mmc->f_max = host->max_clk;
1473 + mmc->f_max = host->max_clk;
1474 + mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
1475 +
1476 + /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
1477 + host->timeout_clk = mmc->f_max / 1000;
1478 + mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
1479 +
1480 + /* host controller capabilities */
1481 + mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL |
1482 + MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED |
1483 + MMC_CAP_MMC_HIGHSPEED;
1484 +
1485 + mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
1486 +
1487 + host->flags = SDHCI_AUTO_CMD23;
1488 +
1489 + dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2);
1490 +#ifdef FORCE_PIO
1491 + dev_info(dev, "Forcing PIO mode\n");
1492 + host->have_dma = false;
1493 +#else
1494 + if (IS_ERR_OR_NULL(host->dma_chan_rxtx)) {
1495 + dev_err(dev, "%s: Unable to initialise DMA channel. Falling back to PIO\n",
1496 + DRIVER_NAME);
1497 + host->have_dma = false;
1498 + } else {
1499 + dev_info(dev, "DMA channel allocated");
1500 +
1501 + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1502 + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1503 + cfg.slave_id = 11; /* DREQ channel */
1504 +
1505 + /* Validate the slave configurations */
1506 +
1507 + cfg.direction = DMA_MEM_TO_DEV;
1508 + cfg.src_addr = 0;
1509 + cfg.dst_addr = host->bus_addr + SDHCI_BUFFER;
1510 +
1511 + ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
1512 +
1513 + if (ret == 0) {
1514 + host->dma_cfg_tx = cfg;
1515 +
1516 + cfg.direction = DMA_DEV_TO_MEM;
1517 + cfg.src_addr = host->bus_addr + SDHCI_BUFFER;
1518 + cfg.dst_addr = 0;
1519 +
1520 + ret = dmaengine_slave_config(host->dma_chan_rxtx, &cfg);
1521 + }
1522 +
1523 + if (ret == 0) {
1524 + host->dma_cfg_rx = cfg;
1525 +
1526 + host->use_dma = true;
1527 + } else {
1528 + pr_err("%s: unable to configure DMA channel. "
1529 + "Faling back to PIO\n",
1530 + mmc_hostname(mmc));
1531 + dma_release_channel(host->dma_chan_rxtx);
1532 + host->dma_chan_rxtx = NULL;
1533 + host->use_dma = false;
1534 + }
1535 + }
1536 +#endif
1537 + mmc->max_segs = 128;
1538 + mmc->max_req_size = 524288;
1539 + mmc->max_seg_size = mmc->max_req_size;
1540 + mmc->max_blk_size = 512;
1541 + mmc->max_blk_count = 65535;
1542 +
1543 + /* report supported voltage ranges */
1544 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1545 +
1546 + tasklet_init(&host->finish_tasklet,
1547 + bcm2835_mmc_tasklet_finish, (unsigned long)host);
1548 +
1549 + setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host);
1550 + init_waitqueue_head(&host->buf_ready_int);
1551 +
1552 + bcm2835_mmc_init(host, 0);
1553 + ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq,
1554 + bcm2835_mmc_thread_irq, IRQF_SHARED,
1555 + mmc_hostname(mmc), host);
1556 + if (ret) {
1557 + dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret);
1558 + goto untasklet;
1559 + }
1560 +
1561 + mmiowb();
1562 + mmc_add_host(mmc);
1563 +
1564 + return 0;
1565 +
1566 +untasklet:
1567 + tasklet_kill(&host->finish_tasklet);
1568 +
1569 + return ret;
1570 +}
1571 +
1572 +static int bcm2835_mmc_probe(struct platform_device *pdev)
1573 +{
1574 + struct device *dev = &pdev->dev;
1575 + struct device_node *node = dev->of_node;
1576 + struct clk *clk;
1577 + struct resource *iomem;
1578 + struct bcm2835_host *host;
1579 + struct mmc_host *mmc;
1580 + const __be32 *addr;
1581 + int ret;
1582 +
1583 + mmc = mmc_alloc_host(sizeof(*host), dev);
1584 + if (!mmc)
1585 + return -ENOMEM;
1586 +
1587 + mmc->ops = &bcm2835_ops;
1588 + host = mmc_priv(mmc);
1589 + host->mmc = mmc;
1590 + host->timeout = msecs_to_jiffies(1000);
1591 + spin_lock_init(&host->lock);
1592 +
1593 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1594 + host->ioaddr = devm_ioremap_resource(dev, iomem);
1595 + if (IS_ERR(host->ioaddr)) {
1596 + ret = PTR_ERR(host->ioaddr);
1597 + goto err;
1598 + }
1599 +
1600 + addr = of_get_address(node, 0, NULL, NULL);
1601 + if (!addr) {
1602 + dev_err(dev, "could not get DMA-register address\n");
1603 + return -ENODEV;
1604 + }
1605 + host->bus_addr = be32_to_cpup(addr);
1606 + pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n",
1607 + (unsigned long)host->ioaddr,
1608 + (unsigned long)iomem->start,
1609 + (unsigned long)host->bus_addr);
1610 +
1611 +#ifndef FORCE_PIO
1612 + if (node) {
1613 + host->dma_chan_rxtx = dma_request_slave_channel(dev, "rx-tx");
1614 + if (!host->dma_chan_rxtx)
1615 + host->dma_chan_rxtx =
1616 + dma_request_slave_channel(dev, "tx");
1617 + if (!host->dma_chan_rxtx)
1618 + host->dma_chan_rxtx =
1619 + dma_request_slave_channel(dev, "rx");
1620 + } else {
1621 + dma_cap_mask_t mask;
1622 +
1623 + dma_cap_zero(mask);
1624 + /* we don't care about the channel, any would work */
1625 + dma_cap_set(DMA_SLAVE, mask);
1626 + host->dma_chan_rxtx = dma_request_channel(mask, NULL, NULL);
1627 + }
1628 +#endif
1629 + clk = devm_clk_get(dev, NULL);
1630 + if (IS_ERR(clk)) {
1631 + ret = PTR_ERR(clk);
1632 + if (ret == -EPROBE_DEFER)
1633 + dev_info(dev, "could not get clk, deferring probe\n");
1634 + else
1635 + dev_err(dev, "could not get clk\n");
1636 + goto err;
1637 + }
1638 +
1639 + host->max_clk = clk_get_rate(clk);
1640 +
1641 + host->irq = platform_get_irq(pdev, 0);
1642 + if (host->irq <= 0) {
1643 + dev_err(dev, "get IRQ failed\n");
1644 + ret = -EINVAL;
1645 + goto err;
1646 + }
1647 +
1648 + if (node) {
1649 + mmc_of_parse(mmc);
1650 +
1651 + /* Read any custom properties */
1652 + of_property_read_u32(node,
1653 + "brcm,overclock-50",
1654 + &host->overclock_50);
1655 + } else {
1656 + mmc->caps |= MMC_CAP_4_BIT_DATA;
1657 + }
1658 +
1659 + ret = bcm2835_mmc_add_host(host);
1660 + if (ret)
1661 + goto err;
1662 +
1663 + platform_set_drvdata(pdev, host);
1664 +
1665 + return 0;
1666 +err:
1667 + mmc_free_host(mmc);
1668 +
1669 + return ret;
1670 +}
1671 +
1672 +static int bcm2835_mmc_remove(struct platform_device *pdev)
1673 +{
1674 + struct bcm2835_host *host = platform_get_drvdata(pdev);
1675 + unsigned long flags;
1676 + int dead;
1677 + u32 scratch;
1678 +
1679 + dead = 0;
1680 + scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1681 + if (scratch == (u32)-1)
1682 + dead = 1;
1683 +
1684 +
1685 + if (dead) {
1686 + spin_lock_irqsave(&host->lock, flags);
1687 +
1688 + host->flags |= SDHCI_DEVICE_DEAD;
1689 +
1690 + if (host->mrq) {
1691 + pr_err("%s: Controller removed during "
1692 + " transfer!\n", mmc_hostname(host->mmc));
1693 +
1694 + host->mrq->cmd->error = -ENOMEDIUM;
1695 + tasklet_schedule(&host->finish_tasklet);
1696 + }
1697 +
1698 + spin_unlock_irqrestore(&host->lock, flags);
1699 + }
1700 +
1701 + mmc_remove_host(host->mmc);
1702 +
1703 + if (!dead)
1704 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
1705 +
1706 + free_irq(host->irq, host);
1707 +
1708 + del_timer_sync(&host->timer);
1709 +
1710 + tasklet_kill(&host->finish_tasklet);
1711 +
1712 + mmc_free_host(host->mmc);
1713 + platform_set_drvdata(pdev, NULL);
1714 +
1715 + return 0;
1716 +}
1717 +
1718 +
1719 +static const struct of_device_id bcm2835_mmc_match[] = {
1720 + { .compatible = "brcm,bcm2835-mmc" },
1721 + { }
1722 +};
1723 +MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);
1724 +
1725 +
1726 +
1727 +static struct platform_driver bcm2835_mmc_driver = {
1728 + .probe = bcm2835_mmc_probe,
1729 + .remove = bcm2835_mmc_remove,
1730 + .driver = {
1731 + .name = DRIVER_NAME,
1732 + .owner = THIS_MODULE,
1733 + .of_match_table = bcm2835_mmc_match,
1734 + },
1735 +};
1736 +module_platform_driver(bcm2835_mmc_driver);
1737 +
1738 +module_param(mmc_debug, uint, 0644);
1739 +module_param(mmc_debug2, uint, 0644);
1740 +MODULE_ALIAS("platform:mmc-bcm2835");
1741 +MODULE_DESCRIPTION("BCM2835 SDHCI driver");
1742 +MODULE_LICENSE("GPL v2");
1743 +MODULE_AUTHOR("Gellert Weisz");
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