kernel: bump 4.9 to 4.9.128
[openwrt/staging/wigyori.git] / target / linux / brcm47xx / patches-4.9 / 159-cpu_fixes.patch
1 --- a/arch/mips/include/asm/r4kcache.h
2 +++ b/arch/mips/include/asm/r4kcache.h
3 @@ -25,6 +25,38 @@
4 extern void (*r4k_blast_dcache)(void);
5 extern void (*r4k_blast_icache)(void);
6
7 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
8 +#include <asm/paccess.h>
9 +#include <linux/ssb/ssb.h>
10 +#define BCM4710_DUMMY_RREG() bcm4710_dummy_rreg()
11 +
12 +static inline unsigned long bcm4710_dummy_rreg(void)
13 +{
14 + return *(volatile unsigned long *)(KSEG1ADDR(SSB_ENUM_BASE));
15 +}
16 +
17 +#define BCM4710_FILL_TLB(addr) bcm4710_fill_tlb((void *)(addr))
18 +
19 +static inline unsigned long bcm4710_fill_tlb(void *addr)
20 +{
21 + return *(unsigned long *)addr;
22 +}
23 +
24 +#define BCM4710_PROTECTED_FILL_TLB(addr) bcm4710_protected_fill_tlb((void *)(addr))
25 +
26 +static inline void bcm4710_protected_fill_tlb(void *addr)
27 +{
28 + unsigned long x;
29 + get_dbe(x, (unsigned long *)addr);;
30 +}
31 +
32 +#else
33 +#define BCM4710_DUMMY_RREG()
34 +
35 +#define BCM4710_FILL_TLB(addr)
36 +#define BCM4710_PROTECTED_FILL_TLB(addr)
37 +#endif
38 +
39 /*
40 * This macro return a properly sign-extended address suitable as base address
41 * for indexed cache operations. Two issues here:
42 @@ -98,6 +130,7 @@ static inline void flush_icache_line_ind
43 static inline void flush_dcache_line_indexed(unsigned long addr)
44 {
45 __dflush_prologue
46 + BCM4710_DUMMY_RREG();
47 cache_op(Index_Writeback_Inv_D, addr);
48 __dflush_epilogue
49 }
50 @@ -125,6 +158,7 @@ static inline void flush_icache_line(uns
51 static inline void flush_dcache_line(unsigned long addr)
52 {
53 __dflush_prologue
54 + BCM4710_DUMMY_RREG();
55 cache_op(Hit_Writeback_Inv_D, addr);
56 __dflush_epilogue
57 }
58 @@ -132,6 +166,7 @@ static inline void flush_dcache_line(uns
59 static inline void invalidate_dcache_line(unsigned long addr)
60 {
61 __dflush_prologue
62 + BCM4710_DUMMY_RREG();
63 cache_op(Hit_Invalidate_D, addr);
64 __dflush_epilogue
65 }
66 @@ -187,6 +222,7 @@ static inline void protected_flush_icach
67 #ifdef CONFIG_EVA
68 protected_cachee_op(Hit_Invalidate_I, addr);
69 #else
70 + BCM4710_DUMMY_RREG();
71 protected_cache_op(Hit_Invalidate_I, addr);
72 #endif
73 break;
74 @@ -201,6 +237,7 @@ static inline void protected_flush_icach
75 */
76 static inline void protected_writeback_dcache_line(unsigned long addr)
77 {
78 + BCM4710_DUMMY_RREG();
79 #ifdef CONFIG_EVA
80 protected_cachee_op(Hit_Writeback_Inv_D, addr);
81 #else
82 @@ -558,8 +595,51 @@ static inline void invalidate_tcache_pag
83 : "r" (base), \
84 "i" (op));
85
86 +static inline void blast_dcache(void)
87 +{
88 + unsigned long start = KSEG0;
89 + unsigned long dcache_size = current_cpu_data.dcache.waysize * current_cpu_data.dcache.ways;
90 + unsigned long end = (start + dcache_size);
91 +
92 + do {
93 + BCM4710_DUMMY_RREG();
94 + cache_op(Index_Writeback_Inv_D, start);
95 + start += current_cpu_data.dcache.linesz;
96 + } while(start < end);
97 +}
98 +
99 +static inline void blast_dcache_page(unsigned long page)
100 +{
101 + unsigned long start = page;
102 + unsigned long end = start + PAGE_SIZE;
103 +
104 + BCM4710_FILL_TLB(start);
105 + do {
106 + BCM4710_DUMMY_RREG();
107 + cache_op(Hit_Writeback_Inv_D, start);
108 + start += current_cpu_data.dcache.linesz;
109 + } while(start < end);
110 +}
111 +
112 +static inline void blast_dcache_page_indexed(unsigned long page)
113 +{
114 + unsigned long start = page;
115 + unsigned long end = start + PAGE_SIZE;
116 + unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
117 + unsigned long ws_end = current_cpu_data.dcache.ways <<
118 + current_cpu_data.dcache.waybit;
119 + unsigned long ws, addr;
120 + for (ws = 0; ws < ws_end; ws += ws_inc) {
121 + start = page + ws;
122 + for (addr = start; addr < end; addr += current_cpu_data.dcache.linesz) {
123 + BCM4710_DUMMY_RREG();
124 + cache_op(Index_Writeback_Inv_D, addr);
125 + }
126 + }
127 +}
128 +
129 /* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
130 -#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra) \
131 +#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize, extra, war) \
132 static inline void extra##blast_##pfx##cache##lsize(void) \
133 { \
134 unsigned long start = INDEX_BASE; \
135 @@ -571,6 +651,7 @@ static inline void extra##blast_##pfx##c
136 \
137 __##pfx##flush_prologue \
138 \
139 + war \
140 for (ws = 0; ws < ws_end; ws += ws_inc) \
141 for (addr = start; addr < end; addr += lsize * 32) \
142 cache##lsize##_unroll32(addr|ws, indexop); \
143 @@ -585,6 +666,7 @@ static inline void extra##blast_##pfx##c
144 \
145 __##pfx##flush_prologue \
146 \
147 + war \
148 do { \
149 cache##lsize##_unroll32(start, hitop); \
150 start += lsize * 32; \
151 @@ -603,6 +685,8 @@ static inline void extra##blast_##pfx##c
152 current_cpu_data.desc.waybit; \
153 unsigned long ws, addr; \
154 \
155 + war \
156 + \
157 __##pfx##flush_prologue \
158 \
159 for (ws = 0; ws < ws_end; ws += ws_inc) \
160 @@ -612,26 +696,26 @@ static inline void extra##blast_##pfx##c
161 __##pfx##flush_epilogue \
162 }
163
164 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
165 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, )
166 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, )
167 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
168 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, )
169 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_)
170 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, )
171 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
172 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
173 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
174 -__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
175 -__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
176 -__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
177 -
178 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
179 -__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
180 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, )
181 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, )
182 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, )
183 -__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, )
184 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, , )
185 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16, , BCM4710_FILL_TLB(start);)
186 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16, , )
187 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, , )
188 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32, , BCM4710_FILL_TLB(start);)
189 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I_Loongson2, 32, loongson2_, BCM4710_FILL_TLB(start);)
190 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32, , )
191 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, , )
192 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, , BCM4710_FILL_TLB(start);)
193 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, , )
194 +__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, , )
195 +__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, , )
196 +__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, , )
197 +
198 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, , )
199 +__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, , )
200 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16, , )
201 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32, , )
202 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64, , )
203 +__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128, , )
204
205 #define __BUILD_BLAST_USER_CACHE(pfx, desc, indexop, hitop, lsize) \
206 static inline void blast_##pfx##cache##lsize##_user_page(unsigned long page) \
207 @@ -660,53 +744,23 @@ __BUILD_BLAST_USER_CACHE(d, dcache, Inde
208 __BUILD_BLAST_USER_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
209
210 /* build blast_xxx_range, protected_blast_xxx_range */
211 -#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra) \
212 +#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot, extra, war, war2) \
213 static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start, \
214 unsigned long end) \
215 { \
216 unsigned long lsize = cpu_##desc##_line_size(); \
217 - unsigned long lsize_2 = lsize * 2; \
218 - unsigned long lsize_3 = lsize * 3; \
219 - unsigned long lsize_4 = lsize * 4; \
220 - unsigned long lsize_5 = lsize * 5; \
221 - unsigned long lsize_6 = lsize * 6; \
222 - unsigned long lsize_7 = lsize * 7; \
223 - unsigned long lsize_8 = lsize * 8; \
224 unsigned long addr = start & ~(lsize - 1); \
225 - unsigned long aend = (end + lsize - 1) & ~(lsize - 1); \
226 - int lines = (aend - addr) / lsize; \
227 + unsigned long aend = (end - 1) & ~(lsize - 1); \
228 + war \
229 \
230 __##pfx##flush_prologue \
231 \
232 - while (lines >= 8) { \
233 - prot##cache_op(hitop, addr); \
234 - prot##cache_op(hitop, addr + lsize); \
235 - prot##cache_op(hitop, addr + lsize_2); \
236 - prot##cache_op(hitop, addr + lsize_3); \
237 - prot##cache_op(hitop, addr + lsize_4); \
238 - prot##cache_op(hitop, addr + lsize_5); \
239 - prot##cache_op(hitop, addr + lsize_6); \
240 - prot##cache_op(hitop, addr + lsize_7); \
241 - addr += lsize_8; \
242 - lines -= 8; \
243 - } \
244 - \
245 - if (lines & 0x4) { \
246 - prot##cache_op(hitop, addr); \
247 - prot##cache_op(hitop, addr + lsize); \
248 - prot##cache_op(hitop, addr + lsize_2); \
249 - prot##cache_op(hitop, addr + lsize_3); \
250 - addr += lsize_4; \
251 - } \
252 - \
253 - if (lines & 0x2) { \
254 - prot##cache_op(hitop, addr); \
255 - prot##cache_op(hitop, addr + lsize); \
256 - addr += lsize_2; \
257 - } \
258 - \
259 - if (lines & 0x1) { \
260 + while (1) { \
261 + war2 \
262 prot##cache_op(hitop, addr); \
263 + if (addr == aend) \
264 + break; \
265 + addr += lsize; \
266 } \
267 \
268 __##pfx##flush_epilogue \
269 @@ -714,8 +768,8 @@ static inline void prot##extra##blast_##
270
271 #ifndef CONFIG_EVA
272
273 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
274 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
275 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, , BCM4710_PROTECTED_FILL_TLB(addr); BCM4710_PROTECTED_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
276 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, , , )
277
278 #else
279
280 @@ -752,14 +806,14 @@ __BUILD_PROT_BLAST_CACHE_RANGE(d, dcache
281 __BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
282
283 #endif
284 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
285 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, , , )
286 __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
287 - protected_, loongson2_)
288 -__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , )
289 -__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , )
290 -__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , )
291 + protected_, loongson2_, , )
292 +__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, , , BCM4710_FILL_TLB(addr); BCM4710_FILL_TLB(aend);, BCM4710_DUMMY_RREG();)
293 +__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, , , , )
294 +__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, , , , )
295 /* blast_inv_dcache_range */
296 -__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , )
297 -__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , )
298 +__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, , , , BCM4710_DUMMY_RREG();)
299 +__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, , , , )
300
301 #endif /* _ASM_R4KCACHE_H */
302 --- a/arch/mips/include/asm/stackframe.h
303 +++ b/arch/mips/include/asm/stackframe.h
304 @@ -365,6 +365,10 @@
305 .macro RESTORE_SP_AND_RET
306 LONG_L sp, PT_R29(sp)
307 .set arch=r4000
308 +#ifdef CONFIG_BCM47XX
309 + nop
310 + nop
311 +#endif
312 eret
313 .set mips0
314 .endm
315 --- a/arch/mips/kernel/genex.S
316 +++ b/arch/mips/kernel/genex.S
317 @@ -21,6 +21,19 @@
318 #include <asm/war.h>
319 #include <asm/thread_info.h>
320
321 +#ifdef CONFIG_BCM47XX
322 +# ifdef eret
323 +# undef eret
324 +# endif
325 +# define eret \
326 + .set push; \
327 + .set noreorder; \
328 + nop; \
329 + nop; \
330 + eret; \
331 + .set pop;
332 +#endif
333 +
334 __INIT
335
336 /*
337 @@ -32,6 +45,9 @@
338 NESTED(except_vec3_generic, 0, sp)
339 .set push
340 .set noat
341 +#ifdef CONFIG_BCM47XX
342 + nop
343 +#endif
344 #if R5432_CP0_INTERRUPT_WAR
345 mfc0 k0, CP0_INDEX
346 #endif
347 @@ -55,6 +71,9 @@ NESTED(except_vec3_r4000, 0, sp)
348 .set push
349 .set arch=r4000
350 .set noat
351 +#ifdef CONFIG_BCM47XX
352 + nop
353 +#endif
354 mfc0 k1, CP0_CAUSE
355 li k0, 31<<2
356 andi k1, k1, 0x7c
357 --- a/arch/mips/mm/c-r4k.c
358 +++ b/arch/mips/mm/c-r4k.c
359 @@ -39,6 +39,9 @@
360 #include <asm/dma-coherence.h>
361 #include <asm/mips-cm.h>
362
363 +/* For enabling BCM4710 cache workarounds */
364 +static int bcm4710 = 0;
365 +
366 /*
367 * Bits describing what cache ops an SMP callback function may perform.
368 *
369 @@ -190,6 +193,9 @@ static void r4k_blast_dcache_user_page_s
370 {
371 unsigned long dc_lsize = cpu_dcache_line_size();
372
373 + if (bcm4710)
374 + r4k_blast_dcache_page = blast_dcache_page;
375 + else
376 if (dc_lsize == 0)
377 r4k_blast_dcache_user_page = (void *)cache_noop;
378 else if (dc_lsize == 16)
379 @@ -208,6 +214,9 @@ static void r4k_blast_dcache_page_indexe
380 {
381 unsigned long dc_lsize = cpu_dcache_line_size();
382
383 + if (bcm4710)
384 + r4k_blast_dcache_page_indexed = blast_dcache_page_indexed;
385 + else
386 if (dc_lsize == 0)
387 r4k_blast_dcache_page_indexed = (void *)cache_noop;
388 else if (dc_lsize == 16)
389 @@ -227,6 +236,9 @@ static void r4k_blast_dcache_setup(void)
390 {
391 unsigned long dc_lsize = cpu_dcache_line_size();
392
393 + if (bcm4710)
394 + r4k_blast_dcache = blast_dcache;
395 + else
396 if (dc_lsize == 0)
397 r4k_blast_dcache = (void *)cache_noop;
398 else if (dc_lsize == 16)
399 @@ -957,6 +969,8 @@ static void local_r4k_flush_cache_sigtra
400 }
401
402 R4600_HIT_CACHEOP_WAR_IMPL;
403 + BCM4710_PROTECTED_FILL_TLB(addr);
404 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
405 if (!cpu_has_ic_fills_f_dc) {
406 if (dc_lsize)
407 vaddr ? flush_dcache_line(addr & ~(dc_lsize - 1))
408 @@ -1845,6 +1859,17 @@ static void coherency_setup(void)
409 * silly idea of putting something else there ...
410 */
411 switch (current_cpu_type()) {
412 + case CPU_BMIPS3300:
413 + {
414 + u32 cm;
415 + cm = read_c0_diag();
416 + /* Enable icache */
417 + cm |= (1 << 31);
418 + /* Enable dcache */
419 + cm |= (1 << 30);
420 + write_c0_diag(cm);
421 + }
422 + break;
423 case CPU_R4000PC:
424 case CPU_R4000SC:
425 case CPU_R4000MC:
426 @@ -1891,6 +1916,15 @@ void r4k_cache_init(void)
427 extern void build_copy_page(void);
428 struct cpuinfo_mips *c = &current_cpu_data;
429
430 + /* Check if special workarounds are required */
431 +#if defined(CONFIG_BCM47XX) && !defined(CONFIG_CPU_MIPS32_R2)
432 + if (current_cpu_data.cputype == CPU_BMIPS32 && (current_cpu_data.processor_id & 0xff) == 0) {
433 + printk("Enabling BCM4710A0 cache workarounds.\n");
434 + bcm4710 = 1;
435 + } else
436 +#endif
437 + bcm4710 = 0;
438 +
439 probe_pcache();
440 probe_vcache();
441 setup_scache();
442 @@ -1968,7 +2002,15 @@ void r4k_cache_init(void)
443 */
444 local_r4k___flush_cache_all(NULL);
445
446 +#ifdef CONFIG_BCM47XX
447 + {
448 + static void (*_coherency_setup)(void);
449 + _coherency_setup = (void (*)(void)) KSEG1ADDR(coherency_setup);
450 + _coherency_setup();
451 + }
452 +#else
453 coherency_setup();
454 +#endif
455 board_cache_error_setup = r4k_cache_error_setup;
456
457 /*
458 --- a/arch/mips/mm/tlbex.c
459 +++ b/arch/mips/mm/tlbex.c
460 @@ -968,6 +968,9 @@ build_get_pgde32(u32 **p, unsigned int t
461 uasm_i_srl(p, ptr, ptr, SMP_CPUID_PTRSHIFT);
462 uasm_i_addu(p, ptr, tmp, ptr);
463 #else
464 +#ifdef CONFIG_BCM47XX
465 + uasm_i_nop(p);
466 +#endif
467 UASM_i_LA_mostly(p, ptr, pgdc);
468 #endif
469 uasm_i_mfc0(p, tmp, C0_BADVADDR); /* get faulting address */
470 @@ -1310,6 +1313,9 @@ static void build_r4000_tlb_refill_handl
471 #ifdef CONFIG_64BIT
472 build_get_pmde64(&p, &l, &r, K0, K1); /* get pmd in K1 */
473 #else
474 +# ifdef CONFIG_BCM47XX
475 + uasm_i_nop(&p);
476 +# endif
477 build_get_pgde32(&p, K0, K1); /* get pgd in K1 */
478 #endif
479
480 @@ -1321,6 +1327,9 @@ static void build_r4000_tlb_refill_handl
481 build_update_entries(&p, K0, K1);
482 build_tlb_write_entry(&p, &l, &r, tlb_random);
483 uasm_l_leave(&l, p);
484 +#ifdef CONFIG_BCM47XX
485 + uasm_i_nop(&p);
486 +#endif
487 uasm_i_eret(&p); /* return from trap */
488 }
489 #ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT
490 @@ -2003,6 +2012,9 @@ build_r4000_tlbchange_handler_head(u32 *
491 #ifdef CONFIG_64BIT
492 build_get_pmde64(p, l, r, wr.r1, wr.r2); /* get pmd in ptr */
493 #else
494 +# ifdef CONFIG_BCM47XX
495 + uasm_i_nop(p);
496 +# endif
497 build_get_pgde32(p, wr.r1, wr.r2); /* get pgd in ptr */
498 #endif
499
500 @@ -2049,6 +2061,9 @@ build_r4000_tlbchange_handler_tail(u32 *
501 build_tlb_write_entry(p, l, r, tlb_indexed);
502 uasm_l_leave(l, *p);
503 build_restore_work_registers(p);
504 +#ifdef CONFIG_BCM47XX
505 + uasm_i_nop(p);
506 +#endif
507 uasm_i_eret(p); /* return from trap */
508
509 #ifdef CONFIG_64BIT