target/linux/brcm63xx-2.6/files/include/asm-mips/mach-bcm963xx/bcmpci.h

   1 /*
   2 <:copyright-gpl
   3  Copyright 2004 Broadcom Corp. All Rights Reserved.
   4
   5  This program is free software; you can distribute it and/or modify it
   6  under the terms of the GNU General Public License (Version 2) as
   7  published by the Free Software Foundation.
   8
   9  This program is distributed in the hope it will be useful, but WITHOUT
  10  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  for more details.
  13
  14  You should have received a copy of the GNU General Public License along
  15  with this program; if not, write to the Free Software Foundation, Inc.,
  16  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17 :>
  18 */
  19
  20 //
  21 // bcmpci.h - bcm96348 PCI, Cardbus, and PCMCIA definition
  22 //
  23 #ifndef BCMPCI_H
  24 #define BCMPCI_H
  25
  26 /* Memory window in internal system bus address space */
  27 #define BCM_PCI_MEM_BASE        0x08000000
  28 /* IO window in internal system bus address space */
  29 #define BCM_PCI_IO_BASE         0x0C000000
  30
  31 #define BCM_PCI_ADDR_MASK       0x1fffffff
  32
  33 /* Memory window size (range) */
  34 #define BCM_PCI_MEM_SIZE_16MB   0x01000000
  35 /* IO window size (range) */
  36 #define BCM_PCI_IO_SIZE_64KB    0x00010000
  37
  38 /* PCI Configuration and I/O space acesss */
  39 #define BCM_PCI_CFG(d, f, o)    ( (d << 11) | (f << 8) | (o/4 << 2) )
  40
  41 /* fake USB PCI slot */
  42 #define USB_HOST_SLOT           9
  43 #define USB_BAR0_MEM_SIZE       0x0800
  44
  45 #define BCM_HOST_MEM_SPACE1     0x10000000
  46 #define BCM_HOST_MEM_SPACE2     0x00000000
  47
  48 /*
  49  * EBI bus clock is 33MHz and share with PCI bus
  50  * each clock cycle is 30ns.
  51  */
  52 /* attribute memory access wait cnt for 4306 */
  53 #define PCMCIA_ATTR_CE_HOLD     3  // data hold time 70ns
  54 #define PCMCIA_ATTR_CE_SETUP    3  // data setup time 50ns
  55 #define PCMCIA_ATTR_INACTIVE    6  // time between read/write cycles 180ns. For the total cycle time 600ns (cnt1+cnt2+cnt3+cnt4)
  56 #define PCMCIA_ATTR_ACTIVE      10 // OE/WE pulse width 300ns
  57
  58 /* common memory access wait cnt for 4306 */
  59 #define PCMCIA_MEM_CE_HOLD      1  // data hold time 30ns
  60 #define PCMCIA_MEM_CE_SETUP     1  // data setup time 30ns
  61 #define PCMCIA_MEM_INACTIVE     2  // time between read/write cycles 40ns. For the total cycle time 250ns (cnt1+cnt2+cnt3+cnt4)
  62 #define PCMCIA_MEM_ACTIVE       5  // OE/WE pulse width 150ns
  63
  64 #define PCCARD_VCC_MASK     0x00070000  // Mask Reset also
  65 #define PCCARD_VCC_33V      0x00010000
  66 #define PCCARD_VCC_50V      0x00020000
  67
  68 typedef enum {
  69     MPI_CARDTYPE_NONE,      // No Card in slot
  70     MPI_CARDTYPE_PCMCIA,    // 16-bit PCMCIA card in slot
  71     MPI_CARDTYPE_CARDBUS,   // 32-bit CardBus card in slot
  72 }   CardType;
  73
  74 #define CARDBUS_SLOT        0    // Slot 0 is default for CardBus
  75
  76 #define pcmciaAttrOffset    0x00200000
  77 #define pcmciaMemOffset     0x00000000
  78 // Needs to be right above PCI I/O space. Give 0x8000 (32K) to PCMCIA.
  79 #define pcmciaIoOffset      (BCM_PCI_IO_BASE + 0x80000)
  80 // Base Address is that mapped into the MPI ChipSelect registers.
  81 // UBUS bridge MemoryWindow 0 outputs a 0x00 for the base.
  82 #define pcmciaBase          0xbf000000
  83 #define pcmciaAttr          (pcmciaAttrOffset | pcmciaBase)
  84 #define pcmciaMem           (pcmciaMemOffset  | pcmciaBase)
  85 #define pcmciaIo            (pcmciaIoOffset   | pcmciaBase)
  86
  87 #endif