target/linux/generic-2.6/files/crypto/ocf/kirkwood/mvHal/mv_hal/pci/mvPciRegs.h

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  64
  65 #ifndef __INCPCIREGSH
  66 #define __INCPCIREGSH
  67
  68
  69 #include "pci-if/mvPciIfRegs.h"
  70 /* defines */
  71 #define MAX_PCI_DEVICES         32
  72 #define MAX_PCI_FUNCS           8
  73 #define MAX_PCI_BUSSES          128
  74
  75 /* enumerators */
  76
  77 /* This enumerator described the possible PCI slave targets.               */
  78 /* PCI slave targets are designated memory/IO address spaces that the  */
  79 /* PCI slave targets can access. They are also refered as "targets"    */
  80 /* this enumeratoe order is determined by the content of :
  81                 PCI_BASE_ADDR_ENABLE_REG                                                                        */
  82
  83
  84 /* registers offsetes defines */
  85
  86
  87
  88 /*************************/
  89 /* PCI control registers */
  90 /*************************/
  91 /* maen : should add new registers */
  92 #define PCI_CMD_REG(pciIf)                                              (0x30c00  + ((pciIf) * 0x80))
  93 #define PCI_MODE_REG(pciIf)                                             (0x30d00  + ((pciIf) * 0x80))
  94 #define PCI_RETRY_REG(pciIf)                                    (0x30c04  + ((pciIf) * 0x80))
  95 #define PCI_DISCARD_TIMER_REG(pciIf)                    (0x30d04  + ((pciIf) * 0x80))
  96 #define PCI_ARBITER_CTRL_REG(pciIf)                             (0x31d00 + ((pciIf) * 0x80))
  97 #define PCI_P2P_CONFIG_REG(pciIf)                               (0x31d14 + ((pciIf) * 0x80))
  98 #define PCI_ACCESS_CTRL_BASEL_REG(pciIf, targetWin) \
  99                                                         (0x31e00 + ((pciIf) * 0x80) + ((targetWin) * 0x10))
 100 #define PCI_ACCESS_CTRL_BASEH_REG(pciIf, targetWin) \
 101                                                         (0x31e04 + ((pciIf) * 0x80) + ((targetWin) * 0x10))
 102 #define PCI_ACCESS_CTRL_SIZE_REG(pciIf, targetWin)      \
 103                                                         (0x31e08 + ((pciIf) * 0x80) + ((targetWin) * 0x10))
 104
 105 #define PCI_DLL_CTRL_REG(pciIf)                                 (0x31d20  + ((pciIf) * 0x80))
 106
 107 /* PCI Dll Control (PDC)*/
 108 #define PDC_DLL_EN                                      BIT0
 109
 110
 111 /* PCI Command Register (PCR) */
 112 #define PCR_MASTER_BYTE_SWAP_EN     BIT0
 113 #define PCR_MASTER_WR_COMBINE_EN    BIT4
 114 #define PCR_MASTER_RD_COMBINE_EN    BIT5
 115 #define PCR_MASTER_WR_TRIG_WHOLE    BIT6
 116 #define PCR_MASTER_RD_TRIG_WHOLE    BIT7
 117 #define PCR_MASTER_MEM_RD_LINE_EN   BIT8
 118 #define PCR_MASTER_MEM_RD_MULT_EN   BIT9
 119 #define PCR_MASTER_WORD_SWAP_EN     BIT10
 120 #define PCR_SLAVE_WORD_SWAP_EN      BIT11
 121 #define PCR_NS_ACCORDING_RCV_TRANS  BIT14
 122 #define PCR_MASTER_PCIX_REQ64N_EN   BIT15
 123 #define PCR_SLAVE_BYTE_SWAP_EN      BIT16
 124 #define PCR_MASTER_DAC_EN           BIT17
 125 #define PCR_MASTER_M64_ALLIGN       BIT18
 126 #define PCR_ERRORS_PROPAGATION_EN   BIT19
 127 #define PCR_SLAVE_SWAP_ENABLE       BIT20
 128 #define PCR_MASTER_SWAP_ENABLE      BIT21
 129 #define PCR_MASTER_INT_SWAP_EN      BIT22
 130 #define PCR_LOOP_BACK_ENABLE        BIT23
 131 #define PCR_SLAVE_INTREG_SWAP_OFFS  24
 132 #define PCR_SLAVE_INTREG_SWAP_MASK  0x3
 133 #define PCR_SLAVE_INTREG_BYTE_SWAP  \
 134                              (MV_BYTE_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK)
 135 #define PCR_SLAVE_INTREG_NO_SWAP    \
 136                              (MV_NO_SWAP   << PCR_SLAVE_INT_REG_SWAP_MASK)
 137 #define PCR_SLAVE_INTREG_BYTE_WORD  \
 138                              (MV_BYTE_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK)
 139 #define PCR_SLAVE_INTREG_WORD_SWAP  \
 140                              (MV_WORD_SWAP << PCR_SLAVE_INT_REG_SWAP_MASK)
 141 #define PCR_RESET_REASSERTION_EN    BIT26
 142 #define PCR_PCI_TO_CPU_REG_ORDER_EN BIT28
 143 #define PCR_CPU_TO_PCI_ORDER_EN     BIT29
 144 #define PCR_PCI_TO_CPU_ORDER_EN     BIT30
 145
 146 /* PCI Mode Register (PMR) */
 147 #define PMR_PCI_ID_OFFS                         0  /* PCI Interface ID */
 148 #define PMR_PCI_ID_MASK                         (0x1 << PMR_PCI_ID_OFFS)
 149 #define PMR_PCI_ID_PCI(pciNum)          ((pciNum) << PCI_MODE_PCIID_OFFS)
 150
 151 #define PMR_PCI_64_OFFS                         2       /* 64-bit PCI Interface */
 152 #define PMR_PCI_64_MASK                         (0x1 << PMR_PCI_64_OFFS)
 153 #define PMR_PCI_64_64BIT                        (0x1 << PMR_PCI_64_OFFS)
 154 #define PMR_PCI_64_32BIT                        (0x0 << PMR_PCI_64_OFFS)
 155
 156 #define PMR_PCI_MODE_OFFS                       4       /* PCI interface mode of operation */
 157 #define PMR_PCI_MODE_MASK                       (0x3 << PMR_PCI_MODE_OFFS)
 158 #define PMR_PCI_MODE_CONV                       (0x0 << PMR_PCI_MODE_OFFS)
 159 #define PMR_PCI_MODE_PCIX_66MHZ         (0x1 << PMR_PCI_MODE_OFFS)
 160 #define PMR_PCI_MODE_PCIX_100MHZ        (0x2 << PMR_PCI_MODE_OFFS)
 161 #define PMR_PCI_MODE_PCIX_133MHZ        (0x3 << PMR_PCI_MODE_OFFS)
 162
 163 #define PMR_EXP_ROM_SUPPORT                     BIT8    /* Expansion ROM Active */
 164
 165 #define PMR_PCI_RESET_OFFS                      31 /* PCI Interface Reset Indication */
 166 #define PMR_PCI_RESET_MASK                      (0x1 << PMR_PCI_RESET_OFFS)
 167 #define PMR_PCI_RESET_PCIXRST           (0x0 << PMR_PCI_RESET_OFFS)
 168
 169
 170 /* PCI Retry Register (PRR) */
 171 #define PRR_RETRY_CNTR_OFFS                     16 /* Retry Counter */
 172 #define PRR_RETRY_CNTR_MAX                      0xff
 173 #define PRR_RETRY_CNTR_MASK                     (PRR_RETRY_CNTR_MAX << PRR_RETRY_CNTR_OFFS)
 174
 175
 176 /* PCI Discard Timer Register (PDTR) */
 177 #define PDTR_TIMER_OFFS                         0       /* Timer */
 178 #define PDTR_TIMER_MAX                          0xffff
 179 #define PDTR_TIMER_MIN                          0x7F
 180 #define PDTR_TIMER_MASK                         (PDTR_TIMER_MAX << PDTR_TIMER_OFFS)
 181
 182
 183 /* PCI Arbiter Control Register (PACR) */
 184 #define PACR_BROKEN_DETECT_EN           BIT1    /* Broken Detection Enable */
 185
 186 #define PACR_BROKEN_VAL_OFFS            3       /* Broken Value */
 187 #define PACR_BROKEN_VAL_MASK            (0xf << PACR_BROKEN_VAL_OFFS)
 188 #define PACR_BROKEN_VAL_CONV_MIN        0x2
 189 #define PACR_BROKEN_VAL_PCIX_MIN        0x6
 190
 191 #define PACR_PARK_DIS_OFFS              14      /* Parking Disable */
 192 #define PACR_PARK_DIS_MAX_AGENT 0x3f
 193 #define PACR_PARK_DIS_MASK              (PACR_PARK_DIS_MAX_AGENT<<PACR_PARK_DIS_OFFS)
 194 #define PACR_PARK_DIS(agent)    ((1 << (agent)) << PACR_PARK_DIS_OFFS)
 195
 196 #define PACR_ARB_ENABLE                         BIT31   /* Enable Internal Arbiter */
 197
 198
 199 /* PCI P2P Configuration Register (PPCR) */
 200 #define PPCR_2ND_BUS_L_OFFS                     0       /* 2nd PCI Interface Bus Range Lower */
 201 #define PPCR_2ND_BUS_L_MASK                     (0xff << PPCR_2ND_BUS_L_OFFS)
 202
 203 #define PPCR_2ND_BUS_H_OFFS                     8       /* 2nd PCI Interface Bus Range Upper */
 204 #define PPCR_2ND_BUS_H_MASK                     (0xff << PPCR_2ND_BUS_H_OFFS)
 205
 206 #define PPCR_BUS_NUM_OFFS                       16  /* The PCI interface's Bus number */
 207 #define PPCR_BUS_NUM_MASK                       (0xff << PPCR_BUS_NUM_OFFS)
 208
 209 #define PPCR_DEV_NUM_OFFS                       24  /* The PCI interface\92s Device number */
 210 #define PPCR_DEV_NUM_MASK                       (0xff << PPCR_DEV_NUM_OFFS)
 211
 212
 213 /* PCI Access Control Base Low Register (PACBLR) */
 214 #define PACBLR_EN                                       BIT0 /* Access control window enable */
 215
 216 #define PACBLR_ACCPROT                          BIT4 /* Access Protect */
 217 #define PACBLR_WRPROT                           BIT5 /* Write Protect */
 218
 219 #define PACBLR_PCISWAP_OFFS                     6        /* PCI slave Data Swap Control */
 220 #define PACBLR_PCISWAP_MASK                     (0x3 << PACBLR_PCISWAP_OFFS)
 221 #define PACBLR_PCISWAP_BYTE                     (0x0 << PACBLR_PCISWAP_OFFS)
 222 #define PACBLR_PCISWAP_NO_SWAP          (0x1 << PACBLR_PCISWAP_OFFS)
 223 #define PACBLR_PCISWAP_BYTE_WORD        (0x2 << PACBLR_PCISWAP_OFFS)
 224 #define PACBLR_PCISWAP_WORD                     (0x3 << PACBLR_PCISWAP_OFFS)
 225
 226 #define PACBLR_RDMBURST_OFFS            8 /* Read Max Burst */
 227 #define PACBLR_RDMBURST_MASK            (0x3 << PACBLR_RDMBURST_OFFS)
 228 #define PACBLR_RDMBURST_32BYTE          (0x0 << PACBLR_RDMBURST_OFFS)
 229 #define PACBLR_RDMBURST_64BYTE          (0x1 << PACBLR_RDMBURST_OFFS)
 230 #define PACBLR_RDMBURST_128BYTE         (0x2 << PACBLR_RDMBURST_OFFS)
 231
 232 #define PACBLR_RDSIZE_OFFS                      10 /* Typical PCI read transaction Size. */
 233 #define PACBLR_RDSIZE_MASK                      (0x3 << PACBLR_RDSIZE_OFFS)
 234 #define PACBLR_RDSIZE_32BYTE            (0x0 << PACBLR_RDSIZE_OFFS)
 235 #define PACBLR_RDSIZE_64BYTE            (0x1 << PACBLR_RDSIZE_OFFS)
 236 #define PACBLR_RDSIZE_128BYTE           (0x2 << PACBLR_RDSIZE_OFFS)
 237 #define PACBLR_RDSIZE_256BYTE           (0x3 << PACBLR_RDSIZE_OFFS)
 238
 239 #define PACBLR_BASE_L_OFFS                      12      /* Corresponds to address bits [31:12] */
 240 #define PACBLR_BASE_L_MASK                      (0xfffff << PACBLR_BASE_L_OFFS)
 241 #define PACBLR_BASE_L_ALIGNMENT         (1 << PACBLR_BASE_L_OFFS)
 242 #define PACBLR_BASE_ALIGN_UP(base)  \
 243                              ((base+PACBLR_BASE_L_ALIGNMENT)&PACBLR_BASE_L_MASK)
 244 #define PACBLR_BASE_ALIGN_DOWN(base)  (base & PACBLR_BASE_L_MASK)
 245
 246
 247 /* PCI Access Control Base High Register (PACBHR)       */
 248 #define PACBHR_BASE_H_OFFS                      0       /* Corresponds to address bits [63:32] */
 249 #define PACBHR_CTRL_BASE_H_MASK         (0xffffffff << PACBHR_BASE_H_OFFS)
 250
 251 /* PCI Access Control Size Register (PACSR)             */
 252 #define PACSR_WRMBURST_OFFS                     8 /* Write Max Burst */
 253 #define PACSR_WRMBURST_MASK                     (0x3 << PACSR_WRMBURST_OFFS)
 254 #define PACSR_WRMBURST_32BYTE           (0x0 << PACSR_WRMBURST_OFFS)
 255 #define PACSR_WRMBURST_64BYTE           (0x1 << PACSR_WRMBURST_OFFS)
 256 #define PACSR_WRMBURST_128BYTE          (0x2 << PACSR_WRMBURST_OFFS)
 257
 258 #define PACSR_PCI_ORDERING                      BIT11 /* PCI Ordering required */
 259
 260 #define PACSR_SIZE_OFFS                         12      /* PCI access window size */
 261 #define PACSR_SIZE_MASK                         (0xfffff << PACSR_SIZE_OFFS)
 262 #define PACSR_SIZE_ALIGNMENT            (1 << PACSR_SIZE_OFFS)
 263 #define PACSR_SIZE_ALIGN_UP(size)   \
 264                                    ((size+PACSR_SIZE_ALIGNMENT)&PACSR_SIZE_MASK)
 265 #define PACSR_SIZE_ALIGN_DOWN(size) (size & PACSR_SIZE_MASK)
 266
 267
 268 /***************************************/
 269 /* PCI Configuration Access Registers  */
 270 /***************************************/
 271
 272 #define PCI_CONFIG_ADDR_REG(pciIf)      (0x30C78 - ((pciIf) * 0x80) )
 273 #define PCI_CONFIG_DATA_REG(pciIf)      (0x30C7C - ((pciIf) * 0x80) )
 274 #define PCI_INT_ACK_REG(pciIf)          (0x30C34 + ((pciIf) * 0x80) )
 275
 276 /* PCI Configuration Address Register (PCAR) */
 277 #define PCAR_REG_NUM_OFFS                       2
 278 #define PCAR_REG_NUM_MASK                       (0x3F << PCAR_REG_NUM_OFFS)
 279
 280 #define PCAR_FUNC_NUM_OFFS                      8
 281 #define PCAR_FUNC_NUM_MASK                      (0x7 << PCAR_FUNC_NUM_OFFS)
 282
 283 #define PCAR_DEVICE_NUM_OFFS            11
 284 #define PCAR_DEVICE_NUM_MASK            (0x1F << PCAR_DEVICE_NUM_OFFS)
 285
 286 #define PCAR_BUS_NUM_OFFS                       16
 287 #define PCAR_BUS_NUM_MASK                       (0xFF << PCAR_BUS_NUM_OFFS)
 288
 289 #define PCAR_CONFIG_EN                          BIT31
 290
 291
 292 /***************************************/
 293 /* PCI Configuration registers */
 294 /***************************************/
 295
 296 /*********************************************/
 297 /* PCI Configuration, Function 0, Registers  */
 298 /*********************************************/
 299
 300 /* Marvell Specific */
 301 #define PCI_SCS0_BASE_ADDR_LOW                                          0x010
 302 #define PCI_SCS0_BASE_ADDR_HIGH                                         0x014
 303 #define PCI_SCS1_BASE_ADDR_LOW                                          0x018
 304 #define PCI_SCS1_BASE_ADDR_HIGH                                         0x01C
 305 #define PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_L            0x020
 306 #define PCI_INTER_REG_MEM_MAPPED_BASE_ADDR_H            0x024
 307
 308 /* capability list */
 309 #define PCI_POWER_MNG_CAPABILITY                            0x040
 310 #define PCI_POWER_MNG_STATUS_CONTROL                    0x044
 311 #define PCI_VPD_ADDRESS_REG                             0x048
 312 #define PCI_VPD_DATA_REG                                0x04c
 313 #define PCI_MSI_MESSAGE_CONTROL                                         0x050
 314 #define PCI_MSI_MESSAGE_ADDR                            0x054
 315 #define PCI_MSI_MESSAGE_UPPER_ADDR                          0x058
 316 #define PCI_MSI_MESSAGE_DATA                            0x05c
 317 #define PCIX_COMMAND                                    0x060
 318 #define PCIX_STATUS                                         0x064
 319 #define PCI_COMPACT_PCI_HOT_SWAP                            0x068
 320
 321
 322 /*********************************************/
 323 /* PCI Configuration, Function 1, Registers  */
 324 /*********************************************/
 325
 326 #define PCI_SCS2_BASE_ADDR_LOW                                          0x10
 327 #define PCI_SCS2_BASE_ADDR_HIGH                                         0x14
 328 #define PCI_SCS3_BASE_ADDR_LOW                                          0x18
 329 #define PCI_SCS3_BASE_ADDR_HIGH                                         0x1c
 330
 331
 332 /***********************************************/
 333 /*  PCI Configuration, Function 2, Registers   */
 334 /***********************************************/
 335
 336 #define PCI_DEVCS0_BASE_ADDR_LOW                                        0x10
 337 #define PCI_DEVCS0_BASE_ADDR_HIGH                                       0x14
 338 #define PCI_DEVCS1_BASE_ADDR_LOW                                        0x18
 339 #define PCI_DEVCS1_BASE_ADDR_HIGH                               0x1c
 340 #define PCI_DEVCS2_BASE_ADDR_LOW                                        0x20
 341 #define PCI_DEVCS2_BASE_ADDR_HIGH                               0x24
 342
 343 /***********************************************/
 344 /*  PCI Configuration, Function 3, Registers   */
 345 /***********************************************/
 346
 347 #define PCI_BOOTCS_BASE_ADDR_LOW                                        0x18
 348 #define PCI_BOOTCS_BASE_ADDR_HIGH                               0x1c
 349
 350 /***********************************************/
 351 /*  PCI Configuration, Function 4, Registers   */
 352 /***********************************************/
 353
 354 #define PCI_P2P_MEM0_BASE_ADDR_LOW                                      0x10
 355 #define PCI_P2P_MEM0_BASE_ADDR_HIGH                                     0x14
 356 #define PCI_P2P_IO_BASE_ADDR                            0x20
 357 #define PCI_INTER_REGS_IO_MAPPED_BASE_ADDR                 0x24
 358
 359 /* PCIX_STATUS  register fields (PXS) */
 360
 361 #define PXS_FN_OFFS             0       /* Description Number */
 362 #define PXS_FN_MASK             (0x7 << PXS_FN_OFFS)
 363
 364 #define PXS_DN_OFFS             3       /* Device Number */
 365 #define PXS_DN_MASK             (0x1f << PXS_DN_OFFS)
 366
 367 #define PXS_BN_OFFS             8       /* Bus Number */
 368 #define PXS_BN_MASK             (0xff << PXS_BN_OFFS)
 369
 370
 371 /* PCI Error Report Register Map */
 372 #define PCI_SERRN_MASK_REG(pciIf)               (0x30c28  + (pciIf * 0x80))
 373 #define PCI_CAUSE_REG(pciIf)                    (0x31d58 + (pciIf * 0x80))
 374 #define PCI_MASK_REG(pciIf)                             (0x31d5C + (pciIf * 0x80))
 375 #define PCI_ERROR_ADDR_LOW_REG(pciIf)   (0x31d40 + (pciIf * 0x80))
 376 #define PCI_ERROR_ADDR_HIGH_REG(pciIf)  (0x31d44 + (pciIf * 0x80))
 377 #define PCI_ERROR_ATTRIBUTE_REG(pciIf)  (0x31d48 + (pciIf * 0x80))
 378 #define PCI_ERROR_COMMAND_REG(pciIf)    (0x31d50 + (pciIf * 0x80))
 379
 380 /* PCI Interrupt Cause Register (PICR) */
 381 #define PICR_ERR_SEL_OFFS           27
 382 #define PICR_ERR_SEL_MASK           (0x1f << PICR_ERR_SEL_OFFS)
 383
 384 /* PCI Error Command Register (PECR) */
 385 #define PECR_ERR_CMD_OFFS                       0
 386 #define PECR_ERR_CMD_MASK                       (0xf << PECR_ERR_CMD_OFFS)
 387 #define PECR_DAC                                        BIT4
 388
 389
 390 /* defaults */
 391 /* Set bits means value is about to change according to new value */
 392 #define PCI_COMMAND_DEFAULT_MASK                0xffffdff1
 393 #define PCI_COMMAND_DEFAULT                             \
 394                 (PCR_MASTER_WR_TRIG_WHOLE   |   \
 395          PCR_MASTER_RD_TRIG_WHOLE       |       \
 396                  PCR_MASTER_MEM_RD_LINE_EN      |       \
 397          PCR_MASTER_MEM_RD_MULT_EN  |   \
 398                  PCR_NS_ACCORDING_RCV_TRANS     |       \
 399                  PCR_MASTER_PCIX_REQ64N_EN      |       \
 400                  PCR_MASTER_DAC_EN                      |       \
 401                  PCR_MASTER_M64_ALLIGN          |       \
 402                  PCR_ERRORS_PROPAGATION_EN)
 403
 404
 405 #define PCI_ARBITER_CTRL_DEFAULT_MASK   0x801fc07a
 406 #define PCI_ARBITER_CTRL_DEFAULT        \
 407         (PACR_BROKEN_VAL_PCIX_MIN << PACR_BROKEN_VAL_OFFS)
 408
 409
 410 #endif /* #ifndef __INCPCIREGSH */
 411