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[openwrt/staging/wigyori.git] / target / linux / ifxmips / files / arch / mips / ifxmips / timer.c
1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/version.h>
4 #include <linux/types.h>
5 #include <linux/fs.h>
6 #include <linux/miscdevice.h>
7 #include <linux/init.h>
8 #include <asm/uaccess.h>
9 #include <asm/unistd.h>
10 #include <asm/irq.h>
11 #include <asm/div64.h>
12 #include <linux/errno.h>
13 #include <linux/interrupt.h>
14
15 #include <asm/ifxmips/ifxmips.h>
16 #include <asm/ifxmips/ifxmips_irq.h>
17 #include <asm/ifxmips/ifxmips_cgu.h>
18 #include <asm/ifxmips/ifxmips_gptu.h>
19 #include <asm/ifxmips/ifxmips_pmu.h>
20
21 #define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
22
23 #ifdef TIMER1A
24 #define FIRST_TIMER TIMER1A
25 #else
26 #define FIRST_TIMER 2
27 #endif
28
29 /*
30 * GPTC divider is set or not.
31 */
32 #define GPTU_CLC_RMC_IS_SET 0
33
34 /*
35 * Timer Interrupt (IRQ)
36 */
37 #define TIMER_INTERRUPT INT_NUM_IM3_IRL0 + 22 // Must be adjusted when ICU driver is available
38
39 /*
40 * Bits Operation
41 */
42 #define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
43 #define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
44
45 /*
46 * GPTU Register Mapping
47 */
48 #define IFXMIPS_GPTU (KSEG1 + 0x1E100A00)
49 #define IFXMIPS_GPTU_CLC ((volatile u32*)(IFXMIPS_GPTU + 0x0000))
50 #define IFXMIPS_GPTU_ID ((volatile u32*)(IFXMIPS_GPTU + 0x0008))
51 #define IFXMIPS_GPTU_CON(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
52 #define IFXMIPS_GPTU_RUN(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
53 #define IFXMIPS_GPTU_RELOAD(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
54 #define IFXMIPS_GPTU_COUNT(n, X) ((volatile u32*)(IFXMIPS_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) // X must be either A or B
55 #define IFXMIPS_GPTU_IRNEN ((volatile u32*)(IFXMIPS_GPTU + 0x00F4))
56 #define IFXMIPS_GPTU_IRNICR ((volatile u32*)(IFXMIPS_GPTU + 0x00F8))
57 #define IFXMIPS_GPTU_IRNCR ((volatile u32*)(IFXMIPS_GPTU + 0x00FC))
58
59 /*
60 * Clock Control Register
61 */
62 #define GPTU_CLC_SMC GET_BITS(*IFXMIPS_GPTU_CLC, 23, 16)
63 #define GPTU_CLC_RMC GET_BITS(*IFXMIPS_GPTU_CLC, 15, 8)
64 #define GPTU_CLC_FSOE (*IFXMIPS_GPTU_CLC & (1 << 5))
65 #define GPTU_CLC_EDIS (*IFXMIPS_GPTU_CLC & (1 << 3))
66 #define GPTU_CLC_SPEN (*IFXMIPS_GPTU_CLC & (1 << 2))
67 #define GPTU_CLC_DISS (*IFXMIPS_GPTU_CLC & (1 << 1))
68 #define GPTU_CLC_DISR (*IFXMIPS_GPTU_CLC & (1 << 0))
69
70 #define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
71 #define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
72 #define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
73 #define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
74 #define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
75 #define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
76 #define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
77
78 /*
79 * ID Register
80 */
81 #define GPTU_ID_ID GET_BITS(*IFXMIPS_GPTU_ID, 15, 8)
82 #define GPTU_ID_CFG GET_BITS(*IFXMIPS_GPTU_ID, 7, 5)
83 #define GPTU_ID_REV GET_BITS(*IFXMIPS_GPTU_ID, 4, 0)
84
85 /*
86 * Control Register of Timer/Counter nX
87 * n is the index of block (1 based index)
88 * X is either A or B
89 */
90 #define GPTU_CON_SRC_EG(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 10))
91 #define GPTU_CON_SRC_EXT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 9))
92 #define GPTU_CON_SYNC(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 8))
93 #define GPTU_CON_EDGE(n, X) GET_BITS(*IFXMIPS_GPTU_CON(n, X), 7, 6)
94 #define GPTU_CON_INV(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 5))
95 #define GPTU_CON_EXT(n, X) (*IFXMIPS_GPTU_CON(n, A) & (1 << 4)) // Timer/Counter B does not have this bit
96 #define GPTU_CON_STP(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 3))
97 #define GPTU_CON_CNT(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 2))
98 #define GPTU_CON_DIR(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 1))
99 #define GPTU_CON_EN(n, X) (*IFXMIPS_GPTU_CON(n, X) & (1 << 0))
100
101 #define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
102 #define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
103 #define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
104 #define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
105 #define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
106 #define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
107 #define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
108 #define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
109 #define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
110
111 #define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
112 #define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
113 #define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
114
115 #define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
116 #define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
117
118 #define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
119 #define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
120 #define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
121 #define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
122 #define TIMER_FLAG_NONE_EDGE 0x0000
123 #define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
124 #define TIMER_FLAG_REAL 0x0000
125 #define TIMER_FLAG_INVERT 0x0040
126 #define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
127 #define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
128 #define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
129 #define TIMER_FLAG_CALLBACK_IN_HB 0x0200
130 #define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
131 #define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
132
133 struct timer_dev_timer {
134 unsigned int f_irq_on;
135 unsigned int irq;
136 unsigned int flag;
137 unsigned long arg1;
138 unsigned long arg2;
139 };
140
141 struct timer_dev {
142 struct mutex gptu_mutex;
143 unsigned int number_of_timers;
144 unsigned int occupation;
145 unsigned int f_gptu_on;
146 struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
147 };
148
149 static int gptu_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
150 static int gptu_open(struct inode *, struct file *);
151 static int gptu_release(struct inode *, struct file *);
152
153 static struct file_operations gptu_fops = {
154 .owner = THIS_MODULE,
155 .ioctl = gptu_ioctl,
156 .open = gptu_open,
157 .release = gptu_release
158 };
159
160 static struct miscdevice gptu_miscdev = {
161 .minor = MISC_DYNAMIC_MINOR,
162 .name = "gptu",
163 .fops = &gptu_fops,
164 };
165
166 static struct timer_dev timer_dev;
167
168
169 static irqreturn_t
170 timer_irq_handler(int irq, void *p)
171 {
172 unsigned int timer;
173 unsigned int flag;
174 struct timer_dev_timer *dev_timer = (struct timer_dev_timer*) p;
175
176 timer = irq - TIMER_INTERRUPT;
177 if(timer < timer_dev.number_of_timers && dev_timer == &timer_dev.timer[timer])
178 {
179 /* Clear interrupt. */
180 ifxmips_w32(1 << timer, IFXMIPS_GPTU_IRNCR);
181
182 /* Call user hanler or signal. */
183 flag = dev_timer->flag;
184 if (!(timer & 0x01) || TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT)
185 { /* 16-bit timer or timer A of 32-bit timer */
186 switch(TIMER_FLAG_MASK_HANDLE (flag))
187 {
188 case TIMER_FLAG_CALLBACK_IN_IRQ:
189 case TIMER_FLAG_CALLBACK_IN_HB:
190 if (dev_timer->arg1)
191 (*(timer_callback) dev_timer->arg1) (dev_timer->arg2);
192 break;
193 case TIMER_FLAG_SIGNAL:
194 send_sig ((int) dev_timer->arg2, (struct task_struct *) dev_timer->arg1, 0);
195 break;
196 }
197 }
198 }
199 return IRQ_HANDLED;
200 }
201
202 static inline void
203 ifxmips_enable_gptu(void)
204 {
205 ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT);
206
207 /* Set divider as 1, disable write protection for SPEN, enable module. */
208 *IFXMIPS_GPTU_CLC =
209 GPTU_CLC_SMC_SET(0x00) | GPTU_CLC_RMC_SET(0x01) | GPTU_CLC_FSOE_SET(0) |
210 GPTU_CLC_SBWE_SET(1) | GPTU_CLC_EDIS_SET(0) | GPTU_CLC_SPEN_SET(0) | GPTU_CLC_DISR_SET(0);
211 }
212
213 static inline void
214 ifxmips_disable_gptu(void)
215 {
216 ifxmips_w32(0x00, IFXMIPS_GPTU_IRNEN);
217 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
218
219 /* Set divider as 0, enable write protection for SPEN, disable module. */
220 *IFXMIPS_GPTU_CLC =
221 GPTU_CLC_SMC_SET (0x00) | GPTU_CLC_RMC_SET (0x00) | GPTU_CLC_FSOE_SET (0) |
222 GPTU_CLC_SBWE_SET (0) | GPTU_CLC_EDIS_SET (0) | GPTU_CLC_SPEN_SET (0) | GPTU_CLC_DISR_SET (1);
223
224 ifxmips_pmu_disable(IFXMIPS_PMU_PWDCR_GPT);
225 }
226
227 int
228 ifxmips_request_timer(unsigned int timer, unsigned int flag, unsigned long value,
229 unsigned long arg1, unsigned long arg2)
230 {
231 int ret = 0;
232 unsigned int con_reg, irnen_reg;
233 int n, X;
234
235 if(timer >= FIRST_TIMER + timer_dev.number_of_timers)
236 return -EINVAL;
237
238 printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", (u32)timer, (u32)flag, value);
239
240 if(TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
241 value &= 0xFFFF;
242 else
243 timer &= ~0x01;
244
245 mutex_lock(&timer_dev.gptu_mutex);
246
247 /*
248 * Allocate timer.
249 */
250 if (timer < FIRST_TIMER) {
251 unsigned int mask;
252 unsigned int shift;
253 unsigned int offset = TIMER2A;/* This takes care of TIMER1B which is the only choice for Voice TAPI system */
254
255 /*
256 * Pick up a free timer.
257 */
258 if (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT) {
259 mask = 1 << offset;
260 shift = 1;
261 }
262 else {
263 mask = 3 << offset;
264 shift = 2;
265 }
266 for (timer = offset;
267 timer < offset + timer_dev.number_of_timers;
268 timer += shift, mask <<= shift)
269 if (!(timer_dev.occupation & mask)) {
270 timer_dev.occupation |= mask;
271 break;
272 }
273 if (timer >= offset + timer_dev.number_of_timers) {
274 printk("failed![%d]\n", __LINE__);
275 mutex_unlock(&timer_dev.gptu_mutex);
276 return -EINVAL;
277 }
278 else
279 ret = timer;
280 }
281 else {
282 register unsigned int mask;
283
284 /*
285 * Check if the requested timer is free.
286 */
287 mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
288 if ((timer_dev.occupation & mask)) {
289 printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", __LINE__, mask, timer_dev.occupation);
290 mutex_unlock(&timer_dev.gptu_mutex);
291 return -EBUSY;
292 }
293 else {
294 timer_dev.occupation |= mask;
295 ret = 0;
296 }
297 }
298
299 /*
300 * Prepare control register value.
301 */
302 switch (TIMER_FLAG_MASK_EDGE (flag)) {
303 default:
304 case TIMER_FLAG_NONE_EDGE:
305 con_reg = GPTU_CON_EDGE_SET (0x00);
306 break;
307 case TIMER_FLAG_RISE_EDGE:
308 con_reg = GPTU_CON_EDGE_SET (0x01);
309 break;
310 case TIMER_FLAG_FALL_EDGE:
311 con_reg = GPTU_CON_EDGE_SET (0x02);
312 break;
313 case TIMER_FLAG_ANY_EDGE:
314 con_reg = GPTU_CON_EDGE_SET (0x03);
315 break;
316 }
317 if (TIMER_FLAG_MASK_TYPE (flag) == TIMER_FLAG_TIMER)
318 con_reg |=
319 TIMER_FLAG_MASK_SRC (flag) ==
320 TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET (1) :
321 GPTU_CON_SRC_EXT_SET (0);
322 else
323 con_reg |=
324 TIMER_FLAG_MASK_SRC (flag) ==
325 TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET (1) :
326 GPTU_CON_SRC_EG_SET (0);
327 con_reg |=
328 TIMER_FLAG_MASK_SYNC (flag) ==
329 TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET (0) :
330 GPTU_CON_SYNC_SET (1);
331 con_reg |=
332 TIMER_FLAG_MASK_INVERT (flag) ==
333 TIMER_FLAG_REAL ? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1);
334 con_reg |=
335 TIMER_FLAG_MASK_SIZE (flag) ==
336 TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET (0) :
337 GPTU_CON_EXT_SET (1);
338 con_reg |=
339 TIMER_FLAG_MASK_STOP (flag) ==
340 TIMER_FLAG_ONCE ? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0);
341 con_reg |=
342 TIMER_FLAG_MASK_TYPE (flag) ==
343 TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET (0) :
344 GPTU_CON_CNT_SET (1);
345 con_reg |=
346 TIMER_FLAG_MASK_DIR (flag) ==
347 TIMER_FLAG_UP ? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0);
348
349 /*
350 * Fill up running data.
351 */
352 timer_dev.timer[timer - FIRST_TIMER].flag = flag;
353 timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
354 timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
355 if (TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
356 timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
357
358 /*
359 * Enable GPTU module.
360 */
361 if (!timer_dev.f_gptu_on) {
362 ifxmips_enable_gptu ();
363 timer_dev.f_gptu_on = 1;
364 }
365
366 /*
367 * Enable IRQ.
368 */
369 if (TIMER_FLAG_MASK_HANDLE (flag) != TIMER_FLAG_NO_HANDLE) {
370 if (TIMER_FLAG_MASK_HANDLE (flag) == TIMER_FLAG_SIGNAL)
371 timer_dev.timer[timer - FIRST_TIMER].arg1 =
372 (unsigned long) find_task_by_pid ((int) arg1);
373
374 irnen_reg = 1 << (timer - FIRST_TIMER);
375
376 if (TIMER_FLAG_MASK_HANDLE (flag) == TIMER_FLAG_SIGNAL
377 || (TIMER_FLAG_MASK_HANDLE (flag) ==
378 TIMER_FLAG_CALLBACK_IN_IRQ
379 && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
380 enable_irq (timer_dev.timer[timer - FIRST_TIMER].irq);
381 timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
382 }
383 }
384 else
385 irnen_reg = 0;
386
387 /*
388 * Write config register, reload value and enable interrupt.
389 */
390 n = timer >> 1;
391 X = timer & 0x01;
392 *IFXMIPS_GPTU_CON (n, X) = con_reg;
393 *IFXMIPS_GPTU_RELOAD (n, X) = value;
394 // printk("reload value = %d\n", (u32)value);
395 *IFXMIPS_GPTU_IRNEN |= irnen_reg;
396
397 mutex_unlock(&timer_dev.gptu_mutex);
398 printk("successful!\n");
399 return ret;
400 }
401
402 int
403 ifxmips_free_timer(unsigned int timer)
404 {
405 unsigned int flag;
406 unsigned int mask;
407 int n, X;
408
409 if(!timer_dev.f_gptu_on)
410 return -EINVAL;
411
412 if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
413 return -EINVAL;
414
415 mutex_lock(&timer_dev.gptu_mutex);
416
417 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
418 if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
419 timer &= ~0x01;
420
421 mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
422 if(((timer_dev.occupation & mask) ^ mask))
423 {
424 mutex_unlock(&timer_dev.gptu_mutex);
425 return -EINVAL;
426 }
427
428 n = timer >> 1;
429 X = timer & 0x01;
430
431 if(GPTU_CON_EN (n, X))
432 *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_CEN_SET (1);
433
434 *IFXMIPS_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET (n, X, 1);
435 *IFXMIPS_GPTU_IRNCR |= GPTU_IRNCR_TC_SET (n, X, 1);
436
437 if(timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
438 disable_irq (timer_dev.timer[timer - FIRST_TIMER].irq);
439 timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
440 }
441
442 timer_dev.occupation &= ~mask;
443 if(!timer_dev.occupation && timer_dev.f_gptu_on)
444 {
445 ifxmips_disable_gptu();
446 timer_dev.f_gptu_on = 0;
447 }
448
449 mutex_unlock(&timer_dev.gptu_mutex);
450
451 return 0;
452 }
453
454 int
455 ifxmips_start_timer(unsigned int timer, int is_resume)
456 {
457 unsigned int flag;
458 unsigned int mask;
459 int n, X;
460
461 if(!timer_dev.f_gptu_on)
462 return -EINVAL;
463
464 if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
465 return -EINVAL;
466
467 mutex_lock(&timer_dev.gptu_mutex);
468
469 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
470 if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
471 timer &= ~0x01;
472
473 mask = (TIMER_FLAG_MASK_SIZE (flag) ==
474 TIMER_FLAG_16BIT ? 1 : 3) << timer;
475 if(((timer_dev.occupation & mask) ^ mask))
476 {
477 mutex_unlock(&timer_dev.gptu_mutex);
478 return -EINVAL;
479 }
480
481 n = timer >> 1;
482 X = timer & 0x01;
483
484 *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_RL_SET (!is_resume) | GPTU_RUN_SEN_SET (1);
485
486 mutex_unlock(&timer_dev.gptu_mutex);
487
488 return 0;
489 }
490
491 int
492 ifxmips_stop_timer(unsigned int timer)
493 {
494 unsigned int flag;
495 unsigned int mask;
496 int n, X;
497
498 if (!timer_dev.f_gptu_on)
499 return -EINVAL;
500
501 if (timer < FIRST_TIMER
502 || timer >= FIRST_TIMER + timer_dev.number_of_timers)
503 return -EINVAL;
504
505 mutex_lock(&timer_dev.gptu_mutex);
506
507 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
508 if(TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
509 timer &= ~0x01;
510
511 mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
512 if(((timer_dev.occupation & mask) ^ mask))
513 {
514 mutex_unlock(&timer_dev.gptu_mutex);
515 return -EINVAL;
516 }
517
518 n = timer >> 1;
519 X = timer & 0x01;
520
521 *IFXMIPS_GPTU_RUN (n, X) = GPTU_RUN_CEN_SET (1);
522
523 mutex_unlock(&timer_dev.gptu_mutex);
524
525 return 0;
526 }
527
528 int
529 ifxmips_reset_counter_flags(u32 timer, u32 flags)
530 {
531 unsigned int oflag;
532 unsigned int mask, con_reg;
533 int n, X;
534
535 if(!timer_dev.f_gptu_on)
536 return -EINVAL;
537
538 if(timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
539 return -EINVAL;
540
541 mutex_lock(&timer_dev.gptu_mutex);
542
543 oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
544 if(TIMER_FLAG_MASK_SIZE (oflag) != TIMER_FLAG_16BIT)
545 timer &= ~0x01;
546
547 mask = (TIMER_FLAG_MASK_SIZE (oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
548 if(((timer_dev.occupation & mask) ^ mask))
549 {
550 mutex_unlock(&timer_dev.gptu_mutex);
551 return -EINVAL;
552 }
553
554 switch(TIMER_FLAG_MASK_EDGE (flags))
555 {
556 default:
557 case TIMER_FLAG_NONE_EDGE:
558 con_reg = GPTU_CON_EDGE_SET(0x00);
559 break;
560 case TIMER_FLAG_RISE_EDGE:
561 con_reg = GPTU_CON_EDGE_SET(0x01);
562 break;
563 case TIMER_FLAG_FALL_EDGE:
564 con_reg = GPTU_CON_EDGE_SET(0x02);
565 break;
566 case TIMER_FLAG_ANY_EDGE:
567 con_reg = GPTU_CON_EDGE_SET(0x03);
568 break;
569 }
570 if(TIMER_FLAG_MASK_TYPE (flags) == TIMER_FLAG_TIMER)
571 con_reg |= TIMER_FLAG_MASK_SRC (flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET (1) : GPTU_CON_SRC_EXT_SET (0);
572 else
573 con_reg |= TIMER_FLAG_MASK_SRC (flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET (1) : GPTU_CON_SRC_EG_SET (0);
574 con_reg |= TIMER_FLAG_MASK_SYNC (flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET (0) : GPTU_CON_SYNC_SET (1);
575 con_reg |= TIMER_FLAG_MASK_INVERT (flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET (0) : GPTU_CON_INV_SET (1);
576 con_reg |= TIMER_FLAG_MASK_SIZE (flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET (0) : GPTU_CON_EXT_SET (1);
577 con_reg |= TIMER_FLAG_MASK_STOP (flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET (1) : GPTU_CON_STP_SET (0);
578 con_reg |= TIMER_FLAG_MASK_TYPE (flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET (0) : GPTU_CON_CNT_SET (1);
579 con_reg |= TIMER_FLAG_MASK_DIR (flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET (1) : GPTU_CON_DIR_SET (0);
580
581 timer_dev.timer[timer - FIRST_TIMER].flag = flags;
582 if(TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
583 timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
584
585 n = timer >> 1;
586 X = timer & 0x01;
587
588 *IFXMIPS_GPTU_CON(n, X) = con_reg;
589 smp_wmb();
590 printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *IFXMIPS_GPTU_CON (n, X));
591 mutex_unlock(&timer_dev.gptu_mutex);
592 return 0;
593 }
594 EXPORT_SYMBOL(ifxmips_reset_counter_flags);
595
596 inline int
597 ifxmips_get_count_value(unsigned int timer, unsigned long *value)
598 {
599
600 unsigned int flag;
601 unsigned int mask;
602 int n, X;
603
604 if(!timer_dev.f_gptu_on)
605 return -EINVAL;
606
607 if(timer < FIRST_TIMER
608 || timer >= FIRST_TIMER + timer_dev.number_of_timers)
609 return -EINVAL;
610
611 mutex_lock(&timer_dev.gptu_mutex);
612
613 flag = timer_dev.timer[timer - FIRST_TIMER].flag;
614 if(TIMER_FLAG_MASK_SIZE (flag) != TIMER_FLAG_16BIT)
615 timer &= ~0x01;
616
617 mask = (TIMER_FLAG_MASK_SIZE (flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
618 if (((timer_dev.occupation & mask) ^ mask))
619 {
620 mutex_unlock(&timer_dev.gptu_mutex);
621 return -EINVAL;
622 }
623
624 n = timer >> 1;
625 X = timer & 0x01;
626
627 *value = *IFXMIPS_GPTU_COUNT (n, X);
628
629 mutex_unlock(&timer_dev.gptu_mutex);
630
631 return 0;
632 }
633
634 u32
635 ifxmips_cal_divider(unsigned long freq)
636 {
637 u64 module_freq, fpi = cgu_get_fpi_bus_clock(2);
638 u32 clock_divider = 1;
639 module_freq = fpi * 1000;
640 do_div(module_freq, clock_divider * freq);
641 return module_freq;
642 }
643
644 int
645 ifxmips_set_timer (unsigned int timer, unsigned int freq, int is_cyclic,
646 int is_ext_src, unsigned int handle_flag, unsigned long arg1,
647 unsigned long arg2)
648 {
649 unsigned long divider;
650 unsigned int flag;
651
652 divider = ifxmips_cal_divider(freq);
653 if (divider == 0)
654 return -EINVAL;
655 flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
656 | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
657 | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
658 | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
659 | TIMER_FLAG_MASK_HANDLE (handle_flag);
660
661 printk(KERN_INFO "set_timer(%d, %d), divider = %lu\n", timer, freq, divider);
662 return ifxmips_request_timer (timer, flag, divider, arg1, arg2);
663 }
664
665 int
666 ifxmips_set_counter(unsigned int timer, unsigned int flag, u32 reload, unsigned long arg1, unsigned long arg2)
667 {
668 printk(KERN_INFO "set_counter(%d, %#x, %d)\n", timer, flag, reload);
669 return ifxmips_request_timer(timer, flag, reload, arg1, arg2);
670 }
671
672 static int
673 gptu_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
674 unsigned long arg)
675 {
676 int ret;
677 struct gptu_ioctl_param param;
678
679 if (!access_ok (VERIFY_READ, arg, sizeof (struct gptu_ioctl_param)))
680 return -EFAULT;
681 copy_from_user (&param, (void *) arg, sizeof (param));
682
683 if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
684 || GPTU_SET_COUNTER) && param.timer < 2)
685 || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
686 && !access_ok (VERIFY_WRITE, arg,
687 sizeof (struct gptu_ioctl_param)))
688 return -EFAULT;
689
690 switch (cmd) {
691 case GPTU_REQUEST_TIMER:
692 ret = ifxmips_request_timer (param.timer, param.flag, param.value,
693 (unsigned long) param.pid,
694 (unsigned long) param.sig);
695 if (ret > 0) {
696 copy_to_user (&((struct gptu_ioctl_param *) arg)->
697 timer, &ret, sizeof (&ret));
698 ret = 0;
699 }
700 break;
701 case GPTU_FREE_TIMER:
702 ret = ifxmips_free_timer (param.timer);
703 break;
704 case GPTU_START_TIMER:
705 ret = ifxmips_start_timer (param.timer, param.flag);
706 break;
707 case GPTU_STOP_TIMER:
708 ret = ifxmips_stop_timer (param.timer);
709 break;
710 case GPTU_GET_COUNT_VALUE:
711 ret = ifxmips_get_count_value (param.timer, &param.value);
712 if (!ret)
713 copy_to_user (&((struct gptu_ioctl_param *) arg)->
714 value, &param.value,
715 sizeof (param.value));
716 break;
717 case GPTU_CALCULATE_DIVIDER:
718 param.value = ifxmips_cal_divider (param.value);
719 if (param.value == 0)
720 ret = -EINVAL;
721 else {
722 copy_to_user (&((struct gptu_ioctl_param *) arg)->
723 value, &param.value,
724 sizeof (param.value));
725 ret = 0;
726 }
727 break;
728 case GPTU_SET_TIMER:
729 ret = ifxmips_set_timer (param.timer, param.value,
730 TIMER_FLAG_MASK_STOP (param.flag) !=
731 TIMER_FLAG_ONCE ? 1 : 0,
732 TIMER_FLAG_MASK_SRC (param.flag) ==
733 TIMER_FLAG_EXT_SRC ? 1 : 0,
734 TIMER_FLAG_MASK_HANDLE (param.flag) ==
735 TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
736 TIMER_FLAG_NO_HANDLE,
737 (unsigned long) param.pid,
738 (unsigned long) param.sig);
739 if (ret > 0) {
740 copy_to_user (&((struct gptu_ioctl_param *) arg)->
741 timer, &ret, sizeof (&ret));
742 ret = 0;
743 }
744 break;
745 case GPTU_SET_COUNTER:
746 ifxmips_set_counter (param.timer, param.flag, param.value, 0, 0);
747 if (ret > 0) {
748 copy_to_user (&((struct gptu_ioctl_param *) arg)->
749 timer, &ret, sizeof (&ret));
750 ret = 0;
751 }
752 break;
753 default:
754 ret = -ENOTTY;
755 }
756
757 return ret;
758 }
759
760 static int
761 gptu_open(struct inode *inode, struct file *file)
762 {
763 return 0;
764 }
765
766 static int
767 gptu_release(struct inode *inode, struct file *file)
768 {
769 return 0;
770 }
771 int __init
772 ifxmips_gptu_init(void)
773 {
774 int ret;
775 unsigned int i;
776
777 ifxmips_w32(0, IFXMIPS_GPTU_IRNEN);
778 ifxmips_w32(0xfff, IFXMIPS_GPTU_IRNCR);
779
780 memset(&timer_dev, 0, sizeof (timer_dev));
781 mutex_init(&timer_dev.gptu_mutex);
782
783 ifxmips_enable_gptu();
784 timer_dev.number_of_timers = GPTU_ID_CFG * 2;
785 ifxmips_disable_gptu ();
786 if(timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
787 timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
788 printk (KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
789
790 ret = misc_register(&gptu_miscdev);
791 if(ret)
792 {
793 printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
794 return ret;
795 } else {
796 printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
797 }
798
799 for(i = 0; i < timer_dev.number_of_timers; i++)
800 {
801 ret = request_irq (TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
802 if(ret)
803 {
804 for (; i >= 0; i--)
805 free_irq (TIMER_INTERRUPT + i, &timer_dev.timer[i]);
806 misc_deregister(&gptu_miscdev);
807 printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
808 return ret;
809 } else {
810 timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
811 disable_irq(timer_dev.timer[i].irq);
812 printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
813 }
814 }
815
816 return 0;
817 }
818
819 void __exit
820 ifxmips_gptu_exit(void)
821 {
822 unsigned int i;
823
824 for(i = 0; i < timer_dev.number_of_timers; i++)
825 {
826 if(timer_dev.timer[i].f_irq_on)
827 disable_irq (timer_dev.timer[i].irq);
828 free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
829 }
830 ifxmips_disable_gptu();
831 misc_deregister(&gptu_miscdev);
832 }
833
834 EXPORT_SYMBOL(ifxmips_request_timer);
835 EXPORT_SYMBOL(ifxmips_free_timer);
836 EXPORT_SYMBOL(ifxmips_start_timer);
837 EXPORT_SYMBOL(ifxmips_stop_timer);
838 EXPORT_SYMBOL(ifxmips_get_count_value);
839 EXPORT_SYMBOL(ifxmips_cal_divider);
840 EXPORT_SYMBOL(ifxmips_set_timer);
841 EXPORT_SYMBOL(ifxmips_set_counter);
842
843 module_init(ifxmips_gptu_init);
844 module_exit(ifxmips_gptu_exit);
Staging tree of Zoltan Herpai