target/linux/ipq40xx/patches-4.14/088-0012-i2c-qup-reorganization-of-driver-code-to-remove-poll.patch

   1 From fbfab1ab065879370541caf0e514987368eb41b2 Mon Sep 17 00:00:00 2001
   2 From: Abhishek Sahu <absahu@codeaurora.org>
   3 Date: Mon, 12 Mar 2018 18:45:01 +0530
   4 Subject: [PATCH 12/13] i2c: qup: reorganization of driver code to remove
   5  polling for qup v1
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Following are the major issues in current driver code
  11
  12 1. The current driver simply assumes the transfer completion
  13    whenever its gets any non-error interrupts and then simply do the
  14    polling of available/free bytes in FIFO.
  15 2. The block mode is not working properly since no handling in
  16    being done for OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ.
  17
  18 Because of above, i2c v1 transfers of size greater than 32 are failing
  19 with following error message
  20
  21         i2c_qup 78b6000.i2c: timeout for fifo out full
  22
  23 To make block mode working properly and move to use the interrupts
  24 instead of polling, major code reorganization is required. Following
  25 are the major changes done in this patch
  26
  27 1. Remove the polling of TX FIFO free space and RX FIFO available
  28    bytes and move to interrupts completely. QUP has QUP_MX_OUTPUT_DONE,
  29    QUP_MX_INPUT_DONE, OUT_BLOCK_WRITE_REQ and IN_BLOCK_READ_REQ
  30    interrupts to handle FIFO’s properly so check all these interrupts.
  31 2. During write, For FIFO mode, TX FIFO can be directly written
  32    without checking for FIFO space. For block mode, the QUP will generate
  33    OUT_BLOCK_WRITE_REQ interrupt whenever it has block size of available
  34    space.
  35 3. During read, both TX and RX FIFO will be used. TX will be used
  36    for writing tags and RX will be used for receiving the data. In QUP,
  37    TX and RX can operate in separate mode so configure modes accordingly.
  38 4. For read FIFO mode, wait for QUP_MX_INPUT_DONE interrupt which
  39    will be generated after all the bytes have been copied in RX FIFO. For
  40    read Block mode, QUP will generate IN_BLOCK_READ_REQ interrupts
  41    whenever it has block size of available data.
  42
  43 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  44 Reviewed-by: Sricharan R <sricharan@codeaurora.org>
  45 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
  46 ---
  47  drivers/i2c/busses/i2c-qup.c | 366 +++++++++++++++++++++--------------
  48  1 file changed, 223 insertions(+), 143 deletions(-)
  49
  50 --- a/drivers/i2c/busses/i2c-qup.c
  51 +++ b/drivers/i2c/busses/i2c-qup.c
  52 @@ -64,8 +64,11 @@
  53  #define QUP_IN_SVC_FLAG                BIT(9)
  54  #define QUP_MX_OUTPUT_DONE     BIT(10)
  55  #define QUP_MX_INPUT_DONE      BIT(11)
  56 +#define OUT_BLOCK_WRITE_REQ    BIT(12)
  57 +#define IN_BLOCK_READ_REQ      BIT(13)
  58
  59  /* I2C mini core related values */
  60 +#define QUP_NO_INPUT           BIT(7)
  61  #define QUP_CLOCK_AUTO_GATE    BIT(13)
  62  #define I2C_MINI_CORE          (2 << 8)
  63  #define I2C_N_VAL              15
  64 @@ -137,13 +140,36 @@
  65  #define DEFAULT_CLK_FREQ 100000
  66  #define DEFAULT_SRC_CLK 20000000
  67
  68 +/*
  69 + * count: no of blocks
  70 + * pos: current block number
  71 + * tx_tag_len: tx tag length for current block
  72 + * rx_tag_len: rx tag length for current block
  73 + * data_len: remaining data length for current message
  74 + * total_tx_len: total tx length including tag bytes for current QUP transfer
  75 + * total_rx_len: total rx length including tag bytes for current QUP transfer
  76 + * tx_fifo_free: number of free bytes in current QUP block write.
  77 + * fifo_available: number of available bytes in RX FIFO for current
  78 + *                QUP block read
  79 + * rx_bytes_read: if all the bytes have been read from rx FIFO.
  80 + * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer.
  81 + * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer.
  82 + * tags: contains tx tag bytes for current QUP transfer
  83 + */
  84  struct qup_i2c_block {
  85 -       int     count;
  86 -       int     pos;
  87 -       int     tx_tag_len;
  88 -       int     rx_tag_len;
  89 -       int     data_len;
  90 -       u8      tags[6];
  91 +       int             count;
  92 +       int             pos;
  93 +       int             tx_tag_len;
  94 +       int             rx_tag_len;
  95 +       int             data_len;
  96 +       int             total_tx_len;
  97 +       int             total_rx_len;
  98 +       int             tx_fifo_free;
  99 +       int             fifo_available;
 100 +       bool            rx_bytes_read;
 101 +       bool            is_tx_blk_mode;
 102 +       bool            is_rx_blk_mode;
 103 +       u8              tags[6];
 104  };
 105
 106  struct qup_i2c_tag {
 107 @@ -186,6 +212,7 @@ struct qup_i2c_dev {
 108
 109         /* To check if this is the last msg */
 110         bool                    is_last;
 111 +       bool                    is_qup_v1;
 112
 113         /* To configure when bus is in run state */
 114         int                     config_run;
 115 @@ -202,11 +229,18 @@ struct qup_i2c_dev {
 116         struct                  qup_i2c_bam btx;
 117
 118         struct completion       xfer;
 119 +       /* function to write data in tx fifo */
 120 +       void (*write_tx_fifo)(struct qup_i2c_dev *qup);
 121 +       /* function to read data from rx fifo */
 122 +       void (*read_rx_fifo)(struct qup_i2c_dev *qup);
 123 +       /* function to write tags in tx fifo for i2c read transfer */
 124 +       void (*write_rx_tags)(struct qup_i2c_dev *qup);
 125  };
 126
 127  static irqreturn_t qup_i2c_interrupt(int irq, void *dev)
 128  {
 129         struct qup_i2c_dev *qup = dev;
 130 +       struct qup_i2c_block *blk = &qup->blk;
 131         u32 bus_err;
 132         u32 qup_err;
 133         u32 opflags;
 134 @@ -253,12 +287,48 @@ static irqreturn_t qup_i2c_interrupt(int
 135                 goto done;
 136         }
 137
 138 -       if (opflags & QUP_IN_SVC_FLAG)
 139 -               writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 140 +       if (!qup->is_qup_v1)
 141 +               goto done;
 142
 143 -       if (opflags & QUP_OUT_SVC_FLAG)
 144 +       if (opflags & QUP_OUT_SVC_FLAG) {
 145                 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 146
 147 +               if (opflags & OUT_BLOCK_WRITE_REQ) {
 148 +                       blk->tx_fifo_free += qup->out_blk_sz;
 149 +                       if (qup->msg->flags & I2C_M_RD)
 150 +                               qup->write_rx_tags(qup);
 151 +                       else
 152 +                               qup->write_tx_fifo(qup);
 153 +               }
 154 +       }
 155 +
 156 +       if (opflags & QUP_IN_SVC_FLAG) {
 157 +               writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);
 158 +
 159 +               if (!blk->is_rx_blk_mode) {
 160 +                       blk->fifo_available += qup->in_fifo_sz;
 161 +                       qup->read_rx_fifo(qup);
 162 +               } else if (opflags & IN_BLOCK_READ_REQ) {
 163 +                       blk->fifo_available += qup->in_blk_sz;
 164 +                       qup->read_rx_fifo(qup);
 165 +               }
 166 +       }
 167 +
 168 +       if (qup->msg->flags & I2C_M_RD) {
 169 +               if (!blk->rx_bytes_read)
 170 +                       return IRQ_HANDLED;
 171 +       } else {
 172 +               /*
 173 +                * Ideally, QUP_MAX_OUTPUT_DONE_FLAG should be checked
 174 +                * for FIFO mode also. But, QUP_MAX_OUTPUT_DONE_FLAG lags
 175 +                * behind QUP_OUTPUT_SERVICE_FLAG sometimes. The only reason
 176 +                * of interrupt for write message in FIFO mode is
 177 +                * QUP_MAX_OUTPUT_DONE_FLAG condition.
 178 +                */
 179 +               if (blk->is_tx_blk_mode && !(opflags & QUP_MX_OUTPUT_DONE))
 180 +                       return IRQ_HANDLED;
 181 +       }
 182 +
 183  done:
 184         qup->qup_err = qup_err;
 185         qup->bus_err = bus_err;
 186 @@ -324,6 +394,28 @@ static int qup_i2c_change_state(struct q
 187         return 0;
 188  }
 189
 190 +/* Check if I2C bus returns to IDLE state */
 191 +static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len)
 192 +{
 193 +       unsigned long timeout;
 194 +       u32 status;
 195 +       int ret = 0;
 196 +
 197 +       timeout = jiffies + len * 4;
 198 +       for (;;) {
 199 +               status = readl(qup->base + QUP_I2C_STATUS);
 200 +               if (!(status & I2C_STATUS_BUS_ACTIVE))
 201 +                       break;
 202 +
 203 +               if (time_after(jiffies, timeout))
 204 +                       ret = -ETIMEDOUT;
 205 +
 206 +               usleep_range(len, len * 2);
 207 +       }
 208 +
 209 +       return ret;
 210 +}
 211 +
 212  /**
 213   * qup_i2c_wait_ready - wait for a give number of bytes in tx/rx path
 214   * @qup: The qup_i2c_dev device
 215 @@ -394,23 +486,6 @@ static void qup_i2c_set_write_mode_v2(st
 216         }
 217  }
 218
 219 -static void qup_i2c_set_write_mode(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 220 -{
 221 -       /* Number of entries to shift out, including the start */
 222 -       int total = msg->len + 1;
 223 -
 224 -       if (total < qup->out_fifo_sz) {
 225 -               /* FIFO mode */
 226 -               writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 227 -               writel(total, qup->base + QUP_MX_WRITE_CNT);
 228 -       } else {
 229 -               /* BLOCK mode (transfer data on chunks) */
 230 -               writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,
 231 -                      qup->base + QUP_IO_MODE);
 232 -               writel(total, qup->base + QUP_MX_OUTPUT_CNT);
 233 -       }
 234 -}
 235 -
 236  static int check_for_fifo_space(struct qup_i2c_dev *qup)
 237  {
 238         int ret;
 239 @@ -443,28 +518,25 @@ out:
 240         return ret;
 241  }
 242
 243 -static int qup_i2c_issue_write(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 244 +static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup)
 245  {
 246 +       struct qup_i2c_block *blk = &qup->blk;
 247 +       struct i2c_msg *msg = qup->msg;
 248         u32 addr = msg->addr << 1;
 249         u32 qup_tag;
 250         int idx;
 251         u32 val;
 252 -       int ret = 0;
 253
 254         if (qup->pos == 0) {
 255                 val = QUP_TAG_START | addr;
 256                 idx = 1;
 257 +               blk->tx_fifo_free--;
 258         } else {
 259                 val = 0;
 260                 idx = 0;
 261         }
 262
 263 -       while (qup->pos < msg->len) {
 264 -               /* Check that there's space in the FIFO for our pair */
 265 -               ret = check_for_fifo_space(qup);
 266 -               if (ret)
 267 -                       return ret;
 268 -
 269 +       while (blk->tx_fifo_free && qup->pos < msg->len) {
 270                 if (qup->pos == msg->len - 1)
 271                         qup_tag = QUP_TAG_STOP;
 272                 else
 273 @@ -481,11 +553,8 @@ static int qup_i2c_issue_write(struct qu
 274
 275                 qup->pos++;
 276                 idx++;
 277 +               blk->tx_fifo_free--;
 278         }
 279 -
 280 -       ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 281 -
 282 -       return ret;
 283  }
 284
 285  static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup,
 286 @@ -1006,64 +1075,6 @@ err:
 287         return ret;
 288  }
 289
 290 -static int qup_i2c_write_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 291 -{
 292 -       int ret;
 293 -
 294 -       qup->msg = msg;
 295 -       qup->pos = 0;
 296 -
 297 -       enable_irq(qup->irq);
 298 -
 299 -       qup_i2c_set_write_mode(qup, msg);
 300 -
 301 -       ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 302 -       if (ret)
 303 -               goto err;
 304 -
 305 -       writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 306 -
 307 -       do {
 308 -               ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 309 -               if (ret)
 310 -                       goto err;
 311 -
 312 -               ret = qup_i2c_issue_write(qup, msg);
 313 -               if (ret)
 314 -                       goto err;
 315 -
 316 -               ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 317 -               if (ret)
 318 -                       goto err;
 319 -
 320 -               ret = qup_i2c_wait_for_complete(qup, msg);
 321 -               if (ret)
 322 -                       goto err;
 323 -       } while (qup->pos < msg->len);
 324 -
 325 -       /* Wait for the outstanding data in the fifo to drain */
 326 -       ret = qup_i2c_wait_ready(qup, QUP_OUT_NOT_EMPTY, RESET_BIT, ONE_BYTE);
 327 -err:
 328 -       disable_irq(qup->irq);
 329 -       qup->msg = NULL;
 330 -
 331 -       return ret;
 332 -}
 333 -
 334 -static void qup_i2c_set_read_mode(struct qup_i2c_dev *qup, int len)
 335 -{
 336 -       if (len < qup->in_fifo_sz) {
 337 -               /* FIFO mode */
 338 -               writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);
 339 -               writel(len, qup->base + QUP_MX_READ_CNT);
 340 -       } else {
 341 -               /* BLOCK mode (transfer data on chunks) */
 342 -               writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,
 343 -                      qup->base + QUP_IO_MODE);
 344 -               writel(len, qup->base + QUP_MX_INPUT_CNT);
 345 -       }
 346 -}
 347 -
 348  static void qup_i2c_set_read_mode_v2(struct qup_i2c_dev *qup, int len)
 349  {
 350         int tx_len = qup->blk.tx_tag_len;
 351 @@ -1086,44 +1097,27 @@ static void qup_i2c_set_read_mode_v2(str
 352         }
 353  }
 354
 355 -static void qup_i2c_issue_read(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 356 -{
 357 -       u32 addr, len, val;
 358 -
 359 -       addr = i2c_8bit_addr_from_msg(msg);
 360 -
 361 -       /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
 362 -       len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
 363 -
 364 -       val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
 365 -       writel(val, qup->base + QUP_OUT_FIFO_BASE);
 366 -}
 367 -
 368 -
 369 -static int qup_i2c_read_fifo(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 370 +static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup)
 371  {
 372 +       struct qup_i2c_block *blk = &qup->blk;
 373 +       struct i2c_msg *msg = qup->msg;
 374         u32 val = 0;
 375 -       int idx;
 376 -       int ret = 0;
 377 +       int idx = 0;
 378
 379 -       for (idx = 0; qup->pos < msg->len; idx++) {
 380 +       while (blk->fifo_available && qup->pos < msg->len) {
 381                 if ((idx & 1) == 0) {
 382 -                       /* Check that FIFO have data */
 383 -                       ret = qup_i2c_wait_ready(qup, QUP_IN_NOT_EMPTY,
 384 -                                                SET_BIT, 4 * ONE_BYTE);
 385 -                       if (ret)
 386 -                               return ret;
 387 -
 388                         /* Reading 2 words at time */
 389                         val = readl(qup->base + QUP_IN_FIFO_BASE);
 390 -
 391                         msg->buf[qup->pos++] = val & 0xFF;
 392                 } else {
 393                         msg->buf[qup->pos++] = val >> QUP_MSW_SHIFT;
 394                 }
 395 +               idx++;
 396 +               blk->fifo_available--;
 397         }
 398
 399 -       return ret;
 400 +       if (qup->pos == msg->len)
 401 +               blk->rx_bytes_read = true;
 402  }
 403
 404  static int qup_i2c_read_fifo_v2(struct qup_i2c_dev *qup,
 405 @@ -1224,49 +1218,130 @@ err:
 406         return ret;
 407  }
 408
 409 -static int qup_i2c_read_one(struct qup_i2c_dev *qup, struct i2c_msg *msg)
 410 +static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup)
 411  {
 412 -       int ret;
 413 +       struct i2c_msg *msg = qup->msg;
 414 +       u32 addr, len, val;
 415
 416 -       qup->msg = msg;
 417 -       qup->pos  = 0;
 418 +       addr = i2c_8bit_addr_from_msg(msg);
 419
 420 -       enable_irq(qup->irq);
 421 -       qup_i2c_set_read_mode(qup, msg->len);
 422 +       /* 0 is used to specify a length 256 (QUP_READ_LIMIT) */
 423 +       len = (msg->len == QUP_READ_LIMIT) ? 0 : msg->len;
 424 +
 425 +       val = ((QUP_TAG_REC | len) << QUP_MSW_SHIFT) | QUP_TAG_START | addr;
 426 +       writel(val, qup->base + QUP_OUT_FIFO_BASE);
 427 +}
 428 +
 429 +static void qup_i2c_conf_v1(struct qup_i2c_dev *qup)
 430 +{
 431 +       struct qup_i2c_block *blk = &qup->blk;
 432 +       u32 qup_config = I2C_MINI_CORE | I2C_N_VAL;
 433 +       u32 io_mode = QUP_REPACK_EN;
 434 +
 435 +       blk->is_tx_blk_mode =
 436 +               blk->total_tx_len > qup->out_fifo_sz ? true : false;
 437 +       blk->is_rx_blk_mode =
 438 +               blk->total_rx_len > qup->in_fifo_sz ? true : false;
 439 +
 440 +       if (blk->is_tx_blk_mode) {
 441 +               io_mode |= QUP_OUTPUT_BLK_MODE;
 442 +               writel(0, qup->base + QUP_MX_WRITE_CNT);
 443 +               writel(blk->total_tx_len, qup->base + QUP_MX_OUTPUT_CNT);
 444 +       } else {
 445 +               writel(0, qup->base + QUP_MX_OUTPUT_CNT);
 446 +               writel(blk->total_tx_len, qup->base + QUP_MX_WRITE_CNT);
 447 +       }
 448 +
 449 +       if (blk->total_rx_len) {
 450 +               if (blk->is_rx_blk_mode) {
 451 +                       io_mode |= QUP_INPUT_BLK_MODE;
 452 +                       writel(0, qup->base + QUP_MX_READ_CNT);
 453 +                       writel(blk->total_rx_len, qup->base + QUP_MX_INPUT_CNT);
 454 +               } else {
 455 +                       writel(0, qup->base + QUP_MX_INPUT_CNT);
 456 +                       writel(blk->total_rx_len, qup->base + QUP_MX_READ_CNT);
 457 +               }
 458 +       } else {
 459 +               qup_config |= QUP_NO_INPUT;
 460 +       }
 461 +
 462 +       writel(qup_config, qup->base + QUP_CONFIG);
 463 +       writel(io_mode, qup->base + QUP_IO_MODE);
 464 +}
 465
 466 +static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk)
 467 +{
 468 +       blk->tx_fifo_free = 0;
 469 +       blk->fifo_available = 0;
 470 +       blk->rx_bytes_read = false;
 471 +}
 472 +
 473 +static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx)
 474 +{
 475 +       struct qup_i2c_block *blk = &qup->blk;
 476 +       int ret;
 477 +
 478 +       qup_i2c_clear_blk_v1(blk);
 479 +       qup_i2c_conf_v1(qup);
 480         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 481         if (ret)
 482 -               goto err;
 483 +               return ret;
 484
 485         writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);
 486
 487         ret = qup_i2c_change_state(qup, QUP_PAUSE_STATE);
 488         if (ret)
 489 -               goto err;
 490 +               return ret;
 491 +
 492 +       reinit_completion(&qup->xfer);
 493 +       enable_irq(qup->irq);
 494 +       if (!blk->is_tx_blk_mode) {
 495 +               blk->tx_fifo_free = qup->out_fifo_sz;
 496
 497 -       qup_i2c_issue_read(qup, msg);
 498 +               if (is_rx)
 499 +                       qup_i2c_write_rx_tags_v1(qup);
 500 +               else
 501 +                       qup_i2c_write_tx_fifo_v1(qup);
 502 +       }
 503
 504         ret = qup_i2c_change_state(qup, QUP_RUN_STATE);
 505         if (ret)
 506                 goto err;
 507
 508 -       do {
 509 -               ret = qup_i2c_wait_for_complete(qup, msg);
 510 -               if (ret)
 511 -                       goto err;
 512 +       ret = qup_i2c_wait_for_complete(qup, qup->msg);
 513 +       if (ret)
 514 +               goto err;
 515
 516 -               ret = qup_i2c_read_fifo(qup, msg);
 517 -               if (ret)
 518 -                       goto err;
 519 -       } while (qup->pos < msg->len);
 520 +       ret = qup_i2c_bus_active(qup, ONE_BYTE);
 521
 522  err:
 523         disable_irq(qup->irq);
 524 -       qup->msg = NULL;
 525 -
 526         return ret;
 527  }
 528
 529 +static int qup_i2c_write_one(struct qup_i2c_dev *qup)
 530 +{
 531 +       struct i2c_msg *msg = qup->msg;
 532 +       struct qup_i2c_block *blk = &qup->blk;
 533 +
 534 +       qup->pos = 0;
 535 +       blk->total_tx_len = msg->len + 1;
 536 +       blk->total_rx_len = 0;
 537 +
 538 +       return qup_i2c_conf_xfer_v1(qup, false);
 539 +}
 540 +
 541 +static int qup_i2c_read_one(struct qup_i2c_dev *qup)
 542 +{
 543 +       struct qup_i2c_block *blk = &qup->blk;
 544 +
 545 +       qup->pos = 0;
 546 +       blk->total_tx_len = 2;
 547 +       blk->total_rx_len = qup->msg->len;
 548 +
 549 +       return qup_i2c_conf_xfer_v1(qup, true);
 550 +}
 551 +
 552  static int qup_i2c_xfer(struct i2c_adapter *adap,
 553                         struct i2c_msg msgs[],
 554                         int num)
 555 @@ -1305,10 +1380,11 @@ static int qup_i2c_xfer(struct i2c_adapt
 556                         goto out;
 557                 }
 558
 559 +               qup->msg = &msgs[idx];
 560                 if (msgs[idx].flags & I2C_M_RD)
 561 -                       ret = qup_i2c_read_one(qup, &msgs[idx]);
 562 +                       ret = qup_i2c_read_one(qup);
 563                 else
 564 -                       ret = qup_i2c_write_one(qup, &msgs[idx]);
 565 +                       ret = qup_i2c_write_one(qup);
 566
 567                 if (ret)
 568                         break;
 569 @@ -1487,6 +1563,10 @@ static int qup_i2c_probe(struct platform
 570         if (of_device_is_compatible(pdev->dev.of_node, "qcom,i2c-qup-v1.1.1")) {
 571                 qup->adap.algo = &qup_i2c_algo;
 572                 qup->adap.quirks = &qup_i2c_quirks;
 573 +               qup->is_qup_v1 = true;
 574 +               qup->write_tx_fifo = qup_i2c_write_tx_fifo_v1;
 575 +               qup->read_rx_fifo = qup_i2c_read_rx_fifo_v1;
 576 +               qup->write_rx_tags = qup_i2c_write_rx_tags_v1;
 577         } else {
 578                 qup->adap.algo = &qup_i2c_algo_v2;
 579                 ret = qup_i2c_req_dma(qup);