target/linux/ipq806x/patches-4.9/0032-phy-add-qcom-dwc3-phy.patch

   1 From b9004f4fd23e4c614d71c972f3a9311665480e29 Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Thu, 9 Mar 2017 08:19:18 +0100
   4 Subject: [PATCH 32/69] phy: add qcom dwc3 phy
   5
   6 Signed-off-by: Andy Gross <agross@codeaurora.org>
   7 ---
   8  drivers/phy/Kconfig         |  12 ++
   9  drivers/phy/Makefile        |   1 +
  10  drivers/phy/phy-qcom-dwc3.c | 484 ++++++++++++++++++++++++++++++++++++++++++++
  11  3 files changed, 497 insertions(+)
  12  create mode 100644 drivers/phy/phy-qcom-dwc3.c
  13
  14 --- a/drivers/phy/Kconfig
  15 +++ b/drivers/phy/Kconfig
  16 @@ -490,4 +490,16 @@ config PHY_NS2_PCIE
  17         help
  18           Enable this to support the Broadcom Northstar2 PCIe PHY.
  19           If unsure, say N.
  20 +
  21 +config PHY_QCOM_DWC3
  22 +       tristate "QCOM DWC3 USB PHY support"
  23 +       depends on ARCH_QCOM
  24 +       depends on HAS_IOMEM
  25 +       depends on OF
  26 +       select GENERIC_PHY
  27 +       help
  28 +         This option enables support for the Synopsis PHYs present inside the
  29 +         Qualcomm USB3.0 DWC3 controller.  This driver supports both HS and SS
  30 +         PHY controllers.
  31 +
  32  endmenu
  33 --- a/drivers/phy/Makefile
  34 +++ b/drivers/phy/Makefile
  35 @@ -60,3 +60,4 @@ obj-$(CONFIG_PHY_PISTACHIO_USB)               += phy-
  36  obj-$(CONFIG_PHY_CYGNUS_PCIE)          += phy-bcm-cygnus-pcie.o
  37  obj-$(CONFIG_ARCH_TEGRA) += tegra/
  38  obj-$(CONFIG_PHY_NS2_PCIE)             += phy-bcm-ns2-pcie.o
  39 +obj-$(CONFIG_PHY_QCOM_DWC3)            += phy-qcom-dwc3.o
  40 --- /dev/null
  41 +++ b/drivers/phy/phy-qcom-dwc3.c
  42 @@ -0,0 +1,492 @@
  43 +/* Copyright (c) 2014-2015, Code Aurora Forum. All rights reserved.
  44 + *
  45 + * This program is free software; you can redistribute it and/or modify
  46 + * it under the terms of the GNU General Public License version 2 and
  47 + * only version 2 as published by the Free Software Foundation.
  48 + *
  49 +* This program is distributed in the hope that it will be useful,
  50 +* but WITHOUT ANY WARRANTY; without even the implied warranty of
  51 +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  52 +* GNU General Public License for more details.
  53 +*/
  54 +
  55 +#include <linux/clk.h>
  56 +#include <linux/err.h>
  57 +#include <linux/io.h>
  58 +#include <linux/module.h>
  59 +#include <linux/of.h>
  60 +#include <linux/phy/phy.h>
  61 +#include <linux/platform_device.h>
  62 +#include <linux/delay.h>
  63 +
  64 +/**
  65 + *  USB QSCRATCH Hardware registers
  66 + */
  67 +#define QSCRATCH_GENERAL_CFG           (0x08)
  68 +#define HSUSB_PHY_CTRL_REG             (0x10)
  69 +
  70 +/* PHY_CTRL_REG */
  71 +#define HSUSB_CTRL_DMSEHV_CLAMP                        BIT(24)
  72 +#define HSUSB_CTRL_USB2_SUSPEND                        BIT(23)
  73 +#define HSUSB_CTRL_UTMI_CLK_EN                 BIT(21)
  74 +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID         BIT(20)
  75 +#define HSUSB_CTRL_USE_CLKCORE                 BIT(18)
  76 +#define HSUSB_CTRL_DPSEHV_CLAMP                        BIT(17)
  77 +#define HSUSB_CTRL_COMMONONN                   BIT(11)
  78 +#define HSUSB_CTRL_ID_HV_CLAMP                 BIT(9)
  79 +#define HSUSB_CTRL_OTGSESSVLD_CLAMP            BIT(8)
  80 +#define HSUSB_CTRL_CLAMP_EN                    BIT(7)
  81 +#define HSUSB_CTRL_RETENABLEN                  BIT(1)
  82 +#define HSUSB_CTRL_POR                         BIT(0)
  83 +
  84 +/* QSCRATCH_GENERAL_CFG */
  85 +#define HSUSB_GCFG_XHCI_REV            BIT(2)
  86 +
  87 +/**
  88 + *  USB QSCRATCH Hardware registers
  89 + */
  90 +#define SSUSB_PHY_CTRL_REG             (0x00)
  91 +#define SSUSB_PHY_PARAM_CTRL_1         (0x04)
  92 +#define SSUSB_PHY_PARAM_CTRL_2         (0x08)
  93 +#define CR_PROTOCOL_DATA_IN_REG                (0x0c)
  94 +#define CR_PROTOCOL_DATA_OUT_REG       (0x10)
  95 +#define CR_PROTOCOL_CAP_ADDR_REG       (0x14)
  96 +#define CR_PROTOCOL_CAP_DATA_REG       (0x18)
  97 +#define CR_PROTOCOL_READ_REG           (0x1c)
  98 +#define CR_PROTOCOL_WRITE_REG          (0x20)
  99 +
 100 +/* PHY_CTRL_REG */
 101 +#define SSUSB_CTRL_REF_USE_PAD         BIT(28)
 102 +#define SSUSB_CTRL_TEST_POWERDOWN      BIT(26)
 103 +#define SSUSB_CTRL_LANE0_PWR_PRESENT   BIT(24)
 104 +#define SSUSB_CTRL_SS_PHY_EN           BIT(8)
 105 +#define SSUSB_CTRL_SS_PHY_RESET                BIT(7)
 106 +
 107 +/* SSPHY control registers */
 108 +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane)
 109 +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane)        (0x1002 + 0x100 * lane)
 110 +
 111 +/* RX OVRD IN HI bits */
 112 +#define RX_OVRD_IN_HI_RX_RESET_OVRD            BIT(13)
 113 +#define RX_OVRD_IN_HI_RX_RX_RESET              BIT(12)
 114 +#define RX_OVRD_IN_HI_RX_EQ_OVRD               BIT(11)
 115 +#define RX_OVRD_IN_HI_RX_EQ_MASK               0x0700
 116 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT              8
 117 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD            BIT(7)
 118 +#define RX_OVRD_IN_HI_RX_EQ_EN                 BIT(6)
 119 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD       BIT(5)
 120 +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK       0x0018
 121 +#define RX_OVRD_IN_HI_RX_RATE_OVRD             BIT(2)
 122 +#define RX_OVRD_IN_HI_RX_RATE_MASK             0x0003
 123 +
 124 +/* TX OVRD DRV LO register bits */
 125 +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK  0x007F
 126 +#define TX_OVRD_DRV_LO_PREEMPH_MASK    0x3F80
 127 +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT   7
 128 +#define TX_OVRD_DRV_LO_EN              BIT(14)
 129 +
 130 +/* SS CAP register bits */
 131 +#define SS_CR_CAP_ADDR_REG             BIT(0)
 132 +#define SS_CR_CAP_DATA_REG             BIT(0)
 133 +#define SS_CR_READ_REG                 BIT(0)
 134 +#define SS_CR_WRITE_REG                        BIT(0)
 135 +
 136 +struct qcom_dwc3_usb_phy {
 137 +       void __iomem            *base;
 138 +       struct device           *dev;
 139 +       struct clk              *xo_clk;
 140 +       struct clk              *ref_clk;
 141 +};
 142 +
 143 +struct qcom_dwc3_phy_drvdata {
 144 +       struct phy_ops  ops;
 145 +       u32             clk_rate;
 146 +};
 147 +
 148 +/**
 149 + * Write register and read back masked value to confirm it is written
 150 + *
 151 + * @base - QCOM DWC3 PHY base virtual address.
 152 + * @offset - register offset.
 153 + * @mask - register bitmask specifying what should be updated
 154 + * @val - value to write.
 155 + */
 156 +static inline void qcom_dwc3_phy_write_readback(
 157 +       struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
 158 +       const u32 mask, u32 val)
 159 +{
 160 +       u32 write_val, tmp = readl(phy_dwc3->base + offset);
 161 +
 162 +       tmp &= ~mask;           /* retain other bits */
 163 +       write_val = tmp | val;
 164 +
 165 +       writel(write_val, phy_dwc3->base + offset);
 166 +
 167 +       /* Read back to see if val was written */
 168 +       tmp = readl(phy_dwc3->base + offset);
 169 +       tmp &= mask;            /* clear other bits */
 170 +
 171 +       if (tmp != val)
 172 +               dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
 173 +                       val, offset);
 174 +}
 175 +
 176 +static int wait_for_latch(void __iomem *addr)
 177 +{
 178 +       u32 retry = 10;
 179 +
 180 +       while (true) {
 181 +               if (!readl(addr))
 182 +                       break;
 183 +
 184 +               if (--retry == 0)
 185 +                       return -ETIMEDOUT;
 186 +
 187 +               usleep_range(10, 20);
 188 +       }
 189 +
 190 +       return 0;
 191 +}
 192 +
 193 +/**
 194 + * Write SSPHY register
 195 + *
 196 + * @base - QCOM DWC3 PHY base virtual address.
 197 + * @addr - SSPHY address to write.
 198 + * @val - value to write.
 199 + */
 200 +static int qcom_dwc3_ss_write_phycreg(struct qcom_dwc3_usb_phy *phy_dwc3,
 201 +                                       u32 addr, u32 val)
 202 +{
 203 +       int ret;
 204 +
 205 +       writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
 206 +       writel(SS_CR_CAP_ADDR_REG, phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 207 +
 208 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
 209 +       if (ret)
 210 +               goto err_wait;
 211 +
 212 +       writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
 213 +       writel(SS_CR_CAP_DATA_REG, phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
 214 +
 215 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
 216 +       if (ret)
 217 +               goto err_wait;
 218 +
 219 +       writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
 220 +
 221 +       ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
 222 +
 223 +err_wait:
 224 +       if (ret)
 225 +               dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
 226 +       return ret;
 227 +}
 228 +
 229 +/**
 230 + * Read SSPHY register.
 231 + *
 232 + * @base - QCOM DWC3 PHY base virtual address.
 233 + * @addr - SSPHY address to read.
 234 + */
 235 +static int qcom_dwc3_ss_read_phycreg(void __iomem *base, u32 addr, u32 *val)
 236 +{
 237 +       int ret;
 238 +
 239 +       writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
 240 +       writel(SS_CR_CAP_ADDR_REG, base + CR_PROTOCOL_CAP_ADDR_REG);
 241 +
 242 +       ret = wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG);
 243 +       if (ret)
 244 +               goto err_wait;
 245 +
 246 +       /*
 247 +        * Due to hardware bug, first read of SSPHY register might be
 248 +        * incorrect. Hence as workaround, SW should perform SSPHY register
 249 +        * read twice, but use only second read and ignore first read.
 250 +        */
 251 +       writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
 252 +
 253 +       ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
 254 +       if (ret)
 255 +               goto err_wait;
 256 +
 257 +       /* throwaway read */
 258 +       readl(base + CR_PROTOCOL_DATA_OUT_REG);
 259 +
 260 +       writel(SS_CR_READ_REG, base + CR_PROTOCOL_READ_REG);
 261 +
 262 +       ret = wait_for_latch(base + CR_PROTOCOL_READ_REG);
 263 +       if (ret)
 264 +               goto err_wait;
 265 +
 266 +       *val = readl(base + CR_PROTOCOL_DATA_OUT_REG);
 267 +
 268 +err_wait:
 269 +       return ret;
 270 +}
 271 +
 272 +static int qcom_dwc3_phy_power_on(struct phy *phy)
 273 +{
 274 +       int ret;
 275 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 276 +
 277 +       ret = clk_prepare_enable(phy_dwc3->xo_clk);
 278 +       if (ret)
 279 +               return ret;
 280 +
 281 +       ret = clk_prepare_enable(phy_dwc3->ref_clk);
 282 +       if (ret)
 283 +               clk_disable_unprepare(phy_dwc3->xo_clk);
 284 +
 285 +       return ret;
 286 +}
 287 +
 288 +static int qcom_dwc3_phy_power_off(struct phy *phy)
 289 +{
 290 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 291 +
 292 +       clk_disable_unprepare(phy_dwc3->ref_clk);
 293 +       clk_disable_unprepare(phy_dwc3->xo_clk);
 294 +
 295 +       return 0;
 296 +}
 297 +
 298 +static int qcom_dwc3_hs_phy_init(struct phy *phy)
 299 +{
 300 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 301 +       u32 val;
 302 +
 303 +       /*
 304 +        * HSPHY Initialization: Enable UTMI clock, select 19.2MHz fsel
 305 +        * enable clamping, and disable RETENTION (power-on default is ENABLED)
 306 +        */
 307 +       val = HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_DMSEHV_CLAMP |
 308 +               HSUSB_CTRL_RETENABLEN  | HSUSB_CTRL_COMMONONN |
 309 +               HSUSB_CTRL_OTGSESSVLD_CLAMP | HSUSB_CTRL_ID_HV_CLAMP |
 310 +               HSUSB_CTRL_DPSEHV_CLAMP | HSUSB_CTRL_UTMI_OTG_VBUS_VALID |
 311 +               HSUSB_CTRL_UTMI_CLK_EN | HSUSB_CTRL_CLAMP_EN | 0x70;
 312 +
 313 +       /* use core clock if external reference is not present */
 314 +       if (!phy_dwc3->xo_clk)
 315 +               val |= HSUSB_CTRL_USE_CLKCORE;
 316 +
 317 +       writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
 318 +       usleep_range(2000, 2200);
 319 +
 320 +       /* Disable (bypass) VBUS and ID filters */
 321 +       writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
 322 +
 323 +       return 0;
 324 +}
 325 +
 326 +static int qcom_dwc3_ss_phy_init(struct phy *phy)
 327 +{
 328 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 329 +       int ret;
 330 +       u32 data = 0;
 331 +
 332 +       /* reset phy */
 333 +       data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 334 +
 335 +       /* Test and clear SSUSB_CTRL_TEST_POWERDOWN */
 336 +       if (data & SSUSB_CTRL_TEST_POWERDOWN) {
 337 +               qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 338 +                               SSUSB_CTRL_TEST_POWERDOWN, 0x0);
 339 +               data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 340 +       }
 341 +
 342 +       writel(data | SSUSB_CTRL_SS_PHY_RESET,
 343 +               phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 344 +       usleep_range(2000, 2200);
 345 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 346 +
 347 +       /* clear REF_PAD if we don't have XO clk */
 348 +       if (!phy_dwc3->xo_clk)
 349 +               data &= ~SSUSB_CTRL_REF_USE_PAD;
 350 +       else
 351 +               data |= SSUSB_CTRL_REF_USE_PAD;
 352 +
 353 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 354 +
 355 +       /* wait for ref clk to become stable, this can take up to 30ms */
 356 +       msleep(30);
 357 +
 358 +       data |= SSUSB_CTRL_SS_PHY_EN | SSUSB_CTRL_LANE0_PWR_PRESENT;
 359 +       writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
 360 +
 361 +       /*
 362 +        * Fix RX Equalization setting as follows
 363 +        * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
 364 +        * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
 365 +        * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
 366 +        * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
 367 +        */
 368 +       ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
 369 +                       SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
 370 +       if (ret)
 371 +               goto err_phy_trans;
 372 +
 373 +       data &= ~RX_OVRD_IN_HI_RX_EQ_EN;
 374 +       data |= RX_OVRD_IN_HI_RX_EQ_EN_OVRD;
 375 +       data &= ~RX_OVRD_IN_HI_RX_EQ_MASK;
 376 +       data |= 0x3 << RX_OVRD_IN_HI_RX_EQ_SHIFT;
 377 +       data |= RX_OVRD_IN_HI_RX_EQ_OVRD;
 378 +       ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
 379 +               SSPHY_CTRL_RX_OVRD_IN_HI(0), data);
 380 +       if (ret)
 381 +               goto err_phy_trans;
 382 +
 383 +       /*
 384 +        * Set EQ and TX launch amplitudes as follows
 385 +        * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
 386 +        * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
 387 +        * LANE0.TX_OVRD_DRV_LO.EN set to 1.
 388 +        */
 389 +       ret = qcom_dwc3_ss_read_phycreg(phy_dwc3->base,
 390 +               SSPHY_CTRL_TX_OVRD_DRV_LO(0), &data);
 391 +       if (ret)
 392 +               goto err_phy_trans;
 393 +
 394 +       data &= ~TX_OVRD_DRV_LO_PREEMPH_MASK;
 395 +       data |= 0x16 << TX_OVRD_DRV_LO_PREEMPH_SHIFT;
 396 +       data &= ~TX_OVRD_DRV_LO_AMPLITUDE_MASK;
 397 +       data |= 0x7f;
 398 +       data |= TX_OVRD_DRV_LO_EN;
 399 +       ret = qcom_dwc3_ss_write_phycreg(phy_dwc3,
 400 +               SSPHY_CTRL_TX_OVRD_DRV_LO(0), data);
 401 +       if (ret)
 402 +               goto err_phy_trans;
 403 +
 404 +       /*
 405 +        * Set the QSCRATCH PHY_PARAM_CTRL1 parameters as follows
 406 +        * TX_FULL_SWING [26:20] amplitude to 127
 407 +        * TX_DEEMPH_3_5DB [13:8] to 22
 408 +        * LOS_BIAS [2:0] to 0x5
 409 +        */
 410 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
 411 +                                  0x07f03f07, 0x07f01605);
 412 +
 413 +err_phy_trans:
 414 +       return ret;
 415 +}
 416 +
 417 +static int qcom_dwc3_ss_phy_exit(struct phy *phy)
 418 +{
 419 +       struct qcom_dwc3_usb_phy *phy_dwc3 = phy_get_drvdata(phy);
 420 +
 421 +       /* Sequence to put SSPHY in low power state:
 422 +        * 1. Clear REF_PHY_EN in PHY_CTRL_REG
 423 +        * 2. Clear REF_USE_PAD in PHY_CTRL_REG
 424 +        * 3. Set TEST_POWERED_DOWN in PHY_CTRL_REG to enable PHY retention
 425 +        */
 426 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 427 +               SSUSB_CTRL_SS_PHY_EN, 0x0);
 428 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 429 +               SSUSB_CTRL_REF_USE_PAD, 0x0);
 430 +       qcom_dwc3_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
 431 +               SSUSB_CTRL_TEST_POWERDOWN, SSUSB_CTRL_TEST_POWERDOWN);
 432 +
 433 +       return 0;
 434 +}
 435 +
 436 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_hs_drvdata = {
 437 +       .ops = {
 438 +               .init           = qcom_dwc3_hs_phy_init,
 439 +               .power_on       = qcom_dwc3_phy_power_on,
 440 +               .power_off      = qcom_dwc3_phy_power_off,
 441 +               .owner          = THIS_MODULE,
 442 +       },
 443 +       .clk_rate = 60000000,
 444 +};
 445 +
 446 +static const struct qcom_dwc3_phy_drvdata qcom_dwc3_ss_drvdata = {
 447 +       .ops = {
 448 +               .init           = qcom_dwc3_ss_phy_init,
 449 +               .exit           = qcom_dwc3_ss_phy_exit,
 450 +               .power_on       = qcom_dwc3_phy_power_on,
 451 +               .power_off      = qcom_dwc3_phy_power_off,
 452 +               .owner          = THIS_MODULE,
 453 +       },
 454 +       .clk_rate = 125000000,
 455 +};
 456 +
 457 +static const struct of_device_id qcom_dwc3_phy_table[] = {
 458 +       { .compatible = "qcom,dwc3-hs-usb-phy", .data = &qcom_dwc3_hs_drvdata },
 459 +       { .compatible = "qcom,dwc3-ss-usb-phy", .data = &qcom_dwc3_ss_drvdata },
 460 +       { /* Sentinel */ }
 461 +};
 462 +MODULE_DEVICE_TABLE(of, qcom_dwc3_phy_table);
 463 +
 464 +static int qcom_dwc3_phy_probe(struct platform_device *pdev)
 465 +{
 466 +       struct qcom_dwc3_usb_phy        *phy_dwc3;
 467 +       struct phy_provider             *phy_provider;
 468 +       struct phy                      *generic_phy;
 469 +       struct resource                 *res;
 470 +       const struct of_device_id *match;
 471 +       const struct qcom_dwc3_phy_drvdata *data;
 472 +
 473 +       phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
 474 +       if (!phy_dwc3)
 475 +               return -ENOMEM;
 476 +
 477 +       match = of_match_node(qcom_dwc3_phy_table, pdev->dev.of_node);
 478 +       data = match->data;
 479 +
 480 +       phy_dwc3->dev = &pdev->dev;
 481 +
 482 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 483 +       phy_dwc3->base = devm_ioremap_resource(phy_dwc3->dev, res);
 484 +       if (IS_ERR(phy_dwc3->base))
 485 +               return PTR_ERR(phy_dwc3->base);
 486 +
 487 +       phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
 488 +       if (IS_ERR(phy_dwc3->ref_clk)) {
 489 +               dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
 490 +               return PTR_ERR(phy_dwc3->ref_clk);
 491 +       }
 492 +
 493 +       clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
 494 +
 495 +       phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
 496 +       if (IS_ERR(phy_dwc3->xo_clk)) {
 497 +               dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
 498 +               phy_dwc3->xo_clk = NULL;
 499 +       }
 500 +
 501 +       generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node,
 502 +                                     &data->ops);
 503 +
 504 +       if (IS_ERR(generic_phy))
 505 +               return PTR_ERR(generic_phy);
 506 +
 507 +       phy_set_drvdata(generic_phy, phy_dwc3);
 508 +       platform_set_drvdata(pdev, phy_dwc3);
 509 +
 510 +       phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,
 511 +                       of_phy_simple_xlate);
 512 +
 513 +       if (IS_ERR(phy_provider))
 514 +               return PTR_ERR(phy_provider);
 515 +
 516 +       return 0;
 517 +}
 518 +
 519 +static struct platform_driver qcom_dwc3_phy_driver = {
 520 +       .probe          = qcom_dwc3_phy_probe,
 521 +       .driver         = {
 522 +               .name   = "qcom-dwc3-usb-phy",
 523 +               .owner  = THIS_MODULE,
 524 +               .of_match_table = qcom_dwc3_phy_table,
 525 +       },
 526 +};
 527 +
 528 +module_platform_driver(qcom_dwc3_phy_driver);
 529 +
 530 +MODULE_ALIAS("platform:phy-qcom-dwc3");
 531 +MODULE_LICENSE("GPL v2");
 532 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
 533 +MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
 534 +MODULE_DESCRIPTION("DesignWare USB3 QCOM PHY driver");