ipq806x: Add support for IPQ806x chip family
[openwrt/staging/wigyori.git] / target / linux / ipq806x / patches / 0159-arm-ipq8064-Add-USB3-DT-information.patch
1 From 269a71c81438604d27f01ec703daa7f5e3f39e8b Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Sun, 15 Jun 2014 00:48:18 -0500
4 Subject: [PATCH 159/182] arm: ipq8064: Add USB3 DT information
5
6 This patch fleshes out the USB3 specific information for the IPQ8064 platform.
7
8 Signed-off-by: Andy Gross <agross@codeaurora.org>
9 ---
10 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 29 ++++++++++
11 arch/arm/boot/dts/qcom-ipq8064.dtsi | 90 ++++++++++++++++++++++++++++++
12 2 files changed, 119 insertions(+)
13
14 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
15 index 4062eb6..2b2d63c 100644
16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 @@ -160,5 +160,34 @@
19 pinctrl-0 = <&nand_pins>;
20 pinctrl-names = "default";
21 };
22 +
23 + tcsr@1a400000 {
24 + status = "ok";
25 + qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
26 + };
27 +
28 + phy@100f8800 { /* USB3 port 1 HS phy */
29 + status = "ok";
30 + };
31 +
32 + phy@100f8830 { /* USB3 port 1 SS phy */
33 + status = "ok";
34 + };
35 +
36 + phy@110f8800 { /* USB3 port 0 HS phy */
37 + status = "ok";
38 + };
39 +
40 + phy@110f8830 { /* USB3 port 0 SS phy */
41 + status = "ok";
42 + };
43 +
44 + usb30@0 {
45 + status = "ok";
46 + };
47 +
48 + usb30@1 {
49 + status = "ok";
50 + };
51 };
52 };
53 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
54 index d9fce15..6be6ac9 100644
55 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
56 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
57 @@ -4,6 +4,7 @@
58 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
59 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
60 #include <dt-bindings/soc/qcom,gsbi.h>
61 +#include <dt-bindings/soc/qcom,tcsr.h>
62
63 / {
64 model = "Qualcomm IPQ8064";
65 @@ -402,5 +403,94 @@
66
67 status = "disabled";
68 };
69 +
70 + tcsr: tcsr@1a400000 {
71 + compatible = "qcom,tcsr";
72 + reg = <0x1a400000 0x100>;
73 +
74 + status = "disabled";
75 + };
76 +
77 + hs_phy_1: phy@100f8800 {
78 + compatible = "qcom,dwc3-hsphy";
79 + reg = <0x100f8800 0x30>;
80 + clocks = <&gcc USB30_1_UTMI_CLK>;
81 + clock-names = "utmi";
82 +
83 + status = "disabled";
84 + };
85 +
86 + ss_phy_1: phy@100f8830 {
87 + compatible = "qcom,dwc3-ssphy";
88 + reg = <0x100f8830 0x30>;
89 +
90 + clocks = <&gcc USB30_1_MASTER_CLK>;
91 + clock-names = "ref";
92 +
93 + status = "disabled";
94 + };
95 +
96 + hs_phy_0: phy@110f8800 {
97 + compatible = "qcom,dwc3-hsphy";
98 + reg = <0x110f8800 0x30>;
99 + clocks = <&gcc USB30_0_UTMI_CLK>;
100 + clock-names = "utmi";
101 +
102 + status = "disabled";
103 + };
104 +
105 + ss_phy_0: phy@110f8830 {
106 + compatible = "qcom,dwc3-ssphy";
107 + reg = <0x110f8830 0x30>;
108 +
109 + clocks = <&gcc USB30_0_MASTER_CLK>;
110 + clock-names = "ref";
111 +
112 + status = "disabled";
113 + };
114 +
115 + usb3_0: usb30@0 {
116 + compatible = "qcom,dwc3";
117 + #address-cells = <1>;
118 + #size-cells = <1>;
119 + clocks = <&gcc USB30_0_MASTER_CLK>;
120 + clock-names = "core";
121 +
122 + ranges;
123 +
124 + status = "disabled";
125 +
126 + dwc3@11000000 {
127 + compatible = "snps,dwc3";
128 + reg = <0x11000000 0xcd00>;
129 + interrupts = <0 110 0x4>;
130 + usb-phy = <&hs_phy_0>, <&ss_phy_0>;
131 + phy-names = "usb2-phy", "usb3-phy";
132 + tx-fifo-resize;
133 + dr_mode = "host";
134 + };
135 + };
136 +
137 + usb3_1: usb30@1 {
138 + compatible = "qcom,dwc3";
139 + #address-cells = <1>;
140 + #size-cells = <1>;
141 + clocks = <&gcc USB30_1_MASTER_CLK>;
142 + clock-names = "core";
143 +
144 + ranges;
145 +
146 + status = "disabled";
147 +
148 + dwc3@10000000 {
149 + compatible = "snps,dwc3";
150 + reg = <0x10000000 0xcd00>;
151 + interrupts = <0 205 0x4>;
152 + usb-phy = <&hs_phy_1>, <&ss_phy_1>;
153 + phy-names = "usb2-phy", "usb3-phy";
154 + tx-fifo-resize;
155 + dr_mode = "host";
156 + };
157 + };
158 };
159 };
160 --
161 1.7.10.4
162