target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch

   1 From 066320dd0643e66bc5afe0d0984e77b2e938a6f4 Mon Sep 17 00:00:00 2001
   2 From: Minghuan Lian <Minghuan.Lian@nxp.com>
   3 Date: Wed, 23 Mar 2016 19:08:19 +0800
   4 Subject: [PATCH 03/13] dt/bindings: Add bindings for Layerscape SCFG MSI
   5
   6 Cherry-pick upstream patch.
   7
   8 Some Layerscape SoCs use a simple MSI controller implementation.
   9 It contains only two SCFG register to trigger and describe a
  10 group 32 MSI interrupts. The patch adds bindings to describe
  11 the controller.
  12
  13 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
  14 Acked-by: Rob Herring <robh@kernel.org>
  15 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  16 ---
  17  .../interrupt-controller/fsl,ls-scfg-msi.txt       | 30 ++++++++++++++++++++++
  18  1 file changed, 30 insertions(+)
  19  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
  20
  21 diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
  22 new file mode 100644
  23 index 0000000..9e38949
  24 --- /dev/null
  25 +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
  26 @@ -0,0 +1,30 @@
  27 +* Freescale Layerscape SCFG PCIe MSI controller
  28 +
  29 +Required properties:
  30 +
  31 +- compatible: should be "fsl,<soc-name>-msi" to identify
  32 +             Layerscape PCIe MSI controller block such as:
  33 +              "fsl,1s1021a-msi"
  34 +              "fsl,1s1043a-msi"
  35 +- msi-controller: indicates that this is a PCIe MSI controller node
  36 +- reg: physical base address of the controller and length of memory mapped.
  37 +- interrupts: an interrupt to the parent interrupt controller.
  38 +
  39 +Optional properties:
  40 +- interrupt-parent: the phandle to the parent interrupt controller.
  41 +
  42 +This interrupt controller hardware is a second level interrupt controller that
  43 +is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
  44 +platforms. If interrupt-parent is not provided, the default parent interrupt
  45 +controller will be used.
  46 +Each PCIe node needs to have property msi-parent that points to
  47 +MSI controller node
  48 +
  49 +Examples:
  50 +
  51 +       msi1: msi-controller@1571000 {
  52 +               compatible = "fsl,1s1043a-msi";
  53 +               reg = <0x0 0x1571000 0x0 0x8>,
  54 +               msi-controller;
  55 +               interrupts = <0 116 0x4>;
  56 +       };
  57 --
  58 2.1.0.27.g96db324
  59