projects / openwrt / staging / wigyori.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
layerscape: add linux 4.9 support
[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-4.9 / 302-dts-support-layercape.patch
1 From 2b2e3b9a0d2abf276b40843f75d97b623e4ee109 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:02:10 +0800
4 Subject: [PATCH] dts: support layercape
5
6 This is a integrated patch for layerscape dts support.
7
8 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
9 Signed-off-by: Alison Wang <b18965@freescale.com>
10 Signed-off-by: Li Yang <leoyang.li@nxp.com>
11 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
12 Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
13 Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
14 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
15 Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
16 Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
17 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
18 Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
19 Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
20 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
21 Signed-off-by: Changming Huang <jerry.huang@nxp.com>
22 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
23 Signed-off-by: Meng Yi <meng.yi@nxp.com>
24 Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
25 Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
26 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
27 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
28 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
29 ---
30 arch/arm/boot/dts/alpine.dtsi | 2 +-
31 arch/arm/boot/dts/axm55xx.dtsi | 2 +-
32 arch/arm/boot/dts/ecx-2000.dts | 2 +-
33 arch/arm/boot/dts/imx6ul.dtsi | 4 +-
34 arch/arm/boot/dts/keystone.dtsi | 4 +-
35 arch/arm/boot/dts/ls1021a-qds.dts | 13 +
36 arch/arm/boot/dts/ls1021a-twr.dts | 13 +
37 arch/arm/boot/dts/ls1021a.dtsi | 155 ++--
38 arch/arm/boot/dts/mt6580.dtsi | 2 +-
39 arch/arm/boot/dts/mt6589.dtsi | 2 +-
40 arch/arm/boot/dts/mt8127.dtsi | 2 +-
41 arch/arm/boot/dts/mt8135.dtsi | 2 +-
42 arch/arm/boot/dts/rk3288.dtsi | 2 +-
43 arch/arm/boot/dts/sun6i-a31.dtsi | 2 +-
44 arch/arm/boot/dts/sun7i-a20.dtsi | 4 +-
45 arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
46 arch/arm/boot/dts/sun9i-a80.dtsi | 2 +-
47 arch/arm64/boot/dts/freescale/Makefile | 16 +
48 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 134 +++
49 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 155 ++++
50 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 91 +++
51 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 517 ++++++++++++
52 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi | 45 +
53 .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts | 69 ++
54 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts | 171 +++-
55 .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts | 69 ++
56 .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++
57 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts | 113 ++-
58 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 302 ++++++-
59 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi | 48 ++
60 .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts | 109 +++
61 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 363 ++++++++
62 .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts | 76 ++
63 .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++
64 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 218 +++++
65 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 793 ++++++++++++++++++
66 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts | 173 ++++
67 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 236 ++++++
68 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 816 ++++++++++++++++++
69 arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 191 ++---
70 arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts | 169 ++--
71 arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts | 9 +-
72 arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 763 +++--------------
73 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++
74 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 162 ++++
75 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 140 ++++
76 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 195 +++++
77 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
78 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
79 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 910 +++++++++++++++++++++
80 .../boot/dts/freescale/qoriq-bman1-portals.dtsi | 81 ++
81 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi | 66 ++
82 .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 +
83 .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 +
84 .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 +
85 .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 +
86 .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 +
87 .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 +
88 .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 +
89 .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 +
90 .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 ++
91 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++
92 .../boot/dts/freescale/qoriq-qman1-portals.dtsi | 104 +++
93 arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 +
94 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +-
95 arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +-
96 66 files changed, 7778 insertions(+), 1021 deletions(-)
97 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
98 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
99 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
100 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
101 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
102 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
103 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
104 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
105 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
106 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
107 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
108 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
109 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
110 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
111 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
112 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
113 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
114 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
115 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
116 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
117 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
118 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
119 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
120 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
121 create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
122 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
123 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
124 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
125 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
126 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
127 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
128 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
129 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
130 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
131 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
132 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
133 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
134 create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
135
136 diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
137 index db8752fc..d0eefc3b 100644
138 --- a/arch/arm/boot/dts/alpine.dtsi
139 +++ b/arch/arm/boot/dts/alpine.dtsi
140 @@ -93,7 +93,7 @@
141 interrupt-controller;
142 reg = <0x0 0xfb001000 0x0 0x1000>,
143 <0x0 0xfb002000 0x0 0x2000>,
144 - <0x0 0xfb004000 0x0 0x1000>,
145 + <0x0 0xfb004000 0x0 0x2000>,
146 <0x0 0xfb006000 0x0 0x2000>;
147 interrupts =
148 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149 diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
150 index a9d6d593..47799f59 100644
151 --- a/arch/arm/boot/dts/axm55xx.dtsi
152 +++ b/arch/arm/boot/dts/axm55xx.dtsi
153 @@ -62,7 +62,7 @@
154 #address-cells = <0>;
155 interrupt-controller;
156 reg = <0x20 0x01001000 0 0x1000>,
157 - <0x20 0x01002000 0 0x1000>,
158 + <0x20 0x01002000 0 0x2000>,
159 <0x20 0x01004000 0 0x2000>,
160 <0x20 0x01006000 0 0x2000>;
161 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
162 diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
163 index 2ccbb57f..c15e7e0c 100644
164 --- a/arch/arm/boot/dts/ecx-2000.dts
165 +++ b/arch/arm/boot/dts/ecx-2000.dts
166 @@ -99,7 +99,7 @@
167 interrupt-controller;
168 interrupts = <1 9 0xf04>;
169 reg = <0xfff11000 0x1000>,
170 - <0xfff12000 0x1000>,
171 + <0xfff12000 0x2000>,
172 <0xfff14000 0x2000>,
173 <0xfff16000 0x2000>;
174 };
175 diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
176 index c5c05fdc..c1396873 100644
177 --- a/arch/arm/boot/dts/imx6ul.dtsi
178 +++ b/arch/arm/boot/dts/imx6ul.dtsi
179 @@ -89,11 +89,11 @@
180 };
181
182 intc: interrupt-controller@00a01000 {
183 - compatible = "arm,cortex-a7-gic";
184 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
185 #interrupt-cells = <3>;
186 interrupt-controller;
187 reg = <0x00a01000 0x1000>,
188 - <0x00a02000 0x1000>,
189 + <0x00a02000 0x2000>,
190 <0x00a04000 0x2000>,
191 <0x00a06000 0x2000>;
192 };
193 diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
194 index 02708ba2..e30c83fc 100644
195 --- a/arch/arm/boot/dts/keystone.dtsi
196 +++ b/arch/arm/boot/dts/keystone.dtsi
197 @@ -30,12 +30,12 @@
198 };
199
200 gic: interrupt-controller {
201 - compatible = "arm,cortex-a15-gic";
202 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
203 #interrupt-cells = <3>;
204 interrupt-controller;
205 reg = <0x0 0x02561000 0x0 0x1000>,
206 <0x0 0x02562000 0x0 0x2000>,
207 - <0x0 0x02564000 0x0 0x1000>,
208 + <0x0 0x02564000 0x0 0x2000>,
209 <0x0 0x02566000 0x0 0x2000>;
210 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
211 IRQ_TYPE_LEVEL_HIGH)>;
212 diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
213 index 94087531..5611a9c9 100644
214 --- a/arch/arm/boot/dts/ls1021a-qds.dts
215 +++ b/arch/arm/boot/dts/ls1021a-qds.dts
216 @@ -124,6 +124,19 @@
217 };
218 };
219
220 +&qspi {
221 + num-cs = <2>;
222 + status = "okay";
223 +
224 + qflash0: s25fl128s@0 {
225 + compatible = "spansion,m25p80";
226 + #address-cells = <1>;
227 + #size-cells = <1>;
228 + spi-max-frequency = <20000000>;
229 + reg = <0>;
230 + };
231 +};
232 +
233 &enet0 {
234 tbi-handle = <&tbi0>;
235 phy-handle = <&sgmii_phy1c>;
236 diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
237 index a8b148ad..907e5392 100644
238 --- a/arch/arm/boot/dts/ls1021a-twr.dts
239 +++ b/arch/arm/boot/dts/ls1021a-twr.dts
240 @@ -142,6 +142,19 @@
241 };
242 };
243
244 +&qspi {
245 + num-cs = <2>;
246 + status = "okay";
247 +
248 + qflash0: n25q128a13@0 {
249 + compatible = "n25q128a13", "jedec,spi-nor";
250 + #address-cells = <1>;
251 + #size-cells = <1>;
252 + spi-max-frequency = <20000000>;
253 + reg = <0>;
254 + };
255 +};
256 +
257 &enet0 {
258 tbi-handle = <&tbi1>;
259 phy-handle = <&sgmii_phy2>;
260 diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
261 index 368e2193..def82fef 100644
262 --- a/arch/arm/boot/dts/ls1021a.dtsi
263 +++ b/arch/arm/boot/dts/ls1021a.dtsi
264 @@ -74,17 +74,24 @@
265 compatible = "arm,cortex-a7";
266 device_type = "cpu";
267 reg = <0xf00>;
268 - clocks = <&cluster1_clk>;
269 + clocks = <&clockgen 1 0>;
270 };
271
272 cpu@f01 {
273 compatible = "arm,cortex-a7";
274 device_type = "cpu";
275 reg = <0xf01>;
276 - clocks = <&cluster1_clk>;
277 + clocks = <&clockgen 1 0>;
278 };
279 };
280
281 + sysclk: sysclk {
282 + compatible = "fixed-clock";
283 + #clock-cells = <0>;
284 + clock-frequency = <100000000>;
285 + clock-output-names = "sysclk";
286 + };
287 +
288 timer {
289 compatible = "arm,armv7-timer";
290 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
291 @@ -108,11 +115,11 @@
292 ranges;
293
294 gic: interrupt-controller@1400000 {
295 - compatible = "arm,cortex-a7-gic";
296 + compatible = "arm,gic-400", "arm,cortex-a7-gic";
297 #interrupt-cells = <3>;
298 interrupt-controller;
299 reg = <0x0 0x1401000 0x0 0x1000>,
300 - <0x0 0x1402000 0x0 0x1000>,
301 + <0x0 0x1402000 0x0 0x2000>,
302 <0x0 0x1404000 0x0 0x2000>,
303 <0x0 0x1406000 0x0 0x2000>;
304 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
305 @@ -120,14 +127,14 @@
306 };
307
308 msi1: msi-controller@1570e00 {
309 - compatible = "fsl,1s1021a-msi";
310 + compatible = "fsl,ls1021a-msi";
311 reg = <0x0 0x1570e00 0x0 0x8>;
312 msi-controller;
313 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
314 };
315
316 msi2: msi-controller@1570e08 {
317 - compatible = "fsl,1s1021a-msi";
318 + compatible = "fsl,ls1021a-msi";
319 reg = <0x0 0x1570e08 0x0 0x8>;
320 msi-controller;
321 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
322 @@ -137,11 +144,12 @@
323 compatible = "fsl,ifc", "simple-bus";
324 reg = <0x0 0x1530000 0x0 0x10000>;
325 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
326 + big-endian;
327 };
328
329 dcfg: dcfg@1ee0000 {
330 compatible = "fsl,ls1021a-dcfg", "syscon";
331 - reg = <0x0 0x1ee0000 0x0 0x10000>;
332 + reg = <0x0 0x1ee0000 0x0 0x1000>;
333 big-endian;
334 };
335
336 @@ -163,7 +171,7 @@
337 <0x0 0x20220520 0x0 0x4>;
338 reg-names = "ahci", "sata-ecc";
339 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
340 - clocks = <&platform_clk 1>;
341 + clocks = <&clockgen 4 1>;
342 dma-coherent;
343 status = "disabled";
344 };
345 @@ -214,41 +222,10 @@
346 };
347
348 clockgen: clocking@1ee1000 {
349 - #address-cells = <1>;
350 - #size-cells = <1>;
351 - ranges = <0x0 0x0 0x1ee1000 0x10000>;
352 -
353 - sysclk: sysclk {
354 - compatible = "fixed-clock";
355 - #clock-cells = <0>;
356 - clock-output-names = "sysclk";
357 - };
358 -
359 - cga_pll1: pll@800 {
360 - compatible = "fsl,qoriq-core-pll-2.0";
361 - #clock-cells = <1>;
362 - reg = <0x800 0x10>;
363 - clocks = <&sysclk>;
364 - clock-output-names = "cga-pll1", "cga-pll1-div2",
365 - "cga-pll1-div4";
366 - };
367 -
368 - platform_clk: pll@c00 {
369 - compatible = "fsl,qoriq-core-pll-2.0";
370 - #clock-cells = <1>;
371 - reg = <0xc00 0x10>;
372 - clocks = <&sysclk>;
373 - clock-output-names = "platform-clk", "platform-clk-div2";
374 - };
375 -
376 - cluster1_clk: clk0c0@0 {
377 - compatible = "fsl,qoriq-core-mux-2.0";
378 - #clock-cells = <0>;
379 - reg = <0x0 0x10>;
380 - clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
381 - clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
382 - clock-output-names = "cluster1-clk";
383 - };
384 + compatible = "fsl,ls1021a-clockgen";
385 + reg = <0x0 0x1ee1000 0x0 0x1000>;
386 + #clock-cells = <2>;
387 + clocks = <&sysclk>;
388 };
389
390 dspi0: dspi@2100000 {
391 @@ -258,7 +235,7 @@
392 reg = <0x0 0x2100000 0x0 0x10000>;
393 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
394 clock-names = "dspi";
395 - clocks = <&platform_clk 1>;
396 + clocks = <&clockgen 4 1>;
397 spi-num-chipselects = <6>;
398 big-endian;
399 status = "disabled";
400 @@ -271,12 +248,27 @@
401 reg = <0x0 0x2110000 0x0 0x10000>;
402 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
403 clock-names = "dspi";
404 - clocks = <&platform_clk 1>;
405 + clocks = <&clockgen 4 1>;
406 spi-num-chipselects = <6>;
407 big-endian;
408 status = "disabled";
409 };
410
411 + qspi: quadspi@1550000 {
412 + compatible = "fsl,ls1021a-qspi";
413 + #address-cells = <1>;
414 + #size-cells = <0>;
415 + reg = <0x0 0x1550000 0x0 0x10000>,
416 + <0x0 0x40000000 0x0 0x4000000>;
417 + reg-names = "QuadSPI", "QuadSPI-memory";
418 + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
419 + clock-names = "qspi_en", "qspi";
420 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
421 + big-endian;
422 + amba-base = <0x40000000>;
423 + status = "disabled";
424 + };
425 +
426 i2c0: i2c@2180000 {
427 compatible = "fsl,vf610-i2c";
428 #address-cells = <1>;
429 @@ -284,7 +276,7 @@
430 reg = <0x0 0x2180000 0x0 0x10000>;
431 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
432 clock-names = "i2c";
433 - clocks = <&platform_clk 1>;
434 + clocks = <&clockgen 4 1>;
435 status = "disabled";
436 };
437
438 @@ -295,7 +287,7 @@
439 reg = <0x0 0x2190000 0x0 0x10000>;
440 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
441 clock-names = "i2c";
442 - clocks = <&platform_clk 1>;
443 + clocks = <&clockgen 4 1>;
444 status = "disabled";
445 };
446
447 @@ -306,7 +298,7 @@
448 reg = <0x0 0x21a0000 0x0 0x10000>;
449 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
450 clock-names = "i2c";
451 - clocks = <&platform_clk 1>;
452 + clocks = <&clockgen 4 1>;
453 status = "disabled";
454 };
455
456 @@ -399,7 +391,7 @@
457 compatible = "fsl,ls1021a-lpuart";
458 reg = <0x0 0x2960000 0x0 0x1000>;
459 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
460 - clocks = <&platform_clk 1>;
461 + clocks = <&clockgen 4 1>;
462 clock-names = "ipg";
463 status = "disabled";
464 };
465 @@ -408,7 +400,7 @@
466 compatible = "fsl,ls1021a-lpuart";
467 reg = <0x0 0x2970000 0x0 0x1000>;
468 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
469 - clocks = <&platform_clk 1>;
470 + clocks = <&clockgen 4 1>;
471 clock-names = "ipg";
472 status = "disabled";
473 };
474 @@ -417,7 +409,7 @@
475 compatible = "fsl,ls1021a-lpuart";
476 reg = <0x0 0x2980000 0x0 0x1000>;
477 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
478 - clocks = <&platform_clk 1>;
479 + clocks = <&clockgen 4 1>;
480 clock-names = "ipg";
481 status = "disabled";
482 };
483 @@ -426,7 +418,7 @@
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2990000 0x0 0x1000>;
486 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
487 - clocks = <&platform_clk 1>;
488 + clocks = <&clockgen 4 1>;
489 clock-names = "ipg";
490 status = "disabled";
491 };
492 @@ -435,16 +427,26 @@
493 compatible = "fsl,ls1021a-lpuart";
494 reg = <0x0 0x29a0000 0x0 0x1000>;
495 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
496 - clocks = <&platform_clk 1>;
497 + clocks = <&clockgen 4 1>;
498 clock-names = "ipg";
499 status = "disabled";
500 };
501
502 + ftm0: ftm0@29d0000 {
503 + compatible = "fsl,ftm-alarm";
504 + reg = <0x0 0x29d0000 0x0 0x10000>,
505 + <0x0 0x1ee2140 0x0 0x4>;
506 + reg-names = "ftm", "FlexTimer1";
507 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
508 + big-endian;
509 + status = "okay";
510 + };
511 +
512 wdog0: watchdog@2ad0000 {
513 compatible = "fsl,imx21-wdt";
514 reg = <0x0 0x2ad0000 0x0 0x10000>;
515 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
516 - clocks = <&platform_clk 1>;
517 + clocks = <&clockgen 4 1>;
518 clock-names = "wdog-en";
519 big-endian;
520 };
521 @@ -454,8 +456,8 @@
522 compatible = "fsl,vf610-sai";
523 reg = <0x0 0x2b50000 0x0 0x10000>;
524 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
525 - clocks = <&platform_clk 1>, <&platform_clk 1>,
526 - <&platform_clk 1>, <&platform_clk 1>;
527 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
528 + <&clockgen 4 1>, <&clockgen 4 1>;
529 clock-names = "bus", "mclk1", "mclk2", "mclk3";
530 dma-names = "tx", "rx";
531 dmas = <&edma0 1 47>,
532 @@ -468,8 +470,8 @@
533 compatible = "fsl,vf610-sai";
534 reg = <0x0 0x2b60000 0x0 0x10000>;
535 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
536 - clocks = <&platform_clk 1>, <&platform_clk 1>,
537 - <&platform_clk 1>, <&platform_clk 1>;
538 + clocks = <&clockgen 4 1>, <&clockgen 4 1>,
539 + <&clockgen 4 1>, <&clockgen 4 1>;
540 clock-names = "bus", "mclk1", "mclk2", "mclk3";
541 dma-names = "tx", "rx";
542 dmas = <&edma0 1 45>,
543 @@ -489,16 +491,31 @@
544 dma-channels = <32>;
545 big-endian;
546 clock-names = "dmamux0", "dmamux1";
547 - clocks = <&platform_clk 1>,
548 - <&platform_clk 1>;
549 + clocks = <&clockgen 4 1>,
550 + <&clockgen 4 1>;
551 + };
552 +
553 + qdma: qdma@8390000 {
554 + compatible = "fsl,ls1021a-qdma";
555 + reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
556 + <0x0 0x8389000 0x0 0x1000>, /* Status regs */
557 + <0x0 0x838a000 0x0 0x2000>; /* Block regs */
558 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
559 + <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
560 + interrupt-names = "qdma-error", "qdma-queue";
561 + channels = <8>;
562 + queues = <2>;
563 + status-sizes = <64>;
564 + queue-sizes = <64 64>;
565 + big-endian;
566 };
567
568 dcu: dcu@2ce0000 {
569 compatible = "fsl,ls1021a-dcu";
570 reg = <0x0 0x2ce0000 0x0 0x10000>;
571 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
572 - clocks = <&platform_clk 0>,
573 - <&platform_clk 0>;
574 + clocks = <&clockgen 4 0>,
575 + <&clockgen 4 0>;
576 clock-names = "dcu", "pix";
577 big-endian;
578 status = "disabled";
579 @@ -626,6 +643,8 @@
580 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
581 dr_mode = "host";
582 snps,quirk-frame-length-adjustment = <0x20>;
583 + configure-gfladj;
584 + dma-coherent;
585 snps,dis_rxdet_inp3_quirk;
586 };
587
588 @@ -634,7 +653,9 @@
589 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
590 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
591 reg-names = "regs", "config";
592 - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
593 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
594 + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
595 + interrupt-names = "pme", "aer";
596 fsl,pcie-scfg = <&scfg 0>;
597 #address-cells = <3>;
598 #size-cells = <2>;
599 @@ -643,7 +664,7 @@
600 bus-range = <0x0 0xff>;
601 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
602 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
603 - msi-parent = <&msi1>;
604 + msi-parent = <&msi1>, <&msi2>;
605 #interrupt-cells = <1>;
606 interrupt-map-mask = <0 0 0 7>;
607 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
608 @@ -657,7 +678,9 @@
609 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
610 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
611 reg-names = "regs", "config";
612 - interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
613 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
614 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
615 + interrupt-names = "pme", "aer";
616 fsl,pcie-scfg = <&scfg 1>;
617 #address-cells = <3>;
618 #size-cells = <2>;
619 @@ -666,7 +689,7 @@
620 bus-range = <0x0 0xff>;
621 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
622 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
623 - msi-parent = <&msi2>;
624 + msi-parent = <&msi1>, <&msi2>;
625 #interrupt-cells = <1>;
626 interrupt-map-mask = <0 0 0 7>;
627 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
628 diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
629 index 06fdf6c2..a349dba5 100644
630 --- a/arch/arm/boot/dts/mt6580.dtsi
631 +++ b/arch/arm/boot/dts/mt6580.dtsi
632 @@ -91,7 +91,7 @@
633 #interrupt-cells = <3>;
634 interrupt-parent = <&gic>;
635 reg = <0x10211000 0x1000>,
636 - <0x10212000 0x1000>,
637 + <0x10212000 0x2000>,
638 <0x10214000 0x2000>,
639 <0x10216000 0x2000>;
640 };
641 diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
642 index 88b3cb12..0d6f60af 100644
643 --- a/arch/arm/boot/dts/mt6589.dtsi
644 +++ b/arch/arm/boot/dts/mt6589.dtsi
645 @@ -102,7 +102,7 @@
646 #interrupt-cells = <3>;
647 interrupt-parent = <&gic>;
648 reg = <0x10211000 0x1000>,
649 - <0x10212000 0x1000>,
650 + <0x10212000 0x2000>,
651 <0x10214000 0x2000>,
652 <0x10216000 0x2000>;
653 };
654 diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
655 index 52086c80..916c095d 100644
656 --- a/arch/arm/boot/dts/mt8127.dtsi
657 +++ b/arch/arm/boot/dts/mt8127.dtsi
658 @@ -129,7 +129,7 @@
659 #interrupt-cells = <3>;
660 interrupt-parent = <&gic>;
661 reg = <0 0x10211000 0 0x1000>,
662 - <0 0x10212000 0 0x1000>,
663 + <0 0x10212000 0 0x2000>,
664 <0 0x10214000 0 0x2000>,
665 <0 0x10216000 0 0x2000>;
666 };
667 diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
668 index 1d7f92bd..a97b4ee4 100644
669 --- a/arch/arm/boot/dts/mt8135.dtsi
670 +++ b/arch/arm/boot/dts/mt8135.dtsi
671 @@ -221,7 +221,7 @@
672 #interrupt-cells = <3>;
673 interrupt-parent = <&gic>;
674 reg = <0 0x10211000 0 0x1000>,
675 - <0 0x10212000 0 0x1000>,
676 + <0 0x10212000 0 0x2000>,
677 <0 0x10214000 0 0x2000>,
678 <0 0x10216000 0 0x2000>;
679 };
680 diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
681 index 17ec2e2d..559fc549 100644
682 --- a/arch/arm/boot/dts/rk3288.dtsi
683 +++ b/arch/arm/boot/dts/rk3288.dtsi
684 @@ -1109,7 +1109,7 @@
685 #address-cells = <0>;
686
687 reg = <0xffc01000 0x1000>,
688 - <0xffc02000 0x1000>,
689 + <0xffc02000 0x2000>,
690 <0xffc04000 0x2000>,
691 <0xffc06000 0x2000>;
692 interrupts = <GIC_PPI 9 0xf04>;
693 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
694 index ce196045..97f28399 100644
695 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
696 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
697 @@ -791,7 +791,7 @@
698 gic: interrupt-controller@01c81000 {
699 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
700 reg = <0x01c81000 0x1000>,
701 - <0x01c82000 0x1000>,
702 + <0x01c82000 0x2000>,
703 <0x01c84000 0x2000>,
704 <0x01c86000 0x2000>;
705 interrupt-controller;
706 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
707 index 94cf5a1c..81e5a44c 100644
708 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
709 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
710 @@ -1685,9 +1685,9 @@
711 };
712
713 gic: interrupt-controller@01c81000 {
714 - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
715 + compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
716 reg = <0x01c81000 0x1000>,
717 - <0x01c82000 0x1000>,
718 + <0x01c82000 0x2000>,
719 <0x01c84000 0x2000>,
720 <0x01c86000 0x2000>;
721 interrupt-controller;
722 diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
723 index 300a1bd5..cdff5888 100644
724 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
725 +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
726 @@ -488,7 +488,7 @@
727 gic: interrupt-controller@01c81000 {
728 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
729 reg = <0x01c81000 0x1000>,
730 - <0x01c82000 0x1000>,
731 + <0x01c82000 0x2000>,
732 <0x01c84000 0x2000>,
733 <0x01c86000 0x2000>;
734 interrupt-controller;
735 diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
736 index 3c5214cb..ba7e7c71 100644
737 --- a/arch/arm/boot/dts/sun9i-a80.dtsi
738 +++ b/arch/arm/boot/dts/sun9i-a80.dtsi
739 @@ -613,7 +613,7 @@
740 gic: interrupt-controller@01c41000 {
741 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
742 reg = <0x01c41000 0x1000>,
743 - <0x01c42000 0x1000>,
744 + <0x01c42000 0x2000>,
745 <0x01c44000 0x2000>,
746 <0x01c46000 0x2000>;
747 interrupt-controller;
748 diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
749 index 1b7783db..2d7986a1 100644
750 --- a/arch/arm64/boot/dts/freescale/Makefile
751 +++ b/arch/arm64/boot/dts/freescale/Makefile
752 @@ -1,8 +1,24 @@
753 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
754 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
755 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
756 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
757 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
758 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
759 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
760 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
761 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
762 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
763 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
764 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
765 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
766 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
767 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
768 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
769 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
770 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
771 dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
772 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
773 +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
774
775 always := $(dtb-y)
776 subdir-y := $(dts-dirs)
777 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
778 new file mode 100644
779 index 00000000..e1274c18
780 --- /dev/null
781 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
782 @@ -0,0 +1,134 @@
783 +/*
784 + * Device Tree file for Freescale LS1012A Freedom Board.
785 + *
786 + * Copyright 2016 Freescale Semiconductor, Inc.
787 + *
788 + * This file is dual-licensed: you can use it either under the terms
789 + * of the GPLv2 or the X11 license, at your option. Note that this dual
790 + * licensing only applies to this file, and not this project as a
791 + * whole.
792 + *
793 + * a) This library is free software; you can redistribute it and/or
794 + * modify it under the terms of the GNU General Public License as
795 + * published by the Free Software Foundation; either version 2 of the
796 + * License, or (at your option) any later version.
797 + *
798 + * This library is distributed in the hope that it will be useful,
799 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
800 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
801 + * GNU General Public License for more details.
802 + *
803 + * Or, alternatively,
804 + *
805 + * b) Permission is hereby granted, free of charge, to any person
806 + * obtaining a copy of this software and associated documentation
807 + * files (the "Software"), to deal in the Software without
808 + * restriction, including without limitation the rights to use,
809 + * copy, modify, merge, publish, distribute, sublicense, and/or
810 + * sell copies of the Software, and to permit persons to whom the
811 + * Software is furnished to do so, subject to the following
812 + * conditions:
813 + *
814 + * The above copyright notice and this permission notice shall be
815 + * included in all copies or substantial portions of the Software.
816 + *
817 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
818 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
819 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
820 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
821 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
822 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
823 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
824 + * OTHER DEALINGS IN THE SOFTWARE.
825 + */
826 +/dts-v1/;
827 +
828 +#include "fsl-ls1012a.dtsi"
829 +
830 +/ {
831 + model = "LS1012A Freedom Board";
832 + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
833 +
834 + sys_mclk: clock-mclk {
835 + compatible = "fixed-clock";
836 + #clock-cells = <0>;
837 + clock-frequency = <25000000>;
838 + };
839 +
840 + reg_1p8v: regulator-1p8v {
841 + compatible = "regulator-fixed";
842 + regulator-name = "1P8V";
843 + regulator-min-microvolt = <1800000>;
844 + regulator-max-microvolt = <1800000>;
845 + regulator-always-on;
846 + };
847 +
848 + sound {
849 + compatible = "simple-audio-card";
850 + simple-audio-card,format = "i2s";
851 + simple-audio-card,widgets =
852 + "Microphone", "Microphone Jack",
853 + "Headphone", "Headphone Jack",
854 + "Speaker", "Speaker Ext",
855 + "Line", "Line In Jack";
856 + simple-audio-card,routing =
857 + "MIC_IN", "Microphone Jack",
858 + "Microphone Jack", "Mic Bias",
859 + "LINE_IN", "Line In Jack",
860 + "Headphone Jack", "HP_OUT",
861 + "Speaker Ext", "LINE_OUT";
862 +
863 + simple-audio-card,cpu {
864 + sound-dai = <&sai2>;
865 + frame-master;
866 + bitclock-master;
867 + };
868 +
869 + simple-audio-card,codec {
870 + sound-dai = <&codec>;
871 + frame-master;
872 + bitclock-master;
873 + system-clock-frequency = <25000000>;
874 + };
875 + };
876 +};
877 +
878 +&duart0 {
879 + status = "okay";
880 +};
881 +
882 +&i2c0 {
883 + status = "okay";
884 +
885 + codec: sgtl5000@a {
886 + #sound-dai-cells = <0>;
887 + compatible = "fsl,sgtl5000";
888 + reg = <0xa>;
889 + VDDA-supply = <&reg_1p8v>;
890 + VDDIO-supply = <&reg_1p8v>;
891 + clocks = <&sys_mclk>;
892 + };
893 +};
894 +
895 +&qspi {
896 + num-cs = <1>;
897 + bus-num = <0>;
898 + status = "okay";
899 +
900 + qflash0: s25fs512s@0 {
901 + compatible = "spansion,m25p80";
902 + #address-cells = <1>;
903 + #size-cells = <1>;
904 + m25p,fast-read;
905 + spi-max-frequency = <20000000>;
906 + reg = <0>;
907 + };
908 +};
909 +
910 +&sai2 {
911 + status = "okay";
912 +};
913 +
914 +&sata {
915 + status = "okay";
916 +};
917 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
918 new file mode 100644
919 index 00000000..1e1b2802
920 --- /dev/null
921 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
922 @@ -0,0 +1,155 @@
923 +/*
924 + * Device Tree file for Freescale LS1012A QDS Board.
925 + *
926 + * Copyright 2016 Freescale Semiconductor, Inc.
927 + *
928 + * This file is dual-licensed: you can use it either under the terms
929 + * of the GPLv2 or the X11 license, at your option. Note that this dual
930 + * licensing only applies to this file, and not this project as a
931 + * whole.
932 + *
933 + * a) This library is free software; you can redistribute it and/or
934 + * modify it under the terms of the GNU General Public License as
935 + * published by the Free Software Foundation; either version 2 of the
936 + * License, or (at your option) any later version.
937 + *
938 + * This library is distributed in the hope that it will be useful,
939 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
940 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
941 + * GNU General Public License for more details.
942 + *
943 + * Or, alternatively,
944 + *
945 + * b) Permission is hereby granted, free of charge, to any person
946 + * obtaining a copy of this software and associated documentation
947 + * files (the "Software"), to deal in the Software without
948 + * restriction, including without limitation the rights to use,
949 + * copy, modify, merge, publish, distribute, sublicense, and/or
950 + * sell copies of the Software, and to permit persons to whom the
951 + * Software is furnished to do so, subject to the following
952 + * conditions:
953 + *
954 + * The above copyright notice and this permission notice shall be
955 + * included in all copies or substantial portions of the Software.
956 + *
957 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
958 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
959 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
960 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
961 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
962 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
963 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
964 + * OTHER DEALINGS IN THE SOFTWARE.
965 + */
966 +/dts-v1/;
967 +
968 +#include "fsl-ls1012a.dtsi"
969 +
970 +/ {
971 + model = "LS1012A QDS Board";
972 + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
973 +
974 + sys_mclk: clock-mclk {
975 + compatible = "fixed-clock";
976 + #clock-cells = <0>;
977 + clock-frequency = <24576000>;
978 + };
979 +
980 + reg_3p3v: regulator-3p3v {
981 + compatible = "regulator-fixed";
982 + regulator-name = "3P3V";
983 + regulator-min-microvolt = <3300000>;
984 + regulator-max-microvolt = <3300000>;
985 + regulator-always-on;
986 + };
987 +
988 + sound {
989 + compatible = "simple-audio-card";
990 + simple-audio-card,format = "i2s";
991 + simple-audio-card,widgets =
992 + "Microphone", "Microphone Jack",
993 + "Headphone", "Headphone Jack",
994 + "Speaker", "Speaker Ext",
995 + "Line", "Line In Jack";
996 + simple-audio-card,routing =
997 + "MIC_IN", "Microphone Jack",
998 + "Microphone Jack", "Mic Bias",
999 + "LINE_IN", "Line In Jack",
1000 + "Headphone Jack", "HP_OUT",
1001 + "Speaker Ext", "LINE_OUT";
1002 +
1003 + simple-audio-card,cpu {
1004 + sound-dai = <&sai2>;
1005 + frame-master;
1006 + bitclock-master;
1007 + };
1008 +
1009 + simple-audio-card,codec {
1010 + sound-dai = <&codec>;
1011 + frame-master;
1012 + bitclock-master;
1013 + system-clock-frequency = <24576000>;
1014 + };
1015 + };
1016 +};
1017 +
1018 +&duart0 {
1019 + status = "okay";
1020 +};
1021 +
1022 +&i2c0 {
1023 + status = "okay";
1024 +
1025 + pca9547@77 {
1026 + compatible = "nxp,pca9547";
1027 + reg = <0x77>;
1028 + #address-cells = <1>;
1029 + #size-cells = <0>;
1030 +
1031 + i2c@4 {
1032 + #address-cells = <1>;
1033 + #size-cells = <0>;
1034 + reg = <0x4>;
1035 +
1036 + codec: sgtl5000@a {
1037 + #sound-dai-cells = <0>;
1038 + compatible = "fsl,sgtl5000";
1039 + reg = <0xa>;
1040 + VDDA-supply = <&reg_3p3v>;
1041 + VDDIO-supply = <&reg_3p3v>;
1042 + clocks = <&sys_mclk>;
1043 + };
1044 + };
1045 + };
1046 +};
1047 +
1048 +&qspi {
1049 + num-cs = <2>;
1050 + bus-num = <0>;
1051 + status = "okay";
1052 +
1053 + qflash0: s25fs512s@0 {
1054 + compatible = "spansion,m25p80";
1055 + #address-cells = <1>;
1056 + #size-cells = <1>;
1057 + spi-max-frequency = <20000000>;
1058 + m25p,fast-read;
1059 + reg = <0>;
1060 + };
1061 +};
1062 +
1063 +&sai2 {
1064 + status = "okay";
1065 +};
1066 +
1067 +&sata {
1068 + status = "okay";
1069 +};
1070 +
1071 +&esdhc0 {
1072 + status = "okay";
1073 +};
1074 +
1075 +&esdhc1 {
1076 + status = "okay";
1077 +};
1078 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1079 new file mode 100644
1080 index 00000000..90bd2307
1081 --- /dev/null
1082 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
1083 @@ -0,0 +1,91 @@
1084 +/*
1085 + * Device Tree file for Freescale LS1012A RDB Board.
1086 + *
1087 + * Copyright 2016 Freescale Semiconductor, Inc.
1088 + *
1089 + * This file is dual-licensed: you can use it either under the terms
1090 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1091 + * licensing only applies to this file, and not this project as a
1092 + * whole.
1093 + *
1094 + * a) This library is free software; you can redistribute it and/or
1095 + * modify it under the terms of the GNU General Public License as
1096 + * published by the Free Software Foundation; either version 2 of the
1097 + * License, or (at your option) any later version.
1098 + *
1099 + * This library is distributed in the hope that it will be useful,
1100 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1101 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1102 + * GNU General Public License for more details.
1103 + *
1104 + * Or, alternatively,
1105 + *
1106 + * b) Permission is hereby granted, free of charge, to any person
1107 + * obtaining a copy of this software and associated documentation
1108 + * files (the "Software"), to deal in the Software without
1109 + * restriction, including without limitation the rights to use,
1110 + * copy, modify, merge, publish, distribute, sublicense, and/or
1111 + * sell copies of the Software, and to permit persons to whom the
1112 + * Software is furnished to do so, subject to the following
1113 + * conditions:
1114 + *
1115 + * The above copyright notice and this permission notice shall be
1116 + * included in all copies or substantial portions of the Software.
1117 + *
1118 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1119 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1120 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1121 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1122 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1123 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1124 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1125 + * OTHER DEALINGS IN THE SOFTWARE.
1126 + */
1127 +/dts-v1/;
1128 +
1129 +#include "fsl-ls1012a.dtsi"
1130 +
1131 +/ {
1132 + model = "LS1012A RDB Board";
1133 + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
1134 +};
1135 +
1136 +&duart0 {
1137 + status = "okay";
1138 +};
1139 +
1140 +&i2c0 {
1141 + status = "okay";
1142 +};
1143 +
1144 +&qspi {
1145 + num-cs = <2>;
1146 + bus-num = <0>;
1147 + status = "okay";
1148 +
1149 + qflash0: s25fs512s@0 {
1150 + compatible = "spansion,m25p80";
1151 + #address-cells = <1>;
1152 + #size-cells = <1>;
1153 + spi-max-frequency = <20000000>;
1154 + m25p,fast-read;
1155 + reg = <0>;
1156 + };
1157 +};
1158 +
1159 +&sata {
1160 + status = "okay";
1161 +};
1162 +
1163 +&esdhc0 {
1164 + sd-uhs-sdr104;
1165 + sd-uhs-sdr50;
1166 + sd-uhs-sdr25;
1167 + sd-uhs-sdr12;
1168 + status = "okay";
1169 +};
1170 +
1171 +&esdhc1 {
1172 + mmc-hs200-1_8v;
1173 + status = "okay";
1174 +};
1175 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1176 new file mode 100644
1177 index 00000000..9ede9d52
1178 --- /dev/null
1179 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
1180 @@ -0,0 +1,517 @@
1181 +/*
1182 + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
1183 + *
1184 + * Copyright 2016 Freescale Semiconductor, Inc.
1185 + *
1186 + * This file is dual-licensed: you can use it either under the terms
1187 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1188 + * licensing only applies to this file, and not this project as a
1189 + * whole.
1190 + *
1191 + * a) This library is free software; you can redistribute it and/or
1192 + * modify it under the terms of the GNU General Public License as
1193 + * published by the Free Software Foundation; either version 2 of the
1194 + * License, or (at your option) any later version.
1195 + *
1196 + * This library is distributed in the hope that it will be useful,
1197 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1198 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1199 + * GNU General Public License for more details.
1200 + *
1201 + * Or, alternatively,
1202 + *
1203 + * b) Permission is hereby granted, free of charge, to any person
1204 + * obtaining a copy of this software and associated documentation
1205 + * files (the "Software"), to deal in the Software without
1206 + * restriction, including without limitation the rights to use,
1207 + * copy, modify, merge, publish, distribute, sublicense, and/or
1208 + * sell copies of the Software, and to permit persons to whom the
1209 + * Software is furnished to do so, subject to the following
1210 + * conditions:
1211 + *
1212 + * The above copyright notice and this permission notice shall be
1213 + * included in all copies or substantial portions of the Software.
1214 + *
1215 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1216 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1217 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1218 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1219 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1220 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1221 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1222 + * OTHER DEALINGS IN THE SOFTWARE.
1223 + */
1224 +
1225 +#include <dt-bindings/interrupt-controller/arm-gic.h>
1226 +#include <dt-bindings/thermal/thermal.h>
1227 +
1228 +/ {
1229 + compatible = "fsl,ls1012a";
1230 + interrupt-parent = <&gic>;
1231 + #address-cells = <2>;
1232 + #size-cells = <2>;
1233 +
1234 + aliases {
1235 + crypto = &crypto;
1236 + rtic_a = &rtic_a;
1237 + rtic_b = &rtic_b;
1238 + rtic_c = &rtic_c;
1239 + rtic_d = &rtic_d;
1240 + sec_mon = &sec_mon;
1241 + };
1242 +
1243 + cpus {
1244 + #address-cells = <1>;
1245 + #size-cells = <0>;
1246 +
1247 + cpu0: cpu@0 {
1248 + device_type = "cpu";
1249 + compatible = "arm,cortex-a53";
1250 + reg = <0x0>;
1251 + clocks = <&clockgen 1 0>;
1252 + #cooling-cells = <2>;
1253 + cpu-idle-states = <&CPU_PH20>;
1254 + };
1255 + };
1256 +
1257 + idle-states {
1258 + /*
1259 + * PSCI node is not added default, U-boot will add missing
1260 + * parts if it determines to use PSCI.
1261 + */
1262 + entry-method = "arm,psci";
1263 +
1264 + CPU_PH20: cpu-ph20 {
1265 + compatible = "arm,idle-state";
1266 + idle-state-name = "PH20";
1267 + arm,psci-suspend-param = <0x0>;
1268 + entry-latency-us = <1000>;
1269 + exit-latency-us = <1000>;
1270 + min-residency-us = <3000>;
1271 + };
1272 + };
1273 +
1274 + sysclk: sysclk {
1275 + compatible = "fixed-clock";
1276 + #clock-cells = <0>;
1277 + clock-frequency = <125000000>;
1278 + clock-output-names = "sysclk";
1279 + };
1280 +
1281 + coreclk: coreclk {
1282 + compatible = "fixed-clock";
1283 + #clock-cells = <0>;
1284 + clock-frequency = <100000000>;
1285 + clock-output-names = "coreclk";
1286 + };
1287 +
1288 + timer {
1289 + compatible = "arm,armv8-timer";
1290 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
1291 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
1292 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
1293 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
1294 + };
1295 +
1296 + pmu {
1297 + compatible = "arm,armv8-pmuv3";
1298 + interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1299 + };
1300 +
1301 + gic: interrupt-controller@1400000 {
1302 + compatible = "arm,gic-400";
1303 + #interrupt-cells = <3>;
1304 + interrupt-controller;
1305 + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
1306 + <0x0 0x1402000 0 0x2000>, /* GICC */
1307 + <0x0 0x1404000 0 0x2000>, /* GICH */
1308 + <0x0 0x1406000 0 0x2000>; /* GICV */
1309 + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
1310 + };
1311 +
1312 + reboot {
1313 + compatible = "syscon-reboot";
1314 + regmap = <&dcfg>;
1315 + offset = <0xb0>;
1316 + mask = <0x02>;
1317 + };
1318 +
1319 + soc {
1320 + compatible = "simple-bus";
1321 + #address-cells = <2>;
1322 + #size-cells = <2>;
1323 + ranges;
1324 +
1325 + scfg: scfg@1570000 {
1326 + compatible = "fsl,ls1012a-scfg", "syscon";
1327 + reg = <0x0 0x1570000 0x0 0x10000>;
1328 + big-endian;
1329 + };
1330 +
1331 + crypto: crypto@1700000 {
1332 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
1333 + "fsl,sec-v4.0";
1334 + fsl,sec-era = <8>;
1335 + #address-cells = <1>;
1336 + #size-cells = <1>;
1337 + ranges = <0x0 0x00 0x1700000 0x100000>;
1338 + reg = <0x00 0x1700000 0x0 0x100000>;
1339 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1340 +
1341 + sec_jr0: jr@10000 {
1342 + compatible = "fsl,sec-v5.4-job-ring",
1343 + "fsl,sec-v5.0-job-ring",
1344 + "fsl,sec-v4.0-job-ring";
1345 + reg = <0x10000 0x10000>;
1346 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1347 + };
1348 +
1349 + sec_jr1: jr@20000 {
1350 + compatible = "fsl,sec-v5.4-job-ring",
1351 + "fsl,sec-v5.0-job-ring",
1352 + "fsl,sec-v4.0-job-ring";
1353 + reg = <0x20000 0x10000>;
1354 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1355 + };
1356 +
1357 + sec_jr2: jr@30000 {
1358 + compatible = "fsl,sec-v5.4-job-ring",
1359 + "fsl,sec-v5.0-job-ring",
1360 + "fsl,sec-v4.0-job-ring";
1361 + reg = <0x30000 0x10000>;
1362 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1363 + };
1364 +
1365 + sec_jr3: jr@40000 {
1366 + compatible = "fsl,sec-v5.4-job-ring",
1367 + "fsl,sec-v5.0-job-ring",
1368 + "fsl,sec-v4.0-job-ring";
1369 + reg = <0x40000 0x10000>;
1370 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1371 + };
1372 +
1373 + rtic@60000 {
1374 + compatible = "fsl,sec-v5.4-rtic",
1375 + "fsl,sec-v5.0-rtic",
1376 + "fsl,sec-v4.0-rtic";
1377 + #address-cells = <1>;
1378 + #size-cells = <1>;
1379 + reg = <0x60000 0x100 0x60e00 0x18>;
1380 + ranges = <0x0 0x60100 0x500>;
1381 +
1382 + rtic_a: rtic-a@0 {
1383 + compatible = "fsl,sec-v5.4-rtic-memory",
1384 + "fsl,sec-v5.0-rtic-memory",
1385 + "fsl,sec-v4.0-rtic-memory";
1386 + reg = <0x00 0x20 0x100 0x100>;
1387 + };
1388 +
1389 + rtic_b: rtic-b@20 {
1390 + compatible = "fsl,sec-v5.4-rtic-memory",
1391 + "fsl,sec-v5.0-rtic-memory",
1392 + "fsl,sec-v4.0-rtic-memory";
1393 + reg = <0x20 0x20 0x200 0x100>;
1394 + };
1395 +
1396 + rtic_c: rtic-c@40 {
1397 + compatible = "fsl,sec-v5.4-rtic-memory",
1398 + "fsl,sec-v5.0-rtic-memory",
1399 + "fsl,sec-v4.0-rtic-memory";
1400 + reg = <0x40 0x20 0x300 0x100>;
1401 + };
1402 +
1403 + rtic_d: rtic-d@60 {
1404 + compatible = "fsl,sec-v5.4-rtic-memory",
1405 + "fsl,sec-v5.0-rtic-memory",
1406 + "fsl,sec-v4.0-rtic-memory";
1407 + reg = <0x60 0x20 0x400 0x100>;
1408 + };
1409 + };
1410 + };
1411 +
1412 + sec_mon: sec_mon@1e90000 {
1413 + compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
1414 + "fsl,sec-v4.0-mon";
1415 + reg = <0x0 0x1e90000 0x0 0x10000>;
1416 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
1417 + <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1418 + };
1419 +
1420 + dcfg: dcfg@1ee0000 {
1421 + compatible = "fsl,ls1012a-dcfg",
1422 + "syscon";
1423 + reg = <0x0 0x1ee0000 0x0 0x10000>;
1424 + big-endian;
1425 + };
1426 +
1427 + clockgen: clocking@1ee1000 {
1428 + compatible = "fsl,ls1012a-clockgen";
1429 + reg = <0x0 0x1ee1000 0x0 0x1000>;
1430 + #clock-cells = <2>;
1431 + clocks = <&sysclk &coreclk>;
1432 + clock-names = "sysclk", "coreclk";
1433 + };
1434 +
1435 + tmu: tmu@1f00000 {
1436 + compatible = "fsl,qoriq-tmu";
1437 + reg = <0x0 0x1f00000 0x0 0x10000>;
1438 + interrupts = <0 33 0x4>;
1439 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
1440 + fsl,tmu-calibration = <0x00000000 0x00000026
1441 + 0x00000001 0x0000002d
1442 + 0x00000002 0x00000032
1443 + 0x00000003 0x00000039
1444 + 0x00000004 0x0000003f
1445 + 0x00000005 0x00000046
1446 + 0x00000006 0x0000004d
1447 + 0x00000007 0x00000054
1448 + 0x00000008 0x0000005a
1449 + 0x00000009 0x00000061
1450 + 0x0000000a 0x0000006a
1451 + 0x0000000b 0x00000071
1452 +
1453 + 0x00010000 0x00000025
1454 + 0x00010001 0x0000002c
1455 + 0x00010002 0x00000035
1456 + 0x00010003 0x0000003d
1457 + 0x00010004 0x00000045
1458 + 0x00010005 0x0000004e
1459 + 0x00010006 0x00000057
1460 + 0x00010007 0x00000061
1461 + 0x00010008 0x0000006b
1462 + 0x00010009 0x00000076
1463 +
1464 + 0x00020000 0x00000029
1465 + 0x00020001 0x00000033
1466 + 0x00020002 0x0000003d
1467 + 0x00020003 0x00000049
1468 + 0x00020004 0x00000056
1469 + 0x00020005 0x00000061
1470 + 0x00020006 0x0000006d
1471 +
1472 + 0x00030000 0x00000021
1473 + 0x00030001 0x0000002a
1474 + 0x00030002 0x0000003c
1475 + 0x00030003 0x0000004e>;
1476 + big-endian;
1477 + #thermal-sensor-cells = <1>;
1478 + };
1479 +
1480 + thermal-zones {
1481 + cpu_thermal: cpu-thermal {
1482 + polling-delay-passive = <1000>;
1483 + polling-delay = <5000>;
1484 + thermal-sensors = <&tmu 0>;
1485 +
1486 + trips {
1487 + cpu_alert: cpu-alert {
1488 + temperature = <85000>;
1489 + hysteresis = <2000>;
1490 + type = "passive";
1491 + };
1492 +
1493 + cpu_crit: cpu-crit {
1494 + temperature = <95000>;
1495 + hysteresis = <2000>;
1496 + type = "critical";
1497 + };
1498 + };
1499 +
1500 + cooling-maps {
1501 + map0 {
1502 + trip = <&cpu_alert>;
1503 + cooling-device =
1504 + <&cpu0 THERMAL_NO_LIMIT
1505 + THERMAL_NO_LIMIT>;
1506 + };
1507 + };
1508 + };
1509 + };
1510 +
1511 + esdhc0: esdhc@1560000 {
1512 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1513 + reg = <0x0 0x1560000 0x0 0x10000>;
1514 + interrupts = <0 62 0x4>;
1515 + clocks = <&clockgen 4 0>;
1516 + voltage-ranges = <1800 1800 3300 3300>;
1517 + sdhci,auto-cmd12;
1518 + big-endian;
1519 + bus-width = <4>;
1520 + status = "disabled";
1521 + };
1522 +
1523 + esdhc1: esdhc@1580000 {
1524 + compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
1525 + reg = <0x0 0x1580000 0x0 0x10000>;
1526 + interrupts = <0 65 0x4>;
1527 + clocks = <&clockgen 4 0>;
1528 + voltage-ranges = <1800 1800 3300 3300>;
1529 + sdhci,auto-cmd12;
1530 + big-endian;
1531 + broken-cd;
1532 + bus-width = <4>;
1533 + status = "disabled";
1534 + };
1535 +
1536 + ftm0: ftm0@29d0000 {
1537 + compatible = "fsl,ftm-alarm";
1538 + reg = <0x0 0x29d0000 0x0 0x10000>,
1539 + <0x0 0x1ee2140 0x0 0x4>;
1540 + reg-names = "ftm", "FlexTimer1";
1541 + interrupts = <0 86 0x4>;
1542 + big-endian;
1543 + };
1544 +
1545 + i2c0: i2c@2180000 {
1546 + compatible = "fsl,vf610-i2c";
1547 + #address-cells = <1>;
1548 + #size-cells = <0>;
1549 + reg = <0x0 0x2180000 0x0 0x10000>;
1550 + interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
1551 + clocks = <&clockgen 4 0>;
1552 + status = "disabled";
1553 + };
1554 +
1555 + i2c1: i2c@2190000 {
1556 + compatible = "fsl,vf610-i2c";
1557 + #address-cells = <1>;
1558 + #size-cells = <0>;
1559 + reg = <0x0 0x2190000 0x0 0x10000>;
1560 + interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
1561 + clocks = <&clockgen 4 0>;
1562 + status = "disabled";
1563 + };
1564 +
1565 + duart0: serial@21c0500 {
1566 + compatible = "fsl,ns16550", "ns16550a";
1567 + reg = <0x00 0x21c0500 0x0 0x100>;
1568 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1569 + clocks = <&clockgen 4 0>;
1570 + status = "disabled";
1571 + };
1572 +
1573 + duart1: serial@21c0600 {
1574 + compatible = "fsl,ns16550", "ns16550a";
1575 + reg = <0x00 0x21c0600 0x0 0x100>;
1576 + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
1577 + clocks = <&clockgen 4 0>;
1578 + status = "disabled";
1579 + };
1580 +
1581 + gpio0: gpio@2300000 {
1582 + compatible = "fsl,qoriq-gpio";
1583 + reg = <0x0 0x2300000 0x0 0x10000>;
1584 + interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
1585 + gpio-controller;
1586 + #gpio-cells = <2>;
1587 + interrupt-controller;
1588 + #interrupt-cells = <2>;
1589 + };
1590 +
1591 + gpio1: gpio@2310000 {
1592 + compatible = "fsl,qoriq-gpio";
1593 + reg = <0x0 0x2310000 0x0 0x10000>;
1594 + interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
1595 + gpio-controller;
1596 + #gpio-cells = <2>;
1597 + interrupt-controller;
1598 + #interrupt-cells = <2>;
1599 + };
1600 +
1601 + qspi: quadspi@1550000 {
1602 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
1603 + #address-cells = <1>;
1604 + #size-cells = <0>;
1605 + reg = <0x0 0x1550000 0x0 0x10000>,
1606 + <0x0 0x40000000 0x0 0x10000000>;
1607 + reg-names = "QuadSPI", "QuadSPI-memory";
1608 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
1609 + clock-names = "qspi_en", "qspi";
1610 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
1611 + big-endian;
1612 + fsl,qspi-has-second-chip;
1613 + status = "disabled";
1614 + };
1615 +
1616 + wdog0: wdog@2ad0000 {
1617 + compatible = "fsl,ls1012a-wdt",
1618 + "fsl,imx21-wdt";
1619 + reg = <0x0 0x2ad0000 0x0 0x10000>;
1620 + interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
1621 + clocks = <&clockgen 4 0>;
1622 + big-endian;
1623 + };
1624 +
1625 + sai1: sai@2b50000 {
1626 + #sound-dai-cells = <0>;
1627 + compatible = "fsl,vf610-sai";
1628 + reg = <0x0 0x2b50000 0x0 0x10000>;
1629 + interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
1630 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1631 + <&clockgen 4 3>, <&clockgen 4 3>;
1632 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1633 + dma-names = "tx", "rx";
1634 + dmas = <&edma0 1 47>,
1635 + <&edma0 1 46>;
1636 + status = "disabled";
1637 + };
1638 +
1639 + sai2: sai@2b60000 {
1640 + #sound-dai-cells = <0>;
1641 + compatible = "fsl,vf610-sai";
1642 + reg = <0x0 0x2b60000 0x0 0x10000>;
1643 + interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
1644 + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
1645 + <&clockgen 4 3>, <&clockgen 4 3>;
1646 + clock-names = "bus", "mclk1", "mclk2", "mclk3";
1647 + dma-names = "tx", "rx";
1648 + dmas = <&edma0 1 45>,
1649 + <&edma0 1 44>;
1650 + status = "disabled";
1651 + };
1652 +
1653 + edma0: edma@2c00000 {
1654 + #dma-cells = <2>;
1655 + compatible = "fsl,vf610-edma";
1656 + reg = <0x0 0x2c00000 0x0 0x10000>,
1657 + <0x0 0x2c10000 0x0 0x10000>,
1658 + <0x0 0x2c20000 0x0 0x10000>;
1659 + interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
1660 + <0 103 IRQ_TYPE_LEVEL_HIGH>;
1661 + interrupt-names = "edma-tx", "edma-err";
1662 + dma-channels = <32>;
1663 + big-endian;
1664 + clock-names = "dmamux0", "dmamux1";
1665 + clocks = <&clockgen 4 3>,
1666 + <&clockgen 4 3>;
1667 + };
1668 +
1669 + usb0: usb3@2f00000 {
1670 + compatible = "snps,dwc3";
1671 + reg = <0x0 0x2f00000 0x0 0x10000>;
1672 + interrupts = <0 60 0x4>;
1673 + dr_mode = "host";
1674 + snps,quirk-frame-length-adjustment = <0x20>;
1675 + snps,dis_rxdet_inp3_quirk;
1676 + };
1677 +
1678 + usb1: usb2@8600000 {
1679 + compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
1680 + reg = <0x0 0x8600000 0x0 0x1000>;
1681 + interrupts = <0 139 0x4>;
1682 + dr_mode = "host";
1683 + phy_type = "ulpi";
1684 + };
1685 +
1686 + sata: sata@3200000 {
1687 + compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
1688 + reg = <0x0 0x3200000 0x0 0x10000>,
1689 + <0x0 0x20140520 0x0 0x4>;
1690 + reg-names = "ahci", "sata-ecc";
1691 + interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
1692 + clocks = <&clockgen 4 0>;
1693 + dma-coherent;
1694 + status = "disabled";
1695 + };
1696 + };
1697 +};
1698 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1699 new file mode 100644
1700 index 00000000..169e1714
1701 --- /dev/null
1702 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
1703 @@ -0,0 +1,45 @@
1704 +/*
1705 + * QorIQ FMan v3 device tree nodes for ls1043
1706 + *
1707 + * Copyright 2015-2016 Freescale Semiconductor Inc.
1708 + *
1709 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
1710 + */
1711 +
1712 +&soc {
1713 +
1714 +/* include used FMan blocks */
1715 +#include "qoriq-fman3-0.dtsi"
1716 +#include "qoriq-fman3-0-1g-0.dtsi"
1717 +#include "qoriq-fman3-0-1g-1.dtsi"
1718 +#include "qoriq-fman3-0-1g-2.dtsi"
1719 +#include "qoriq-fman3-0-1g-3.dtsi"
1720 +#include "qoriq-fman3-0-1g-4.dtsi"
1721 +#include "qoriq-fman3-0-1g-5.dtsi"
1722 +#include "qoriq-fman3-0-10g-0.dtsi"
1723 +
1724 +};
1725 +
1726 +&fman0 {
1727 + /* these aliases provide the FMan ports mapping */
1728 + enet0: ethernet@e0000 {
1729 + };
1730 +
1731 + enet1: ethernet@e2000 {
1732 + };
1733 +
1734 + enet2: ethernet@e4000 {
1735 + };
1736 +
1737 + enet3: ethernet@e6000 {
1738 + };
1739 +
1740 + enet4: ethernet@e8000 {
1741 + };
1742 +
1743 + enet5: ethernet@ea000 {
1744 + };
1745 +
1746 + enet6: ethernet@f0000 {
1747 + };
1748 +};
1749 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1750 new file mode 100644
1751 index 00000000..6c13b416
1752 --- /dev/null
1753 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
1754 @@ -0,0 +1,69 @@
1755 +/*
1756 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1757 + *
1758 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1759 + *
1760 + * Mingkai Hu <Mingkai.hu@freescale.com>
1761 + *
1762 + * This file is dual-licensed: you can use it either under the terms
1763 + * of the GPLv2 or the X11 license, at your option. Note that this dual
1764 + * licensing only applies to this file, and not this project as a
1765 + * whole.
1766 + *
1767 + * a) This library is free software; you can redistribute it and/or
1768 + * modify it under the terms of the GNU General Public License as
1769 + * published by the Free Software Foundation; either version 2 of the
1770 + * License, or (at your option) any later version.
1771 + *
1772 + * This library is distributed in the hope that it will be useful,
1773 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1774 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1775 + * GNU General Public License for more details.
1776 + *
1777 + * Or, alternatively,
1778 + *
1779 + * b) Permission is hereby granted, free of charge, to any person
1780 + * obtaining a copy of this software and associated documentation
1781 + * files (the "Software"), to deal in the Software without
1782 + * restriction, including without limitation the rights to use,
1783 + * copy, modify, merge, publish, distribute, sublicense, and/or
1784 + * sell copies of the Software, and to permit persons to whom the
1785 + * Software is furnished to do so, subject to the following
1786 + * conditions:
1787 + *
1788 + * The above copyright notice and this permission notice shall be
1789 + * included in all copies or substantial portions of the Software.
1790 + *
1791 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
1792 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
1793 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
1794 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
1795 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
1796 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
1797 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
1798 + * OTHER DEALINGS IN THE SOFTWARE.
1799 + */
1800 +
1801 +#include "fsl-ls1043a-qds.dts"
1802 +
1803 +&bman_fbpr {
1804 + compatible = "fsl,bman-fbpr";
1805 + alloc-ranges = <0 0 0x10000 0>;
1806 +};
1807 +&qman_fqd {
1808 + compatible = "fsl,qman-fqd";
1809 + alloc-ranges = <0 0 0x10000 0>;
1810 +};
1811 +&qman_pfdr {
1812 + compatible = "fsl,qman-pfdr";
1813 + alloc-ranges = <0 0 0x10000 0>;
1814 +};
1815 +
1816 +&soc {
1817 +#include "qoriq-dpaa-eth.dtsi"
1818 +#include "qoriq-fman3-0-6oh.dtsi"
1819 +};
1820 +
1821 +&fman0 {
1822 + compatible = "fsl,fman", "simple-bus";
1823 +};
1824 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1825 index dd9e9194..08abff73 100644
1826 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1827 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
1828 @@ -1,7 +1,7 @@
1829 /*
1830 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
1831 *
1832 - * Copyright 2014-2015, Freescale Semiconductor
1833 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
1834 *
1835 * Mingkai Hu <Mingkai.hu@freescale.com>
1836 *
1837 @@ -45,7 +45,7 @@
1838 */
1839
1840 /dts-v1/;
1841 -/include/ "fsl-ls1043a.dtsi"
1842 +#include "fsl-ls1043a.dtsi"
1843
1844 / {
1845 model = "LS1043A QDS Board";
1846 @@ -60,6 +60,22 @@
1847 serial1 = &duart1;
1848 serial2 = &duart2;
1849 serial3 = &duart3;
1850 + sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
1851 + sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
1852 + sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
1853 + sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
1854 + qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
1855 + qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
1856 + qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
1857 + qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
1858 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
1859 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
1860 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
1861 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
1862 + emi1_slot1 = &ls1043mdio_s1;
1863 + emi1_slot2 = &ls1043mdio_s2;
1864 + emi1_slot3 = &ls1043mdio_s3;
1865 + emi1_slot4 = &ls1043mdio_s4;
1866 };
1867
1868 chosen {
1869 @@ -97,8 +113,11 @@
1870 };
1871
1872 fpga: board-control@2,0 {
1873 - compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
1874 + #address-cells = <1>;
1875 + #size-cells = <1>;
1876 + compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
1877 reg = <0x2 0x0 0x0000100>;
1878 + ranges = <0 2 0 0x100>;
1879 };
1880 };
1881
1882 @@ -181,3 +200,149 @@
1883 reg = <0>;
1884 };
1885 };
1886 +
1887 +#include "fsl-ls1043-post.dtsi"
1888 +
1889 +&fman0 {
1890 + ethernet@e0000 {
1891 + phy-handle = <&qsgmii_phy_s2_p1>;
1892 + phy-connection-type = "sgmii";
1893 + };
1894 +
1895 + ethernet@e2000 {
1896 + phy-handle = <&qsgmii_phy_s2_p2>;
1897 + phy-connection-type = "sgmii";
1898 + };
1899 +
1900 + ethernet@e4000 {
1901 + phy-handle = <&rgmii_phy1>;
1902 + phy-connection-type = "rgmii";
1903 + };
1904 +
1905 + ethernet@e6000 {
1906 + phy-handle = <&rgmii_phy2>;
1907 + phy-connection-type = "rgmii";
1908 + };
1909 +
1910 + ethernet@e8000 {
1911 + phy-handle = <&qsgmii_phy_s2_p3>;
1912 + phy-connection-type = "sgmii";
1913 + };
1914 +
1915 + ethernet@ea000 {
1916 + phy-handle = <&qsgmii_phy_s2_p4>;
1917 + phy-connection-type = "sgmii";
1918 + };
1919 +
1920 + ethernet@f0000 { /* DTSEC9/10GEC1 */
1921 + fixed-link = <1 1 10000 0 0>;
1922 + phy-connection-type = "xgmii";
1923 + };
1924 +};
1925 +
1926 +&fpga {
1927 + mdio-mux-emi1 {
1928 + compatible = "mdio-mux-mmioreg", "mdio-mux";
1929 + mdio-parent-bus = <&mdio0>;
1930 + #address-cells = <1>;
1931 + #size-cells = <0>;
1932 + reg = <0x54 1>; /* BRDCFG4 */
1933 + mux-mask = <0xe0>; /* EMI1 */
1934 +
1935 + /* On-board RGMII1 PHY */
1936 + ls1043mdio0: mdio@0 {
1937 + reg = <0>;
1938 + #address-cells = <1>;
1939 + #size-cells = <0>;
1940 +
1941 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
1942 + reg = <0x1>;
1943 + };
1944 + };
1945 +
1946 + /* On-board RGMII2 PHY */
1947 + ls1043mdio1: mdio@1 {
1948 + reg = <0x20>;
1949 + #address-cells = <1>;
1950 + #size-cells = <0>;
1951 +
1952 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
1953 + reg = <0x2>;
1954 + };
1955 + };
1956 +
1957 + /* Slot 1 */
1958 + ls1043mdio_s1: mdio@2 {
1959 + reg = <0x40>;
1960 + #address-cells = <1>;
1961 + #size-cells = <0>;
1962 + status = "disabled";
1963 +
1964 + qsgmii_phy_s1_p1: ethernet-phy@4 {
1965 + reg = <0x4>;
1966 + };
1967 + qsgmii_phy_s1_p2: ethernet-phy@5 {
1968 + reg = <0x5>;
1969 + };
1970 + qsgmii_phy_s1_p3: ethernet-phy@6 {
1971 + reg = <0x6>;
1972 + };
1973 + qsgmii_phy_s1_p4: ethernet-phy@7 {
1974 + reg = <0x7>;
1975 + };
1976 +
1977 + sgmii_phy_s1_p1: ethernet-phy@1c {
1978 + reg = <0x1c>;
1979 + };
1980 + };
1981 +
1982 + /* Slot 2 */
1983 + ls1043mdio_s2: mdio@3 {
1984 + reg = <0x60>;
1985 + #address-cells = <1>;
1986 + #size-cells = <0>;
1987 + status = "disabled";
1988 +
1989 + qsgmii_phy_s2_p1: ethernet-phy@8 {
1990 + reg = <0x8>;
1991 + };
1992 + qsgmii_phy_s2_p2: ethernet-phy@9 {
1993 + reg = <0x9>;
1994 + };
1995 + qsgmii_phy_s2_p3: ethernet-phy@a {
1996 + reg = <0xa>;
1997 + };
1998 + qsgmii_phy_s2_p4: ethernet-phy@b {
1999 + reg = <0xb>;
2000 + };
2001 +
2002 + sgmii_phy_s2_p1: ethernet-phy@1c {
2003 + reg = <0x1c>;
2004 + };
2005 + };
2006 +
2007 + /* Slot 3 */
2008 + ls1043mdio_s3: mdio@4 {
2009 + reg = <0x80>;
2010 + #address-cells = <1>;
2011 + #size-cells = <0>;
2012 + status = "disabled";
2013 +
2014 + sgmii_phy_s3_p1: ethernet-phy@1c {
2015 + reg = <0x1c>;
2016 + };
2017 + };
2018 +
2019 + /* Slot 4 */
2020 + ls1043mdio_s4: mdio@5 {
2021 + reg = <0xa0>;
2022 + #address-cells = <1>;
2023 + #size-cells = <0>;
2024 + status = "disabled";
2025 +
2026 + sgmii_phy_s4_p1: ethernet-phy@1c {
2027 + reg = <0x1c>;
2028 + };
2029 + };
2030 + };
2031 +};
2032 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2033 new file mode 100644
2034 index 00000000..ac4b9a41
2035 --- /dev/null
2036 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
2037 @@ -0,0 +1,69 @@
2038 +/*
2039 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2040 + *
2041 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2042 + *
2043 + * Mingkai Hu <Mingkai.hu@freescale.com>
2044 + *
2045 + * This file is dual-licensed: you can use it either under the terms
2046 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2047 + * licensing only applies to this file, and not this project as a
2048 + * whole.
2049 + *
2050 + * a) This library is free software; you can redistribute it and/or
2051 + * modify it under the terms of the GNU General Public License as
2052 + * published by the Free Software Foundation; either version 2 of the
2053 + * License, or (at your option) any later version.
2054 + *
2055 + * This library is distributed in the hope that it will be useful,
2056 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2057 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2058 + * GNU General Public License for more details.
2059 + *
2060 + * Or, alternatively,
2061 + *
2062 + * b) Permission is hereby granted, free of charge, to any person
2063 + * obtaining a copy of this software and associated documentation
2064 + * files (the "Software"), to deal in the Software without
2065 + * restriction, including without limitation the rights to use,
2066 + * copy, modify, merge, publish, distribute, sublicense, and/or
2067 + * sell copies of the Software, and to permit persons to whom the
2068 + * Software is furnished to do so, subject to the following
2069 + * conditions:
2070 + *
2071 + * The above copyright notice and this permission notice shall be
2072 + * included in all copies or substantial portions of the Software.
2073 + *
2074 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2075 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2076 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2077 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2078 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2079 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2080 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2081 + * OTHER DEALINGS IN THE SOFTWARE.
2082 + */
2083 +
2084 +#include "fsl-ls1043a-rdb.dts"
2085 +
2086 +&bman_fbpr {
2087 + compatible = "fsl,bman-fbpr";
2088 + alloc-ranges = <0 0 0x10000 0>;
2089 +};
2090 +&qman_fqd {
2091 + compatible = "fsl,qman-fqd";
2092 + alloc-ranges = <0 0 0x10000 0>;
2093 +};
2094 +&qman_pfdr {
2095 + compatible = "fsl,qman-pfdr";
2096 + alloc-ranges = <0 0 0x10000 0>;
2097 +};
2098 +
2099 +&soc {
2100 +#include "qoriq-dpaa-eth.dtsi"
2101 +#include "qoriq-fman3-0-6oh.dtsi"
2102 +};
2103 +
2104 +&fman0 {
2105 + compatible = "fsl,fman", "simple-bus";
2106 +};
2107 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2108 new file mode 100644
2109 index 00000000..4e46a0a5
2110 --- /dev/null
2111 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
2112 @@ -0,0 +1,117 @@
2113 +/*
2114 + * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2115 + *
2116 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2117 + *
2118 + * This file is licensed under the terms of the GNU General Public
2119 + * License version 2. This program is licensed "as is" without any
2120 + * warranty of any kind, whether express or implied.
2121 + */
2122 +
2123 +#include "fsl-ls1043a-rdb-sdk.dts"
2124 +
2125 +&soc {
2126 + bp7: buffer-pool@7 {
2127 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2128 + fsl,bpid = <7>;
2129 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
2130 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
2131 + };
2132 +
2133 + bp8: buffer-pool@8 {
2134 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2135 + fsl,bpid = <8>;
2136 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
2137 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2138 + };
2139 +
2140 + bp9: buffer-pool@9 {
2141 + compatible = "fsl,p4080-bpool", "fsl,bpool";
2142 + fsl,bpid = <9>;
2143 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
2144 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
2145 + };
2146 +
2147 + fsl,dpaa {
2148 + compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
2149 +
2150 + ethernet@0 {
2151 + compatible = "fsl,dpa-ethernet-init";
2152 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2153 + fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
2154 + fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
2155 + };
2156 +
2157 + ethernet@1 {
2158 + compatible = "fsl,dpa-ethernet-init";
2159 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2160 + fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
2161 + fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
2162 + };
2163 +
2164 + ethernet@2 {
2165 + compatible = "fsl,dpa-ethernet-init";
2166 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2167 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
2168 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
2169 + };
2170 +
2171 + ethernet@3 {
2172 + compatible = "fsl,dpa-ethernet-init";
2173 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2174 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
2175 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
2176 + };
2177 +
2178 + ethernet@4 {
2179 + compatible = "fsl,dpa-ethernet-init";
2180 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2181 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
2182 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
2183 + };
2184 +
2185 + ethernet@5 {
2186 + compatible = "fsl,dpa-ethernet-init";
2187 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2188 + fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
2189 + fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
2190 + };
2191 +
2192 + ethernet@8 {
2193 + compatible = "fsl,dpa-ethernet-init";
2194 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
2195 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
2196 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
2197 +
2198 + };
2199 + dpa-fman0-oh@2 {
2200 + compatible = "fsl,dpa-oh";
2201 + /* Define frame queues for the OH port*/
2202 + /* <OH Rx error, OH Rx default> */
2203 + fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
2204 + fsl,fman-oh-port = <&fman0_oh2>;
2205 + };
2206 + };
2207 +};
2208 +/ {
2209 + reserved-memory {
2210 + #address-cells = <2>;
2211 + #size-cells = <2>;
2212 + ranges;
2213 +
2214 + usdpaa_mem: usdpaa_mem {
2215 + compatible = "fsl,usdpaa-mem";
2216 + alloc-ranges = <0 0 0x10000 0>;
2217 + size = <0 0x10000000>;
2218 + alignment = <0 0x10000000>;
2219 + };
2220 + };
2221 +};
2222 +
2223 +&fman0 {
2224 + fman0_oh2: port@83000 {
2225 + cell-index = <1>;
2226 + compatible = "fsl,fman-port-oh";
2227 + reg = <0x83000 0x1000>;
2228 + };
2229 +};
2230 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2231 index d2313e05..f92ae325 100644
2232 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2233 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
2234 @@ -1,7 +1,7 @@
2235 /*
2236 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2237 *
2238 - * Copyright 2014-2015, Freescale Semiconductor
2239 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2240 *
2241 * Mingkai Hu <Mingkai.hu@freescale.com>
2242 *
2243 @@ -45,7 +45,7 @@
2244 */
2245
2246 /dts-v1/;
2247 -/include/ "fsl-ls1043a.dtsi"
2248 +#include "fsl-ls1043a.dtsi"
2249
2250 / {
2251 model = "LS1043A RDB Board";
2252 @@ -86,6 +86,10 @@
2253 compatible = "pericom,pt7c4338";
2254 reg = <0x68>;
2255 };
2256 + rtc@51 {
2257 + compatible = "nxp,pcf85263";
2258 + reg = <0x51>;
2259 + };
2260 };
2261
2262 &ifc {
2263 @@ -130,6 +134,38 @@
2264 reg = <0>;
2265 spi-max-frequency = <1000000>; /* input clock */
2266 };
2267 +
2268 + slic@2 {
2269 + compatible = "maxim,ds26522";
2270 + reg = <2>;
2271 + spi-max-frequency = <2000000>;
2272 + fsl,spi-cs-sck-delay = <100>;
2273 + fsl,spi-sck-cs-delay = <50>;
2274 + };
2275 +
2276 + slic@3 {
2277 + compatible = "maxim,ds26522";
2278 + reg = <3>;
2279 + spi-max-frequency = <2000000>;
2280 + fsl,spi-cs-sck-delay = <100>;
2281 + fsl,spi-sck-cs-delay = <50>;
2282 + };
2283 +};
2284 +
2285 +&uqe {
2286 + ucc_hdlc: ucc@2000 {
2287 + compatible = "fsl,ucc-hdlc";
2288 + rx-clock-name = "clk8";
2289 + tx-clock-name = "clk9";
2290 + fsl,rx-sync-clock = "rsync_pin";
2291 + fsl,tx-sync-clock = "tsync_pin";
2292 + fsl,tx-timeslot-mask = <0xfffffffe>;
2293 + fsl,rx-timeslot-mask = <0xfffffffe>;
2294 + fsl,tdm-framer-type = "e1";
2295 + fsl,tdm-id = <0>;
2296 + fsl,siram-entry-id = <0>;
2297 + fsl,tdm-interface;
2298 + };
2299 };
2300
2301 &duart0 {
2302 @@ -139,3 +175,76 @@
2303 &duart1 {
2304 status = "okay";
2305 };
2306 +
2307 +#include "fsl-ls1043-post.dtsi"
2308 +
2309 +&fman0 {
2310 + ethernet@e0000 {
2311 + phy-handle = <&qsgmii_phy1>;
2312 + phy-connection-type = "qsgmii";
2313 + };
2314 +
2315 + ethernet@e2000 {
2316 + phy-handle = <&qsgmii_phy2>;
2317 + phy-connection-type = "qsgmii";
2318 + };
2319 +
2320 + ethernet@e4000 {
2321 + phy-handle = <&rgmii_phy1>;
2322 + phy-connection-type = "rgmii-txid";
2323 + };
2324 +
2325 + ethernet@e6000 {
2326 + phy-handle = <&rgmii_phy2>;
2327 + phy-connection-type = "rgmii-txid";
2328 + };
2329 +
2330 + ethernet@e8000 {
2331 + phy-handle = <&qsgmii_phy3>;
2332 + phy-connection-type = "qsgmii";
2333 + };
2334 +
2335 + ethernet@ea000 {
2336 + phy-handle = <&qsgmii_phy4>;
2337 + phy-connection-type = "qsgmii";
2338 + };
2339 +
2340 + ethernet@f0000 { /* 10GEC1 */
2341 + phy-handle = <&aqr105_phy>;
2342 + phy-connection-type = "xgmii";
2343 + };
2344 +
2345 + mdio@fc000 {
2346 + rgmii_phy1: ethernet-phy@1 {
2347 + reg = <0x1>;
2348 + };
2349 +
2350 + rgmii_phy2: ethernet-phy@2 {
2351 + reg = <0x2>;
2352 + };
2353 +
2354 + qsgmii_phy1: ethernet-phy@4 {
2355 + reg = <0x4>;
2356 + };
2357 +
2358 + qsgmii_phy2: ethernet-phy@5 {
2359 + reg = <0x5>;
2360 + };
2361 +
2362 + qsgmii_phy3: ethernet-phy@6 {
2363 + reg = <0x6>;
2364 + };
2365 +
2366 + qsgmii_phy4: ethernet-phy@7 {
2367 + reg = <0x7>;
2368 + };
2369 + };
2370 +
2371 + mdio@fd000 {
2372 + aqr105_phy: ethernet-phy@1 {
2373 + compatible = "ethernet-phy-ieee802.3-c45";
2374 + interrupts = <0 132 4>;
2375 + reg = <0x1>;
2376 + };
2377 + };
2378 +};
2379 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2380 index 97d331ec..8b27faaf 100644
2381 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2382 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
2383 @@ -1,7 +1,7 @@
2384 /*
2385 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
2386 *
2387 - * Copyright 2014-2015, Freescale Semiconductor
2388 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2389 *
2390 * Mingkai Hu <Mingkai.hu@freescale.com>
2391 *
2392 @@ -44,12 +44,25 @@
2393 * OTHER DEALINGS IN THE SOFTWARE.
2394 */
2395
2396 +#include <dt-bindings/thermal/thermal.h>
2397 +
2398 / {
2399 compatible = "fsl,ls1043a";
2400 interrupt-parent = <&gic>;
2401 #address-cells = <2>;
2402 #size-cells = <2>;
2403
2404 + aliases {
2405 + fman0 = &fman0;
2406 + ethernet0 = &enet0;
2407 + ethernet1 = &enet1;
2408 + ethernet2 = &enet2;
2409 + ethernet3 = &enet3;
2410 + ethernet4 = &enet4;
2411 + ethernet5 = &enet5;
2412 + ethernet6 = &enet6;
2413 + };
2414 +
2415 cpus {
2416 #address-cells = <1>;
2417 #size-cells = <0>;
2418 @@ -66,6 +79,8 @@
2419 reg = <0x0>;
2420 clocks = <&clockgen 1 0>;
2421 next-level-cache = <&l2>;
2422 + #cooling-cells = <2>;
2423 + cpu-idle-states = <&CPU_PH20>;
2424 };
2425
2426 cpu1: cpu@1 {
2427 @@ -74,6 +89,7 @@
2428 reg = <0x1>;
2429 clocks = <&clockgen 1 0>;
2430 next-level-cache = <&l2>;
2431 + cpu-idle-states = <&CPU_PH20>;
2432 };
2433
2434 cpu2: cpu@2 {
2435 @@ -82,6 +98,7 @@
2436 reg = <0x2>;
2437 clocks = <&clockgen 1 0>;
2438 next-level-cache = <&l2>;
2439 + cpu-idle-states = <&CPU_PH20>;
2440 };
2441
2442 cpu3: cpu@3 {
2443 @@ -90,6 +107,7 @@
2444 reg = <0x3>;
2445 clocks = <&clockgen 1 0>;
2446 next-level-cache = <&l2>;
2447 + cpu-idle-states = <&CPU_PH20>;
2448 };
2449
2450 l2: l2-cache {
2451 @@ -97,12 +115,56 @@
2452 };
2453 };
2454
2455 + idle-states {
2456 + /*
2457 + * PSCI node is not added default, U-boot will add missing
2458 + * parts if it determines to use PSCI.
2459 + */
2460 + entry-method = "arm,psci";
2461 +
2462 + CPU_PH20: cpu-ph20 {
2463 + compatible = "arm,idle-state";
2464 + idle-state-name = "PH20";
2465 + arm,psci-suspend-param = <0x0>;
2466 + entry-latency-us = <1000>;
2467 + exit-latency-us = <1000>;
2468 + min-residency-us = <3000>;
2469 + };
2470 + };
2471 +
2472 memory@80000000 {
2473 device_type = "memory";
2474 reg = <0x0 0x80000000 0 0x80000000>;
2475 /* DRAM space 1, size: 2GiB DRAM */
2476 };
2477
2478 + reserved-memory {
2479 + #address-cells = <2>;
2480 + #size-cells = <2>;
2481 + ranges;
2482 +
2483 + bman_fbpr: bman-fbpr {
2484 + compatible = "shared-dma-pool";
2485 + size = <0 0x1000000>;
2486 + alignment = <0 0x1000000>;
2487 + no-map;
2488 + };
2489 +
2490 + qman_fqd: qman-fqd {
2491 + compatible = "shared-dma-pool";
2492 + size = <0 0x400000>;
2493 + alignment = <0 0x400000>;
2494 + no-map;
2495 + };
2496 +
2497 + qman_pfdr: qman-pfdr {
2498 + compatible = "shared-dma-pool";
2499 + size = <0 0x2000000>;
2500 + alignment = <0 0x2000000>;
2501 + no-map;
2502 + };
2503 + };
2504 +
2505 sysclk: sysclk {
2506 compatible = "fixed-clock";
2507 #clock-cells = <0>;
2508 @@ -149,7 +211,7 @@
2509 interrupts = <1 9 0xf08>;
2510 };
2511
2512 - soc {
2513 + soc: soc {
2514 compatible = "simple-bus";
2515 #address-cells = <2>;
2516 #size-cells = <2>;
2517 @@ -213,13 +275,14 @@
2518
2519 dcfg: dcfg@1ee0000 {
2520 compatible = "fsl,ls1043a-dcfg", "syscon";
2521 - reg = <0x0 0x1ee0000 0x0 0x10000>;
2522 + reg = <0x0 0x1ee0000 0x0 0x1000>;
2523 big-endian;
2524 };
2525
2526 ifc: ifc@1530000 {
2527 compatible = "fsl,ifc", "simple-bus";
2528 reg = <0x0 0x1530000 0x0 0x10000>;
2529 + big-endian;
2530 interrupts = <0 43 0x4>;
2531 };
2532
2533 @@ -255,6 +318,103 @@
2534 big-endian;
2535 };
2536
2537 + tmu: tmu@1f00000 {
2538 + compatible = "fsl,qoriq-tmu";
2539 + reg = <0x0 0x1f00000 0x0 0x10000>;
2540 + interrupts = <0 33 0x4>;
2541 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
2542 + fsl,tmu-calibration = <0x00000000 0x00000026
2543 + 0x00000001 0x0000002d
2544 + 0x00000002 0x00000032
2545 + 0x00000003 0x00000039
2546 + 0x00000004 0x0000003f
2547 + 0x00000005 0x00000046
2548 + 0x00000006 0x0000004d
2549 + 0x00000007 0x00000054
2550 + 0x00000008 0x0000005a
2551 + 0x00000009 0x00000061
2552 + 0x0000000a 0x0000006a
2553 + 0x0000000b 0x00000071
2554 +
2555 + 0x00010000 0x00000025
2556 + 0x00010001 0x0000002c
2557 + 0x00010002 0x00000035
2558 + 0x00010003 0x0000003d
2559 + 0x00010004 0x00000045
2560 + 0x00010005 0x0000004e
2561 + 0x00010006 0x00000057
2562 + 0x00010007 0x00000061
2563 + 0x00010008 0x0000006b
2564 + 0x00010009 0x00000076
2565 +
2566 + 0x00020000 0x00000029
2567 + 0x00020001 0x00000033
2568 + 0x00020002 0x0000003d
2569 + 0x00020003 0x00000049
2570 + 0x00020004 0x00000056
2571 + 0x00020005 0x00000061
2572 + 0x00020006 0x0000006d
2573 +
2574 + 0x00030000 0x00000021
2575 + 0x00030001 0x0000002a
2576 + 0x00030002 0x0000003c
2577 + 0x00030003 0x0000004e>;
2578 + #thermal-sensor-cells = <1>;
2579 + };
2580 +
2581 + thermal-zones {
2582 + cpu_thermal: cpu-thermal {
2583 + polling-delay-passive = <1000>;
2584 + polling-delay = <5000>;
2585 +
2586 + thermal-sensors = <&tmu 3>;
2587 +
2588 + trips {
2589 + cpu_alert: cpu-alert {
2590 + temperature = <85000>;
2591 + hysteresis = <2000>;
2592 + type = "passive";
2593 + };
2594 + cpu_crit: cpu-crit {
2595 + temperature = <95000>;
2596 + hysteresis = <2000>;
2597 + type = "critical";
2598 + };
2599 + };
2600 +
2601 + cooling-maps {
2602 + map0 {
2603 + trip = <&cpu_alert>;
2604 + cooling-device =
2605 + <&cpu0 THERMAL_NO_LIMIT
2606 + THERMAL_NO_LIMIT>;
2607 + };
2608 + };
2609 + };
2610 + };
2611 +
2612 + qman: qman@1880000 {
2613 + compatible = "fsl,qman";
2614 + reg = <0x00 0x1880000 0x0 0x10000>;
2615 + interrupts = <0 45 0x4>;
2616 + memory-region = <&qman_fqd &qman_pfdr>;
2617 + };
2618 +
2619 + bman: bman@1890000 {
2620 + compatible = "fsl,bman";
2621 + reg = <0x00 0x1890000 0x0 0x10000>;
2622 + interrupts = <0 45 0x4>;
2623 + memory-region = <&bman_fbpr>;
2624 + };
2625 +
2626 + bportals: bman-portals@508000000 {
2627 + ranges = <0x0 0x5 0x08000000 0x8000000>;
2628 + };
2629 +
2630 + qportals: qman-portals@500000000 {
2631 + ranges = <0x0 0x5 0x00000000 0x8000000>;
2632 + };
2633 +
2634 dspi0: dspi@2100000 {
2635 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
2636 #address-cells = <1>;
2637 @@ -396,6 +556,72 @@
2638 #interrupt-cells = <2>;
2639 };
2640
2641 + uqe: uqe@2400000 {
2642 + #address-cells = <1>;
2643 + #size-cells = <1>;
2644 + device_type = "qe";
2645 + compatible = "fsl,qe", "simple-bus";
2646 + ranges = <0x0 0x0 0x2400000 0x40000>;
2647 + reg = <0x0 0x2400000 0x0 0x480>;
2648 + brg-frequency = <100000000>;
2649 + bus-frequency = <200000000>;
2650 +
2651 + fsl,qe-num-riscs = <1>;
2652 + fsl,qe-num-snums = <28>;
2653 +
2654 + qeic: qeic@80 {
2655 + compatible = "fsl,qe-ic";
2656 + reg = <0x80 0x80>;
2657 + #address-cells = <0>;
2658 + interrupt-controller;
2659 + #interrupt-cells = <1>;
2660 + interrupts = <0 77 0x04 0 77 0x04>;
2661 + };
2662 +
2663 + si1: si@700 {
2664 + #address-cells = <1>;
2665 + #size-cells = <0>;
2666 + compatible = "fsl,ls1043-qe-si",
2667 + "fsl,t1040-qe-si";
2668 + reg = <0x700 0x80>;
2669 + };
2670 +
2671 + siram1: siram@1000 {
2672 + #address-cells = <1>;
2673 + #size-cells = <1>;
2674 + compatible = "fsl,ls1043-qe-siram",
2675 + "fsl,t1040-qe-siram";
2676 + reg = <0x1000 0x800>;
2677 + };
2678 +
2679 + ucc@2000 {
2680 + cell-index = <1>;
2681 + reg = <0x2000 0x200>;
2682 + interrupts = <32>;
2683 + interrupt-parent = <&qeic>;
2684 + };
2685 +
2686 + ucc@2200 {
2687 + cell-index = <3>;
2688 + reg = <0x2200 0x200>;
2689 + interrupts = <34>;
2690 + interrupt-parent = <&qeic>;
2691 + };
2692 +
2693 + muram@10000 {
2694 + #address-cells = <1>;
2695 + #size-cells = <1>;
2696 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
2697 + ranges = <0x0 0x10000 0x6000>;
2698 +
2699 + data-only@0 {
2700 + compatible = "fsl,qe-muram-data",
2701 + "fsl,cpm-muram-data";
2702 + reg = <0x0 0x6000>;
2703 + };
2704 + };
2705 + };
2706 +
2707 lpuart0: serial@2950000 {
2708 compatible = "fsl,ls1021a-lpuart";
2709 reg = <0x0 0x2950000 0x0 0x1000>;
2710 @@ -450,6 +676,16 @@
2711 status = "disabled";
2712 };
2713
2714 + ftm0: ftm0@29d0000 {
2715 + compatible = "fsl,ftm-alarm";
2716 + reg = <0x0 0x29d0000 0x0 0x10000>,
2717 + <0x0 0x1ee2140 0x0 0x4>;
2718 + reg-names = "ftm", "FlexTimer1";
2719 + interrupts = <0 86 0x4>;
2720 + big-endian;
2721 + status = "okay";
2722 + };
2723 +
2724 wdog0: wdog@2ad0000 {
2725 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
2726 reg = <0x0 0x2ad0000 0x0 0x10000>;
2727 @@ -482,6 +718,8 @@
2728 dr_mode = "host";
2729 snps,quirk-frame-length-adjustment = <0x20>;
2730 snps,dis_rxdet_inp3_quirk;
2731 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2732 + snps,dma-snooping;
2733 };
2734
2735 usb1: usb3@3000000 {
2736 @@ -491,6 +729,9 @@
2737 dr_mode = "host";
2738 snps,quirk-frame-length-adjustment = <0x20>;
2739 snps,dis_rxdet_inp3_quirk;
2740 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2741 + snps,dma-snooping;
2742 + configure-gfladj;
2743 };
2744
2745 usb2: usb3@3100000 {
2746 @@ -500,32 +741,52 @@
2747 dr_mode = "host";
2748 snps,quirk-frame-length-adjustment = <0x20>;
2749 snps,dis_rxdet_inp3_quirk;
2750 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
2751 + snps,dma-snooping;
2752 + configure-gfladj;
2753 };
2754
2755 sata: sata@3200000 {
2756 compatible = "fsl,ls1043a-ahci";
2757 - reg = <0x0 0x3200000 0x0 0x10000>;
2758 + reg = <0x0 0x3200000 0x0 0x10000>,
2759 + <0x0 0x20140520 0x0 0x4>;
2760 + reg-names = "ahci", "sata-ecc";
2761 interrupts = <0 69 0x4>;
2762 clocks = <&clockgen 4 0>;
2763 dma-coherent;
2764 };
2765
2766 + qdma: qdma@8380000 {
2767 + compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
2768 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
2769 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
2770 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
2771 + interrupts = <0 152 0x4>,
2772 + <0 39 0x4>;
2773 + interrupt-names = "qdma-error", "qdma-queue";
2774 + channels = <8>;
2775 + queues = <2>;
2776 + status-sizes = <64>;
2777 + queue-sizes = <64 64>;
2778 + big-endian;
2779 + };
2780 +
2781 msi1: msi-controller1@1571000 {
2782 - compatible = "fsl,1s1043a-msi";
2783 + compatible = "fsl,ls1043a-msi";
2784 reg = <0x0 0x1571000 0x0 0x8>;
2785 msi-controller;
2786 interrupts = <0 116 0x4>;
2787 };
2788
2789 msi2: msi-controller2@1572000 {
2790 - compatible = "fsl,1s1043a-msi";
2791 + compatible = "fsl,ls1043a-msi";
2792 reg = <0x0 0x1572000 0x0 0x8>;
2793 msi-controller;
2794 interrupts = <0 126 0x4>;
2795 };
2796
2797 msi3: msi-controller3@1573000 {
2798 - compatible = "fsl,1s1043a-msi";
2799 + compatible = "fsl,ls1043a-msi";
2800 reg = <0x0 0x1573000 0x0 0x8>;
2801 msi-controller;
2802 interrupts = <0 160 0x4>;
2803 @@ -536,9 +797,9 @@
2804 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
2805 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
2806 reg-names = "regs", "config";
2807 - interrupts = <0 118 0x4>, /* controller interrupt */
2808 - <0 117 0x4>; /* PME interrupt */
2809 - interrupt-names = "intr", "pme";
2810 + interrupts = <0 117 0x4>, /* PME interrupt */
2811 + <0 118 0x4>; /* aer interrupt */
2812 + interrupt-names = "pme", "aer";
2813 #address-cells = <3>;
2814 #size-cells = <2>;
2815 device_type = "pci";
2816 @@ -547,7 +808,7 @@
2817 bus-range = <0x0 0xff>;
2818 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
2819 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2820 - msi-parent = <&msi1>;
2821 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2822 #interrupt-cells = <1>;
2823 interrupt-map-mask = <0 0 0 7>;
2824 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
2825 @@ -561,9 +822,9 @@
2826 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
2827 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
2828 reg-names = "regs", "config";
2829 - interrupts = <0 128 0x4>,
2830 - <0 127 0x4>;
2831 - interrupt-names = "intr", "pme";
2832 + interrupts = <0 127 0x4>,
2833 + <0 128 0x4>;
2834 + interrupt-names = "pme", "aer";
2835 #address-cells = <3>;
2836 #size-cells = <2>;
2837 device_type = "pci";
2838 @@ -572,7 +833,7 @@
2839 bus-range = <0x0 0xff>;
2840 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
2841 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2842 - msi-parent = <&msi2>;
2843 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2844 #interrupt-cells = <1>;
2845 interrupt-map-mask = <0 0 0 7>;
2846 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
2847 @@ -586,9 +847,9 @@
2848 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
2849 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
2850 reg-names = "regs", "config";
2851 - interrupts = <0 162 0x4>,
2852 - <0 161 0x4>;
2853 - interrupt-names = "intr", "pme";
2854 + interrupts = <0 161 0x4>,
2855 + <0 162 0x4>;
2856 + interrupt-names = "pme", "aer";
2857 #address-cells = <3>;
2858 #size-cells = <2>;
2859 device_type = "pci";
2860 @@ -597,7 +858,7 @@
2861 bus-range = <0x0 0xff>;
2862 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
2863 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
2864 - msi-parent = <&msi3>;
2865 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
2866 #interrupt-cells = <1>;
2867 interrupt-map-mask = <0 0 0 7>;
2868 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
2869 @@ -608,3 +869,6 @@
2870 };
2871
2872 };
2873 +
2874 +#include "qoriq-qman1-portals.dtsi"
2875 +#include "qoriq-bman1-portals.dtsi"
2876 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
2877 new file mode 100644
2878 index 00000000..f5017dba
2879 --- /dev/null
2880 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
2881 @@ -0,0 +1,48 @@
2882 +/*
2883 + * QorIQ FMan v3 device tree nodes for ls1046
2884 + *
2885 + * Copyright 2015-2016 Freescale Semiconductor Inc.
2886 + *
2887 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2888 + */
2889 +
2890 +&soc {
2891 +
2892 +/* include used FMan blocks */
2893 +#include "qoriq-fman3-0.dtsi"
2894 +#include "qoriq-fman3-0-1g-0.dtsi"
2895 +#include "qoriq-fman3-0-1g-1.dtsi"
2896 +#include "qoriq-fman3-0-1g-2.dtsi"
2897 +#include "qoriq-fman3-0-1g-3.dtsi"
2898 +#include "qoriq-fman3-0-1g-4.dtsi"
2899 +#include "qoriq-fman3-0-1g-5.dtsi"
2900 +#include "qoriq-fman3-0-10g-0.dtsi"
2901 +#include "qoriq-fman3-0-10g-1.dtsi"
2902 +};
2903 +
2904 +&fman0 {
2905 + /* these aliases provide the FMan ports mapping */
2906 + enet0: ethernet@e0000 {
2907 + };
2908 +
2909 + enet1: ethernet@e2000 {
2910 + };
2911 +
2912 + enet2: ethernet@e4000 {
2913 + };
2914 +
2915 + enet3: ethernet@e6000 {
2916 + };
2917 +
2918 + enet4: ethernet@e8000 {
2919 + };
2920 +
2921 + enet5: ethernet@ea000 {
2922 + };
2923 +
2924 + enet6: ethernet@f0000 {
2925 + };
2926 +
2927 + enet7: ethernet@f2000 {
2928 + };
2929 +};
2930 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
2931 new file mode 100644
2932 index 00000000..c375af47
2933 --- /dev/null
2934 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
2935 @@ -0,0 +1,109 @@
2936 +/*
2937 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
2938 + *
2939 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
2940 + *
2941 + * Mingkai Hu <Mingkai.hu@freescale.com>
2942 + *
2943 + * This file is dual-licensed: you can use it either under the terms
2944 + * of the GPLv2 or the X11 license, at your option. Note that this dual
2945 + * licensing only applies to this file, and not this project as a
2946 + * whole.
2947 + *
2948 + * a) This library is free software; you can redistribute it and/or
2949 + * modify it under the terms of the GNU General Public License as
2950 + * published by the Free Software Foundation; either version 2 of the
2951 + * License, or (at your option) any later version.
2952 + *
2953 + * This library is distributed in the hope that it will be useful,
2954 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2955 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2956 + * GNU General Public License for more details.
2957 + *
2958 + * Or, alternatively,
2959 + *
2960 + * b) Permission is hereby granted, free of charge, to any person
2961 + * obtaining a copy of this software and associated documentation
2962 + * files (the "Software"), to deal in the Software without
2963 + * restriction, including without limitation the rights to use,
2964 + * copy, modify, merge, publish, distribute, sublicense, and/or
2965 + * sell copies of the Software, and to permit persons to whom the
2966 + * Software is furnished to do so, subject to the following
2967 + * conditions:
2968 + *
2969 + * The above copyright notice and this permission notice shall be
2970 + * included in all copies or substantial portions of the Software.
2971 + *
2972 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
2973 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
2974 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
2975 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
2976 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
2977 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
2978 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
2979 + * OTHER DEALINGS IN THE SOFTWARE.
2980 + */
2981 +
2982 +#include "fsl-ls1046a-qds.dts"
2983 +
2984 +&bman_fbpr {
2985 + compatible = "fsl,bman-fbpr";
2986 + alloc-ranges = <0 0 0x10000 0>;
2987 +};
2988 +&qman_fqd {
2989 + compatible = "fsl,qman-fqd";
2990 + alloc-ranges = <0 0 0x10000 0>;
2991 +};
2992 +&qman_pfdr {
2993 + compatible = "fsl,qman-pfdr";
2994 + alloc-ranges = <0 0 0x10000 0>;
2995 +};
2996 +
2997 +&soc {
2998 +#include "qoriq-dpaa-eth.dtsi"
2999 +#include "qoriq-fman3-0-6oh.dtsi"
3000 +};
3001 +
3002 +&fsldpaa {
3003 + ethernet@9 {
3004 + compatible = "fsl,dpa-ethernet";
3005 + fsl,fman-mac = <&enet7>;
3006 + };
3007 +};
3008 +
3009 +&fman0 {
3010 + compatible = "fsl,fman", "simple-bus";
3011 +};
3012 +
3013 +&dspi {
3014 + bus-num = <0>;
3015 + status = "okay";
3016 +
3017 + flash@0 {
3018 + #address-cells = <1>;
3019 + #size-cells = <1>;
3020 + compatible = "n25q128a11", "jedec,spi-nor";
3021 + reg = <0>;
3022 + spi-max-frequency = <10000000>;
3023 + };
3024 +
3025 + flash@1 {
3026 + #address-cells = <1>;
3027 + #size-cells = <1>;
3028 + compatible = "sst25wf040b", "jedec,spi-nor";
3029 + spi-cpol;
3030 + spi-cpha;
3031 + reg = <1>;
3032 + spi-max-frequency = <10000000>;
3033 + };
3034 +
3035 + flash@2 {
3036 + #address-cells = <1>;
3037 + #size-cells = <1>;
3038 + compatible = "en25s64", "jedec,spi-nor";
3039 + spi-cpol;
3040 + spi-cpha;
3041 + reg = <2>;
3042 + spi-max-frequency = <10000000>;
3043 + };
3044 +};
3045 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3046 new file mode 100644
3047 index 00000000..3b8e9b7e
3048 --- /dev/null
3049 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
3050 @@ -0,0 +1,363 @@
3051 +/*
3052 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3053 + *
3054 + * Copyright 2016 Freescale Semiconductor, Inc.
3055 + *
3056 + * Shaohui Xie <Shaohui.Xie@nxp.com>
3057 + *
3058 + * This file is dual-licensed: you can use it either under the terms
3059 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3060 + * licensing only applies to this file, and not this project as a
3061 + * whole.
3062 + *
3063 + * a) This library is free software; you can redistribute it and/or
3064 + * modify it under the terms of the GNU General Public License as
3065 + * published by the Free Software Foundation; either version 2 of the
3066 + * License, or (at your option) any later version.
3067 + *
3068 + * This library is distributed in the hope that it will be useful,
3069 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3070 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3071 + * GNU General Public License for more details.
3072 + *
3073 + * Or, alternatively,
3074 + *
3075 + * b) Permission is hereby granted, free of charge, to any person
3076 + * obtaining a copy of this software and associated documentation
3077 + * files (the "Software"), to deal in the Software without
3078 + * restriction, including without limitation the rights to use,
3079 + * copy, modify, merge, publish, distribute, sublicense, and/or
3080 + * sell copies of the Software, and to permit persons to whom the
3081 + * Software is furnished to do so, subject to the following
3082 + * conditions:
3083 + *
3084 + * The above copyright notice and this permission notice shall be
3085 + * included in all copies or substantial portions of the Software.
3086 + *
3087 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3088 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3089 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3090 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3091 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3092 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3093 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3094 + * OTHER DEALINGS IN THE SOFTWARE.
3095 + */
3096 +
3097 +/dts-v1/;
3098 +
3099 +#include "fsl-ls1046a.dtsi"
3100 +
3101 +/ {
3102 + model = "LS1046A QDS Board";
3103 + compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
3104 +
3105 + aliases {
3106 + gpio0 = &gpio0;
3107 + gpio1 = &gpio1;
3108 + gpio2 = &gpio2;
3109 + gpio3 = &gpio3;
3110 + serial0 = &duart0;
3111 + serial1 = &duart1;
3112 + serial2 = &duart2;
3113 + serial3 = &duart3;
3114 +
3115 + emi1_slot1 = &ls1046mdio_s1;
3116 + emi1_slot2 = &ls1046mdio_s2;
3117 + emi1_slot4 = &ls1046mdio_s4;
3118 +
3119 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
3120 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
3121 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
3122 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
3123 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
3124 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
3125 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
3126 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
3127 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
3128 + };
3129 +
3130 + chosen {
3131 + stdout-path = "serial0:115200n8";
3132 + };
3133 +};
3134 +
3135 +&dspi {
3136 + bus-num = <0>;
3137 + status = "okay";
3138 +
3139 + flash@0 {
3140 + #address-cells = <1>;
3141 + #size-cells = <1>;
3142 + compatible = "n25q128a11", "jedec,spi-nor";
3143 + reg = <0>;
3144 + spi-max-frequency = <10000000>;
3145 + };
3146 +
3147 + flash@1 {
3148 + #address-cells = <1>;
3149 + #size-cells = <1>;
3150 + compatible = "sst25wf040b", "jedec,spi-nor";
3151 + spi-cpol;
3152 + spi-cpha;
3153 + reg = <1>;
3154 + spi-max-frequency = <10000000>;
3155 + };
3156 +
3157 + flash@2 {
3158 + #address-cells = <1>;
3159 + #size-cells = <1>;
3160 + compatible = "en25s64", "jedec,spi-nor";
3161 + spi-cpol;
3162 + spi-cpha;
3163 + reg = <2>;
3164 + spi-max-frequency = <10000000>;
3165 + };
3166 +};
3167 +
3168 +&duart0 {
3169 + status = "okay";
3170 +};
3171 +
3172 +&duart1 {
3173 + status = "okay";
3174 +};
3175 +
3176 +&i2c0 {
3177 + status = "okay";
3178 +
3179 + pca9547@77 {
3180 + compatible = "nxp,pca9547";
3181 + reg = <0x77>;
3182 + #address-cells = <1>;
3183 + #size-cells = <0>;
3184 +
3185 + i2c@2 {
3186 + #address-cells = <1>;
3187 + #size-cells = <0>;
3188 + reg = <0x2>;
3189 +
3190 + ina220@40 {
3191 + compatible = "ti,ina220";
3192 + reg = <0x40>;
3193 + shunt-resistor = <1000>;
3194 + };
3195 +
3196 + ina220@41 {
3197 + compatible = "ti,ina220";
3198 + reg = <0x41>;
3199 + shunt-resistor = <1000>;
3200 + };
3201 + };
3202 +
3203 + i2c@3 {
3204 + #address-cells = <1>;
3205 + #size-cells = <0>;
3206 + reg = <0x3>;
3207 +
3208 + rtc@51 {
3209 + compatible = "nxp,pcf2129";
3210 + reg = <0x51>;
3211 + /* IRQ10_B */
3212 + interrupts = <0 150 0x4>;
3213 + };
3214 +
3215 + eeprom@56 {
3216 + compatible = "atmel,24c512";
3217 + reg = <0x56>;
3218 + };
3219 +
3220 + eeprom@57 {
3221 + compatible = "atmel,24c512";
3222 + reg = <0x57>;
3223 + };
3224 +
3225 + temp-sensor@4c {
3226 + compatible = "adi,adt7461a";
3227 + reg = <0x4c>;
3228 + };
3229 + };
3230 + };
3231 +};
3232 +
3233 +&ifc {
3234 + #address-cells = <2>;
3235 + #size-cells = <1>;
3236 + /* NOR, NAND Flashes and FPGA on board */
3237 + ranges = <0x0 0x0 0x0 0x60000000 0x08000000
3238 + 0x1 0x0 0x0 0x7e800000 0x00010000
3239 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3240 + status = "okay";
3241 +
3242 + nor@0,0 {
3243 + compatible = "cfi-flash";
3244 + reg = <0x0 0x0 0x8000000>;
3245 + bank-width = <2>;
3246 + device-width = <1>;
3247 + };
3248 +
3249 + nand@1,0 {
3250 + compatible = "fsl,ifc-nand";
3251 + reg = <0x1 0x0 0x10000>;
3252 + };
3253 +
3254 + fpga: board-control@2,0 {
3255 + compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
3256 + reg = <0x2 0x0 0x0000100>;
3257 + ranges = <0 2 0 0x100>;
3258 + };
3259 +};
3260 +
3261 +&lpuart0 {
3262 + status = "okay";
3263 +};
3264 +
3265 +&qspi {
3266 + num-cs = <2>;
3267 + bus-num = <0>;
3268 + status = "okay";
3269 +
3270 + qflash0: s25fl128s@0 {
3271 + compatible = "spansion,m25p80";
3272 + #address-cells = <1>;
3273 + #size-cells = <1>;
3274 + spi-max-frequency = <20000000>;
3275 + reg = <0>;
3276 + };
3277 +};
3278 +
3279 +#include "fsl-ls1046-post.dtsi"
3280 +
3281 +&fman0 {
3282 + ethernet@e0000 {
3283 + phy-handle = <&qsgmii_phy_s2_p1>;
3284 + phy-connection-type = "sgmii";
3285 + };
3286 +
3287 + ethernet@e2000 {
3288 + phy-handle = <&sgmii_phy_s4_p1>;
3289 + phy-connection-type = "sgmii";
3290 + };
3291 +
3292 + ethernet@e4000 {
3293 + phy-handle = <&rgmii_phy1>;
3294 + phy-connection-type = "rgmii";
3295 + };
3296 +
3297 + ethernet@e6000 {
3298 + phy-handle = <&rgmii_phy2>;
3299 + phy-connection-type = "rgmii";
3300 + };
3301 +
3302 + ethernet@e8000 {
3303 + phy-handle = <&sgmii_phy_s1_p3>;
3304 + phy-connection-type = "sgmii";
3305 + };
3306 +
3307 + ethernet@ea000 {
3308 + phy-handle = <&sgmii_phy_s1_p4>;
3309 + phy-connection-type = "sgmii";
3310 + };
3311 +
3312 + ethernet@f0000 { /* DTSEC9/10GEC1 */
3313 + phy-handle = <&sgmii_phy_s1_p1>;
3314 + phy-connection-type = "xgmii";
3315 + };
3316 +
3317 + ethernet@f2000 { /* DTSEC10/10GEC2 */
3318 + phy-handle = <&sgmii_phy_s1_p2>;
3319 + phy-connection-type = "xgmii";
3320 + };
3321 +};
3322 +
3323 +&fpga {
3324 + #address-cells = <1>;
3325 + #size-cells = <1>;
3326 + mdio-mux-emi1 {
3327 + compatible = "mdio-mux-mmioreg", "mdio-mux";
3328 + mdio-parent-bus = <&mdio0>;
3329 + #address-cells = <1>;
3330 + #size-cells = <0>;
3331 + reg = <0x54 1>; /* BRDCFG4 */
3332 + mux-mask = <0xe0>; /* EMI1 */
3333 +
3334 + /* On-board RGMII1 PHY */
3335 + ls1046mdio0: mdio@0 {
3336 + reg = <0>;
3337 + #address-cells = <1>;
3338 + #size-cells = <0>;
3339 +
3340 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
3341 + reg = <0x1>;
3342 + };
3343 + };
3344 +
3345 + /* On-board RGMII2 PHY */
3346 + ls1046mdio1: mdio@1 {
3347 + reg = <0x20>;
3348 + #address-cells = <1>;
3349 + #size-cells = <0>;
3350 +
3351 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
3352 + reg = <0x2>;
3353 + };
3354 + };
3355 +
3356 + /* Slot 1 */
3357 + ls1046mdio_s1: mdio@2 {
3358 + reg = <0x40>;
3359 + #address-cells = <1>;
3360 + #size-cells = <0>;
3361 + status = "disabled";
3362 +
3363 + sgmii_phy_s1_p1: ethernet-phy@1c {
3364 + reg = <0x1c>;
3365 + };
3366 +
3367 + sgmii_phy_s1_p2: ethernet-phy@1d {
3368 + reg = <0x1d>;
3369 + };
3370 +
3371 + sgmii_phy_s1_p3: ethernet-phy@1e {
3372 + reg = <0x1e>;
3373 + };
3374 +
3375 + sgmii_phy_s1_p4: ethernet-phy@1f {
3376 + reg = <0x1f>;
3377 + };
3378 + };
3379 +
3380 + /* Slot 2 */
3381 + ls1046mdio_s2: mdio@3 {
3382 + reg = <0x60>;
3383 + #address-cells = <1>;
3384 + #size-cells = <0>;
3385 + status = "disabled";
3386 +
3387 + qsgmii_phy_s2_p1: ethernet-phy@8 {
3388 + reg = <0x8>;
3389 + };
3390 + qsgmii_phy_s2_p2: ethernet-phy@9 {
3391 + reg = <0x9>;
3392 + };
3393 + qsgmii_phy_s2_p3: ethernet-phy@a {
3394 + reg = <0xa>;
3395 + };
3396 + qsgmii_phy_s2_p4: ethernet-phy@b {
3397 + reg = <0xb>;
3398 + };
3399 + };
3400 +
3401 + /* Slot 4 */
3402 + ls1046mdio_s4: mdio@5 {
3403 + reg = <0x80>;
3404 + #address-cells = <1>;
3405 + #size-cells = <0>;
3406 + status = "disabled";
3407 +
3408 + sgmii_phy_s4_p1: ethernet-phy@1c {
3409 + reg = <0x1c>;
3410 + };
3411 + };
3412 + };
3413 +};
3414 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3415 new file mode 100644
3416 index 00000000..bfe2f36c
3417 --- /dev/null
3418 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
3419 @@ -0,0 +1,76 @@
3420 +/*
3421 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3422 + *
3423 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
3424 + *
3425 + * Mingkai Hu <Mingkai.hu@freescale.com>
3426 + *
3427 + * This file is dual-licensed: you can use it either under the terms
3428 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3429 + * licensing only applies to this file, and not this project as a
3430 + * whole.
3431 + *
3432 + * a) This library is free software; you can redistribute it and/or
3433 + * modify it under the terms of the GNU General Public License as
3434 + * published by the Free Software Foundation; either version 2 of the
3435 + * License, or (at your option) any later version.
3436 + *
3437 + * This library is distributed in the hope that it will be useful,
3438 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3439 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3440 + * GNU General Public License for more details.
3441 + *
3442 + * Or, alternatively,
3443 + *
3444 + * b) Permission is hereby granted, free of charge, to any person
3445 + * obtaining a copy of this software and associated documentation
3446 + * files (the "Software"), to deal in the Software without
3447 + * restriction, including without limitation the rights to use,
3448 + * copy, modify, merge, publish, distribute, sublicense, and/or
3449 + * sell copies of the Software, and to permit persons to whom the
3450 + * Software is furnished to do so, subject to the following
3451 + * conditions:
3452 + *
3453 + * The above copyright notice and this permission notice shall be
3454 + * included in all copies or substantial portions of the Software.
3455 + *
3456 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3457 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3458 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3459 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3460 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3461 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3462 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3463 + * OTHER DEALINGS IN THE SOFTWARE.
3464 + */
3465 +
3466 +#include "fsl-ls1046a-rdb.dts"
3467 +
3468 +&bman_fbpr {
3469 + compatible = "fsl,bman-fbpr";
3470 + alloc-ranges = <0 0 0x10000 0>;
3471 +};
3472 +&qman_fqd {
3473 + compatible = "fsl,qman-fqd";
3474 + alloc-ranges = <0 0 0x10000 0>;
3475 +};
3476 +&qman_pfdr {
3477 + compatible = "fsl,qman-pfdr";
3478 + alloc-ranges = <0 0 0x10000 0>;
3479 +};
3480 +
3481 +&soc {
3482 +#include "qoriq-dpaa-eth.dtsi"
3483 +#include "qoriq-fman3-0-6oh.dtsi"
3484 +};
3485 +
3486 +&fsldpaa {
3487 + ethernet@9 {
3488 + compatible = "fsl,dpa-ethernet";
3489 + fsl,fman-mac = <&enet7>;
3490 + };
3491 +};
3492 +
3493 +&fman0 {
3494 + compatible = "fsl,fman", "simple-bus";
3495 +};
3496 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3497 new file mode 100644
3498 index 00000000..54336aa6
3499 --- /dev/null
3500 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
3501 @@ -0,0 +1,110 @@
3502 +/*
3503 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3504 + *
3505 + * Copyright 2016 Freescale Semiconductor, Inc.
3506 + *
3507 + * This file is licensed under the terms of the GNU General Public
3508 + * License version 2. This program is licensed "as is" without any
3509 + * warranty of any kind, whether express or implied.
3510 + */
3511 +
3512 +#include "fsl-ls1046a-rdb-sdk.dts"
3513 +
3514 +&soc {
3515 + bp7: buffer-pool@7 {
3516 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3517 + fsl,bpid = <7>;
3518 + fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
3519 + fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
3520 + };
3521 +
3522 + bp8: buffer-pool@8 {
3523 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3524 + fsl,bpid = <8>;
3525 + fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
3526 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3527 + };
3528 +
3529 + bp9: buffer-pool@9 {
3530 + compatible = "fsl,ls1046a-bpool", "fsl,bpool";
3531 + fsl,bpid = <9>;
3532 + fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
3533 + fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
3534 + };
3535 +
3536 + fsl,dpaa {
3537 + compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
3538 +
3539 + ethernet@2 {
3540 + compatible = "fsl,dpa-ethernet-init";
3541 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3542 + fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
3543 + fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
3544 + };
3545 +
3546 + ethernet@3 {
3547 + compatible = "fsl,dpa-ethernet-init";
3548 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3549 + fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
3550 + fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
3551 + };
3552 +
3553 + ethernet@4 {
3554 + compatible = "fsl,dpa-ethernet-init";
3555 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3556 + fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
3557 + fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
3558 + };
3559 +
3560 + ethernet@5 {
3561 + compatible = "fsl,dpa-ethernet-init";
3562 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3563 + fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
3564 + fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
3565 + };
3566 +
3567 + ethernet@8 {
3568 + compatible = "fsl,dpa-ethernet-init";
3569 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3570 + fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
3571 + fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
3572 + };
3573 +
3574 + ethernet@9 {
3575 + compatible = "fsl,dpa-ethernet-init";
3576 + fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
3577 + fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
3578 + fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
3579 + };
3580 +
3581 + dpa-fman0-oh@2 {
3582 + compatible = "fsl,dpa-oh";
3583 + /* Define frame queues for the OH port*/
3584 + /* <OH Rx error, OH Rx default> */
3585 + fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
3586 + fsl,fman-oh-port = <&fman0_oh2>;
3587 + };
3588 + };
3589 +};
3590 +/ {
3591 + reserved-memory {
3592 + #address-cells = <2>;
3593 + #size-cells = <2>;
3594 + ranges;
3595 +
3596 + usdpaa_mem: usdpaa_mem {
3597 + compatible = "fsl,usdpaa-mem";
3598 + alloc-ranges = <0 0 0x10000 0>;
3599 + size = <0 0x10000000>;
3600 + alignment = <0 0x10000000>;
3601 + };
3602 + };
3603 +};
3604 +
3605 +&fman0 {
3606 + fman0_oh2: port@83000 {
3607 + cell-index = <1>;
3608 + compatible = "fsl,fman-port-oh";
3609 + reg = <0x83000 0x1000>;
3610 + };
3611 +};
3612 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3613 new file mode 100644
3614 index 00000000..be9b62ca
3615 --- /dev/null
3616 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
3617 @@ -0,0 +1,218 @@
3618 +/*
3619 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3620 + *
3621 + * Copyright 2016 Freescale Semiconductor, Inc.
3622 + *
3623 + * Mingkai Hu <mingkai.hu@nxp.com>
3624 + *
3625 + * This file is dual-licensed: you can use it either under the terms
3626 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3627 + * licensing only applies to this file, and not this project as a
3628 + * whole.
3629 + *
3630 + * a) This library is free software; you can redistribute it and/or
3631 + * modify it under the terms of the GNU General Public License as
3632 + * published by the Free Software Foundation; either version 2 of the
3633 + * License, or (at your option) any later version.
3634 + *
3635 + * This library is distributed in the hope that it will be useful,
3636 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3637 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3638 + * GNU General Public License for more details.
3639 + *
3640 + * Or, alternatively,
3641 + *
3642 + * b) Permission is hereby granted, free of charge, to any person
3643 + * obtaining a copy of this software and associated documentation
3644 + * files (the "Software"), to deal in the Software without
3645 + * restriction, including without limitation the rights to use,
3646 + * copy, modify, merge, publish, distribute, sublicense, and/or
3647 + * sell copies of the Software, and to permit persons to whom the
3648 + * Software is furnished to do so, subject to the following
3649 + * conditions:
3650 + *
3651 + * The above copyright notice and this permission notice shall be
3652 + * included in all copies or substantial portions of the Software.
3653 + *
3654 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3655 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3656 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3657 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3658 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3659 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3660 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3661 + * OTHER DEALINGS IN THE SOFTWARE.
3662 + */
3663 +
3664 +/dts-v1/;
3665 +
3666 +#include "fsl-ls1046a.dtsi"
3667 +
3668 +/ {
3669 + model = "LS1046A RDB Board";
3670 + compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
3671 +
3672 + aliases {
3673 + serial0 = &duart0;
3674 + serial1 = &duart1;
3675 + serial2 = &duart2;
3676 + serial3 = &duart3;
3677 + };
3678 +
3679 + chosen {
3680 + stdout-path = "serial0:115200n8";
3681 + };
3682 +};
3683 +
3684 +&esdhc {
3685 + mmc-hs200-1_8v;
3686 + sd-uhs-sdr104;
3687 + sd-uhs-sdr50;
3688 + sd-uhs-sdr25;
3689 + sd-uhs-sdr12;
3690 +};
3691 +
3692 +&duart0 {
3693 + status = "okay";
3694 +};
3695 +
3696 +&duart1 {
3697 + status = "okay";
3698 +};
3699 +
3700 +&i2c0 {
3701 + status = "okay";
3702 +
3703 + ina220@40 {
3704 + compatible = "ti,ina220";
3705 + reg = <0x40>;
3706 + shunt-resistor = <1000>;
3707 + };
3708 +
3709 + temp-sensor@4c {
3710 + compatible = "adi,adt7461";
3711 + reg = <0x4c>;
3712 + };
3713 +
3714 + eeprom@56 {
3715 + compatible = "atmel,24c512";
3716 + reg = <0x52>;
3717 + };
3718 +
3719 + eeprom@57 {
3720 + compatible = "atmel,24c512";
3721 + reg = <0x53>;
3722 + };
3723 +};
3724 +
3725 +&i2c3 {
3726 + status = "okay";
3727 +
3728 + rtc@51 {
3729 + compatible = "nxp,pcf2129";
3730 + reg = <0x51>;
3731 + };
3732 +};
3733 +
3734 +&ifc {
3735 + #address-cells = <2>;
3736 + #size-cells = <1>;
3737 + /* NAND Flashe and CPLD on board */
3738 + ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
3739 + 0x2 0x0 0x0 0x7fb00000 0x00000100>;
3740 + status = "okay";
3741 +
3742 + nand@0,0 {
3743 + compatible = "fsl,ifc-nand";
3744 + #address-cells = <1>;
3745 + #size-cells = <1>;
3746 + reg = <0x0 0x0 0x10000>;
3747 + };
3748 +
3749 + cpld: board-control@2,0 {
3750 + compatible = "fsl,ls1046ardb-cpld";
3751 + reg = <0x2 0x0 0x0000100>;
3752 + };
3753 +};
3754 +
3755 +&qspi {
3756 + num-cs = <2>;
3757 + bus-num = <0>;
3758 + status = "okay";
3759 +
3760 + qflash0: s25fs512s@0 {
3761 + compatible = "spansion,m25p80";
3762 + #address-cells = <1>;
3763 + #size-cells = <1>;
3764 + spi-max-frequency = <20000000>;
3765 + reg = <0>;
3766 + };
3767 +
3768 + qflash1: s25fs512s@1 {
3769 + compatible = "spansion,m25p80";
3770 + #address-cells = <1>;
3771 + #size-cells = <1>;
3772 + spi-max-frequency = <20000000>;
3773 + reg = <1>;
3774 + };
3775 +};
3776 +
3777 +#include "fsl-ls1046-post.dtsi"
3778 +
3779 +&fman0 {
3780 + ethernet@e4000 {
3781 + phy-handle = <&rgmii_phy1>;
3782 + phy-connection-type = "rgmii";
3783 + };
3784 +
3785 + ethernet@e6000 {
3786 + phy-handle = <&rgmii_phy2>;
3787 + phy-connection-type = "rgmii";
3788 + };
3789 +
3790 + ethernet@e8000 {
3791 + phy-handle = <&sgmii_phy1>;
3792 + phy-connection-type = "sgmii";
3793 + };
3794 +
3795 + ethernet@ea000 {
3796 + phy-handle = <&sgmii_phy2>;
3797 + phy-connection-type = "sgmii";
3798 + };
3799 +
3800 + ethernet@f0000 { /* 10GEC1 */
3801 + phy-handle = <&aqr106_phy>;
3802 + phy-connection-type = "xgmii";
3803 + };
3804 +
3805 + ethernet@f2000 { /* 10GEC2 */
3806 + fixed-link = <0 1 1000 0 0>;
3807 + phy-connection-type = "xgmii";
3808 + };
3809 +
3810 + mdio@fc000 {
3811 + rgmii_phy1: ethernet-phy@1 {
3812 + reg = <0x1>;
3813 + };
3814 +
3815 + rgmii_phy2: ethernet-phy@2 {
3816 + reg = <0x2>;
3817 + };
3818 +
3819 + sgmii_phy1: ethernet-phy@3 {
3820 + reg = <0x3>;
3821 + };
3822 +
3823 + sgmii_phy2: ethernet-phy@4 {
3824 + reg = <0x4>;
3825 + };
3826 + };
3827 +
3828 + mdio@fd000 {
3829 + aqr106_phy: ethernet-phy@0 {
3830 + compatible = "ethernet-phy-ieee802.3-c45";
3831 + interrupts = <0 131 4>;
3832 + reg = <0x0>;
3833 + };
3834 + };
3835 +};
3836 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
3837 new file mode 100644
3838 index 00000000..6b87266f
3839 --- /dev/null
3840 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
3841 @@ -0,0 +1,793 @@
3842 +/*
3843 + * Device Tree Include file for Freescale Layerscape-1046A family SoC.
3844 + *
3845 + * Copyright 2016 Freescale Semiconductor, Inc.
3846 + *
3847 + * Mingkai Hu <mingkai.hu@nxp.com>
3848 + *
3849 + * This file is dual-licensed: you can use it either under the terms
3850 + * of the GPLv2 or the X11 license, at your option. Note that this dual
3851 + * licensing only applies to this file, and not this project as a
3852 + * whole.
3853 + *
3854 + * a) This library is free software; you can redistribute it and/or
3855 + * modify it under the terms of the GNU General Public License as
3856 + * published by the Free Software Foundation; either version 2 of the
3857 + * License, or (at your option) any later version.
3858 + *
3859 + * This library is distributed in the hope that it will be useful,
3860 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3861 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3862 + * GNU General Public License for more details.
3863 + *
3864 + * Or, alternatively,
3865 + *
3866 + * b) Permission is hereby granted, free of charge, to any person
3867 + * obtaining a copy of this software and associated documentation
3868 + * files (the "Software"), to deal in the Software without
3869 + * restriction, including without limitation the rights to use,
3870 + * copy, modify, merge, publish, distribute, sublicense, and/or
3871 + * sell copies of the Software, and to permit persons to whom the
3872 + * Software is furnished to do so, subject to the following
3873 + * conditions:
3874 + *
3875 + * The above copyright notice and this permission notice shall be
3876 + * included in all copies or substantial portions of the Software.
3877 + *
3878 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
3879 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
3880 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
3881 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
3882 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
3883 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
3884 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
3885 + * OTHER DEALINGS IN THE SOFTWARE.
3886 + */
3887 +
3888 +#include <dt-bindings/interrupt-controller/arm-gic.h>
3889 +#include <dt-bindings/thermal/thermal.h>
3890 +
3891 +/ {
3892 + compatible = "fsl,ls1046a";
3893 + interrupt-parent = <&gic>;
3894 + #address-cells = <2>;
3895 + #size-cells = <2>;
3896 +
3897 + aliases {
3898 + crypto = &crypto;
3899 + fman0 = &fman0;
3900 + ethernet0 = &enet0;
3901 + ethernet1 = &enet1;
3902 + ethernet2 = &enet2;
3903 + ethernet3 = &enet3;
3904 + ethernet4 = &enet4;
3905 + ethernet5 = &enet5;
3906 + ethernet6 = &enet6;
3907 + ethernet7 = &enet7;
3908 + };
3909 +
3910 + cpus {
3911 + #address-cells = <1>;
3912 + #size-cells = <0>;
3913 +
3914 + cpu0: cpu@0 {
3915 + device_type = "cpu";
3916 + compatible = "arm,cortex-a72";
3917 + reg = <0x0>;
3918 + clocks = <&clockgen 1 0>;
3919 + next-level-cache = <&l2>;
3920 + cpu-idle-states = <&CPU_PH20>;
3921 + #cooling-cells = <2>;
3922 + };
3923 +
3924 + cpu1: cpu@1 {
3925 + device_type = "cpu";
3926 + compatible = "arm,cortex-a72";
3927 + reg = <0x1>;
3928 + clocks = <&clockgen 1 0>;
3929 + next-level-cache = <&l2>;
3930 + cpu-idle-states = <&CPU_PH20>;
3931 + };
3932 +
3933 + cpu2: cpu@2 {
3934 + device_type = "cpu";
3935 + compatible = "arm,cortex-a72";
3936 + reg = <0x2>;
3937 + clocks = <&clockgen 1 0>;
3938 + next-level-cache = <&l2>;
3939 + cpu-idle-states = <&CPU_PH20>;
3940 + };
3941 +
3942 + cpu3: cpu@3 {
3943 + device_type = "cpu";
3944 + compatible = "arm,cortex-a72";
3945 + reg = <0x3>;
3946 + clocks = <&clockgen 1 0>;
3947 + next-level-cache = <&l2>;
3948 + cpu-idle-states = <&CPU_PH20>;
3949 + };
3950 +
3951 + l2: l2-cache {
3952 + compatible = "cache";
3953 + };
3954 + };
3955 +
3956 + idle-states {
3957 + /*
3958 + * PSCI node is not added default, U-boot will add missing
3959 + * parts if it determines to use PSCI.
3960 + */
3961 + entry-method = "arm,psci";
3962 +
3963 + CPU_PH20: cpu-ph20 {
3964 + compatible = "arm,idle-state";
3965 + idle-state-name = "PH20";
3966 + arm,psci-suspend-param = <0x0>;
3967 + entry-latency-us = <1000>;
3968 + exit-latency-us = <1000>;
3969 + min-residency-us = <3000>;
3970 + };
3971 + };
3972 +
3973 + memory@80000000 {
3974 + device_type = "memory";
3975 + };
3976 +
3977 + sysclk: sysclk {
3978 + compatible = "fixed-clock";
3979 + #clock-cells = <0>;
3980 + clock-frequency = <100000000>;
3981 + clock-output-names = "sysclk";
3982 + };
3983 +
3984 + reboot {
3985 + compatible ="syscon-reboot";
3986 + regmap = <&dcfg>;
3987 + offset = <0xb0>;
3988 + mask = <0x02>;
3989 + };
3990 +
3991 + timer {
3992 + compatible = "arm,armv8-timer";
3993 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
3994 + IRQ_TYPE_LEVEL_LOW)>,
3995 + <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
3996 + IRQ_TYPE_LEVEL_LOW)>,
3997 + <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
3998 + IRQ_TYPE_LEVEL_LOW)>,
3999 + <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
4000 + IRQ_TYPE_LEVEL_LOW)>;
4001 + };
4002 +
4003 + pmu {
4004 + compatible = "arm,cortex-a72-pmu";
4005 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
4006 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
4007 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
4008 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
4009 + interrupt-affinity = <&cpu0>,
4010 + <&cpu1>,
4011 + <&cpu2>,
4012 + <&cpu3>;
4013 + };
4014 +
4015 + gic: interrupt-controller@1400000 {
4016 + compatible = "arm,gic-400";
4017 + #interrupt-cells = <3>;
4018 + interrupt-controller;
4019 + reg = <0x0 0x1410000 0 0x10000>, /* GICD */
4020 + <0x0 0x1420000 0 0x20000>, /* GICC */
4021 + <0x0 0x1440000 0 0x20000>, /* GICH */
4022 + <0x0 0x1460000 0 0x20000>; /* GICV */
4023 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
4024 + IRQ_TYPE_LEVEL_LOW)>;
4025 + };
4026 +
4027 + soc: soc {
4028 + compatible = "simple-bus";
4029 + #address-cells = <2>;
4030 + #size-cells = <2>;
4031 + ranges;
4032 +
4033 + ddr: memory-controller@1080000 {
4034 + compatible = "fsl,qoriq-memory-controller";
4035 + reg = <0x0 0x1080000 0x0 0x1000>;
4036 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
4037 + big-endian;
4038 + };
4039 +
4040 + ifc: ifc@1530000 {
4041 + compatible = "fsl,ifc", "simple-bus";
4042 + reg = <0x0 0x1530000 0x0 0x10000>;
4043 + big-endian;
4044 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
4045 + };
4046 +
4047 + qspi: quadspi@1550000 {
4048 + compatible = "fsl,ls1021a-qspi";
4049 + #address-cells = <1>;
4050 + #size-cells = <0>;
4051 + reg = <0x0 0x1550000 0x0 0x10000>,
4052 + <0x0 0x40000000 0x0 0x10000000>;
4053 + reg-names = "QuadSPI", "QuadSPI-memory";
4054 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
4055 + clock-names = "qspi_en", "qspi";
4056 + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
4057 + big-endian;
4058 + fsl,qspi-has-second-chip;
4059 + status = "disabled";
4060 + };
4061 +
4062 + esdhc: esdhc@1560000 {
4063 + compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
4064 + reg = <0x0 0x1560000 0x0 0x10000>;
4065 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
4066 + clocks = <&clockgen 2 1>;
4067 + voltage-ranges = <1800 1800 3300 3300>;
4068 + sdhci,auto-cmd12;
4069 + big-endian;
4070 + bus-width = <4>;
4071 + };
4072 +
4073 + scfg: scfg@1570000 {
4074 + compatible = "fsl,ls1046a-scfg", "syscon";
4075 + reg = <0x0 0x1570000 0x0 0x10000>;
4076 + big-endian;
4077 + };
4078 +
4079 + crypto: crypto@1700000 {
4080 + compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
4081 + "fsl,sec-v4.0";
4082 + fsl,sec-era = <8>;
4083 + #address-cells = <1>;
4084 + #size-cells = <1>;
4085 + ranges = <0x0 0x00 0x1700000 0x100000>;
4086 + reg = <0x00 0x1700000 0x0 0x100000>;
4087 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4088 +
4089 + sec_jr0: jr@10000 {
4090 + compatible = "fsl,sec-v5.4-job-ring",
4091 + "fsl,sec-v5.0-job-ring",
4092 + "fsl,sec-v4.0-job-ring";
4093 + reg = <0x10000 0x10000>;
4094 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
4095 + };
4096 +
4097 + sec_jr1: jr@20000 {
4098 + compatible = "fsl,sec-v5.4-job-ring",
4099 + "fsl,sec-v5.0-job-ring",
4100 + "fsl,sec-v4.0-job-ring";
4101 + reg = <0x20000 0x10000>;
4102 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
4103 + };
4104 +
4105 + sec_jr2: jr@30000 {
4106 + compatible = "fsl,sec-v5.4-job-ring",
4107 + "fsl,sec-v5.0-job-ring",
4108 + "fsl,sec-v4.0-job-ring";
4109 + reg = <0x30000 0x10000>;
4110 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
4111 + };
4112 +
4113 + sec_jr3: jr@40000 {
4114 + compatible = "fsl,sec-v5.4-job-ring",
4115 + "fsl,sec-v5.0-job-ring",
4116 + "fsl,sec-v4.0-job-ring";
4117 + reg = <0x40000 0x10000>;
4118 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
4119 + };
4120 + };
4121 +
4122 + qman: qman@1880000 {
4123 + compatible = "fsl,qman";
4124 + reg = <0x00 0x1880000 0x0 0x10000>;
4125 + interrupts = <0 45 0x4>;
4126 + memory-region = <&qman_fqd &qman_pfdr>;
4127 +
4128 + };
4129 +
4130 + bman: bman@1890000 {
4131 + compatible = "fsl,bman";
4132 + reg = <0x00 0x1890000 0x0 0x10000>;
4133 + interrupts = <0 45 0x4>;
4134 + memory-region = <&bman_fbpr>;
4135 +
4136 + };
4137 +
4138 + qportals: qman-portals@500000000 {
4139 + ranges = <0x0 0x5 0x00000000 0x8000000>;
4140 + };
4141 +
4142 + bportals: bman-portals@508000000 {
4143 + ranges = <0x0 0x5 0x08000000 0x8000000>;
4144 + };
4145 +
4146 + dcfg: dcfg@1ee0000 {
4147 + compatible = "fsl,ls1046a-dcfg", "syscon";
4148 + reg = <0x0 0x1ee0000 0x0 0x1000>;
4149 + big-endian;
4150 + };
4151 +
4152 + clockgen: clocking@1ee1000 {
4153 + compatible = "fsl,ls1046a-clockgen";
4154 + reg = <0x0 0x1ee1000 0x0 0x1000>;
4155 + #clock-cells = <2>;
4156 + clocks = <&sysclk>;
4157 + };
4158 +
4159 + tmu: tmu@1f00000 {
4160 + compatible = "fsl,qoriq-tmu";
4161 + reg = <0x0 0x1f00000 0x0 0x10000>;
4162 + interrupts = <0 33 0x4>;
4163 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
4164 + fsl,tmu-calibration =
4165 + /* Calibration data group 1 */
4166 + <0x00000000 0x00000026
4167 + 0x00000001 0x0000002d
4168 + 0x00000002 0x00000032
4169 + 0x00000003 0x00000039
4170 + 0x00000004 0x0000003f
4171 + 0x00000005 0x00000046
4172 + 0x00000006 0x0000004d
4173 + 0x00000007 0x00000054
4174 + 0x00000008 0x0000005a
4175 + 0x00000009 0x00000061
4176 + 0x0000000a 0x0000006a
4177 + 0x0000000b 0x00000071
4178 + /* Calibration data group 2 */
4179 + 0x00010000 0x00000025
4180 + 0x00010001 0x0000002c
4181 + 0x00010002 0x00000035
4182 + 0x00010003 0x0000003d
4183 + 0x00010004 0x00000045
4184 + 0x00010005 0x0000004e
4185 + 0x00010006 0x00000057
4186 + 0x00010007 0x00000061
4187 + 0x00010008 0x0000006b
4188 + 0x00010009 0x00000076
4189 + /* Calibration data group 3 */
4190 + 0x00020000 0x00000029
4191 + 0x00020001 0x00000033
4192 + 0x00020002 0x0000003d
4193 + 0x00020003 0x00000049
4194 + 0x00020004 0x00000056
4195 + 0x00020005 0x00000061
4196 + 0x00020006 0x0000006d
4197 + /* Calibration data group 4 */
4198 + 0x00030000 0x00000021
4199 + 0x00030001 0x0000002a
4200 + 0x00030002 0x0000003c
4201 + 0x00030003 0x0000004e>;
4202 + big-endian;
4203 + #thermal-sensor-cells = <1>;
4204 + };
4205 +
4206 + thermal-zones {
4207 + cpu_thermal: cpu-thermal {
4208 + polling-delay-passive = <1000>;
4209 + polling-delay = <5000>;
4210 + thermal-sensors = <&tmu 3>;
4211 +
4212 + trips {
4213 + cpu_alert: cpu-alert {
4214 + temperature = <85000>;
4215 + hysteresis = <2000>;
4216 + type = "passive";
4217 + };
4218 +
4219 + cpu_crit: cpu-crit {
4220 + temperature = <95000>;
4221 + hysteresis = <2000>;
4222 + type = "critical";
4223 + };
4224 + };
4225 +
4226 + cooling-maps {
4227 + map0 {
4228 + trip = <&cpu_alert>;
4229 + cooling-device =
4230 + <&cpu0 THERMAL_NO_LIMIT
4231 + THERMAL_NO_LIMIT>;
4232 + };
4233 + };
4234 + };
4235 + };
4236 +
4237 + dspi: dspi@2100000 {
4238 + compatible = "fsl,ls1021a-v1.0-dspi";
4239 + #address-cells = <1>;
4240 + #size-cells = <0>;
4241 + reg = <0x0 0x2100000 0x0 0x10000>;
4242 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
4243 + clock-names = "dspi";
4244 + clocks = <&clockgen 4 1>;
4245 + spi-num-chipselects = <5>;
4246 + big-endian;
4247 + status = "disabled";
4248 + };
4249 +
4250 + i2c0: i2c@2180000 {
4251 + compatible = "fsl,vf610-i2c";
4252 + #address-cells = <1>;
4253 + #size-cells = <0>;
4254 + reg = <0x0 0x2180000 0x0 0x10000>;
4255 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
4256 + clocks = <&clockgen 4 1>;
4257 + dmas = <&edma0 1 39>,
4258 + <&edma0 1 38>;
4259 + dma-names = "tx", "rx";
4260 + status = "disabled";
4261 + };
4262 +
4263 + i2c1: i2c@2190000 {
4264 + compatible = "fsl,vf610-i2c";
4265 + #address-cells = <1>;
4266 + #size-cells = <0>;
4267 + reg = <0x0 0x2190000 0x0 0x10000>;
4268 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
4269 + clocks = <&clockgen 4 1>;
4270 + status = "disabled";
4271 + };
4272 +
4273 + i2c2: i2c@21a0000 {
4274 + compatible = "fsl,vf610-i2c";
4275 + #address-cells = <1>;
4276 + #size-cells = <0>;
4277 + reg = <0x0 0x21a0000 0x0 0x10000>;
4278 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
4279 + clocks = <&clockgen 4 1>;
4280 + status = "disabled";
4281 + };
4282 +
4283 + i2c3: i2c@21b0000 {
4284 + compatible = "fsl,vf610-i2c";
4285 + #address-cells = <1>;
4286 + #size-cells = <0>;
4287 + reg = <0x0 0x21b0000 0x0 0x10000>;
4288 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
4289 + clocks = <&clockgen 4 1>;
4290 + status = "disabled";
4291 + };
4292 +
4293 + duart0: serial@21c0500 {
4294 + compatible = "fsl,ns16550", "ns16550a";
4295 + reg = <0x00 0x21c0500 0x0 0x100>;
4296 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4297 + clocks = <&clockgen 4 1>;
4298 + };
4299 +
4300 + duart1: serial@21c0600 {
4301 + compatible = "fsl,ns16550", "ns16550a";
4302 + reg = <0x00 0x21c0600 0x0 0x100>;
4303 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
4304 + clocks = <&clockgen 4 1>;
4305 + };
4306 +
4307 + duart2: serial@21d0500 {
4308 + compatible = "fsl,ns16550", "ns16550a";
4309 + reg = <0x0 0x21d0500 0x0 0x100>;
4310 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4311 + clocks = <&clockgen 4 1>;
4312 + };
4313 +
4314 + duart3: serial@21d0600 {
4315 + compatible = "fsl,ns16550", "ns16550a";
4316 + reg = <0x0 0x21d0600 0x0 0x100>;
4317 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
4318 + clocks = <&clockgen 4 1>;
4319 + };
4320 +
4321 + gpio0: gpio@2300000 {
4322 + compatible = "fsl,qoriq-gpio";
4323 + reg = <0x0 0x2300000 0x0 0x10000>;
4324 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
4325 + gpio-controller;
4326 + #gpio-cells = <2>;
4327 + interrupt-controller;
4328 + #interrupt-cells = <2>;
4329 + };
4330 +
4331 + gpio1: gpio@2310000 {
4332 + compatible = "fsl,qoriq-gpio";
4333 + reg = <0x0 0x2310000 0x0 0x10000>;
4334 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
4335 + gpio-controller;
4336 + #gpio-cells = <2>;
4337 + interrupt-controller;
4338 + #interrupt-cells = <2>;
4339 + };
4340 +
4341 + gpio2: gpio@2320000 {
4342 + compatible = "fsl,qoriq-gpio";
4343 + reg = <0x0 0x2320000 0x0 0x10000>;
4344 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
4345 + gpio-controller;
4346 + #gpio-cells = <2>;
4347 + interrupt-controller;
4348 + #interrupt-cells = <2>;
4349 + };
4350 +
4351 + gpio3: gpio@2330000 {
4352 + compatible = "fsl,qoriq-gpio";
4353 + reg = <0x0 0x2330000 0x0 0x10000>;
4354 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
4355 + gpio-controller;
4356 + #gpio-cells = <2>;
4357 + interrupt-controller;
4358 + #interrupt-cells = <2>;
4359 + };
4360 +
4361 + lpuart0: serial@2950000 {
4362 + compatible = "fsl,ls1021a-lpuart";
4363 + reg = <0x0 0x2950000 0x0 0x1000>;
4364 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
4365 + clocks = <&clockgen 4 0>;
4366 + clock-names = "ipg";
4367 + status = "disabled";
4368 + };
4369 +
4370 + lpuart1: serial@2960000 {
4371 + compatible = "fsl,ls1021a-lpuart";
4372 + reg = <0x0 0x2960000 0x0 0x1000>;
4373 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
4374 + clocks = <&clockgen 4 1>;
4375 + clock-names = "ipg";
4376 + status = "disabled";
4377 + };
4378 +
4379 + lpuart2: serial@2970000 {
4380 + compatible = "fsl,ls1021a-lpuart";
4381 + reg = <0x0 0x2970000 0x0 0x1000>;
4382 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
4383 + clocks = <&clockgen 4 1>;
4384 + clock-names = "ipg";
4385 + status = "disabled";
4386 + };
4387 +
4388 + lpuart3: serial@2980000 {
4389 + compatible = "fsl,ls1021a-lpuart";
4390 + reg = <0x0 0x2980000 0x0 0x1000>;
4391 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
4392 + clocks = <&clockgen 4 1>;
4393 + clock-names = "ipg";
4394 + status = "disabled";
4395 + };
4396 +
4397 + lpuart4: serial@2990000 {
4398 + compatible = "fsl,ls1021a-lpuart";
4399 + reg = <0x0 0x2990000 0x0 0x1000>;
4400 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
4401 + clocks = <&clockgen 4 1>;
4402 + clock-names = "ipg";
4403 + status = "disabled";
4404 + };
4405 +
4406 + lpuart5: serial@29a0000 {
4407 + compatible = "fsl,ls1021a-lpuart";
4408 + reg = <0x0 0x29a0000 0x0 0x1000>;
4409 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
4410 + clocks = <&clockgen 4 1>;
4411 + clock-names = "ipg";
4412 + status = "disabled";
4413 + };
4414 +
4415 + ftm0: ftm0@29d0000 {
4416 + compatible = "fsl,ftm-alarm";
4417 + reg = <0x0 0x29d0000 0x0 0x10000>,
4418 + <0x0 0x1ee2140 0x0 0x4>;
4419 + reg-names = "ftm", "FlexTimer1";
4420 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
4421 + big-endian;
4422 + };
4423 +
4424 + wdog0: watchdog@2ad0000 {
4425 + compatible = "fsl,imx21-wdt";
4426 + reg = <0x0 0x2ad0000 0x0 0x10000>;
4427 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
4428 + clocks = <&clockgen 4 1>;
4429 + big-endian;
4430 + };
4431 +
4432 + edma0: edma@2c00000 {
4433 + #dma-cells = <2>;
4434 + compatible = "fsl,vf610-edma";
4435 + reg = <0x0 0x2c00000 0x0 0x10000>,
4436 + <0x0 0x2c10000 0x0 0x10000>,
4437 + <0x0 0x2c20000 0x0 0x10000>;
4438 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
4439 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
4440 + interrupt-names = "edma-tx", "edma-err";
4441 + dma-channels = <32>;
4442 + big-endian;
4443 + clock-names = "dmamux0", "dmamux1";
4444 + clocks = <&clockgen 4 1>,
4445 + <&clockgen 4 1>;
4446 + };
4447 +
4448 + usb0: usb@2f00000 {
4449 + compatible = "snps,dwc3";
4450 + reg = <0x0 0x2f00000 0x0 0x10000>;
4451 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
4452 + dr_mode = "host";
4453 + snps,quirk-frame-length-adjustment = <0x20>;
4454 + snps,dis_rxdet_inp3_quirk;
4455 + };
4456 +
4457 + usb1: usb@3000000 {
4458 + compatible = "snps,dwc3";
4459 + reg = <0x0 0x3000000 0x0 0x10000>;
4460 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
4461 + dr_mode = "host";
4462 + snps,quirk-frame-length-adjustment = <0x20>;
4463 + snps,dis_rxdet_inp3_quirk;
4464 + };
4465 +
4466 + usb2: usb@3100000 {
4467 + compatible = "snps,dwc3";
4468 + reg = <0x0 0x3100000 0x0 0x10000>;
4469 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
4470 + dr_mode = "host";
4471 + snps,quirk-frame-length-adjustment = <0x20>;
4472 + snps,dis_rxdet_inp3_quirk;
4473 + };
4474 +
4475 + sata: sata@3200000 {
4476 + compatible = "fsl,ls1046a-ahci";
4477 + reg = <0x0 0x3200000 0x0 0x10000>,
4478 + <0x0 0x20140520 0x0 0x4>;
4479 + reg-names = "ahci", "sata-ecc";
4480 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
4481 + clocks = <&clockgen 4 1>;
4482 + dma-coherent;
4483 + };
4484 +
4485 + qdma: qdma@8380000 {
4486 + compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
4487 + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
4488 + <0x0 0x8390000 0x0 0x10000>, /* Status regs */
4489 + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
4490 + interrupts = <0 153 0x4>,
4491 + <0 39 0x4>;
4492 + interrupt-names = "qdma-error", "qdma-queue";
4493 + channels = <8>;
4494 + queues = <2>;
4495 + status-sizes = <64>;
4496 + queue-sizes = <64 64>;
4497 + big-endian;
4498 + };
4499 +
4500 + msi1: msi-controller@1580000 {
4501 + compatible = "fsl,ls1046a-msi";
4502 + msi-controller;
4503 + reg = <0x0 0x1580000 0x0 0x10000>;
4504 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
4505 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
4506 + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
4507 + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
4508 + };
4509 +
4510 + msi2: msi-controller@1590000 {
4511 + compatible = "fsl,ls1046a-msi";
4512 + msi-controller;
4513 + reg = <0x0 0x1590000 0x0 0x10000>;
4514 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
4515 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
4516 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
4517 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
4518 + };
4519 +
4520 + msi3: msi-controller@15a0000 {
4521 + compatible = "fsl,ls1046a-msi";
4522 + msi-controller;
4523 + reg = <0x0 0x15a0000 0x0 0x10000>;
4524 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
4525 + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
4526 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
4527 + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
4528 + };
4529 +
4530 + pcie@3400000 {
4531 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4532 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
4533 + 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
4534 + reg-names = "regs", "config";
4535 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
4536 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
4537 + interrupt-names = "pme", "aer";
4538 + #address-cells = <3>;
4539 + #size-cells = <2>;
4540 + device_type = "pci";
4541 + dma-coherent;
4542 + num-lanes = <4>;
4543 + bus-range = <0x0 0xff>;
4544 + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
4545 + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4546 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4547 + #interrupt-cells = <1>;
4548 + interrupt-map-mask = <0 0 0 7>;
4549 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4550 + <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4551 + <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
4552 + <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
4553 + };
4554 +
4555 + pcie@3500000 {
4556 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4557 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
4558 + 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
4559 + reg-names = "regs", "config";
4560 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
4561 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
4562 + interrupt-names = "pme", "aer";
4563 + #address-cells = <3>;
4564 + #size-cells = <2>;
4565 + device_type = "pci";
4566 + dma-coherent;
4567 + num-lanes = <2>;
4568 + bus-range = <0x0 0xff>;
4569 + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
4570 + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4571 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4572 + #interrupt-cells = <1>;
4573 + interrupt-map-mask = <0 0 0 7>;
4574 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4575 + <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4576 + <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
4577 + <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
4578 + };
4579 +
4580 + pcie@3600000 {
4581 + compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
4582 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
4583 + 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
4584 + reg-names = "regs", "config";
4585 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
4586 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
4587 + interrupt-names = "pme", "aer";
4588 + #address-cells = <3>;
4589 + #size-cells = <2>;
4590 + device_type = "pci";
4591 + dma-coherent;
4592 + num-lanes = <2>;
4593 + bus-range = <0x0 0xff>;
4594 + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
4595 + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
4596 + msi-parent = <&msi1>, <&msi2>, <&msi3>;
4597 + #interrupt-cells = <1>;
4598 + interrupt-map-mask = <0 0 0 7>;
4599 + interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4600 + <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4601 + <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
4602 + <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
4603 + };
4604 +
4605 + };
4606 +
4607 + reserved-memory {
4608 + #address-cells = <2>;
4609 + #size-cells = <2>;
4610 + ranges;
4611 +
4612 + bman_fbpr: bman-fbpr {
4613 + compatible = "shared-dma-pool";
4614 + size = <0 0x1000000>;
4615 + alignment = <0 0x1000000>;
4616 + no-map;
4617 + };
4618 + qman_fqd: qman-fqd {
4619 + compatible = "shared-dma-pool";
4620 + size = <0 0x800000>;
4621 + alignment = <0 0x800000>;
4622 + no-map;
4623 + };
4624 + qman_pfdr: qman-pfdr {
4625 + compatible = "shared-dma-pool";
4626 + size = <0 0x2000000>;
4627 + alignment = <0 0x2000000>;
4628 + no-map;
4629 + };
4630 + };
4631 +};
4632 +
4633 +#include "qoriq-qman1-portals.dtsi"
4634 +#include "qoriq-bman1-portals.dtsi"
4635 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
4636 new file mode 100644
4637 index 00000000..f61ec261
4638 --- /dev/null
4639 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
4640 @@ -0,0 +1,173 @@
4641 +/*
4642 + * Device Tree file for NXP LS1088A QDS Board.
4643 + *
4644 + * Copyright 2017 NXP
4645 + *
4646 + * Harninder Rai <harninder.rai@nxp.com>
4647 + *
4648 + * This file is dual-licensed: you can use it either under the terms
4649 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4650 + * licensing only applies to this file, and not this project as a
4651 + * whole.
4652 + *
4653 + * a) This library is free software; you can redistribute it and/or
4654 + * modify it under the terms of the GNU General Public License as
4655 + * published by the Free Software Foundation; either version 2 of the
4656 + * License, or (at your option) any later version.
4657 + *
4658 + * This library is distributed in the hope that it will be useful,
4659 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4660 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4661 + * GNU General Public License for more details.
4662 + *
4663 + * Or, alternatively,
4664 + *
4665 + * b) Permission is hereby granted, free of charge, to any person
4666 + * obtaining a copy of this software and associated documentation
4667 + * files (the "Software"), to deal in the Software without
4668 + * restriction, including without limitation the rights to use,
4669 + * copy, modify, merge, publish, distribute, sublicense, and/or
4670 + * sell copies of the Software, and to permit persons to whom the
4671 + * Software is furnished to do so, subject to the following
4672 + * conditions:
4673 + *
4674 + * The above copyright notice and this permission notice shall be
4675 + * included in all copies or substantial portions of the Software.
4676 + *
4677 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4678 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4679 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4680 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4681 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4682 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4683 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4684 + * OTHER DEALINGS IN THE SOFTWARE.
4685 + */
4686 +
4687 +/dts-v1/;
4688 +
4689 +#include "fsl-ls1088a.dtsi"
4690 +
4691 +/ {
4692 + model = "LS1088A QDS Board";
4693 + compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
4694 +};
4695 +
4696 +&i2c0 {
4697 + status = "okay";
4698 +
4699 + i2c-switch@77 {
4700 + compatible = "nxp,pca9547";
4701 + reg = <0x77>;
4702 + #address-cells = <1>;
4703 + #size-cells = <0>;
4704 +
4705 + i2c@2 {
4706 + #address-cells = <1>;
4707 + #size-cells = <0>;
4708 + reg = <0x2>;
4709 +
4710 + ina220@40 {
4711 + compatible = "ti,ina220";
4712 + reg = <0x40>;
4713 + shunt-resistor = <1000>;
4714 + };
4715 +
4716 + ina220@41 {
4717 + compatible = "ti,ina220";
4718 + reg = <0x41>;
4719 + shunt-resistor = <1000>;
4720 + };
4721 + };
4722 +
4723 + i2c@3 {
4724 + #address-cells = <1>;
4725 + #size-cells = <0>;
4726 + reg = <0x3>;
4727 +
4728 + temp-sensor@4c {
4729 + compatible = "adi,adt7461a";
4730 + reg = <0x4c>;
4731 + };
4732 +
4733 + rtc@51 {
4734 + compatible = "nxp,pcf2129";
4735 + reg = <0x51>;
4736 + /* IRQ10_B */
4737 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
4738 + };
4739 +
4740 + eeprom@56 {
4741 + compatible = "atmel,24c512";
4742 + reg = <0x56>;
4743 + };
4744 +
4745 + eeprom@57 {
4746 + compatible = "atmel,24c512";
4747 + reg = <0x57>;
4748 + };
4749 + };
4750 + };
4751 +};
4752 +
4753 +&qspi {
4754 + status = "okay";
4755 + qflash0: s25fs512s@0 {
4756 + compatible = "spansion,m25p80";
4757 + #address-cells = <1>;
4758 + #size-cells = <1>;
4759 + spi-max-frequency = <20000000>;
4760 + m25p,fast-read;
4761 + reg = <0>;
4762 + };
4763 +
4764 + qflash1: s25fs512s@1 {
4765 + compatible = "spansion,m25p80";
4766 + #address-cells = <1>;
4767 + #size-cells = <1>;
4768 + spi-max-frequency = <20000000>;
4769 + m25p,fast-read;
4770 + reg = <1>;
4771 + };
4772 +};
4773 +
4774 +&ifc {
4775 + status = "okay";
4776 +
4777 + ranges = <0 0 0x5 0x80000000 0x08000000
4778 + 2 0 0x5 0x30000000 0x00010000
4779 + 3 0 0x5 0x20000000 0x00010000>;
4780 +
4781 + nor@0,0 {
4782 + compatible = "cfi-flash";
4783 + reg = <0x0 0x0 0x8000000>;
4784 + bank-width = <2>;
4785 + device-width = <1>;
4786 + };
4787 +
4788 + nand@2,0 {
4789 + compatible = "fsl,ifc-nand";
4790 + reg = <0x2 0x0 0x10000>;
4791 + };
4792 +
4793 + fpga: board-control@3,0 {
4794 + compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
4795 + reg = <0x3 0x0 0x0000100>;
4796 + };
4797 +};
4798 +
4799 +&duart0 {
4800 + status = "okay";
4801 +};
4802 +
4803 +&duart1 {
4804 + status = "okay";
4805 +};
4806 +
4807 +&esdhc {
4808 + status = "okay";
4809 +};
4810 +
4811 +&sata {
4812 + status = "okay";
4813 +};
4814 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
4815 new file mode 100644
4816 index 00000000..a4cbc2d5
4817 --- /dev/null
4818 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
4819 @@ -0,0 +1,236 @@
4820 +/*
4821 + * Device Tree file for NXP LS1088A RDB Board.
4822 + *
4823 + * Copyright 2017 NXP
4824 + *
4825 + * Harninder Rai <harninder.rai@nxp.com>
4826 + *
4827 + * This file is dual-licensed: you can use it either under the terms
4828 + * of the GPLv2 or the X11 license, at your option. Note that this dual
4829 + * licensing only applies to this file, and not this project as a
4830 + * whole.
4831 + *
4832 + * a) This library is free software; you can redistribute it and/or
4833 + * modify it under the terms of the GNU General Public License as
4834 + * published by the Free Software Foundation; either version 2 of the
4835 + * License, or (at your option) any later version.
4836 + *
4837 + * This library is distributed in the hope that it will be useful,
4838 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4839 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4840 + * GNU General Public License for more details.
4841 + *
4842 + * Or, alternatively,
4843 + *
4844 + * b) Permission is hereby granted, free of charge, to any person
4845 + * obtaining a copy of this software and associated documentation
4846 + * files (the "Software"), to deal in the Software without
4847 + * restriction, including without limitation the rights to use,
4848 + * copy, modify, merge, publish, distribute, sublicense, and/or
4849 + * sell copies of the Software, and to permit persons to whom the
4850 + * Software is furnished to do so, subject to the following
4851 + * conditions:
4852 + *
4853 + * The above copyright notice and this permission notice shall be
4854 + * included in all copies or substantial portions of the Software.
4855 + *
4856 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
4857 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
4858 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
4859 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
4860 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
4861 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
4862 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
4863 + * OTHER DEALINGS IN THE SOFTWARE.
4864 + */
4865 +
4866 +/dts-v1/;
4867 +
4868 +#include "fsl-ls1088a.dtsi"
4869 +
4870 +/ {
4871 + model = "L1088A RDB Board";
4872 + compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
4873 +};
4874 +
4875 +&i2c0 {
4876 + status = "okay";
4877 +
4878 + i2c-switch@77 {
4879 + compatible = "nxp,pca9547";
4880 + reg = <0x77>;
4881 + #address-cells = <1>;
4882 + #size-cells = <0>;
4883 +
4884 + i2c@2 {
4885 + #address-cells = <1>;
4886 + #size-cells = <0>;
4887 + reg = <0x2>;
4888 +
4889 + ina220@40 {
4890 + compatible = "ti,ina220";
4891 + reg = <0x40>;
4892 + shunt-resistor = <1000>;
4893 + };
4894 + };
4895 +
4896 + i2c@3 {
4897 + #address-cells = <1>;
4898 + #size-cells = <0>;
4899 + reg = <0x3>;
4900 +
4901 + temp-sensor@4c {
4902 + compatible = "adi,adt7461a";
4903 + reg = <0x4c>;
4904 + };
4905 +
4906 + rtc@51 {
4907 + compatible = "nxp,pcf2129";
4908 + reg = <0x51>;
4909 + /* IRQ10_B */
4910 + interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
4911 + };
4912 + };
4913 + };
4914 +};
4915 +
4916 +&qspi {
4917 + status = "okay";
4918 + qflash0: s25fs512s@0 {
4919 + compatible = "spansion,m25p80";
4920 + #address-cells = <1>;
4921 + #size-cells = <1>;
4922 + m25p,fast-read;
4923 + spi-max-frequency = <20000000>;
4924 + reg = <0>;
4925 + };
4926 +
4927 + qflash1: s25fs512s@1 {
4928 + compatible = "spansion,m25p80";
4929 + #address-cells = <1>;
4930 + #size-cells = <1>;
4931 + m25p,fast-read;
4932 + spi-max-frequency = <20000000>;
4933 + reg = <1>;
4934 + };
4935 +};
4936 +
4937 +&ifc {
4938 + status = "okay";
4939 +
4940 + ranges = <0 0 0x5 0x30000000 0x00010000
4941 + 2 0 0x5 0x20000000 0x00010000>;
4942 +
4943 + nand@0,0 {
4944 + compatible = "fsl,ifc-nand";
4945 + reg = <0x0 0x0 0x10000>;
4946 + };
4947 +
4948 + fpga: board-control@2,0 {
4949 + compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
4950 + reg = <0x2 0x0 0x0000100>;
4951 + };
4952 +};
4953 +
4954 +&duart0 {
4955 + status = "okay";
4956 +};
4957 +
4958 +&duart1 {
4959 + status = "okay";
4960 +};
4961 +
4962 +&usb0 {
4963 + status = "okay";
4964 +};
4965 +
4966 +&usb1 {
4967 + status = "okay";
4968 +};
4969 +
4970 +&esdhc {
4971 + status = "okay";
4972 +};
4973 +
4974 +&sata {
4975 + status = "okay";
4976 +};
4977 +
4978 +&emdio1 {
4979 + /* Freescale F104 PHY1 */
4980 + mdio1_phy1: emdio1_phy@1 {
4981 + reg = <0x1c>;
4982 + phy-connection-type = "qsgmii";
4983 + };
4984 + mdio1_phy2: emdio1_phy@2 {
4985 + reg = <0x1d>;
4986 + phy-connection-type = "qsgmii";
4987 + };
4988 + mdio1_phy3: emdio1_phy@3 {
4989 + reg = <0x1e>;
4990 + phy-connection-type = "qsgmii";
4991 + };
4992 + mdio1_phy4: emdio1_phy@4 {
4993 + reg = <0x1f>;
4994 + phy-connection-type = "qsgmii";
4995 + };
4996 + /* F104 PHY2 */
4997 + mdio1_phy5: emdio1_phy@5 {
4998 + reg = <0x0c>;
4999 + phy-connection-type = "qsgmii";
5000 + };
5001 + mdio1_phy6: emdio1_phy@6 {
5002 + reg = <0x0d>;
5003 + phy-connection-type = "qsgmii";
5004 + };
5005 + mdio1_phy7: emdio1_phy@7 {
5006 + reg = <0x0e>;
5007 + phy-connection-type = "qsgmii";
5008 + };
5009 + mdio1_phy8: emdio1_phy@8 {
5010 + reg = <0x0f>;
5011 + phy-connection-type = "qsgmii";
5012 + };
5013 +};
5014 +
5015 +&emdio2 {
5016 + /* Aquantia AQR105 10G PHY */
5017 + mdio2_phy1: emdio2_phy@1 {
5018 + compatible = "ethernet-phy-ieee802.3-c45";
5019 + interrupts = <0 2 0x4>;
5020 + reg = <0x0>;
5021 + phy-connection-type = "xfi";
5022 + };
5023 +};
5024 +
5025 +/* DPMAC connections to external PHYs
5026 + * based on LS1088A RM RevC - $24.1.2 SerDes Options
5027 + */
5028 +/* DPMAC1 is 10G SFP+, fixed link */
5029 +&dpmac2 {
5030 + phy-handle = <&mdio2_phy1>;
5031 +};
5032 +&dpmac3 {
5033 + phy-handle = <&mdio1_phy5>;
5034 +};
5035 +&dpmac4 {
5036 + phy-handle = <&mdio1_phy6>;
5037 +};
5038 +&dpmac5 {
5039 + phy-handle = <&mdio1_phy7>;
5040 +};
5041 +&dpmac6 {
5042 + phy-handle = <&mdio1_phy8>;
5043 +};
5044 +&dpmac7 {
5045 + phy-handle = <&mdio1_phy1>;
5046 +};
5047 +&dpmac8 {
5048 + phy-handle = <&mdio1_phy2>;
5049 +};
5050 +&dpmac9 {
5051 + phy-handle = <&mdio1_phy3>;
5052 +};
5053 +&dpmac10 {
5054 + phy-handle = <&mdio1_phy4>;
5055 +};
5056 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5057 new file mode 100644
5058 index 00000000..14585ab2
5059 --- /dev/null
5060 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
5061 @@ -0,0 +1,816 @@
5062 +/*
5063 + * Device Tree Include file for NXP Layerscape-1088A family SoC.
5064 + *
5065 + * Copyright 2017 NXP
5066 + *
5067 + * Harninder Rai <harninder.rai@nxp.com>
5068 + *
5069 + * This file is dual-licensed: you can use it either under the terms
5070 + * of the GPLv2 or the X11 license, at your option. Note that this dual
5071 + * licensing only applies to this file, and not this project as a
5072 + * whole.
5073 + *
5074 + * a) This library is free software; you can redistribute it and/or
5075 + * modify it under the terms of the GNU General Public License as
5076 + * published by the Free Software Foundation; either version 2 of the
5077 + * License, or (at your option) any later version.
5078 + *
5079 + * This library is distributed in the hope that it will be useful,
5080 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5081 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5082 + * GNU General Public License for more details.
5083 + *
5084 + * Or, alternatively,
5085 + *
5086 + * b) Permission is hereby granted, free of charge, to any person
5087 + * obtaining a copy of this software and associated documentation
5088 + * files (the "Software"), to deal in the Software without
5089 + * restriction, including without limitation the rights to use,
5090 + * copy, modify, merge, publish, distribute, sublicense, and/or
5091 + * sell copies of the Software, and to permit persons to whom the
5092 + * Software is furnished to do so, subject to the following
5093 + * conditions:
5094 + *
5095 + * The above copyright notice and this permission notice shall be
5096 + * included in all copies or substantial portions of the Software.
5097 + *
5098 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
5099 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
5100 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
5101 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
5102 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
5103 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
5104 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
5105 + * OTHER DEALINGS IN THE SOFTWARE.
5106 + */
5107 +#include <dt-bindings/interrupt-controller/arm-gic.h>
5108 +#include <dt-bindings/thermal/thermal.h>
5109 +
5110 +/ {
5111 + compatible = "fsl,ls1088a";
5112 + interrupt-parent = <&gic>;
5113 + #address-cells = <2>;
5114 + #size-cells = <2>;
5115 +
5116 + aliases {
5117 + crypto = &crypto;
5118 + };
5119 +
5120 + cpus {
5121 + #address-cells = <1>;
5122 + #size-cells = <0>;
5123 +
5124 + /* We have 2 clusters having 4 Cortex-A53 cores each */
5125 + cpu0: cpu@0 {
5126 + device_type = "cpu";
5127 + compatible = "arm,cortex-a53";
5128 + reg = <0x0>;
5129 + clocks = <&clockgen 1 0>;
5130 + #cooling-cells = <2>;
5131 + cpu-idle-states = <&CPU_PH20>;
5132 + };
5133 +
5134 + cpu1: cpu@1 {
5135 + device_type = "cpu";
5136 + compatible = "arm,cortex-a53";
5137 + reg = <0x1>;
5138 + clocks = <&clockgen 1 0>;
5139 + cpu-idle-states = <&CPU_PH20>;
5140 + };
5141 +
5142 + cpu2: cpu@2 {
5143 + device_type = "cpu";
5144 + compatible = "arm,cortex-a53";
5145 + reg = <0x2>;
5146 + clocks = <&clockgen 1 0>;
5147 + cpu-idle-states = <&CPU_PH20>;
5148 + };
5149 +
5150 + cpu3: cpu@3 {
5151 + device_type = "cpu";
5152 + compatible = "arm,cortex-a53";
5153 + reg = <0x3>;
5154 + clocks = <&clockgen 1 0>;
5155 + cpu-idle-states = <&CPU_PH20>;
5156 + };
5157 +
5158 + cpu4: cpu@100 {
5159 + device_type = "cpu";
5160 + compatible = "arm,cortex-a53";
5161 + reg = <0x100>;
5162 + clocks = <&clockgen 1 1>;
5163 + #cooling-cells = <2>;
5164 + cpu-idle-states = <&CPU_PH20>;
5165 + };
5166 +
5167 + cpu5: cpu@101 {
5168 + device_type = "cpu";
5169 + compatible = "arm,cortex-a53";
5170 + reg = <0x101>;
5171 + clocks = <&clockgen 1 1>;
5172 + cpu-idle-states = <&CPU_PH20>;
5173 + };
5174 +
5175 + cpu6: cpu@102 {
5176 + device_type = "cpu";
5177 + compatible = "arm,cortex-a53";
5178 + reg = <0x102>;
5179 + clocks = <&clockgen 1 1>;
5180 + cpu-idle-states = <&CPU_PH20>;
5181 + };
5182 +
5183 + cpu7: cpu@103 {
5184 + device_type = "cpu";
5185 + compatible = "arm,cortex-a53";
5186 + reg = <0x103>;
5187 + clocks = <&clockgen 1 1>;
5188 + cpu-idle-states = <&CPU_PH20>;
5189 + };
5190 + };
5191 +
5192 + idle-states {
5193 + /*
5194 + * PSCI node is not added default, U-boot will add missing
5195 + * parts if it determines to use PSCI.
5196 + */
5197 + entry-method = "arm,psci";
5198 +
5199 + CPU_PH20: cpu-ph20 {
5200 + compatible = "arm,idle-state";
5201 + idle-state-name = "PH20";
5202 + arm,psci-suspend-param = <0x0>;
5203 + entry-latency-us = <1000>;
5204 + exit-latency-us = <1000>;
5205 + min-residency-us = <3000>;
5206 + };
5207 + };
5208 +
5209 + gic: interrupt-controller@6000000 {
5210 + compatible = "arm,gic-v3";
5211 + #interrupt-cells = <3>;
5212 + #address-cells = <2>;
5213 + #size-cells = <2>;
5214 + ranges;
5215 + interrupt-controller;
5216 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
5217 + <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
5218 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
5219 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
5220 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
5221 + interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
5222 +
5223 + its: gic-its@6020000 {
5224 + compatible = "arm,gic-v3-its";
5225 + msi-controller;
5226 + reg = <0x0 0x6020000 0 0x20000>;
5227 + };
5228 + };
5229 +
5230 + timer {
5231 + compatible = "arm,armv8-timer";
5232 + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
5233 + <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
5234 + <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
5235 + <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
5236 + };
5237 +
5238 + fsl_mc: fsl-mc@80c000000 {
5239 + compatible = "fsl,qoriq-mc";
5240 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
5241 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
5242 + msi-parent = <&its>;
5243 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
5244 + #address-cells = <3>;
5245 + #size-cells = <1>;
5246 +
5247 + /*
5248 + * Region type 0x0 - MC portals
5249 + * Region type 0x1 - QBMAN portals
5250 + */
5251 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
5252 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
5253 +
5254 + dpmacs {
5255 + #address-cells = <1>;
5256 + #size-cells = <0>;
5257 +
5258 + dpmac1: dpmac@1 {
5259 + compatible = "fsl,qoriq-mc-dpmac";
5260 + reg = <1>;
5261 + };
5262 + dpmac2: dpmac@2 {
5263 + compatible = "fsl,qoriq-mc-dpmac";
5264 + reg = <2>;
5265 + };
5266 + dpmac3: dpmac@3 {
5267 + compatible = "fsl,qoriq-mc-dpmac";
5268 + reg = <3>;
5269 + };
5270 + dpmac4: dpmac@4 {
5271 + compatible = "fsl,qoriq-mc-dpmac";
5272 + reg = <4>;
5273 + };
5274 + dpmac5: dpmac@5 {
5275 + compatible = "fsl,qoriq-mc-dpmac";
5276 + reg = <5>;
5277 + };
5278 + dpmac6: dpmac@6 {
5279 + compatible = "fsl,qoriq-mc-dpmac";
5280 + reg = <6>;
5281 + };
5282 + dpmac7: dpmac@7 {
5283 + compatible = "fsl,qoriq-mc-dpmac";
5284 + reg = <7>;
5285 + };
5286 + dpmac8: dpmac@8 {
5287 + compatible = "fsl,qoriq-mc-dpmac";
5288 + reg = <8>;
5289 + };
5290 + dpmac9: dpmac@9 {
5291 + compatible = "fsl,qoriq-mc-dpmac";
5292 + reg = <9>;
5293 + };
5294 + dpmac10: dpmac@10 {
5295 + compatible = "fsl,qoriq-mc-dpmac";
5296 + reg = <0xa>;
5297 + };
5298 + };
5299 +
5300 + };
5301 +
5302 + sysclk: sysclk {
5303 + compatible = "fixed-clock";
5304 + #clock-cells = <0>;
5305 + clock-frequency = <100000000>;
5306 + clock-output-names = "sysclk";
5307 + };
5308 +
5309 + dcfg: dcfg@1e00000 {
5310 + compatible = "fsl,ls1088a-dcfg", "syscon";
5311 + reg = <0x0 0x1e00000 0x0 0x10000>;
5312 + little-endian;
5313 + };
5314 +
5315 + rstcr: syscon@1e60000 {
5316 + compatible = "fsl,ls1088a-rstcr", "syscon";
5317 + reg = <0x0 0x1e60000 0x0 0x4>;
5318 + };
5319 +
5320 + reboot {
5321 + compatible = "syscon-reboot";
5322 + regmap = <&rstcr>;
5323 + offset = <0x0>;
5324 + mask = <0x02>;
5325 + };
5326 +
5327 +
5328 + soc {
5329 + compatible = "simple-bus";
5330 + #address-cells = <2>;
5331 + #size-cells = <2>;
5332 + ranges;
5333 +
5334 + clockgen: clocking@1300000 {
5335 + compatible = "fsl,ls1088a-clockgen";
5336 + reg = <0 0x1300000 0 0xa0000>;
5337 + #clock-cells = <2>;
5338 + clocks = <&sysclk>;
5339 + };
5340 +
5341 + tmu: tmu@1f80000 {
5342 + compatible = "fsl,qoriq-tmu";
5343 + reg = <0x0 0x1f80000 0x0 0x10000>;
5344 + interrupts = <0 23 0x4>;
5345 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
5346 + fsl,tmu-calibration =
5347 + /* Calibration data group 1 */
5348 + <0x00000000 0x00000026
5349 + 0x00000001 0x0000002d
5350 + 0x00000002 0x00000032
5351 + 0x00000003 0x00000039
5352 + 0x00000004 0x0000003f
5353 + 0x00000005 0x00000046
5354 + 0x00000006 0x0000004d
5355 + 0x00000007 0x00000054
5356 + 0x00000008 0x0000005a
5357 + 0x00000009 0x00000061
5358 + 0x0000000a 0x0000006a
5359 + 0x0000000b 0x00000071
5360 + /* Calibration data group 2 */
5361 + 0x00010000 0x00000025
5362 + 0x00010001 0x0000002c
5363 + 0x00010002 0x00000035
5364 + 0x00010003 0x0000003d
5365 + 0x00010004 0x00000045
5366 + 0x00010005 0x0000004e
5367 + 0x00010006 0x00000057
5368 + 0x00010007 0x00000061
5369 + 0x00010008 0x0000006b
5370 + 0x00010009 0x00000076
5371 + /* Calibration data group 3 */
5372 + 0x00020000 0x00000029
5373 + 0x00020001 0x00000033
5374 + 0x00020002 0x0000003d
5375 + 0x00020003 0x00000049
5376 + 0x00020004 0x00000056
5377 + 0x00020005 0x00000061
5378 + 0x00020006 0x0000006d
5379 + /* Calibration data group 4 */
5380 + 0x00030000 0x00000021
5381 + 0x00030001 0x0000002a
5382 + 0x00030002 0x0000003c
5383 + 0x00030003 0x0000004e>;
5384 + little-endian;
5385 + #thermal-sensor-cells = <1>;
5386 + };
5387 +
5388 + thermal-zones {
5389 + cpu_thermal: cpu-thermal {
5390 + polling-delay-passive = <1000>;
5391 + polling-delay = <5000>;
5392 + thermal-sensors = <&tmu 0>;
5393 +
5394 + trips {
5395 + cpu_alert: cpu-alert {
5396 + temperature = <85000>;
5397 + hysteresis = <2000>;
5398 + type = "passive";
5399 + };
5400 +
5401 + cpu_crit: cpu-crit {
5402 + temperature = <95000>;
5403 + hysteresis = <2000>;
5404 + type = "critical";
5405 + };
5406 + };
5407 +
5408 + cooling-maps {
5409 + map0 {
5410 + trip = <&cpu_alert>;
5411 + cooling-device =
5412 + <&cpu0 THERMAL_NO_LIMIT
5413 + THERMAL_NO_LIMIT>;
5414 + };
5415 + map1 {
5416 + trip = <&cpu_alert>;
5417 + cooling-device =
5418 + <&cpu4 THERMAL_NO_LIMIT
5419 + THERMAL_NO_LIMIT>;
5420 + };
5421 + };
5422 + };
5423 + };
5424 +
5425 + duart0: serial@21c0500 {
5426 + compatible = "fsl,ns16550", "ns16550a";
5427 + reg = <0x0 0x21c0500 0x0 0x100>;
5428 + clocks = <&clockgen 4 3>;
5429 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5430 + status = "disabled";
5431 + };
5432 +
5433 + duart1: serial@21c0600 {
5434 + compatible = "fsl,ns16550", "ns16550a";
5435 + reg = <0x0 0x21c0600 0x0 0x100>;
5436 + clocks = <&clockgen 4 3>;
5437 + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
5438 + status = "disabled";
5439 + };
5440 +
5441 + cluster1_core0_watchdog: wdt@c000000 {
5442 + compatible = "arm,sp805-wdt", "arm,primecell";
5443 + reg = <0x0 0xc000000 0x0 0x1000>;
5444 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5445 + clock-names = "apb_pclk", "wdog_clk";
5446 + };
5447 +
5448 + cluster1_core1_watchdog: wdt@c010000 {
5449 + compatible = "arm,sp805-wdt", "arm,primecell";
5450 + reg = <0x0 0xc010000 0x0 0x1000>;
5451 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5452 + clock-names = "apb_pclk", "wdog_clk";
5453 + };
5454 +
5455 + cluster1_core2_watchdog: wdt@c020000 {
5456 + compatible = "arm,sp805-wdt", "arm,primecell";
5457 + reg = <0x0 0xc020000 0x0 0x1000>;
5458 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5459 + clock-names = "apb_pclk", "wdog_clk";
5460 + };
5461 +
5462 + cluster1_core3_watchdog: wdt@c030000 {
5463 + compatible = "arm,sp805-wdt", "arm,primecell";
5464 + reg = <0x0 0xc030000 0x0 0x1000>;
5465 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5466 + clock-names = "apb_pclk", "wdog_clk";
5467 + };
5468 +
5469 + cluster2_core0_watchdog: wdt@c100000 {
5470 + compatible = "arm,sp805-wdt", "arm,primecell";
5471 + reg = <0x0 0xc100000 0x0 0x1000>;
5472 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5473 + clock-names = "apb_pclk", "wdog_clk";
5474 + };
5475 +
5476 + cluster2_core1_watchdog: wdt@c110000 {
5477 + compatible = "arm,sp805-wdt", "arm,primecell";
5478 + reg = <0x0 0xc110000 0x0 0x1000>;
5479 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5480 + clock-names = "apb_pclk", "wdog_clk";
5481 + };
5482 +
5483 + cluster2_core2_watchdog: wdt@c120000 {
5484 + compatible = "arm,sp805-wdt", "arm,primecell";
5485 + reg = <0x0 0xc120000 0x0 0x1000>;
5486 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5487 + clock-names = "apb_pclk", "wdog_clk";
5488 + };
5489 +
5490 + cluster2_core3_watchdog: wdt@c130000 {
5491 + compatible = "arm,sp805-wdt", "arm,primecell";
5492 + reg = <0x0 0xc130000 0x0 0x1000>;
5493 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5494 + clock-names = "apb_pclk", "wdog_clk";
5495 + };
5496 +
5497 + gpio0: gpio@2300000 {
5498 + compatible = "fsl,qoriq-gpio";
5499 + reg = <0x0 0x2300000 0x0 0x10000>;
5500 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5501 + gpio-controller;
5502 + #gpio-cells = <2>;
5503 + interrupt-controller;
5504 + #interrupt-cells = <2>;
5505 + };
5506 +
5507 + gpio1: gpio@2310000 {
5508 + compatible = "fsl,qoriq-gpio";
5509 + reg = <0x0 0x2310000 0x0 0x10000>;
5510 + interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
5511 + gpio-controller;
5512 + #gpio-cells = <2>;
5513 + interrupt-controller;
5514 + #interrupt-cells = <2>;
5515 + };
5516 +
5517 + gpio2: gpio@2320000 {
5518 + compatible = "fsl,qoriq-gpio";
5519 + reg = <0x0 0x2320000 0x0 0x10000>;
5520 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5521 + gpio-controller;
5522 + #gpio-cells = <2>;
5523 + interrupt-controller;
5524 + #interrupt-cells = <2>;
5525 + };
5526 +
5527 + gpio3: gpio@2330000 {
5528 + compatible = "fsl,qoriq-gpio";
5529 + reg = <0x0 0x2330000 0x0 0x10000>;
5530 + interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
5531 + gpio-controller;
5532 + #gpio-cells = <2>;
5533 + interrupt-controller;
5534 + #interrupt-cells = <2>;
5535 + };
5536 +
5537 + /* TODO: WRIOP (CCSR?) */
5538 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
5539 + * E-MDIO1: 0x1_6000
5540 + */
5541 + compatible = "fsl,fman-memac-mdio";
5542 + reg = <0x0 0x8B96000 0x0 0x1000>;
5543 + device_type = "mdio";
5544 + little-endian; /* force the driver in LE mode */
5545 +
5546 + /* Not necessary on the QDS, but needed on the RDB */
5547 + #address-cells = <1>;
5548 + #size-cells = <0>;
5549 + };
5550 +
5551 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
5552 + * E-MDIO2: 0x1_7000
5553 + */
5554 + compatible = "fsl,fman-memac-mdio";
5555 + reg = <0x0 0x8B97000 0x0 0x1000>;
5556 + device_type = "mdio";
5557 + little-endian; /* force the driver in LE mode */
5558 +
5559 + #address-cells = <1>;
5560 + #size-cells = <0>;
5561 + };
5562 +
5563 + ifc: ifc@2240000 {
5564 + compatible = "fsl,ifc", "simple-bus";
5565 + reg = <0x0 0x2240000 0x0 0x20000>;
5566 + interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
5567 + little-endian;
5568 + #address-cells = <2>;
5569 + #size-cells = <1>;
5570 +
5571 + };
5572 +
5573 + ftm0: ftm0@2800000 {
5574 + compatible = "fsl,ftm-alarm";
5575 + reg = <0x0 0x2800000 0x0 0x10000>;
5576 + interrupts = <0 44 4>;
5577 + };
5578 +
5579 + i2c0: i2c@2000000 {
5580 + compatible = "fsl,vf610-i2c";
5581 + #address-cells = <1>;
5582 + #size-cells = <0>;
5583 + reg = <0x0 0x2000000 0x0 0x10000>;
5584 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5585 + clocks = <&clockgen 4 3>;
5586 + status = "disabled";
5587 + };
5588 +
5589 + i2c1: i2c@2010000 {
5590 + compatible = "fsl,vf610-i2c";
5591 + #address-cells = <1>;
5592 + #size-cells = <0>;
5593 + reg = <0x0 0x2010000 0x0 0x10000>;
5594 + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
5595 + clocks = <&clockgen 4 3>;
5596 + status = "disabled";
5597 + };
5598 +
5599 + i2c2: i2c@2020000 {
5600 + compatible = "fsl,vf610-i2c";
5601 + #address-cells = <1>;
5602 + #size-cells = <0>;
5603 + reg = <0x0 0x2020000 0x0 0x10000>;
5604 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5605 + clocks = <&clockgen 4 3>;
5606 + status = "disabled";
5607 + };
5608 +
5609 + i2c3: i2c@2030000 {
5610 + compatible = "fsl,vf610-i2c";
5611 + #address-cells = <1>;
5612 + #size-cells = <0>;
5613 + reg = <0x0 0x2030000 0x0 0x10000>;
5614 + interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
5615 + clocks = <&clockgen 4 3>;
5616 + status = "disabled";
5617 + };
5618 +
5619 + qspi: quadspi@20c0000 {
5620 + compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi";
5621 + #address-cells = <1>;
5622 + #size-cells = <0>;
5623 + reg = <0x0 0x20c0000 0x0 0x10000>,
5624 + <0x0 0x20000000 0x0 0x10000000>;
5625 + reg-names = "QuadSPI", "QuadSPI-memory";
5626 + interrupts = <0 25 0x4>; /* Level high type */
5627 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
5628 + clock-names = "qspi_en", "qspi";
5629 + fsl,qspi-has-second-chip;
5630 + };
5631 +
5632 + esdhc: esdhc@2140000 {
5633 + compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
5634 + reg = <0x0 0x2140000 0x0 0x10000>;
5635 + interrupts = <0 28 0x4>; /* Level high type */
5636 + clock-frequency = <0>;
5637 + voltage-ranges = <1800 1800 3300 3300>;
5638 + sdhci,auto-cmd12;
5639 + little-endian;
5640 + bus-width = <4>;
5641 + status = "disabled";
5642 + };
5643 +
5644 + usb0: usb3@3100000 {
5645 + compatible = "snps,dwc3";
5646 + reg = <0x0 0x3100000 0x0 0x10000>;
5647 + interrupts = <0 80 0x4>; /* Level high type */
5648 + dr_mode = "host";
5649 + configure-gfladj;
5650 + snps,dis_rxdet_inp3_quirk;
5651 + };
5652 +
5653 + usb1: usb3@3110000 {
5654 + compatible = "snps,dwc3";
5655 + reg = <0x0 0x3110000 0x0 0x10000>;
5656 + interrupts = <0 81 0x4>; /* Level high type */
5657 + dr_mode = "host";
5658 + configure-gfladj;
5659 + snps,dis_rxdet_inp3_quirk;
5660 + };
5661 +
5662 + sata: sata@3200000 {
5663 + compatible = "fsl,ls1088a-ahci";
5664 + reg = <0x0 0x3200000 0x0 0x10000>,
5665 + <0x7 0x100520 0x0 0x4>;
5666 + reg-names = "ahci", "sata-ecc";
5667 + interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
5668 + clocks = <&clockgen 4 3>;
5669 + dma-coherent;
5670 + status = "disabled";
5671 + };
5672 +
5673 + pcie@3400000 {
5674 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5675 + "snps,dw-pcie";
5676 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
5677 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
5678 + reg-names = "regs", "config";
5679 + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5680 + interrupt-names = "aer";
5681 + #address-cells = <3>;
5682 + #size-cells = <2>;
5683 + device_type = "pci";
5684 + dma-coherent;
5685 + num-lanes = <4>;
5686 + bus-range = <0x0 0xff>;
5687 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
5688 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5689 + msi-parent = <&its>;
5690 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5691 + #interrupt-cells = <1>;
5692 + interrupt-map-mask = <0 0 0 7>;
5693 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
5694 + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
5695 + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
5696 + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
5697 + };
5698 +
5699 + pcie@3500000 {
5700 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5701 + "snps,dw-pcie";
5702 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
5703 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
5704 + reg-names = "regs", "config";
5705 + interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5706 + interrupt-names = "aer";
5707 + #address-cells = <3>;
5708 + #size-cells = <2>;
5709 + device_type = "pci";
5710 + dma-coherent;
5711 + num-lanes = <4>;
5712 + bus-range = <0x0 0xff>;
5713 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
5714 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5715 + msi-parent = <&its>;
5716 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5717 + #interrupt-cells = <1>;
5718 + interrupt-map-mask = <0 0 0 7>;
5719 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
5720 + <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
5721 + <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
5722 + <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
5723 + };
5724 +
5725 + pcie@3600000 {
5726 + compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie",
5727 + "snps,dw-pcie";
5728 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
5729 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
5730 + reg-names = "regs", "config";
5731 + interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
5732 + interrupt-names = "aer";
5733 + #address-cells = <3>;
5734 + #size-cells = <2>;
5735 + device_type = "pci";
5736 + dma-coherent;
5737 + num-lanes = <8>;
5738 + bus-range = <0x0 0xff>;
5739 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
5740 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
5741 + msi-parent = <&its>;
5742 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
5743 + #interrupt-cells = <1>;
5744 + interrupt-map-mask = <0 0 0 7>;
5745 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
5746 + <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
5747 + <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
5748 + <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
5749 + };
5750 +
5751 + smmu: iommu@5000000 {
5752 + compatible = "arm,mmu-500";
5753 + reg = <0 0x5000000 0 0x800000>;
5754 + #global-interrupts = <12>;
5755 + #iommu-cells = <1>;
5756 + stream-match-mask = <0x7C00>;
5757 + interrupts = <0 13 4>, /* global secure fault */
5758 + <0 14 4>, /* combined secure interrupt */
5759 + <0 15 4>, /* global non-secure fault */
5760 + <0 16 4>, /* combined non-secure interrupt */
5761 + /* performance counter interrupts 0-7 */
5762 + <0 211 4>,
5763 + <0 212 4>,
5764 + <0 213 4>,
5765 + <0 214 4>,
5766 + <0 215 4>,
5767 + <0 216 4>,
5768 + <0 217 4>,
5769 + <0 218 4>,
5770 + /* per context interrupt, 64 interrupts */
5771 + <0 146 4>,
5772 + <0 147 4>,
5773 + <0 148 4>,
5774 + <0 149 4>,
5775 + <0 150 4>,
5776 + <0 151 4>,
5777 + <0 152 4>,
5778 + <0 153 4>,
5779 + <0 154 4>,
5780 + <0 155 4>,
5781 + <0 156 4>,
5782 + <0 157 4>,
5783 + <0 158 4>,
5784 + <0 159 4>,
5785 + <0 160 4>,
5786 + <0 161 4>,
5787 + <0 162 4>,
5788 + <0 163 4>,
5789 + <0 164 4>,
5790 + <0 165 4>,
5791 + <0 166 4>,
5792 + <0 167 4>,
5793 + <0 168 4>,
5794 + <0 169 4>,
5795 + <0 170 4>,
5796 + <0 171 4>,
5797 + <0 172 4>,
5798 + <0 173 4>,
5799 + <0 174 4>,
5800 + <0 175 4>,
5801 + <0 176 4>,
5802 + <0 177 4>,
5803 + <0 178 4>,
5804 + <0 179 4>,
5805 + <0 180 4>,
5806 + <0 181 4>,
5807 + <0 182 4>,
5808 + <0 183 4>,
5809 + <0 184 4>,
5810 + <0 185 4>,
5811 + <0 186 4>,
5812 + <0 187 4>,
5813 + <0 188 4>,
5814 + <0 189 4>,
5815 + <0 190 4>,
5816 + <0 191 4>,
5817 + <0 192 4>,
5818 + <0 193 4>,
5819 + <0 194 4>,
5820 + <0 195 4>,
5821 + <0 196 4>,
5822 + <0 197 4>,
5823 + <0 198 4>,
5824 + <0 199 4>,
5825 + <0 200 4>,
5826 + <0 201 4>,
5827 + <0 202 4>,
5828 + <0 203 4>,
5829 + <0 204 4>,
5830 + <0 205 4>,
5831 + <0 206 4>,
5832 + <0 207 4>,
5833 + <0 208 4>,
5834 + <0 209 4>;
5835 + };
5836 +
5837 + crypto: crypto@8000000 {
5838 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
5839 + fsl,sec-era = <8>;
5840 + #address-cells = <1>;
5841 + #size-cells = <1>;
5842 + ranges = <0x0 0x00 0x8000000 0x100000>;
5843 + reg = <0x00 0x8000000 0x0 0x100000>;
5844 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
5845 + dma-coherent;
5846 +
5847 + sec_jr0: jr@10000 {
5848 + compatible = "fsl,sec-v5.0-job-ring",
5849 + "fsl,sec-v4.0-job-ring";
5850 + reg = <0x10000 0x10000>;
5851 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
5852 + };
5853 +
5854 + sec_jr1: jr@20000 {
5855 + compatible = "fsl,sec-v5.0-job-ring",
5856 + "fsl,sec-v4.0-job-ring";
5857 + reg = <0x20000 0x10000>;
5858 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
5859 + };
5860 +
5861 + sec_jr2: jr@30000 {
5862 + compatible = "fsl,sec-v5.0-job-ring",
5863 + "fsl,sec-v4.0-job-ring";
5864 + reg = <0x30000 0x10000>;
5865 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
5866 + };
5867 +
5868 + sec_jr3: jr@40000 {
5869 + compatible = "fsl,sec-v5.0-job-ring",
5870 + "fsl,sec-v4.0-job-ring";
5871 + reg = <0x40000 0x10000>;
5872 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
5873 + };
5874 + };
5875 + };
5876 +
5877 +};
5878 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
5879 index b0dd0109..ba1a79dd 100644
5880 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
5881 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts
5882 @@ -1,8 +1,10 @@
5883 /*
5884 * Device Tree file for Freescale LS2080a QDS Board.
5885 *
5886 - * Copyright (C) 2015, Freescale Semiconductor
5887 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
5888 + * Copyright 2017 NXP
5889 *
5890 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
5891 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
5892 *
5893 * This file is dual-licensed: you can use it either under the terms
5894 @@ -46,169 +48,76 @@
5895
5896 /dts-v1/;
5897
5898 -/include/ "fsl-ls2080a.dtsi"
5899 +#include "fsl-ls2080a.dtsi"
5900 +#include "fsl-ls208xa-qds.dtsi"
5901
5902 / {
5903 model = "Freescale Layerscape 2080a QDS Board";
5904 compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
5905
5906 - aliases {
5907 - serial0 = &serial0;
5908 - serial1 = &serial1;
5909 - };
5910 -
5911 chosen {
5912 stdout-path = "serial0:115200n8";
5913 };
5914 };
5915
5916 -&esdhc {
5917 - status = "okay";
5918 -};
5919 -
5920 &ifc {
5921 - status = "okay";
5922 - #address-cells = <2>;
5923 - #size-cells = <1>;
5924 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
5925 - 0x2 0x0 0x5 0x30000000 0x00010000
5926 - 0x3 0x0 0x5 0x20000000 0x00010000>;
5927 -
5928 - nor@0,0 {
5929 + boardctrl: board-control@3,0 {
5930 #address-cells = <1>;
5931 #size-cells = <1>;
5932 - compatible = "cfi-flash";
5933 - reg = <0x0 0x0 0x8000000>;
5934 - bank-width = <2>;
5935 - device-width = <1>;
5936 - };
5937 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
5938 + reg = <3 0 0x300>; /* TODO check address */
5939 + ranges = <0 3 0 0x300>;
5940
5941 - nand@2,0 {
5942 - compatible = "fsl,ifc-nand";
5943 - reg = <0x2 0x0 0x10000>;
5944 - };
5945 + mdio_mux_emi1 {
5946 + compatible = "mdio-mux-mmioreg", "mdio-mux";
5947 + mdio-parent-bus = <&emdio1>;
5948 + reg = <0x54 1>; /* BRDCFG4 */
5949 + mux-mask = <0xe0>; /* EMI1_MDIO */
5950
5951 - cpld@3,0 {
5952 - reg = <0x3 0x0 0x10000>;
5953 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
5954 - };
5955 -};
5956 -
5957 -&i2c0 {
5958 - status = "okay";
5959 - pca9547@77 {
5960 - compatible = "nxp,pca9547";
5961 - reg = <0x77>;
5962 - #address-cells = <1>;
5963 - #size-cells = <0>;
5964 - i2c@0 {
5965 - #address-cells = <1>;
5966 + #address-cells=<1>;
5967 #size-cells = <0>;
5968 - reg = <0x00>;
5969 - rtc@68 {
5970 - compatible = "dallas,ds3232";
5971 - reg = <0x68>;
5972 - };
5973 - };
5974
5975 - i2c@2 {
5976 - #address-cells = <1>;
5977 - #size-cells = <0>;
5978 - reg = <0x02>;
5979 -
5980 - ina220@40 {
5981 - compatible = "ti,ina220";
5982 - reg = <0x40>;
5983 - shunt-resistor = <500>;
5984 - };
5985 -
5986 - ina220@41 {
5987 - compatible = "ti,ina220";
5988 - reg = <0x41>;
5989 - shunt-resistor = <1000>;
5990 - };
5991 - };
5992 -
5993 - i2c@3 {
5994 - #address-cells = <1>;
5995 - #size-cells = <0>;
5996 - reg = <0x3>;
5997 -
5998 - adt7481@4c {
5999 - compatible = "adi,adt7461";
6000 - reg = <0x4c>;
6001 + /* Child MDIO buses, one for each riser card:
6002 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
6003 + * VSC8234 PHYs on the riser cards.
6004 + */
6005 +
6006 + mdio_mux3: mdio@60 {
6007 + reg = <0x60>;
6008 + #address-cells = <1>;
6009 + #size-cells = <0>;
6010 +
6011 + mdio0_phy12: mdio_phy0@1c {
6012 + reg = <0x1c>;
6013 + phy-connection-type = "sgmii";
6014 + };
6015 + mdio0_phy13: mdio_phy1@1d {
6016 + reg = <0x1d>;
6017 + phy-connection-type = "sgmii";
6018 + };
6019 + mdio0_phy14: mdio_phy2@1e {
6020 + reg = <0x1e>;
6021 + phy-connection-type = "sgmii";
6022 + };
6023 + mdio0_phy15: mdio_phy3@1f {
6024 + reg = <0x1f>;
6025 + phy-connection-type = "sgmii";
6026 + };
6027 };
6028 };
6029 };
6030 };
6031
6032 -&i2c1 {
6033 - status = "disabled";
6034 -};
6035 -
6036 -&i2c2 {
6037 - status = "disabled";
6038 -};
6039 -
6040 -&i2c3 {
6041 - status = "disabled";
6042 -};
6043 -
6044 -&dspi {
6045 - status = "okay";
6046 - dflash0: n25q128a {
6047 - #address-cells = <1>;
6048 - #size-cells = <1>;
6049 - compatible = "st,m25p80";
6050 - spi-max-frequency = <3000000>;
6051 - reg = <0>;
6052 - };
6053 - dflash1: sst25wf040b {
6054 - #address-cells = <1>;
6055 - #size-cells = <1>;
6056 - compatible = "st,m25p80";
6057 - spi-max-frequency = <3000000>;
6058 - reg = <1>;
6059 - };
6060 - dflash2: en25s64 {
6061 - #address-cells = <1>;
6062 - #size-cells = <1>;
6063 - compatible = "st,m25p80";
6064 - spi-max-frequency = <3000000>;
6065 - reg = <2>;
6066 - };
6067 -};
6068 -
6069 -&qspi {
6070 - status = "okay";
6071 - flash0: s25fl256s1@0 {
6072 - #address-cells = <1>;
6073 - #size-cells = <1>;
6074 - compatible = "st,m25p80";
6075 - spi-max-frequency = <20000000>;
6076 - reg = <0>;
6077 - };
6078 - flash2: s25fl256s1@2 {
6079 - #address-cells = <1>;
6080 - #size-cells = <1>;
6081 - compatible = "st,m25p80";
6082 - spi-max-frequency = <20000000>;
6083 - reg = <0>;
6084 - };
6085 -};
6086 -
6087 -&sata0 {
6088 - status = "okay";
6089 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
6090 +&dpmac9 {
6091 + phy-handle = <&mdio0_phy12>;
6092 };
6093 -
6094 -&sata1 {
6095 - status = "okay";
6096 +&dpmac10 {
6097 + phy-handle = <&mdio0_phy13>;
6098 };
6099 -
6100 -&usb0 {
6101 - status = "okay";
6102 +&dpmac11 {
6103 + phy-handle = <&mdio0_phy14>;
6104 };
6105 -
6106 -&usb1 {
6107 - status = "okay";
6108 +&dpmac12 {
6109 + phy-handle = <&mdio0_phy15>;
6110 };
6111 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6112 index ad0ebb8a..025f0f54 100644
6113 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6114 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts
6115 @@ -1,8 +1,10 @@
6116 /*
6117 * Device Tree file for Freescale LS2080a RDB Board.
6118 *
6119 - * Copyright (C) 2015, Freescale Semiconductor
6120 + * Copyright 2016 Freescale Semiconductor, Inc.
6121 + * Copyright 2017 NXP
6122 *
6123 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6124 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6125 *
6126 * This file is dual-licensed: you can use it either under the terms
6127 @@ -46,125 +48,94 @@
6128
6129 /dts-v1/;
6130
6131 -/include/ "fsl-ls2080a.dtsi"
6132 +#include "fsl-ls2080a.dtsi"
6133 +#include "fsl-ls208xa-rdb.dtsi"
6134
6135 / {
6136 model = "Freescale Layerscape 2080a RDB Board";
6137 compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
6138
6139 - aliases {
6140 - serial0 = &serial0;
6141 - serial1 = &serial1;
6142 - };
6143 -
6144 chosen {
6145 stdout-path = "serial1:115200n8";
6146 };
6147 };
6148
6149 -&esdhc {
6150 - status = "okay";
6151 -};
6152 -
6153 -&ifc {
6154 - status = "okay";
6155 - #address-cells = <2>;
6156 - #size-cells = <1>;
6157 - ranges = <0x0 0x0 0x5 0x80000000 0x08000000
6158 - 0x2 0x0 0x5 0x30000000 0x00010000
6159 - 0x3 0x0 0x5 0x20000000 0x00010000>;
6160 -
6161 - nor@0,0 {
6162 - #address-cells = <1>;
6163 - #size-cells = <1>;
6164 - compatible = "cfi-flash";
6165 - reg = <0x0 0x0 0x8000000>;
6166 - bank-width = <2>;
6167 - device-width = <1>;
6168 +&emdio1 {
6169 + status = "disabled";
6170 + /* CS4340 PHYs */
6171 + mdio1_phy1: emdio1_phy@1 {
6172 + reg = <0x10>;
6173 + phy-connection-type = "xfi";
6174 };
6175 -
6176 - nand@2,0 {
6177 - compatible = "fsl,ifc-nand";
6178 - reg = <0x2 0x0 0x10000>;
6179 + mdio1_phy2: emdio1_phy@2 {
6180 + reg = <0x11>;
6181 + phy-connection-type = "xfi";
6182 };
6183 -
6184 - cpld@3,0 {
6185 - reg = <0x3 0x0 0x10000>;
6186 - compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
6187 + mdio1_phy3: emdio1_phy@3 {
6188 + reg = <0x12>;
6189 + phy-connection-type = "xfi";
6190 };
6191 -
6192 -};
6193 -
6194 -&i2c0 {
6195 - status = "okay";
6196 - pca9547@75 {
6197 - compatible = "nxp,pca9547";
6198 - reg = <0x75>;
6199 - #address-cells = <1>;
6200 - #size-cells = <0>;
6201 - status = "disabled";
6202 - i2c@1 {
6203 - #address-cells = <1>;
6204 - #size-cells = <0>;
6205 - reg = <0x01>;
6206 - rtc@68 {
6207 - compatible = "dallas,ds3232";
6208 - reg = <0x68>;
6209 - };
6210 - };
6211 -
6212 - i2c@3 {
6213 - #address-cells = <1>;
6214 - #size-cells = <0>;
6215 - reg = <0x3>;
6216 -
6217 - adt7481@4c {
6218 - compatible = "adi,adt7461";
6219 - reg = <0x4c>;
6220 - };
6221 - };
6222 + mdio1_phy4: emdio1_phy@4 {
6223 + reg = <0x13>;
6224 + phy-connection-type = "xfi";
6225 };
6226 };
6227
6228 -&i2c1 {
6229 - status = "disabled";
6230 -};
6231 -
6232 -&i2c2 {
6233 - status = "disabled";
6234 -};
6235 -
6236 -&i2c3 {
6237 - status = "disabled";
6238 -};
6239 -
6240 -&dspi {
6241 - status = "okay";
6242 - dflash0: n25q512a {
6243 - #address-cells = <1>;
6244 - #size-cells = <1>;
6245 - compatible = "st,m25p80";
6246 - spi-max-frequency = <3000000>;
6247 - reg = <0>;
6248 +&emdio2 {
6249 + /* AQR405 PHYs */
6250 + mdio2_phy1: emdio2_phy@1 {
6251 + compatible = "ethernet-phy-ieee802.3-c45";
6252 + interrupts = <0 1 0x4>; /* Level high type */
6253 + reg = <0x0>;
6254 + phy-connection-type = "xfi";
6255 + };
6256 + mdio2_phy2: emdio2_phy@2 {
6257 + compatible = "ethernet-phy-ieee802.3-c45";
6258 + interrupts = <0 2 0x4>; /* Level high type */
6259 + reg = <0x1>;
6260 + phy-connection-type = "xfi";
6261 + };
6262 + mdio2_phy3: emdio2_phy@3 {
6263 + compatible = "ethernet-phy-ieee802.3-c45";
6264 + interrupts = <0 4 0x4>; /* Level high type */
6265 + reg = <0x2>;
6266 + phy-connection-type = "xfi";
6267 + };
6268 + mdio2_phy4: emdio2_phy@4 {
6269 + compatible = "ethernet-phy-ieee802.3-c45";
6270 + interrupts = <0 5 0x4>; /* Level high type */
6271 + reg = <0x3>;
6272 + phy-connection-type = "xfi";
6273 };
6274 };
6275
6276 -&qspi {
6277 - status = "disabled";
6278 -};
6279 +/* Update DPMAC connections to external PHYs, under the assumption of
6280 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
6281 + */
6282 +/* Leave Cortina nodes commented out until driver is integrated
6283 + *&dpmac1 {
6284 + * phy-handle = <&mdio1_phy1>;
6285 + *};
6286 + *&dpmac2 {
6287 + * phy-handle = <&mdio1_phy2>;
6288 + *};
6289 + *&dpmac3 {
6290 + * phy-handle = <&mdio1_phy3>;
6291 + *};
6292 + *&dpmac4 {
6293 + * phy-handle = <&mdio1_phy4>;
6294 + *};
6295 + */
6296
6297 -&sata0 {
6298 - status = "okay";
6299 +&dpmac5 {
6300 + phy-handle = <&mdio2_phy1>;
6301 };
6302 -
6303 -&sata1 {
6304 - status = "okay";
6305 +&dpmac6 {
6306 + phy-handle = <&mdio2_phy2>;
6307 };
6308 -
6309 -&usb0 {
6310 - status = "okay";
6311 +&dpmac7 {
6312 + phy-handle = <&mdio2_phy3>;
6313 };
6314 -
6315 -&usb1 {
6316 - status = "okay";
6317 +&dpmac8 {
6318 + phy-handle = <&mdio2_phy4>;
6319 };
6320 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6321 index 505d0380..fbbb73e5 100644
6322 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6323 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts
6324 @@ -1,7 +1,7 @@
6325 /*
6326 * Device Tree file for Freescale LS2080a software Simulator model
6327 *
6328 - * Copyright (C) 2014-2015, Freescale Semiconductor
6329 + * Copyright 2014-2015 Freescale Semiconductor, Inc.
6330 *
6331 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6332 *
6333 @@ -46,17 +46,12 @@
6334
6335 /dts-v1/;
6336
6337 -/include/ "fsl-ls2080a.dtsi"
6338 +#include "fsl-ls2080a.dtsi"
6339
6340 / {
6341 model = "Freescale Layerscape 2080a software Simulator model";
6342 compatible = "fsl,ls2080a-simu", "fsl,ls2080a";
6343
6344 - aliases {
6345 - serial0 = &serial0;
6346 - serial1 = &serial1;
6347 - };
6348 -
6349 ethernet@2210000 {
6350 compatible = "smsc,lan91c111";
6351 reg = <0x0 0x2210000 0x0 0x100>;
6352 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6353 index 7f0dc13b..71f15fab 100644
6354 --- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6355 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi
6356 @@ -1,8 +1,9 @@
6357 /*
6358 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
6359 *
6360 - * Copyright (C) 2014-2015, Freescale Semiconductor
6361 + * Copyright 2014-2016 Freescale Semiconductor, Inc.
6362 *
6363 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
6364 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
6365 *
6366 * This file is dual-licensed: you can use it either under the terms
6367 @@ -44,696 +45,132 @@
6368 * OTHER DEALINGS IN THE SOFTWARE.
6369 */
6370
6371 -/ {
6372 - compatible = "fsl,ls2080a";
6373 - interrupt-parent = <&gic>;
6374 - #address-cells = <2>;
6375 - #size-cells = <2>;
6376 +#include "fsl-ls208xa.dtsi"
6377
6378 - cpus {
6379 - #address-cells = <1>;
6380 - #size-cells = <0>;
6381 -
6382 - /*
6383 - * We expect the enable-method for cpu's to be "psci", but this
6384 - * is dependent on the SoC FW, which will fill this in.
6385 - *
6386 - * Currently supported enable-method is psci v0.2
6387 - */
6388 -
6389 - /* We have 4 clusters having 2 Cortex-A57 cores each */
6390 - cpu@0 {
6391 - device_type = "cpu";
6392 - compatible = "arm,cortex-a57";
6393 - reg = <0x0>;
6394 - clocks = <&clockgen 1 0>;
6395 - next-level-cache = <&cluster0_l2>;
6396 - };
6397 -
6398 - cpu@1 {
6399 - device_type = "cpu";
6400 - compatible = "arm,cortex-a57";
6401 - reg = <0x1>;
6402 - clocks = <&clockgen 1 0>;
6403 - next-level-cache = <&cluster0_l2>;
6404 - };
6405 -
6406 - cpu@100 {
6407 - device_type = "cpu";
6408 - compatible = "arm,cortex-a57";
6409 - reg = <0x100>;
6410 - clocks = <&clockgen 1 1>;
6411 - next-level-cache = <&cluster1_l2>;
6412 - };
6413 -
6414 - cpu@101 {
6415 - device_type = "cpu";
6416 - compatible = "arm,cortex-a57";
6417 - reg = <0x101>;
6418 - clocks = <&clockgen 1 1>;
6419 - next-level-cache = <&cluster1_l2>;
6420 - };
6421 -
6422 - cpu@200 {
6423 - device_type = "cpu";
6424 - compatible = "arm,cortex-a57";
6425 - reg = <0x200>;
6426 - clocks = <&clockgen 1 2>;
6427 - next-level-cache = <&cluster2_l2>;
6428 - };
6429 -
6430 - cpu@201 {
6431 - device_type = "cpu";
6432 - compatible = "arm,cortex-a57";
6433 - reg = <0x201>;
6434 - clocks = <&clockgen 1 2>;
6435 - next-level-cache = <&cluster2_l2>;
6436 - };
6437 -
6438 - cpu@300 {
6439 - device_type = "cpu";
6440 - compatible = "arm,cortex-a57";
6441 - reg = <0x300>;
6442 - clocks = <&clockgen 1 3>;
6443 - next-level-cache = <&cluster3_l2>;
6444 - };
6445 -
6446 - cpu@301 {
6447 - device_type = "cpu";
6448 - compatible = "arm,cortex-a57";
6449 - reg = <0x301>;
6450 - clocks = <&clockgen 1 3>;
6451 - next-level-cache = <&cluster3_l2>;
6452 - };
6453 -
6454 - cluster0_l2: l2-cache0 {
6455 - compatible = "cache";
6456 - };
6457 -
6458 - cluster1_l2: l2-cache1 {
6459 - compatible = "cache";
6460 - };
6461 -
6462 - cluster2_l2: l2-cache2 {
6463 - compatible = "cache";
6464 - };
6465 -
6466 - cluster3_l2: l2-cache3 {
6467 - compatible = "cache";
6468 - };
6469 +&cpu {
6470 + cpu0: cpu@0 {
6471 + device_type = "cpu";
6472 + compatible = "arm,cortex-a57";
6473 + reg = <0x0>;
6474 + clocks = <&clockgen 1 0>;
6475 + next-level-cache = <&cluster0_l2>;
6476 + #cooling-cells = <2>;
6477 };
6478
6479 - memory@80000000 {
6480 - device_type = "memory";
6481 - reg = <0x00000000 0x80000000 0 0x80000000>;
6482 - /* DRAM space - 1, size : 2 GB DRAM */
6483 + cpu1: cpu@1 {
6484 + device_type = "cpu";
6485 + compatible = "arm,cortex-a57";
6486 + reg = <0x1>;
6487 + clocks = <&clockgen 1 0>;
6488 + next-level-cache = <&cluster0_l2>;
6489 };
6490
6491 - sysclk: sysclk {
6492 - compatible = "fixed-clock";
6493 - #clock-cells = <0>;
6494 - clock-frequency = <100000000>;
6495 - clock-output-names = "sysclk";
6496 + cpu2: cpu@100 {
6497 + device_type = "cpu";
6498 + compatible = "arm,cortex-a57";
6499 + reg = <0x100>;
6500 + clocks = <&clockgen 1 1>;
6501 + next-level-cache = <&cluster1_l2>;
6502 + #cooling-cells = <2>;
6503 };
6504
6505 - gic: interrupt-controller@6000000 {
6506 - compatible = "arm,gic-v3";
6507 - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
6508 - <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
6509 - <0x0 0x0c0c0000 0 0x2000>, /* GICC */
6510 - <0x0 0x0c0d0000 0 0x1000>, /* GICH */
6511 - <0x0 0x0c0e0000 0 0x20000>; /* GICV */
6512 - #interrupt-cells = <3>;
6513 - #address-cells = <2>;
6514 - #size-cells = <2>;
6515 - ranges;
6516 - interrupt-controller;
6517 - interrupts = <1 9 0x4>;
6518 -
6519 - its: gic-its@6020000 {
6520 - compatible = "arm,gic-v3-its";
6521 - msi-controller;
6522 - reg = <0x0 0x6020000 0 0x20000>;
6523 - };
6524 + cpu3: cpu@101 {
6525 + device_type = "cpu";
6526 + compatible = "arm,cortex-a57";
6527 + reg = <0x101>;
6528 + clocks = <&clockgen 1 1>;
6529 + next-level-cache = <&cluster1_l2>;
6530 };
6531
6532 - rstcr: syscon@1e60000 {
6533 - compatible = "fsl,ls2080a-rstcr", "syscon";
6534 - reg = <0x0 0x1e60000 0x0 0x4>;
6535 + cpu4: cpu@200 {
6536 + device_type = "cpu";
6537 + compatible = "arm,cortex-a57";
6538 + reg = <0x200>;
6539 + clocks = <&clockgen 1 2>;
6540 + next-level-cache = <&cluster2_l2>;
6541 + #cooling-cells = <2>;
6542 };
6543
6544 - reboot {
6545 - compatible ="syscon-reboot";
6546 - regmap = <&rstcr>;
6547 - offset = <0x0>;
6548 - mask = <0x2>;
6549 + cpu5: cpu@201 {
6550 + device_type = "cpu";
6551 + compatible = "arm,cortex-a57";
6552 + reg = <0x201>;
6553 + clocks = <&clockgen 1 2>;
6554 + next-level-cache = <&cluster2_l2>;
6555 };
6556
6557 - timer {
6558 - compatible = "arm,armv8-timer";
6559 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
6560 - <1 14 4>, /* Physical Non-Secure PPI, active-low */
6561 - <1 11 4>, /* Virtual PPI, active-low */
6562 - <1 10 4>; /* Hypervisor PPI, active-low */
6563 - fsl,erratum-a008585;
6564 + cpu6: cpu@300 {
6565 + device_type = "cpu";
6566 + compatible = "arm,cortex-a57";
6567 + reg = <0x300>;
6568 + clocks = <&clockgen 1 3>;
6569 + next-level-cache = <&cluster3_l2>;
6570 + #cooling-cells = <2>;
6571 };
6572
6573 - pmu {
6574 - compatible = "arm,armv8-pmuv3";
6575 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
6576 + cpu7: cpu@301 {
6577 + device_type = "cpu";
6578 + compatible = "arm,cortex-a57";
6579 + reg = <0x301>;
6580 + clocks = <&clockgen 1 3>;
6581 + next-level-cache = <&cluster3_l2>;
6582 };
6583
6584 - soc {
6585 - compatible = "simple-bus";
6586 - #address-cells = <2>;
6587 - #size-cells = <2>;
6588 - ranges;
6589 -
6590 - clockgen: clocking@1300000 {
6591 - compatible = "fsl,ls2080a-clockgen";
6592 - reg = <0 0x1300000 0 0xa0000>;
6593 - #clock-cells = <2>;
6594 - clocks = <&sysclk>;
6595 - };
6596 -
6597 - serial0: serial@21c0500 {
6598 - compatible = "fsl,ns16550", "ns16550a";
6599 - reg = <0x0 0x21c0500 0x0 0x100>;
6600 - clocks = <&clockgen 4 3>;
6601 - interrupts = <0 32 0x4>; /* Level high type */
6602 - };
6603 -
6604 - serial1: serial@21c0600 {
6605 - compatible = "fsl,ns16550", "ns16550a";
6606 - reg = <0x0 0x21c0600 0x0 0x100>;
6607 - clocks = <&clockgen 4 3>;
6608 - interrupts = <0 32 0x4>; /* Level high type */
6609 - };
6610 -
6611 - cluster1_core0_watchdog: wdt@c000000 {
6612 - compatible = "arm,sp805-wdt", "arm,primecell";
6613 - reg = <0x0 0xc000000 0x0 0x1000>;
6614 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6615 - clock-names = "apb_pclk", "wdog_clk";
6616 - };
6617 -
6618 - cluster1_core1_watchdog: wdt@c010000 {
6619 - compatible = "arm,sp805-wdt", "arm,primecell";
6620 - reg = <0x0 0xc010000 0x0 0x1000>;
6621 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6622 - clock-names = "apb_pclk", "wdog_clk";
6623 - };
6624 -
6625 - cluster2_core0_watchdog: wdt@c100000 {
6626 - compatible = "arm,sp805-wdt", "arm,primecell";
6627 - reg = <0x0 0xc100000 0x0 0x1000>;
6628 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6629 - clock-names = "apb_pclk", "wdog_clk";
6630 - };
6631 -
6632 - cluster2_core1_watchdog: wdt@c110000 {
6633 - compatible = "arm,sp805-wdt", "arm,primecell";
6634 - reg = <0x0 0xc110000 0x0 0x1000>;
6635 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6636 - clock-names = "apb_pclk", "wdog_clk";
6637 - };
6638 -
6639 - cluster3_core0_watchdog: wdt@c200000 {
6640 - compatible = "arm,sp805-wdt", "arm,primecell";
6641 - reg = <0x0 0xc200000 0x0 0x1000>;
6642 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6643 - clock-names = "apb_pclk", "wdog_clk";
6644 - };
6645 -
6646 - cluster3_core1_watchdog: wdt@c210000 {
6647 - compatible = "arm,sp805-wdt", "arm,primecell";
6648 - reg = <0x0 0xc210000 0x0 0x1000>;
6649 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6650 - clock-names = "apb_pclk", "wdog_clk";
6651 - };
6652 -
6653 - cluster4_core0_watchdog: wdt@c300000 {
6654 - compatible = "arm,sp805-wdt", "arm,primecell";
6655 - reg = <0x0 0xc300000 0x0 0x1000>;
6656 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6657 - clock-names = "apb_pclk", "wdog_clk";
6658 - };
6659 -
6660 - cluster4_core1_watchdog: wdt@c310000 {
6661 - compatible = "arm,sp805-wdt", "arm,primecell";
6662 - reg = <0x0 0xc310000 0x0 0x1000>;
6663 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6664 - clock-names = "apb_pclk", "wdog_clk";
6665 - };
6666 -
6667 - fsl_mc: fsl-mc@80c000000 {
6668 - compatible = "fsl,qoriq-mc";
6669 - reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
6670 - <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
6671 - msi-parent = <&its>;
6672 - #address-cells = <3>;
6673 - #size-cells = <1>;
6674 -
6675 - /*
6676 - * Region type 0x0 - MC portals
6677 - * Region type 0x1 - QBMAN portals
6678 - */
6679 - ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
6680 - 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
6681 -
6682 - /*
6683 - * Define the maximum number of MACs present on the SoC.
6684 - */
6685 - dpmacs {
6686 - #address-cells = <1>;
6687 - #size-cells = <0>;
6688 -
6689 - dpmac1: dpmac@1 {
6690 - compatible = "fsl,qoriq-mc-dpmac";
6691 - reg = <0x1>;
6692 - };
6693 -
6694 - dpmac2: dpmac@2 {
6695 - compatible = "fsl,qoriq-mc-dpmac";
6696 - reg = <0x2>;
6697 - };
6698 -
6699 - dpmac3: dpmac@3 {
6700 - compatible = "fsl,qoriq-mc-dpmac";
6701 - reg = <0x3>;
6702 - };
6703 -
6704 - dpmac4: dpmac@4 {
6705 - compatible = "fsl,qoriq-mc-dpmac";
6706 - reg = <0x4>;
6707 - };
6708 -
6709 - dpmac5: dpmac@5 {
6710 - compatible = "fsl,qoriq-mc-dpmac";
6711 - reg = <0x5>;
6712 - };
6713 -
6714 - dpmac6: dpmac@6 {
6715 - compatible = "fsl,qoriq-mc-dpmac";
6716 - reg = <0x6>;
6717 - };
6718 -
6719 - dpmac7: dpmac@7 {
6720 - compatible = "fsl,qoriq-mc-dpmac";
6721 - reg = <0x7>;
6722 - };
6723 -
6724 - dpmac8: dpmac@8 {
6725 - compatible = "fsl,qoriq-mc-dpmac";
6726 - reg = <0x8>;
6727 - };
6728 -
6729 - dpmac9: dpmac@9 {
6730 - compatible = "fsl,qoriq-mc-dpmac";
6731 - reg = <0x9>;
6732 - };
6733 -
6734 - dpmac10: dpmac@a {
6735 - compatible = "fsl,qoriq-mc-dpmac";
6736 - reg = <0xa>;
6737 - };
6738 -
6739 - dpmac11: dpmac@b {
6740 - compatible = "fsl,qoriq-mc-dpmac";
6741 - reg = <0xb>;
6742 - };
6743 -
6744 - dpmac12: dpmac@c {
6745 - compatible = "fsl,qoriq-mc-dpmac";
6746 - reg = <0xc>;
6747 - };
6748 -
6749 - dpmac13: dpmac@d {
6750 - compatible = "fsl,qoriq-mc-dpmac";
6751 - reg = <0xd>;
6752 - };
6753 -
6754 - dpmac14: dpmac@e {
6755 - compatible = "fsl,qoriq-mc-dpmac";
6756 - reg = <0xe>;
6757 - };
6758 -
6759 - dpmac15: dpmac@f {
6760 - compatible = "fsl,qoriq-mc-dpmac";
6761 - reg = <0xf>;
6762 - };
6763 -
6764 - dpmac16: dpmac@10 {
6765 - compatible = "fsl,qoriq-mc-dpmac";
6766 - reg = <0x10>;
6767 - };
6768 - };
6769 - };
6770 -
6771 - smmu: iommu@5000000 {
6772 - compatible = "arm,mmu-500";
6773 - reg = <0 0x5000000 0 0x800000>;
6774 - #global-interrupts = <12>;
6775 - interrupts = <0 13 4>, /* global secure fault */
6776 - <0 14 4>, /* combined secure interrupt */
6777 - <0 15 4>, /* global non-secure fault */
6778 - <0 16 4>, /* combined non-secure interrupt */
6779 - /* performance counter interrupts 0-7 */
6780 - <0 211 4>, <0 212 4>,
6781 - <0 213 4>, <0 214 4>,
6782 - <0 215 4>, <0 216 4>,
6783 - <0 217 4>, <0 218 4>,
6784 - /* per context interrupt, 64 interrupts */
6785 - <0 146 4>, <0 147 4>,
6786 - <0 148 4>, <0 149 4>,
6787 - <0 150 4>, <0 151 4>,
6788 - <0 152 4>, <0 153 4>,
6789 - <0 154 4>, <0 155 4>,
6790 - <0 156 4>, <0 157 4>,
6791 - <0 158 4>, <0 159 4>,
6792 - <0 160 4>, <0 161 4>,
6793 - <0 162 4>, <0 163 4>,
6794 - <0 164 4>, <0 165 4>,
6795 - <0 166 4>, <0 167 4>,
6796 - <0 168 4>, <0 169 4>,
6797 - <0 170 4>, <0 171 4>,
6798 - <0 172 4>, <0 173 4>,
6799 - <0 174 4>, <0 175 4>,
6800 - <0 176 4>, <0 177 4>,
6801 - <0 178 4>, <0 179 4>,
6802 - <0 180 4>, <0 181 4>,
6803 - <0 182 4>, <0 183 4>,
6804 - <0 184 4>, <0 185 4>,
6805 - <0 186 4>, <0 187 4>,
6806 - <0 188 4>, <0 189 4>,
6807 - <0 190 4>, <0 191 4>,
6808 - <0 192 4>, <0 193 4>,
6809 - <0 194 4>, <0 195 4>,
6810 - <0 196 4>, <0 197 4>,
6811 - <0 198 4>, <0 199 4>,
6812 - <0 200 4>, <0 201 4>,
6813 - <0 202 4>, <0 203 4>,
6814 - <0 204 4>, <0 205 4>,
6815 - <0 206 4>, <0 207 4>,
6816 - <0 208 4>, <0 209 4>;
6817 - mmu-masters = <&fsl_mc 0x300 0>;
6818 - };
6819 -
6820 - dspi: dspi@2100000 {
6821 - status = "disabled";
6822 - compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
6823 - #address-cells = <1>;
6824 - #size-cells = <0>;
6825 - reg = <0x0 0x2100000 0x0 0x10000>;
6826 - interrupts = <0 26 0x4>; /* Level high type */
6827 - clocks = <&clockgen 4 3>;
6828 - clock-names = "dspi";
6829 - spi-num-chipselects = <5>;
6830 - bus-num = <0>;
6831 - };
6832 -
6833 - esdhc: esdhc@2140000 {
6834 - status = "disabled";
6835 - compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
6836 - reg = <0x0 0x2140000 0x0 0x10000>;
6837 - interrupts = <0 28 0x4>; /* Level high type */
6838 - clock-frequency = <0>; /* Updated by bootloader */
6839 - voltage-ranges = <1800 1800 3300 3300>;
6840 - sdhci,auto-cmd12;
6841 - little-endian;
6842 - bus-width = <4>;
6843 - };
6844 -
6845 - gpio0: gpio@2300000 {
6846 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6847 - reg = <0x0 0x2300000 0x0 0x10000>;
6848 - interrupts = <0 36 0x4>; /* Level high type */
6849 - gpio-controller;
6850 - little-endian;
6851 - #gpio-cells = <2>;
6852 - interrupt-controller;
6853 - #interrupt-cells = <2>;
6854 - };
6855 -
6856 - gpio1: gpio@2310000 {
6857 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6858 - reg = <0x0 0x2310000 0x0 0x10000>;
6859 - interrupts = <0 36 0x4>; /* Level high type */
6860 - gpio-controller;
6861 - little-endian;
6862 - #gpio-cells = <2>;
6863 - interrupt-controller;
6864 - #interrupt-cells = <2>;
6865 - };
6866 -
6867 - gpio2: gpio@2320000 {
6868 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6869 - reg = <0x0 0x2320000 0x0 0x10000>;
6870 - interrupts = <0 37 0x4>; /* Level high type */
6871 - gpio-controller;
6872 - little-endian;
6873 - #gpio-cells = <2>;
6874 - interrupt-controller;
6875 - #interrupt-cells = <2>;
6876 - };
6877 -
6878 - gpio3: gpio@2330000 {
6879 - compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
6880 - reg = <0x0 0x2330000 0x0 0x10000>;
6881 - interrupts = <0 37 0x4>; /* Level high type */
6882 - gpio-controller;
6883 - little-endian;
6884 - #gpio-cells = <2>;
6885 - interrupt-controller;
6886 - #interrupt-cells = <2>;
6887 - };
6888 -
6889 - i2c0: i2c@2000000 {
6890 - status = "disabled";
6891 - compatible = "fsl,vf610-i2c";
6892 - #address-cells = <1>;
6893 - #size-cells = <0>;
6894 - reg = <0x0 0x2000000 0x0 0x10000>;
6895 - interrupts = <0 34 0x4>; /* Level high type */
6896 - clock-names = "i2c";
6897 - clocks = <&clockgen 4 3>;
6898 - };
6899 -
6900 - i2c1: i2c@2010000 {
6901 - status = "disabled";
6902 - compatible = "fsl,vf610-i2c";
6903 - #address-cells = <1>;
6904 - #size-cells = <0>;
6905 - reg = <0x0 0x2010000 0x0 0x10000>;
6906 - interrupts = <0 34 0x4>; /* Level high type */
6907 - clock-names = "i2c";
6908 - clocks = <&clockgen 4 3>;
6909 - };
6910 -
6911 - i2c2: i2c@2020000 {
6912 - status = "disabled";
6913 - compatible = "fsl,vf610-i2c";
6914 - #address-cells = <1>;
6915 - #size-cells = <0>;
6916 - reg = <0x0 0x2020000 0x0 0x10000>;
6917 - interrupts = <0 35 0x4>; /* Level high type */
6918 - clock-names = "i2c";
6919 - clocks = <&clockgen 4 3>;
6920 - };
6921 -
6922 - i2c3: i2c@2030000 {
6923 - status = "disabled";
6924 - compatible = "fsl,vf610-i2c";
6925 - #address-cells = <1>;
6926 - #size-cells = <0>;
6927 - reg = <0x0 0x2030000 0x0 0x10000>;
6928 - interrupts = <0 35 0x4>; /* Level high type */
6929 - clock-names = "i2c";
6930 - clocks = <&clockgen 4 3>;
6931 - };
6932 -
6933 - ifc: ifc@2240000 {
6934 - compatible = "fsl,ifc", "simple-bus";
6935 - reg = <0x0 0x2240000 0x0 0x20000>;
6936 - interrupts = <0 21 0x4>; /* Level high type */
6937 - little-endian;
6938 - #address-cells = <2>;
6939 - #size-cells = <1>;
6940 + cluster0_l2: l2-cache0 {
6941 + compatible = "cache";
6942 + };
6943
6944 - ranges = <0 0 0x5 0x80000000 0x08000000
6945 - 2 0 0x5 0x30000000 0x00010000
6946 - 3 0 0x5 0x20000000 0x00010000>;
6947 - };
6948 + cluster1_l2: l2-cache1 {
6949 + compatible = "cache";
6950 + };
6951
6952 - qspi: quadspi@20c0000 {
6953 - status = "disabled";
6954 - compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
6955 - #address-cells = <1>;
6956 - #size-cells = <0>;
6957 - reg = <0x0 0x20c0000 0x0 0x10000>,
6958 - <0x0 0x20000000 0x0 0x10000000>;
6959 - reg-names = "QuadSPI", "QuadSPI-memory";
6960 - interrupts = <0 25 0x4>; /* Level high type */
6961 - clocks = <&clockgen 4 3>, <&clockgen 4 3>;
6962 - clock-names = "qspi_en", "qspi";
6963 - };
6964 + cluster2_l2: l2-cache2 {
6965 + compatible = "cache";
6966 + };
6967
6968 - pcie@3400000 {
6969 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
6970 - "snps,dw-pcie";
6971 - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
6972 - 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
6973 - reg-names = "regs", "config";
6974 - interrupts = <0 108 0x4>; /* Level high type */
6975 - interrupt-names = "intr";
6976 - #address-cells = <3>;
6977 - #size-cells = <2>;
6978 - device_type = "pci";
6979 - dma-coherent;
6980 - num-lanes = <4>;
6981 - bus-range = <0x0 0xff>;
6982 - ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
6983 - 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
6984 - msi-parent = <&its>;
6985 - #interrupt-cells = <1>;
6986 - interrupt-map-mask = <0 0 0 7>;
6987 - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
6988 - <0000 0 0 2 &gic 0 0 0 110 4>,
6989 - <0000 0 0 3 &gic 0 0 0 111 4>,
6990 - <0000 0 0 4 &gic 0 0 0 112 4>;
6991 - };
6992 + cluster3_l2: l2-cache3 {
6993 + compatible = "cache";
6994 + };
6995 +};
6996
6997 - pcie@3500000 {
6998 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
6999 - "snps,dw-pcie";
7000 - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7001 - 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7002 - reg-names = "regs", "config";
7003 - interrupts = <0 113 0x4>; /* Level high type */
7004 - interrupt-names = "intr";
7005 - #address-cells = <3>;
7006 - #size-cells = <2>;
7007 - device_type = "pci";
7008 - dma-coherent;
7009 - num-lanes = <4>;
7010 - bus-range = <0x0 0xff>;
7011 - ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7012 - 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7013 - msi-parent = <&its>;
7014 - #interrupt-cells = <1>;
7015 - interrupt-map-mask = <0 0 0 7>;
7016 - interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
7017 - <0000 0 0 2 &gic 0 0 0 115 4>,
7018 - <0000 0 0 3 &gic 0 0 0 116 4>,
7019 - <0000 0 0 4 &gic 0 0 0 117 4>;
7020 - };
7021 +&usb0 {
7022 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7023 + snps,dma-snooping;
7024 +};
7025
7026 - pcie@3600000 {
7027 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7028 - "snps,dw-pcie";
7029 - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7030 - 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7031 - reg-names = "regs", "config";
7032 - interrupts = <0 118 0x4>; /* Level high type */
7033 - interrupt-names = "intr";
7034 - #address-cells = <3>;
7035 - #size-cells = <2>;
7036 - device_type = "pci";
7037 - dma-coherent;
7038 - num-lanes = <8>;
7039 - bus-range = <0x0 0xff>;
7040 - ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7041 - 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7042 - msi-parent = <&its>;
7043 - #interrupt-cells = <1>;
7044 - interrupt-map-mask = <0 0 0 7>;
7045 - interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
7046 - <0000 0 0 2 &gic 0 0 0 120 4>,
7047 - <0000 0 0 3 &gic 0 0 0 121 4>,
7048 - <0000 0 0 4 &gic 0 0 0 122 4>;
7049 - };
7050 +&usb1 {
7051 + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
7052 + snps,dma-snooping;
7053 +};
7054
7055 - pcie@3700000 {
7056 - compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
7057 - "snps,dw-pcie";
7058 - reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7059 - 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7060 - reg-names = "regs", "config";
7061 - interrupts = <0 123 0x4>; /* Level high type */
7062 - interrupt-names = "intr";
7063 - #address-cells = <3>;
7064 - #size-cells = <2>;
7065 - device_type = "pci";
7066 - dma-coherent;
7067 - num-lanes = <4>;
7068 - bus-range = <0x0 0xff>;
7069 - ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7070 - 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7071 - msi-parent = <&its>;
7072 - #interrupt-cells = <1>;
7073 - interrupt-map-mask = <0 0 0 7>;
7074 - interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
7075 - <0000 0 0 2 &gic 0 0 0 125 4>,
7076 - <0000 0 0 3 &gic 0 0 0 126 4>,
7077 - <0000 0 0 4 &gic 0 0 0 127 4>;
7078 - };
7079 +&pcie1 {
7080 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7081 + 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
7082
7083 - sata0: sata@3200000 {
7084 - status = "disabled";
7085 - compatible = "fsl,ls2080a-ahci";
7086 - reg = <0x0 0x3200000 0x0 0x10000>;
7087 - interrupts = <0 133 0x4>; /* Level high type */
7088 - clocks = <&clockgen 4 3>;
7089 - dma-coherent;
7090 - };
7091 + ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
7092 + 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7093 +};
7094
7095 - sata1: sata@3210000 {
7096 - status = "disabled";
7097 - compatible = "fsl,ls2080a-ahci";
7098 - reg = <0x0 0x3210000 0x0 0x10000>;
7099 - interrupts = <0 136 0x4>; /* Level high type */
7100 - clocks = <&clockgen 4 3>;
7101 - dma-coherent;
7102 - };
7103 +&pcie2 {
7104 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7105 + 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
7106
7107 - usb0: usb3@3100000 {
7108 - status = "disabled";
7109 - compatible = "snps,dwc3";
7110 - reg = <0x0 0x3100000 0x0 0x10000>;
7111 - interrupts = <0 80 0x4>; /* Level high type */
7112 - dr_mode = "host";
7113 - snps,quirk-frame-length-adjustment = <0x20>;
7114 - snps,dis_rxdet_inp3_quirk;
7115 - };
7116 + ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
7117 + 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7118 +};
7119
7120 - usb1: usb3@3110000 {
7121 - status = "disabled";
7122 - compatible = "snps,dwc3";
7123 - reg = <0x0 0x3110000 0x0 0x10000>;
7124 - interrupts = <0 81 0x4>; /* Level high type */
7125 - dr_mode = "host";
7126 - snps,quirk-frame-length-adjustment = <0x20>;
7127 - snps,dis_rxdet_inp3_quirk;
7128 - };
7129 +&pcie3 {
7130 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7131 + 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
7132
7133 - ccn@4000000 {
7134 - compatible = "arm,ccn-504";
7135 - reg = <0x0 0x04000000 0x0 0x01000000>;
7136 - interrupts = <0 12 4>;
7137 - };
7138 - };
7139 + ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
7140 + 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7141 +};
7142
7143 - ddr1: memory-controller@1080000 {
7144 - compatible = "fsl,qoriq-memory-controller";
7145 - reg = <0x0 0x1080000 0x0 0x1000>;
7146 - interrupts = <0 17 0x4>;
7147 - little-endian;
7148 - };
7149 +&pcie4 {
7150 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7151 + 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
7152
7153 - ddr2: memory-controller@1090000 {
7154 - compatible = "fsl,qoriq-memory-controller";
7155 - reg = <0x0 0x1090000 0x0 0x1000>;
7156 - interrupts = <0 18 0x4>;
7157 - little-endian;
7158 - };
7159 + ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
7160 + 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
7161 };
7162 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7163 new file mode 100644
7164 index 00000000..c3375bf7
7165 --- /dev/null
7166 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
7167 @@ -0,0 +1,161 @@
7168 +/*
7169 + * Device Tree file for NXP LS2081A RDB Board.
7170 + *
7171 + * Copyright 2017 NXP
7172 + *
7173 + * Priyanka Jain <priyanka.jain@nxp.com>
7174 + *
7175 + * This file is dual-licensed: you can use it either under the terms
7176 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7177 + * licensing only applies to this file, and not this project as a
7178 + * whole.
7179 + *
7180 + * a) This library is free software; you can redistribute it and/or
7181 + * modify it under the terms of the GNU General Public License as
7182 + * published by the Free Software Foundation; either version 2 of the
7183 + * License, or (at your option) any later version.
7184 + *
7185 + * This library is distributed in the hope that it will be useful,
7186 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7187 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7188 + * GNU General Public License for more details.
7189 + *
7190 + * Or, alternatively,
7191 + *
7192 + * b) Permission is hereby granted, free of charge, to any person
7193 + * obtaining a copy of this software and associated documentation
7194 + * files (the "Software"), to deal in the Software without
7195 + * restriction, including without limitation the rights to use,
7196 + * copy, modify, merge, publish, distribute, sublicense, and/or
7197 + * sell copies of the Software, and to permit persons to whom the
7198 + * Software is furnished to do so, subject to the following
7199 + * conditions:
7200 + *
7201 + * The above copyright notice and this permission notice shall be
7202 + * included in all copies or substantial portions of the Software.
7203 + *
7204 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7205 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7206 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7207 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7208 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7209 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7210 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7211 + * OTHER DEALINGS IN THE SOFTWARE.
7212 + */
7213 +
7214 +/dts-v1/;
7215 +
7216 +#include "fsl-ls2088a.dtsi"
7217 +
7218 +/ {
7219 + model = "NXP Layerscape 2081A RDB Board";
7220 + compatible = "fsl,ls2081a-rdb", "fsl,ls2081a";
7221 +
7222 + aliases {
7223 + serial0 = &serial0;
7224 + serial1 = &serial1;
7225 + };
7226 +
7227 + chosen {
7228 + stdout-path = "serial1:115200n8";
7229 + };
7230 +};
7231 +
7232 +&esdhc {
7233 + status = "okay";
7234 +};
7235 +
7236 +&ifc {
7237 + status = "disabled";
7238 +};
7239 +
7240 +&i2c0 {
7241 + status = "okay";
7242 + pca9547@75 {
7243 + compatible = "nxp,pca9547";
7244 + reg = <0x75>;
7245 + #address-cells = <1>;
7246 + #size-cells = <0>;
7247 + i2c@1 {
7248 + #address-cells = <1>;
7249 + #size-cells = <0>;
7250 + reg = <0x01>;
7251 + rtc@51 {
7252 + compatible = "nxp,pcf2129";
7253 + reg = <0x51>;
7254 + };
7255 + };
7256 +
7257 + i2c@2 {
7258 + #address-cells = <1>;
7259 + #size-cells = <0>;
7260 + reg = <0x02>;
7261 +
7262 + ina220@40 {
7263 + compatible = "ti,ina220";
7264 + reg = <0x40>;
7265 + shunt-resistor = <500>;
7266 + };
7267 + };
7268 +
7269 + i2c@3 {
7270 + #address-cells = <1>;
7271 + #size-cells = <0>;
7272 + reg = <0x3>;
7273 +
7274 + adt7481@4c {
7275 + compatible = "adi,adt7461";
7276 + reg = <0x4c>;
7277 + };
7278 + };
7279 + };
7280 +};
7281 +
7282 +&dspi {
7283 + status = "okay";
7284 + dflash0: n25q512a {
7285 + #address-cells = <1>;
7286 + #size-cells = <1>;
7287 + compatible = "st,m25p80";
7288 + spi-max-frequency = <3000000>;
7289 + reg = <0>;
7290 + };
7291 +};
7292 +
7293 +&qspi {
7294 + status = "okay";
7295 + fsl,qspi-has-second-chip;
7296 + flash0: s25fs512s@0 {
7297 + #address-cells = <1>;
7298 + #size-cells = <1>;
7299 + compatible = "spansion,m25p80";
7300 + m25p,fast-read;
7301 + spi-max-frequency = <20000000>;
7302 + reg = <0>;
7303 + };
7304 + flash1: s25fs512s@1 {
7305 + #address-cells = <1>;
7306 + #size-cells = <1>;
7307 + compatible = "spansion,m25p80";
7308 + m25p,fast-read;
7309 + spi-max-frequency = <20000000>;
7310 + reg = <1>;
7311 + };
7312 +};
7313 +
7314 +&sata0 {
7315 + status = "okay";
7316 +};
7317 +
7318 +&sata1 {
7319 + status = "okay";
7320 +};
7321 +
7322 +&usb0 {
7323 + status = "okay";
7324 +};
7325 +
7326 +&usb1 {
7327 + status = "okay";
7328 +};
7329 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7330 new file mode 100644
7331 index 00000000..1dbc7aa8
7332 --- /dev/null
7333 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
7334 @@ -0,0 +1,162 @@
7335 +/*
7336 + * Device Tree file for Freescale LS2088A QDS Board.
7337 + *
7338 + * Copyright 2016 Freescale Semiconductor, Inc.
7339 + * Copyright 2017 NXP
7340 + *
7341 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7342 + *
7343 + * This file is dual-licensed: you can use it either under the terms
7344 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7345 + * licensing only applies to this file, and not this project as a
7346 + * whole.
7347 + *
7348 + * a) This library is free software; you can redistribute it and/or
7349 + * modify it under the terms of the GNU General Public License as
7350 + * published by the Free Software Foundation; either version 2 of the
7351 + * License, or (at your option) any later version.
7352 + *
7353 + * This library is distributed in the hope that it will be useful,
7354 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7355 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7356 + * GNU General Public License for more details.
7357 + *
7358 + * Or, alternatively,
7359 + *
7360 + * b) Permission is hereby granted, free of charge, to any person
7361 + * obtaining a copy of this software and associated documentation
7362 + * files (the "Software"), to deal in the Software without
7363 + * restriction, including without limitation the rights to use,
7364 + * copy, modify, merge, publish, distribute, sublicense, and/or
7365 + * sell copies of the Software, and to permit persons to whom the
7366 + * Software is furnished to do so, subject to the following
7367 + * conditions:
7368 + *
7369 + * The above copyright notice and this permission notice shall be
7370 + * included in all copies or substantial portions of the Software.
7371 + *
7372 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7373 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7374 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7375 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7376 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7377 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7378 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7379 + * OTHER DEALINGS IN THE SOFTWARE.
7380 + */
7381 +
7382 +/dts-v1/;
7383 +
7384 +#include "fsl-ls2088a.dtsi"
7385 +#include "fsl-ls208xa-qds.dtsi"
7386 +
7387 +/ {
7388 + model = "Freescale Layerscape 2088A QDS Board";
7389 + compatible = "fsl,ls2088a-qds", "fsl,ls2088a";
7390 +
7391 + chosen {
7392 + stdout-path = "serial0:115200n8";
7393 + };
7394 +};
7395 +
7396 +&ifc {
7397 + boardctrl: board-control@3,0 {
7398 + #address-cells = <1>;
7399 + #size-cells = <1>;
7400 + compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus";
7401 + reg = <3 0 0x300>; /* TODO check address */
7402 + ranges = <0 3 0 0x300>;
7403 +
7404 + mdio_mux_emi1 {
7405 + compatible = "mdio-mux-mmioreg", "mdio-mux";
7406 + mdio-parent-bus = <&emdio1>;
7407 + reg = <0x54 1>; /* BRDCFG4 */
7408 + mux-mask = <0xe0>; /* EMI1_MDIO */
7409 +
7410 + #address-cells=<1>;
7411 + #size-cells = <0>;
7412 +
7413 + /* Child MDIO buses, one for each riser card:
7414 + * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0.
7415 + * VSC8234 PHYs on the riser cards.
7416 + */
7417 +
7418 + mdio_mux3: mdio@60 {
7419 + reg = <0x60>;
7420 + #address-cells = <1>;
7421 + #size-cells = <0>;
7422 +
7423 + mdio0_phy12: mdio_phy0@1c {
7424 + reg = <0x1c>;
7425 + phy-connection-type = "sgmii";
7426 + };
7427 + mdio0_phy13: mdio_phy1@1d {
7428 + reg = <0x1d>;
7429 + phy-connection-type = "sgmii";
7430 + };
7431 + mdio0_phy14: mdio_phy2@1e {
7432 + reg = <0x1e>;
7433 + phy-connection-type = "sgmii";
7434 + };
7435 + mdio0_phy15: mdio_phy3@1f {
7436 + reg = <0x1f>;
7437 + phy-connection-type = "sgmii";
7438 + };
7439 + };
7440 + };
7441 + };
7442 +};
7443 +
7444 +&pcs_mdio1 {
7445 + pcs_phy1: ethernet-phy@0 {
7446 + backplane-mode = "10gbase-kr";
7447 + compatible = "ethernet-phy-ieee802.3-c45";
7448 + reg = <0x0>;
7449 + fsl,lane-handle = <&serdes1>;
7450 + fsl,lane-reg = <0x9C0 0x40>;/* lane H */
7451 + };
7452 +};
7453 +
7454 +&pcs_mdio2 {
7455 + pcs_phy2: ethernet-phy@0 {
7456 + backplane-mode = "10gbase-kr";
7457 + compatible = "ethernet-phy-ieee802.3-c45";
7458 + reg = <0x0>;
7459 + fsl,lane-handle = <&serdes1>;
7460 + fsl,lane-reg = <0x980 0x40>;/* lane G */
7461 + };
7462 +};
7463 +
7464 +&pcs_mdio3 {
7465 + pcs_phy3: ethernet-phy@0 {
7466 + backplane-mode = "10gbase-kr";
7467 + compatible = "ethernet-phy-ieee802.3-c45";
7468 + reg = <0x0>;
7469 + fsl,lane-handle = <&serdes1>;
7470 + fsl,lane-reg = <0x940 0x40>;/* lane F */
7471 + };
7472 +};
7473 +
7474 +&pcs_mdio4 {
7475 + pcs_phy4: ethernet-phy@0 {
7476 + backplane-mode = "10gbase-kr";
7477 + compatible = "ethernet-phy-ieee802.3-c45";
7478 + reg = <0x0>;
7479 + fsl,lane-handle = <&serdes1>;
7480 + fsl,lane-reg = <0x900 0x40>;/* lane E */
7481 + };
7482 +};
7483 +
7484 +/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */
7485 +&dpmac9 {
7486 + phy-handle = <&mdio0_phy12>;
7487 +};
7488 +&dpmac10 {
7489 + phy-handle = <&mdio0_phy13>;
7490 +};
7491 +&dpmac11 {
7492 + phy-handle = <&mdio0_phy14>;
7493 +};
7494 +&dpmac12 {
7495 + phy-handle = <&mdio0_phy15>;
7496 +};
7497 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7498 new file mode 100644
7499 index 00000000..9300119b
7500 --- /dev/null
7501 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
7502 @@ -0,0 +1,140 @@
7503 +/*
7504 + * Device Tree file for Freescale LS2088A RDB Board.
7505 + *
7506 + * Copyright 2016 Freescale Semiconductor, Inc.
7507 + * Copyright 2017 NXP
7508 + *
7509 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7510 + *
7511 + * This file is dual-licensed: you can use it either under the terms
7512 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7513 + * licensing only applies to this file, and not this project as a
7514 + * whole.
7515 + *
7516 + * a) This library is free software; you can redistribute it and/or
7517 + * modify it under the terms of the GNU General Public License as
7518 + * published by the Free Software Foundation; either version 2 of the
7519 + * License, or (at your option) any later version.
7520 + *
7521 + * This library is distributed in the hope that it will be useful,
7522 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7523 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7524 + * GNU General Public License for more details.
7525 + *
7526 + * Or, alternatively,
7527 + *
7528 + * b) Permission is hereby granted, free of charge, to any person
7529 + * obtaining a copy of this software and associated documentation
7530 + * files (the "Software"), to deal in the Software without
7531 + * restriction, including without limitation the rights to use,
7532 + * copy, modify, merge, publish, distribute, sublicense, and/or
7533 + * sell copies of the Software, and to permit persons to whom the
7534 + * Software is furnished to do so, subject to the following
7535 + * conditions:
7536 + *
7537 + * The above copyright notice and this permission notice shall be
7538 + * included in all copies or substantial portions of the Software.
7539 + *
7540 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7541 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7542 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7543 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7544 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7545 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7546 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7547 + * OTHER DEALINGS IN THE SOFTWARE.
7548 + */
7549 +
7550 +/dts-v1/;
7551 +
7552 +#include "fsl-ls2088a.dtsi"
7553 +#include "fsl-ls208xa-rdb.dtsi"
7554 +
7555 +/ {
7556 + model = "Freescale Layerscape 2088A RDB Board";
7557 + compatible = "fsl,ls2088a-rdb", "fsl,ls2088a";
7558 +
7559 + chosen {
7560 + stdout-path = "serial1:115200n8";
7561 + };
7562 +};
7563 +
7564 +&emdio1 {
7565 + status = "disabled";
7566 + /* CS4340 PHYs */
7567 + mdio1_phy1: emdio1_phy@1 {
7568 + reg = <0x10>;
7569 + phy-connection-type = "xfi";
7570 + };
7571 + mdio1_phy2: emdio1_phy@2 {
7572 + reg = <0x11>;
7573 + phy-connection-type = "xfi";
7574 + };
7575 + mdio1_phy3: emdio1_phy@3 {
7576 + reg = <0x12>;
7577 + phy-connection-type = "xfi";
7578 + };
7579 + mdio1_phy4: emdio1_phy@4 {
7580 + reg = <0x13>;
7581 + phy-connection-type = "xfi";
7582 + };
7583 +};
7584 +
7585 +&emdio2 {
7586 + /* AQR405 PHYs */
7587 + mdio2_phy1: emdio2_phy@1 {
7588 + compatible = "ethernet-phy-ieee802.3-c45";
7589 + interrupts = <0 1 0x4>; /* Level high type */
7590 + reg = <0x0>;
7591 + phy-connection-type = "xfi";
7592 + };
7593 + mdio2_phy2: emdio2_phy@2 {
7594 + compatible = "ethernet-phy-ieee802.3-c45";
7595 + interrupts = <0 2 0x4>; /* Level high type */
7596 + reg = <0x1>;
7597 + phy-connection-type = "xfi";
7598 + };
7599 + mdio2_phy3: emdio2_phy@3 {
7600 + compatible = "ethernet-phy-ieee802.3-c45";
7601 + interrupts = <0 4 0x4>; /* Level high type */
7602 + reg = <0x2>;
7603 + phy-connection-type = "xfi";
7604 + };
7605 + mdio2_phy4: emdio2_phy@4 {
7606 + compatible = "ethernet-phy-ieee802.3-c45";
7607 + interrupts = <0 5 0x4>; /* Level high type */
7608 + reg = <0x3>;
7609 + phy-connection-type = "xfi";
7610 + };
7611 +};
7612 +
7613 +/* Update DPMAC connections to external PHYs, under the assumption of
7614 + * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board.
7615 + */
7616 +/* Leave Cortina PHYs commented out until proper driver is integrated
7617 + *&dpmac1 {
7618 + * phy-handle = <&mdio1_phy1>;
7619 + *};
7620 + *&dpmac2 {
7621 + * phy-handle = <&mdio1_phy2>;
7622 + *};
7623 + *&dpmac3 {
7624 + * phy-handle = <&mdio1_phy3>;
7625 + *};
7626 + *&dpmac4 {
7627 + * phy-handle = <&mdio1_phy4>;
7628 + *};
7629 + */
7630 +
7631 +&dpmac5 {
7632 + phy-handle = <&mdio2_phy1>;
7633 +};
7634 +&dpmac6 {
7635 + phy-handle = <&mdio2_phy2>;
7636 +};
7637 +&dpmac7 {
7638 + phy-handle = <&mdio2_phy3>;
7639 +};
7640 +&dpmac8 {
7641 + phy-handle = <&mdio2_phy4>;
7642 +};
7643 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
7644 new file mode 100644
7645 index 00000000..833699ea
7646 --- /dev/null
7647 +++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
7648 @@ -0,0 +1,195 @@
7649 +/*
7650 + * Device Tree Include file for Freescale Layerscape-2088A family SoC.
7651 + *
7652 + * Copyright 2016 Freescale Semiconductor, Inc.
7653 + * Copyright 2017 NXP
7654 + *
7655 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7656 + *
7657 + * This file is dual-licensed: you can use it either under the terms
7658 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7659 + * licensing only applies to this file, and not this project as a
7660 + * whole.
7661 + *
7662 + * a) This library is free software; you can redistribute it and/or
7663 + * modify it under the terms of the GNU General Public License as
7664 + * published by the Free Software Foundation; either version 2 of the
7665 + * License, or (at your option) any later version.
7666 + *
7667 + * This library is distributed in the hope that it will be useful,
7668 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7669 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7670 + * GNU General Public License for more details.
7671 + *
7672 + * Or, alternatively,
7673 + *
7674 + * b) Permission is hereby granted, free of charge, to any person
7675 + * obtaining a copy of this software and associated documentation
7676 + * files (the "Software"), to deal in the Software without
7677 + * restriction, including without limitation the rights to use,
7678 + * copy, modify, merge, publish, distribute, sublicense, and/or
7679 + * sell copies of the Software, and to permit persons to whom the
7680 + * Software is furnished to do so, subject to the following
7681 + * conditions:
7682 + *
7683 + * The above copyright notice and this permission notice shall be
7684 + * included in all copies or substantial portions of the Software.
7685 + *
7686 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7687 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7688 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7689 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7690 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7691 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7692 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7693 + * OTHER DEALINGS IN THE SOFTWARE.
7694 + */
7695 +
7696 +#include "fsl-ls208xa.dtsi"
7697 +
7698 +&cpu {
7699 + cpu0: cpu@0 {
7700 + device_type = "cpu";
7701 + compatible = "arm,cortex-a72";
7702 + reg = <0x0>;
7703 + clocks = <&clockgen 1 0>;
7704 + next-level-cache = <&cluster0_l2>;
7705 + #cooling-cells = <2>;
7706 + cpu-idle-states = <&CPU_PH20>;
7707 + };
7708 +
7709 + cpu1: cpu@1 {
7710 + device_type = "cpu";
7711 + compatible = "arm,cortex-a72";
7712 + reg = <0x1>;
7713 + clocks = <&clockgen 1 0>;
7714 + next-level-cache = <&cluster0_l2>;
7715 + cpu-idle-states = <&CPU_PH20>;
7716 + };
7717 +
7718 + cpu2: cpu@100 {
7719 + device_type = "cpu";
7720 + compatible = "arm,cortex-a72";
7721 + reg = <0x100>;
7722 + clocks = <&clockgen 1 1>;
7723 + next-level-cache = <&cluster1_l2>;
7724 + #cooling-cells = <2>;
7725 + cpu-idle-states = <&CPU_PH20>;
7726 + };
7727 +
7728 + cpu3: cpu@101 {
7729 + device_type = "cpu";
7730 + compatible = "arm,cortex-a72";
7731 + reg = <0x101>;
7732 + clocks = <&clockgen 1 1>;
7733 + next-level-cache = <&cluster1_l2>;
7734 + cpu-idle-states = <&CPU_PH20>;
7735 + };
7736 +
7737 + cpu4: cpu@200 {
7738 + device_type = "cpu";
7739 + compatible = "arm,cortex-a72";
7740 + reg = <0x200>;
7741 + clocks = <&clockgen 1 2>;
7742 + next-level-cache = <&cluster2_l2>;
7743 + #cooling-cells = <2>;
7744 + cpu-idle-states = <&CPU_PH20>;
7745 + };
7746 +
7747 + cpu5: cpu@201 {
7748 + device_type = "cpu";
7749 + compatible = "arm,cortex-a72";
7750 + reg = <0x201>;
7751 + clocks = <&clockgen 1 2>;
7752 + next-level-cache = <&cluster2_l2>;
7753 + cpu-idle-states = <&CPU_PH20>;
7754 + };
7755 +
7756 + cpu6: cpu@300 {
7757 + device_type = "cpu";
7758 + compatible = "arm,cortex-a72";
7759 + reg = <0x300>;
7760 + clocks = <&clockgen 1 3>;
7761 + next-level-cache = <&cluster3_l2>;
7762 + #cooling-cells = <2>;
7763 + cpu-idle-states = <&CPU_PH20>;
7764 + };
7765 +
7766 + cpu7: cpu@301 {
7767 + device_type = "cpu";
7768 + compatible = "arm,cortex-a72";
7769 + reg = <0x301>;
7770 + clocks = <&clockgen 1 3>;
7771 + next-level-cache = <&cluster3_l2>;
7772 + cpu-idle-states = <&CPU_PH20>;
7773 + };
7774 +
7775 + idle-states {
7776 + /*
7777 + * PSCI node is not added default, U-boot will add missing
7778 + * parts if it determines to use PSCI.
7779 + */
7780 + entry-method = "arm,psci";
7781 +
7782 + CPU_PH20: cpu-ph20 {
7783 + compatible = "arm,idle-state";
7784 + idle-state-name = "PH20";
7785 + arm,psci-suspend-param = <0x0>;
7786 + entry-latency-us = <1000>;
7787 + exit-latency-us = <1000>;
7788 + min-residency-us = <3000>;
7789 + };
7790 + };
7791 +
7792 + cluster0_l2: l2-cache0 {
7793 + compatible = "cache";
7794 + };
7795 +
7796 + cluster1_l2: l2-cache1 {
7797 + compatible = "cache";
7798 + };
7799 +
7800 + cluster2_l2: l2-cache2 {
7801 + compatible = "cache";
7802 + };
7803 +
7804 + cluster3_l2: l2-cache3 {
7805 + compatible = "cache";
7806 + };
7807 +};
7808 +
7809 +&pcie1 {
7810 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7811 + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
7812 + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
7813 +
7814 + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000
7815 + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>;
7816 +};
7817 +
7818 +&pcie2 {
7819 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7820 + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
7821 + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
7822 +
7823 + ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000
7824 + 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>;
7825 +};
7826 +
7827 +&pcie3 {
7828 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7829 + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
7830 + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
7831 +
7832 + ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000
7833 + 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>;
7834 +};
7835 +
7836 +&pcie4 {
7837 + compatible = "fsl,ls2088a-pcie", "snps,dw-pcie";
7838 + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
7839 + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */
7840 +
7841 + ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000
7842 + 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>;
7843 +};
7844 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
7845 new file mode 100644
7846 index 00000000..b2374469
7847 --- /dev/null
7848 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
7849 @@ -0,0 +1,198 @@
7850 +/*
7851 + * Device Tree file for Freescale LS2080A QDS Board.
7852 + *
7853 + * Copyright 2016 Freescale Semiconductor, Inc.
7854 + * Copyright 2017 NXP
7855 + *
7856 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
7857 + *
7858 + * This file is dual-licensed: you can use it either under the terms
7859 + * of the GPLv2 or the X11 license, at your option. Note that this dual
7860 + * licensing only applies to this file, and not this project as a
7861 + * whole.
7862 + *
7863 + * a) This library is free software; you can redistribute it and/or
7864 + * modify it under the terms of the GNU General Public License as
7865 + * published by the Free Software Foundation; either version 2 of the
7866 + * License, or (at your option) any later version.
7867 + *
7868 + * This library is distributed in the hope that it will be useful,
7869 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7870 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7871 + * GNU General Public License for more details.
7872 + *
7873 + * Or, alternatively,
7874 + *
7875 + * b) Permission is hereby granted, free of charge, to any person
7876 + * obtaining a copy of this software and associated documentation
7877 + * files (the "Software"), to deal in the Software without
7878 + * restriction, including without limitation the rights to use,
7879 + * copy, modify, merge, publish, distribute, sublicense, and/or
7880 + * sell copies of the Software, and to permit persons to whom the
7881 + * Software is furnished to do so, subject to the following
7882 + * conditions:
7883 + *
7884 + * The above copyright notice and this permission notice shall be
7885 + * included in all copies or substantial portions of the Software.
7886 + *
7887 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
7888 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
7889 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
7890 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
7891 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
7892 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
7893 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
7894 + * OTHER DEALINGS IN THE SOFTWARE.
7895 + */
7896 +
7897 +&esdhc {
7898 + mmc-hs200-1_8v;
7899 + status = "okay";
7900 +};
7901 +
7902 +&ifc {
7903 + status = "okay";
7904 + #address-cells = <2>;
7905 + #size-cells = <1>;
7906 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
7907 + 0x2 0x0 0x5 0x30000000 0x00010000
7908 + 0x3 0x0 0x5 0x20000000 0x00010000>;
7909 +
7910 + nor@0,0 {
7911 + #address-cells = <1>;
7912 + #size-cells = <1>;
7913 + compatible = "cfi-flash";
7914 + reg = <0x0 0x0 0x8000000>;
7915 + bank-width = <2>;
7916 + device-width = <1>;
7917 + };
7918 +
7919 + nand@2,0 {
7920 + compatible = "fsl,ifc-nand";
7921 + reg = <0x2 0x0 0x10000>;
7922 + };
7923 +
7924 + cpld@3,0 {
7925 + reg = <0x3 0x0 0x10000>;
7926 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
7927 + };
7928 +};
7929 +
7930 +&i2c0 {
7931 + status = "okay";
7932 + pca9547@77 {
7933 + compatible = "nxp,pca9547";
7934 + reg = <0x77>;
7935 + #address-cells = <1>;
7936 + #size-cells = <0>;
7937 + i2c@0 {
7938 + #address-cells = <1>;
7939 + #size-cells = <0>;
7940 + reg = <0x00>;
7941 + rtc@68 {
7942 + compatible = "dallas,ds3232";
7943 + reg = <0x68>;
7944 + };
7945 + };
7946 +
7947 + i2c@2 {
7948 + #address-cells = <1>;
7949 + #size-cells = <0>;
7950 + reg = <0x02>;
7951 +
7952 + ina220@40 {
7953 + compatible = "ti,ina220";
7954 + reg = <0x40>;
7955 + shunt-resistor = <500>;
7956 + };
7957 +
7958 + ina220@41 {
7959 + compatible = "ti,ina220";
7960 + reg = <0x41>;
7961 + shunt-resistor = <1000>;
7962 + };
7963 + };
7964 +
7965 + i2c@3 {
7966 + #address-cells = <1>;
7967 + #size-cells = <0>;
7968 + reg = <0x3>;
7969 +
7970 + adt7481@4c {
7971 + compatible = "adi,adt7461";
7972 + reg = <0x4c>;
7973 + };
7974 + };
7975 + };
7976 +};
7977 +
7978 +&i2c1 {
7979 + status = "disabled";
7980 +};
7981 +
7982 +&i2c2 {
7983 + status = "disabled";
7984 +};
7985 +
7986 +&i2c3 {
7987 + status = "disabled";
7988 +};
7989 +
7990 +&dspi {
7991 + status = "okay";
7992 + dflash0: n25q128a {
7993 + #address-cells = <1>;
7994 + #size-cells = <1>;
7995 + compatible = "st,m25p80";
7996 + spi-max-frequency = <3000000>;
7997 + reg = <0>;
7998 + };
7999 + dflash1: sst25wf040b {
8000 + #address-cells = <1>;
8001 + #size-cells = <1>;
8002 + compatible = "st,m25p80";
8003 + spi-max-frequency = <3000000>;
8004 + reg = <1>;
8005 + };
8006 + dflash2: en25s64 {
8007 + #address-cells = <1>;
8008 + #size-cells = <1>;
8009 + compatible = "st,m25p80";
8010 + spi-max-frequency = <3000000>;
8011 + reg = <2>;
8012 + };
8013 +};
8014 +
8015 +&qspi {
8016 + status = "okay";
8017 + flash0: s25fl256s1@0 {
8018 + #address-cells = <1>;
8019 + #size-cells = <1>;
8020 + compatible = "st,m25p80";
8021 + spi-max-frequency = <20000000>;
8022 + reg = <0>;
8023 + };
8024 + flash2: s25fl256s1@2 {
8025 + #address-cells = <1>;
8026 + #size-cells = <1>;
8027 + compatible = "st,m25p80";
8028 + spi-max-frequency = <20000000>;
8029 + reg = <0>;
8030 + };
8031 +};
8032 +
8033 +&sata0 {
8034 + status = "okay";
8035 +};
8036 +
8037 +&sata1 {
8038 + status = "okay";
8039 +};
8040 +
8041 +&usb0 {
8042 + status = "okay";
8043 +};
8044 +
8045 +&usb1 {
8046 + status = "okay";
8047 +};
8048 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8049 new file mode 100644
8050 index 00000000..8e919dc8
8051 --- /dev/null
8052 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
8053 @@ -0,0 +1,161 @@
8054 +/*
8055 + * Device Tree file for Freescale LS2080A RDB Board.
8056 + *
8057 + * Copyright 2016 Freescale Semiconductor, Inc.
8058 + * Copyright 2017 NXP
8059 + *
8060 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8061 + *
8062 + * This file is dual-licensed: you can use it either under the terms
8063 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8064 + * licensing only applies to this file, and not this project as a
8065 + * whole.
8066 + *
8067 + * a) This library is free software; you can redistribute it and/or
8068 + * modify it under the terms of the GNU General Public License as
8069 + * published by the Free Software Foundation; either version 2 of the
8070 + * License, or (at your option) any later version.
8071 + *
8072 + * This library is distributed in the hope that it will be useful,
8073 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8074 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8075 + * GNU General Public License for more details.
8076 + *
8077 + * Or, alternatively,
8078 + *
8079 + * b) Permission is hereby granted, free of charge, to any person
8080 + * obtaining a copy of this software and associated documentation
8081 + * files (the "Software"), to deal in the Software without
8082 + * restriction, including without limitation the rights to use,
8083 + * copy, modify, merge, publish, distribute, sublicense, and/or
8084 + * sell copies of the Software, and to permit persons to whom the
8085 + * Software is furnished to do so, subject to the following
8086 + * conditions:
8087 + *
8088 + * The above copyright notice and this permission notice shall be
8089 + * included in all copies or substantial portions of the Software.
8090 + *
8091 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8092 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8093 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8094 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8095 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8096 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8097 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8098 + * OTHER DEALINGS IN THE SOFTWARE.
8099 + */
8100 +
8101 +&esdhc {
8102 + status = "okay";
8103 +};
8104 +
8105 +&ifc {
8106 + status = "okay";
8107 + #address-cells = <2>;
8108 + #size-cells = <1>;
8109 + ranges = <0x0 0x0 0x5 0x80000000 0x08000000
8110 + 0x2 0x0 0x5 0x30000000 0x00010000
8111 + 0x3 0x0 0x5 0x20000000 0x00010000>;
8112 +
8113 + nor@0,0 {
8114 + #address-cells = <1>;
8115 + #size-cells = <1>;
8116 + compatible = "cfi-flash";
8117 + reg = <0x0 0x0 0x8000000>;
8118 + bank-width = <2>;
8119 + device-width = <1>;
8120 + };
8121 +
8122 + nand@2,0 {
8123 + compatible = "fsl,ifc-nand";
8124 + reg = <0x2 0x0 0x10000>;
8125 + };
8126 +
8127 + cpld@3,0 {
8128 + reg = <0x3 0x0 0x10000>;
8129 + compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis";
8130 + };
8131 +
8132 +};
8133 +
8134 +&i2c0 {
8135 + status = "okay";
8136 + pca9547@75 {
8137 + compatible = "nxp,pca9547";
8138 + reg = <0x75>;
8139 + #address-cells = <1>;
8140 + #size-cells = <0>;
8141 + i2c-mux-never-disable;
8142 + i2c@1 {
8143 + #address-cells = <1>;
8144 + #size-cells = <0>;
8145 + reg = <0x01>;
8146 + rtc@68 {
8147 + compatible = "dallas,ds3232";
8148 + reg = <0x68>;
8149 + };
8150 + };
8151 +
8152 + i2c@3 {
8153 + #address-cells = <1>;
8154 + #size-cells = <0>;
8155 + reg = <0x3>;
8156 +
8157 + adt7481@4c {
8158 + compatible = "adi,adt7461";
8159 + reg = <0x4c>;
8160 + };
8161 + };
8162 + };
8163 +};
8164 +
8165 +&i2c1 {
8166 + status = "disabled";
8167 +};
8168 +
8169 +&i2c2 {
8170 + status = "disabled";
8171 +};
8172 +
8173 +&i2c3 {
8174 + status = "disabled";
8175 +};
8176 +
8177 +&dspi {
8178 + status = "okay";
8179 + dflash0: n25q512a {
8180 + #address-cells = <1>;
8181 + #size-cells = <1>;
8182 + compatible = "st,m25p80";
8183 + spi-max-frequency = <3000000>;
8184 + reg = <0>;
8185 + };
8186 +};
8187 +
8188 +&qspi {
8189 + status = "okay";
8190 + flash0: s25fs512s@0 {
8191 + #address-cells = <1>;
8192 + #size-cells = <1>;
8193 + compatible = "spansion,m25p80";
8194 + m25p,fast-read;
8195 + spi-max-frequency = <20000000>;
8196 + reg = <0>;
8197 + };
8198 +};
8199 +
8200 +&sata0 {
8201 + status = "okay";
8202 +};
8203 +
8204 +&sata1 {
8205 + status = "okay";
8206 +};
8207 +
8208 +&usb0 {
8209 + status = "okay";
8210 +};
8211 +
8212 +&usb1 {
8213 + status = "okay";
8214 +};
8215 diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8216 new file mode 100644
8217 index 00000000..f694cac0
8218 --- /dev/null
8219 +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
8220 @@ -0,0 +1,910 @@
8221 +/*
8222 + * Device Tree Include file for Freescale Layerscape-2080A family SoC.
8223 + *
8224 + * Copyright 2016 Freescale Semiconductor, Inc.
8225 + * Copyright 2017 NXP
8226 + *
8227 + * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8228 + *
8229 + * This file is dual-licensed: you can use it either under the terms
8230 + * of the GPLv2 or the X11 license, at your option. Note that this dual
8231 + * licensing only applies to this file, and not this project as a
8232 + * whole.
8233 + *
8234 + * a) This library is free software; you can redistribute it and/or
8235 + * modify it under the terms of the GNU General Public License as
8236 + * published by the Free Software Foundation; either version 2 of the
8237 + * License, or (at your option) any later version.
8238 + *
8239 + * This library is distributed in the hope that it will be useful,
8240 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8241 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8242 + * GNU General Public License for more details.
8243 + *
8244 + * Or, alternatively,
8245 + *
8246 + * b) Permission is hereby granted, free of charge, to any person
8247 + * obtaining a copy of this software and associated documentation
8248 + * files (the "Software"), to deal in the Software without
8249 + * restriction, including without limitation the rights to use,
8250 + * copy, modify, merge, publish, distribute, sublicense, and/or
8251 + * sell copies of the Software, and to permit persons to whom the
8252 + * Software is furnished to do so, subject to the following
8253 + * conditions:
8254 + *
8255 + * The above copyright notice and this permission notice shall be
8256 + * included in all copies or substantial portions of the Software.
8257 + *
8258 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
8259 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
8260 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8261 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
8262 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
8263 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
8264 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
8265 + * OTHER DEALINGS IN THE SOFTWARE.
8266 + */
8267 +
8268 +#include <dt-bindings/thermal/thermal.h>
8269 +#include <dt-bindings/interrupt-controller/arm-gic.h>
8270 +
8271 +/ {
8272 + compatible = "fsl,ls2080a";
8273 + interrupt-parent = <&gic>;
8274 + #address-cells = <2>;
8275 + #size-cells = <2>;
8276 +
8277 + aliases {
8278 + crypto = &crypto;
8279 + serial0 = &serial0;
8280 + serial1 = &serial1;
8281 + };
8282 +
8283 + cpu: cpus {
8284 + #address-cells = <1>;
8285 + #size-cells = <0>;
8286 + };
8287 +
8288 + memory@80000000 {
8289 + device_type = "memory";
8290 + reg = <0x00000000 0x80000000 0 0x80000000>;
8291 + /* DRAM space - 1, size : 2 GB DRAM */
8292 + };
8293 +
8294 + sysclk: sysclk {
8295 + compatible = "fixed-clock";
8296 + #clock-cells = <0>;
8297 + clock-frequency = <100000000>;
8298 + clock-output-names = "sysclk";
8299 + };
8300 +
8301 + gic: interrupt-controller@6000000 {
8302 + compatible = "arm,gic-v3";
8303 + reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
8304 + <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
8305 + <0x0 0x0c0c0000 0 0x2000>, /* GICC */
8306 + <0x0 0x0c0d0000 0 0x1000>, /* GICH */
8307 + <0x0 0x0c0e0000 0 0x20000>; /* GICV */
8308 + #interrupt-cells = <3>;
8309 + #address-cells = <2>;
8310 + #size-cells = <2>;
8311 + ranges;
8312 + interrupt-controller;
8313 + interrupts = <1 9 0x4>;
8314 +
8315 + its: gic-its@6020000 {
8316 + compatible = "arm,gic-v3-its";
8317 + msi-controller;
8318 + reg = <0x0 0x6020000 0 0x20000>;
8319 + };
8320 + };
8321 +
8322 + rstcr: syscon@1e60000 {
8323 + compatible = "fsl,ls2080a-rstcr", "syscon";
8324 + reg = <0x0 0x1e60000 0x0 0x4>;
8325 + };
8326 +
8327 + reboot {
8328 + compatible ="syscon-reboot";
8329 + regmap = <&rstcr>;
8330 + offset = <0x0>;
8331 + mask = <0x2>;
8332 + };
8333 +
8334 + timer {
8335 + compatible = "arm,armv8-timer";
8336 + interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
8337 + <1 14 4>, /* Physical Non-Secure PPI, active-low */
8338 + <1 11 4>, /* Virtual PPI, active-low */
8339 + <1 10 4>; /* Hypervisor PPI, active-low */
8340 + fsl,erratum-a008585;
8341 + };
8342 +
8343 + pmu {
8344 + compatible = "arm,armv8-pmuv3";
8345 + interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
8346 + };
8347 +
8348 + soc {
8349 + compatible = "simple-bus";
8350 + #address-cells = <2>;
8351 + #size-cells = <2>;
8352 + ranges;
8353 +
8354 + clockgen: clocking@1300000 {
8355 + compatible = "fsl,ls2080a-clockgen";
8356 + reg = <0 0x1300000 0 0xa0000>;
8357 + #clock-cells = <2>;
8358 + clocks = <&sysclk>;
8359 + };
8360 +
8361 + dcfg: dcfg@1e00000 {
8362 + compatible = "fsl,ls2080a-dcfg", "syscon";
8363 + reg = <0x0 0x1e00000 0x0 0x10000>;
8364 + little-endian;
8365 + };
8366 +
8367 + tmu: tmu@1f80000 {
8368 + compatible = "fsl,qoriq-tmu";
8369 + reg = <0x0 0x1f80000 0x0 0x10000>;
8370 + interrupts = <0 23 0x4>;
8371 + fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
8372 + fsl,tmu-calibration = <0x00000000 0x00000026
8373 + 0x00000001 0x0000002d
8374 + 0x00000002 0x00000032
8375 + 0x00000003 0x00000039
8376 + 0x00000004 0x0000003f
8377 + 0x00000005 0x00000046
8378 + 0x00000006 0x0000004d
8379 + 0x00000007 0x00000054
8380 + 0x00000008 0x0000005a
8381 + 0x00000009 0x00000061
8382 + 0x0000000a 0x0000006a
8383 + 0x0000000b 0x00000071
8384 +
8385 + 0x00010000 0x00000025
8386 + 0x00010001 0x0000002c
8387 + 0x00010002 0x00000035
8388 + 0x00010003 0x0000003d
8389 + 0x00010004 0x00000045
8390 + 0x00010005 0x0000004e
8391 + 0x00010006 0x00000057
8392 + 0x00010007 0x00000061
8393 + 0x00010008 0x0000006b
8394 + 0x00010009 0x00000076
8395 +
8396 + 0x00020000 0x00000029
8397 + 0x00020001 0x00000033
8398 + 0x00020002 0x0000003d
8399 + 0x00020003 0x00000049
8400 + 0x00020004 0x00000056
8401 + 0x00020005 0x00000061
8402 + 0x00020006 0x0000006d
8403 +
8404 + 0x00030000 0x00000021
8405 + 0x00030001 0x0000002a
8406 + 0x00030002 0x0000003c
8407 + 0x00030003 0x0000004e>;
8408 + little-endian;
8409 + #thermal-sensor-cells = <1>;
8410 + };
8411 +
8412 + thermal-zones {
8413 + cpu_thermal: cpu-thermal {
8414 + polling-delay-passive = <1000>;
8415 + polling-delay = <5000>;
8416 +
8417 + thermal-sensors = <&tmu 4>;
8418 +
8419 + trips {
8420 + cpu_alert: cpu-alert {
8421 + temperature = <75000>;
8422 + hysteresis = <2000>;
8423 + type = "passive";
8424 + };
8425 + cpu_crit: cpu-crit {
8426 + temperature = <85000>;
8427 + hysteresis = <2000>;
8428 + type = "critical";
8429 + };
8430 + };
8431 +
8432 + cooling-maps {
8433 + map0 {
8434 + trip = <&cpu_alert>;
8435 + cooling-device =
8436 + <&cpu0 THERMAL_NO_LIMIT
8437 + THERMAL_NO_LIMIT>;
8438 + };
8439 + map1 {
8440 + trip = <&cpu_alert>;
8441 + cooling-device =
8442 + <&cpu2 THERMAL_NO_LIMIT
8443 + THERMAL_NO_LIMIT>;
8444 + };
8445 + map2 {
8446 + trip = <&cpu_alert>;
8447 + cooling-device =
8448 + <&cpu4 THERMAL_NO_LIMIT
8449 + THERMAL_NO_LIMIT>;
8450 + };
8451 + map3 {
8452 + trip = <&cpu_alert>;
8453 + cooling-device =
8454 + <&cpu6 THERMAL_NO_LIMIT
8455 + THERMAL_NO_LIMIT>;
8456 + };
8457 + };
8458 + };
8459 + };
8460 +
8461 + serial0: serial@21c0500 {
8462 + compatible = "fsl,ns16550", "ns16550a";
8463 + reg = <0x0 0x21c0500 0x0 0x100>;
8464 + clocks = <&clockgen 4 3>;
8465 + interrupts = <0 32 0x4>; /* Level high type */
8466 + };
8467 +
8468 + serial1: serial@21c0600 {
8469 + compatible = "fsl,ns16550", "ns16550a";
8470 + reg = <0x0 0x21c0600 0x0 0x100>;
8471 + clocks = <&clockgen 4 3>;
8472 + interrupts = <0 32 0x4>; /* Level high type */
8473 + };
8474 +
8475 + cluster1_core0_watchdog: wdt@c000000 {
8476 + compatible = "arm,sp805-wdt", "arm,primecell";
8477 + reg = <0x0 0xc000000 0x0 0x1000>;
8478 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8479 + clock-names = "apb_pclk", "wdog_clk";
8480 + };
8481 +
8482 + cluster1_core1_watchdog: wdt@c010000 {
8483 + compatible = "arm,sp805-wdt", "arm,primecell";
8484 + reg = <0x0 0xc010000 0x0 0x1000>;
8485 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8486 + clock-names = "apb_pclk", "wdog_clk";
8487 + };
8488 +
8489 + cluster2_core0_watchdog: wdt@c100000 {
8490 + compatible = "arm,sp805-wdt", "arm,primecell";
8491 + reg = <0x0 0xc100000 0x0 0x1000>;
8492 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8493 + clock-names = "apb_pclk", "wdog_clk";
8494 + };
8495 +
8496 + cluster2_core1_watchdog: wdt@c110000 {
8497 + compatible = "arm,sp805-wdt", "arm,primecell";
8498 + reg = <0x0 0xc110000 0x0 0x1000>;
8499 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8500 + clock-names = "apb_pclk", "wdog_clk";
8501 + };
8502 +
8503 + cluster3_core0_watchdog: wdt@c200000 {
8504 + compatible = "arm,sp805-wdt", "arm,primecell";
8505 + reg = <0x0 0xc200000 0x0 0x1000>;
8506 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8507 + clock-names = "apb_pclk", "wdog_clk";
8508 + };
8509 +
8510 + cluster3_core1_watchdog: wdt@c210000 {
8511 + compatible = "arm,sp805-wdt", "arm,primecell";
8512 + reg = <0x0 0xc210000 0x0 0x1000>;
8513 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8514 + clock-names = "apb_pclk", "wdog_clk";
8515 + };
8516 +
8517 + cluster4_core0_watchdog: wdt@c300000 {
8518 + compatible = "arm,sp805-wdt", "arm,primecell";
8519 + reg = <0x0 0xc300000 0x0 0x1000>;
8520 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8521 + clock-names = "apb_pclk", "wdog_clk";
8522 + };
8523 +
8524 + cluster4_core1_watchdog: wdt@c310000 {
8525 + compatible = "arm,sp805-wdt", "arm,primecell";
8526 + reg = <0x0 0xc310000 0x0 0x1000>;
8527 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8528 + clock-names = "apb_pclk", "wdog_clk";
8529 + };
8530 +
8531 + crypto: crypto@8000000 {
8532 + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
8533 + fsl,sec-era = <8>;
8534 + #address-cells = <1>;
8535 + #size-cells = <1>;
8536 + ranges = <0x0 0x00 0x8000000 0x100000>;
8537 + reg = <0x00 0x8000000 0x0 0x100000>;
8538 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
8539 + dma-coherent;
8540 +
8541 + sec_jr0: jr@10000 {
8542 + compatible = "fsl,sec-v5.0-job-ring",
8543 + "fsl,sec-v4.0-job-ring";
8544 + reg = <0x10000 0x10000>;
8545 + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
8546 + };
8547 +
8548 + sec_jr1: jr@20000 {
8549 + compatible = "fsl,sec-v5.0-job-ring",
8550 + "fsl,sec-v4.0-job-ring";
8551 + reg = <0x20000 0x10000>;
8552 + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
8553 + };
8554 +
8555 + sec_jr2: jr@30000 {
8556 + compatible = "fsl,sec-v5.0-job-ring",
8557 + "fsl,sec-v4.0-job-ring";
8558 + reg = <0x30000 0x10000>;
8559 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
8560 + };
8561 +
8562 + sec_jr3: jr@40000 {
8563 + compatible = "fsl,sec-v5.0-job-ring",
8564 + "fsl,sec-v4.0-job-ring";
8565 + reg = <0x40000 0x10000>;
8566 + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
8567 + };
8568 + };
8569 +
8570 + fsl_mc: fsl-mc@80c000000 {
8571 + compatible = "fsl,qoriq-mc";
8572 + reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
8573 + <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
8574 + msi-parent = <&its>;
8575 + iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
8576 + #address-cells = <3>;
8577 + #size-cells = <1>;
8578 +
8579 + /*
8580 + * Region type 0x0 - MC portals
8581 + * Region type 0x1 - QBMAN portals
8582 + */
8583 + ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
8584 + 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
8585 +
8586 + /*
8587 + * Define the maximum number of MACs present on the SoC.
8588 + */
8589 + dpmacs {
8590 + #address-cells = <1>;
8591 + #size-cells = <0>;
8592 +
8593 + dpmac1: dpmac@1 {
8594 + compatible = "fsl,qoriq-mc-dpmac";
8595 + reg = <0x1>;
8596 + };
8597 +
8598 + dpmac2: dpmac@2 {
8599 + compatible = "fsl,qoriq-mc-dpmac";
8600 + reg = <0x2>;
8601 + };
8602 +
8603 + dpmac3: dpmac@3 {
8604 + compatible = "fsl,qoriq-mc-dpmac";
8605 + reg = <0x3>;
8606 + };
8607 +
8608 + dpmac4: dpmac@4 {
8609 + compatible = "fsl,qoriq-mc-dpmac";
8610 + reg = <0x4>;
8611 + };
8612 +
8613 + dpmac5: dpmac@5 {
8614 + compatible = "fsl,qoriq-mc-dpmac";
8615 + reg = <0x5>;
8616 + };
8617 +
8618 + dpmac6: dpmac@6 {
8619 + compatible = "fsl,qoriq-mc-dpmac";
8620 + reg = <0x6>;
8621 + };
8622 +
8623 + dpmac7: dpmac@7 {
8624 + compatible = "fsl,qoriq-mc-dpmac";
8625 + reg = <0x7>;
8626 + };
8627 +
8628 + dpmac8: dpmac@8 {
8629 + compatible = "fsl,qoriq-mc-dpmac";
8630 + reg = <0x8>;
8631 + };
8632 +
8633 + dpmac9: dpmac@9 {
8634 + compatible = "fsl,qoriq-mc-dpmac";
8635 + reg = <0x9>;
8636 + };
8637 +
8638 + dpmac10: dpmac@a {
8639 + compatible = "fsl,qoriq-mc-dpmac";
8640 + reg = <0xa>;
8641 + };
8642 +
8643 + dpmac11: dpmac@b {
8644 + compatible = "fsl,qoriq-mc-dpmac";
8645 + reg = <0xb>;
8646 + };
8647 +
8648 + dpmac12: dpmac@c {
8649 + compatible = "fsl,qoriq-mc-dpmac";
8650 + reg = <0xc>;
8651 + };
8652 +
8653 + dpmac13: dpmac@d {
8654 + compatible = "fsl,qoriq-mc-dpmac";
8655 + reg = <0xd>;
8656 + };
8657 +
8658 + dpmac14: dpmac@e {
8659 + compatible = "fsl,qoriq-mc-dpmac";
8660 + reg = <0xe>;
8661 + };
8662 +
8663 + dpmac15: dpmac@f {
8664 + compatible = "fsl,qoriq-mc-dpmac";
8665 + reg = <0xf>;
8666 + };
8667 +
8668 + dpmac16: dpmac@10 {
8669 + compatible = "fsl,qoriq-mc-dpmac";
8670 + reg = <0x10>;
8671 + };
8672 + };
8673 + };
8674 +
8675 + smmu: iommu@5000000 {
8676 + compatible = "arm,mmu-500";
8677 + reg = <0 0x5000000 0 0x800000>;
8678 + #global-interrupts = <12>;
8679 + #iommu-cells = <1>;
8680 + stream-match-mask = <0x7C00>;
8681 + interrupts = <0 13 4>, /* global secure fault */
8682 + <0 14 4>, /* combined secure interrupt */
8683 + <0 15 4>, /* global non-secure fault */
8684 + <0 16 4>, /* combined non-secure interrupt */
8685 + /* performance counter interrupts 0-7 */
8686 + <0 211 4>, <0 212 4>,
8687 + <0 213 4>, <0 214 4>,
8688 + <0 215 4>, <0 216 4>,
8689 + <0 217 4>, <0 218 4>,
8690 + /* per context interrupt, 64 interrupts */
8691 + <0 146 4>, <0 147 4>,
8692 + <0 148 4>, <0 149 4>,
8693 + <0 150 4>, <0 151 4>,
8694 + <0 152 4>, <0 153 4>,
8695 + <0 154 4>, <0 155 4>,
8696 + <0 156 4>, <0 157 4>,
8697 + <0 158 4>, <0 159 4>,
8698 + <0 160 4>, <0 161 4>,
8699 + <0 162 4>, <0 163 4>,
8700 + <0 164 4>, <0 165 4>,
8701 + <0 166 4>, <0 167 4>,
8702 + <0 168 4>, <0 169 4>,
8703 + <0 170 4>, <0 171 4>,
8704 + <0 172 4>, <0 173 4>,
8705 + <0 174 4>, <0 175 4>,
8706 + <0 176 4>, <0 177 4>,
8707 + <0 178 4>, <0 179 4>,
8708 + <0 180 4>, <0 181 4>,
8709 + <0 182 4>, <0 183 4>,
8710 + <0 184 4>, <0 185 4>,
8711 + <0 186 4>, <0 187 4>,
8712 + <0 188 4>, <0 189 4>,
8713 + <0 190 4>, <0 191 4>,
8714 + <0 192 4>, <0 193 4>,
8715 + <0 194 4>, <0 195 4>,
8716 + <0 196 4>, <0 197 4>,
8717 + <0 198 4>, <0 199 4>,
8718 + <0 200 4>, <0 201 4>,
8719 + <0 202 4>, <0 203 4>,
8720 + <0 204 4>, <0 205 4>,
8721 + <0 206 4>, <0 207 4>,
8722 + <0 208 4>, <0 209 4>;
8723 + };
8724 +
8725 + dspi: dspi@2100000 {
8726 + status = "disabled";
8727 + compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
8728 + #address-cells = <1>;
8729 + #size-cells = <0>;
8730 + reg = <0x0 0x2100000 0x0 0x10000>;
8731 + interrupts = <0 26 0x4>; /* Level high type */
8732 + clocks = <&clockgen 4 3>;
8733 + clock-names = "dspi";
8734 + spi-num-chipselects = <5>;
8735 + bus-num = <0>;
8736 + };
8737 +
8738 + esdhc: esdhc@2140000 {
8739 + status = "disabled";
8740 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
8741 + reg = <0x0 0x2140000 0x0 0x10000>;
8742 + interrupts = <0 28 0x4>; /* Level high type */
8743 + clocks = <&clockgen 4 1>;
8744 + voltage-ranges = <1800 1800 3300 3300>;
8745 + sdhci,auto-cmd12;
8746 + little-endian;
8747 + bus-width = <4>;
8748 + };
8749 +
8750 + gpio0: gpio@2300000 {
8751 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8752 + reg = <0x0 0x2300000 0x0 0x10000>;
8753 + interrupts = <0 36 0x4>; /* Level high type */
8754 + gpio-controller;
8755 + little-endian;
8756 + #gpio-cells = <2>;
8757 + interrupt-controller;
8758 + #interrupt-cells = <2>;
8759 + };
8760 +
8761 + gpio1: gpio@2310000 {
8762 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8763 + reg = <0x0 0x2310000 0x0 0x10000>;
8764 + interrupts = <0 36 0x4>; /* Level high type */
8765 + gpio-controller;
8766 + little-endian;
8767 + #gpio-cells = <2>;
8768 + interrupt-controller;
8769 + #interrupt-cells = <2>;
8770 + };
8771 +
8772 + gpio2: gpio@2320000 {
8773 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8774 + reg = <0x0 0x2320000 0x0 0x10000>;
8775 + interrupts = <0 37 0x4>; /* Level high type */
8776 + gpio-controller;
8777 + little-endian;
8778 + #gpio-cells = <2>;
8779 + interrupt-controller;
8780 + #interrupt-cells = <2>;
8781 + };
8782 +
8783 + gpio3: gpio@2330000 {
8784 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
8785 + reg = <0x0 0x2330000 0x0 0x10000>;
8786 + interrupts = <0 37 0x4>; /* Level high type */
8787 + gpio-controller;
8788 + little-endian;
8789 + #gpio-cells = <2>;
8790 + interrupt-controller;
8791 + #interrupt-cells = <2>;
8792 + };
8793 +
8794 + /* TODO: WRIOP (CCSR?) */
8795 + emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000,
8796 + * E-MDIO1: 0x1_6000
8797 + */
8798 + compatible = "fsl,fman-memac-mdio";
8799 + reg = <0x0 0x8B96000 0x0 0x1000>;
8800 + device_type = "mdio"; /* TODO: is this necessary? */
8801 + little-endian; /* force the driver in LE mode */
8802 +
8803 + /* Not necessary on the QDS, but needed on the RDB */
8804 + #address-cells = <1>;
8805 + #size-cells = <0>;
8806 + };
8807 +
8808 + emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000,
8809 + * E-MDIO2: 0x1_7000
8810 + */
8811 + compatible = "fsl,fman-memac-mdio";
8812 + reg = <0x0 0x8B97000 0x0 0x1000>;
8813 + device_type = "mdio"; /* TODO: is this necessary? */
8814 + little-endian; /* force the driver in LE mode */
8815 +
8816 + #address-cells = <1>;
8817 + #size-cells = <0>;
8818 + };
8819 +
8820 + pcs_mdio1: mdio@0x8c07000 {
8821 + compatible = "fsl,fman-memac-mdio";
8822 + reg = <0x0 0x8c07000 0x0 0x1000>;
8823 + device_type = "mdio";
8824 + little-endian;
8825 +
8826 + #address-cells = <1>;
8827 + #size-cells = <0>;
8828 + };
8829 +
8830 + pcs_mdio2: mdio@0x8c0b000 {
8831 + compatible = "fsl,fman-memac-mdio";
8832 + reg = <0x0 0x8c0b000 0x0 0x1000>;
8833 + device_type = "mdio";
8834 + little-endian;
8835 +
8836 + #address-cells = <1>;
8837 + #size-cells = <0>;
8838 + };
8839 +
8840 + pcs_mdio3: mdio@0x8c0f000 {
8841 + compatible = "fsl,fman-memac-mdio";
8842 + reg = <0x0 0x8c0f000 0x0 0x1000>;
8843 + device_type = "mdio";
8844 + little-endian;
8845 +
8846 + #address-cells = <1>;
8847 + #size-cells = <0>;
8848 + };
8849 +
8850 + pcs_mdio4: mdio@0x8c13000 {
8851 + compatible = "fsl,fman-memac-mdio";
8852 + reg = <0x0 0x8c13000 0x0 0x1000>;
8853 + device_type = "mdio";
8854 + little-endian;
8855 +
8856 + #address-cells = <1>;
8857 + #size-cells = <0>;
8858 + };
8859 +
8860 + pcs_mdio5: mdio@0x8c17000 {
8861 + status = "disabled";
8862 + compatible = "fsl,fman-memac-mdio";
8863 + reg = <0x0 0x8c17000 0x0 0x1000>;
8864 + device_type = "mdio";
8865 + little-endian;
8866 +
8867 + #address-cells = <1>;
8868 + #size-cells = <0>;
8869 + };
8870 +
8871 + pcs_mdio6: mdio@0x8c1b000 {
8872 + status = "disabled";
8873 + compatible = "fsl,fman-memac-mdio";
8874 + reg = <0x0 0x8c1b000 0x0 0x1000>;
8875 + device_type = "mdio";
8876 + little-endian;
8877 +
8878 + #address-cells = <1>;
8879 + #size-cells = <0>;
8880 + };
8881 +
8882 + pcs_mdio7: mdio@0x8c1f000 {
8883 + status = "disabled";
8884 + compatible = "fsl,fman-memac-mdio";
8885 + reg = <0x0 0x8c1f000 0x0 0x1000>;
8886 + device_type = "mdio";
8887 + little-endian;
8888 +
8889 + #address-cells = <1>;
8890 + #size-cells = <0>;
8891 + };
8892 +
8893 + pcs_mdio8: mdio@0x8c23000 {
8894 + status = "disabled";
8895 + compatible = "fsl,fman-memac-mdio";
8896 + reg = <0x0 0x8c23000 0x0 0x1000>;
8897 + device_type = "mdio";
8898 + little-endian;
8899 +
8900 + #address-cells = <1>;
8901 + #size-cells = <0>;
8902 + };
8903 +
8904 + i2c0: i2c@2000000 {
8905 + status = "disabled";
8906 + compatible = "fsl,vf610-i2c";
8907 + #address-cells = <1>;
8908 + #size-cells = <0>;
8909 + reg = <0x0 0x2000000 0x0 0x10000>;
8910 + interrupts = <0 34 0x4>; /* Level high type */
8911 + clock-names = "i2c";
8912 + clocks = <&clockgen 4 3>;
8913 + };
8914 +
8915 + i2c1: i2c@2010000 {
8916 + status = "disabled";
8917 + compatible = "fsl,vf610-i2c";
8918 + #address-cells = <1>;
8919 + #size-cells = <0>;
8920 + reg = <0x0 0x2010000 0x0 0x10000>;
8921 + interrupts = <0 34 0x4>; /* Level high type */
8922 + clock-names = "i2c";
8923 + clocks = <&clockgen 4 3>;
8924 + };
8925 +
8926 + i2c2: i2c@2020000 {
8927 + status = "disabled";
8928 + compatible = "fsl,vf610-i2c";
8929 + #address-cells = <1>;
8930 + #size-cells = <0>;
8931 + reg = <0x0 0x2020000 0x0 0x10000>;
8932 + interrupts = <0 35 0x4>; /* Level high type */
8933 + clock-names = "i2c";
8934 + clocks = <&clockgen 4 3>;
8935 + };
8936 +
8937 + i2c3: i2c@2030000 {
8938 + status = "disabled";
8939 + compatible = "fsl,vf610-i2c";
8940 + #address-cells = <1>;
8941 + #size-cells = <0>;
8942 + reg = <0x0 0x2030000 0x0 0x10000>;
8943 + interrupts = <0 35 0x4>; /* Level high type */
8944 + clock-names = "i2c";
8945 + clocks = <&clockgen 4 3>;
8946 + };
8947 +
8948 + ifc: ifc@2240000 {
8949 + compatible = "fsl,ifc", "simple-bus";
8950 + reg = <0x0 0x2240000 0x0 0x20000>;
8951 + interrupts = <0 21 0x4>; /* Level high type */
8952 + little-endian;
8953 + #address-cells = <2>;
8954 + #size-cells = <1>;
8955 +
8956 + ranges = <0 0 0x5 0x80000000 0x08000000
8957 + 2 0 0x5 0x30000000 0x00010000
8958 + 3 0 0x5 0x20000000 0x00010000>;
8959 + };
8960 +
8961 + qspi: quadspi@20c0000 {
8962 + status = "disabled";
8963 + compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi";
8964 + #address-cells = <1>;
8965 + #size-cells = <0>;
8966 + reg = <0x0 0x20c0000 0x0 0x10000>,
8967 + <0x0 0x20000000 0x0 0x10000000>;
8968 + reg-names = "QuadSPI", "QuadSPI-memory";
8969 + interrupts = <0 25 0x4>; /* Level high type */
8970 + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
8971 + clock-names = "qspi_en", "qspi";
8972 + };
8973 +
8974 + pcie1: pcie@3400000 {
8975 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
8976 + "snps,dw-pcie";
8977 + reg-names = "regs", "config";
8978 + interrupts = <0 108 0x4>; /* aer interrupt */
8979 + interrupt-names = "aer";
8980 + #address-cells = <3>;
8981 + #size-cells = <2>;
8982 + device_type = "pci";
8983 + dma-coherent;
8984 + num-lanes = <4>;
8985 + bus-range = <0x0 0xff>;
8986 + msi-parent = <&its>;
8987 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
8988 + #interrupt-cells = <1>;
8989 + interrupt-map-mask = <0 0 0 7>;
8990 + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
8991 + <0000 0 0 2 &gic 0 0 0 110 4>,
8992 + <0000 0 0 3 &gic 0 0 0 111 4>,
8993 + <0000 0 0 4 &gic 0 0 0 112 4>;
8994 + };
8995 +
8996 + pcie2: pcie@3500000 {
8997 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
8998 + "snps,dw-pcie";
8999 + reg-names = "regs", "config";
9000 + interrupts = <0 113 0x4>; /* aer interrupt */
9001 + interrupt-names = "aer";
9002 + #address-cells = <3>;
9003 + #size-cells = <2>;
9004 + device_type = "pci";
9005 + dma-coherent;
9006 + num-lanes = <4>;
9007 + bus-range = <0x0 0xff>;
9008 + msi-parent = <&its>;
9009 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9010 + #interrupt-cells = <1>;
9011 + interrupt-map-mask = <0 0 0 7>;
9012 + interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
9013 + <0000 0 0 2 &gic 0 0 0 115 4>,
9014 + <0000 0 0 3 &gic 0 0 0 116 4>,
9015 + <0000 0 0 4 &gic 0 0 0 117 4>;
9016 + };
9017 +
9018 + pcie3: pcie@3600000 {
9019 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9020 + "snps,dw-pcie";
9021 + reg-names = "regs", "config";
9022 + interrupts = <0 118 0x4>; /* aer interrupt */
9023 + interrupt-names = "aer";
9024 + #address-cells = <3>;
9025 + #size-cells = <2>;
9026 + device_type = "pci";
9027 + dma-coherent;
9028 + num-lanes = <8>;
9029 + bus-range = <0x0 0xff>;
9030 + msi-parent = <&its>;
9031 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9032 + #interrupt-cells = <1>;
9033 + interrupt-map-mask = <0 0 0 7>;
9034 + interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
9035 + <0000 0 0 2 &gic 0 0 0 120 4>,
9036 + <0000 0 0 3 &gic 0 0 0 121 4>,
9037 + <0000 0 0 4 &gic 0 0 0 122 4>;
9038 + };
9039 +
9040 + pcie4: pcie@3700000 {
9041 + compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie",
9042 + "snps,dw-pcie";
9043 + reg-names = "regs", "config";
9044 + interrupts = <0 123 0x4>; /* aer interrupt */
9045 + interrupt-names = "aer";
9046 + #address-cells = <3>;
9047 + #size-cells = <2>;
9048 + device_type = "pci";
9049 + dma-coherent;
9050 + num-lanes = <4>;
9051 + bus-range = <0x0 0xff>;
9052 + msi-parent = <&its>;
9053 + iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */
9054 + #interrupt-cells = <1>;
9055 + interrupt-map-mask = <0 0 0 7>;
9056 + interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
9057 + <0000 0 0 2 &gic 0 0 0 125 4>,
9058 + <0000 0 0 3 &gic 0 0 0 126 4>,
9059 + <0000 0 0 4 &gic 0 0 0 127 4>;
9060 + };
9061 +
9062 + sata0: sata@3200000 {
9063 + status = "disabled";
9064 + compatible = "fsl,ls2080a-ahci";
9065 + reg = <0x0 0x3200000 0x0 0x10000>;
9066 + interrupts = <0 133 0x4>; /* Level high type */
9067 + clocks = <&clockgen 4 3>;
9068 + dma-coherent;
9069 + };
9070 +
9071 + sata1: sata@3210000 {
9072 + status = "disabled";
9073 + compatible = "fsl,ls2080a-ahci";
9074 + reg = <0x0 0x3210000 0x0 0x10000>;
9075 + interrupts = <0 136 0x4>; /* Level high type */
9076 + clocks = <&clockgen 4 3>;
9077 + dma-coherent;
9078 + };
9079 +
9080 + usb0: usb3@3100000 {
9081 + status = "disabled";
9082 + compatible = "snps,dwc3";
9083 + reg = <0x0 0x3100000 0x0 0x10000>;
9084 + interrupts = <0 80 0x4>; /* Level high type */
9085 + dr_mode = "host";
9086 + snps,quirk-frame-length-adjustment = <0x20>;
9087 + snps,dis_rxdet_inp3_quirk;
9088 + };
9089 +
9090 + usb1: usb3@3110000 {
9091 + status = "disabled";
9092 + compatible = "snps,dwc3";
9093 + reg = <0x0 0x3110000 0x0 0x10000>;
9094 + interrupts = <0 81 0x4>; /* Level high type */
9095 + dr_mode = "host";
9096 + snps,quirk-frame-length-adjustment = <0x20>;
9097 + snps,dis_rxdet_inp3_quirk;
9098 + };
9099 +
9100 + serdes1: serdes@1ea0000 {
9101 + reg = <0x0 0x1ea0000 0 0x00002000>;
9102 + };
9103 +
9104 + ccn@4000000 {
9105 + compatible = "arm,ccn-504";
9106 + reg = <0x0 0x04000000 0x0 0x01000000>;
9107 + interrupts = <0 12 4>;
9108 + };
9109 +
9110 + ftm0: ftm0@2800000 {
9111 + compatible = "fsl,ftm-alarm";
9112 + reg = <0x0 0x2800000 0x0 0x10000>;
9113 + interrupts = <0 44 4>;
9114 + };
9115 + };
9116 +
9117 + ddr1: memory-controller@1080000 {
9118 + compatible = "fsl,qoriq-memory-controller";
9119 + reg = <0x0 0x1080000 0x0 0x1000>;
9120 + interrupts = <0 17 0x4>;
9121 + little-endian;
9122 + };
9123 +
9124 + ddr2: memory-controller@1090000 {
9125 + compatible = "fsl,qoriq-memory-controller";
9126 + reg = <0x0 0x1090000 0x0 0x1000>;
9127 + interrupts = <0 18 0x4>;
9128 + little-endian;
9129 + };
9130 +};
9131 diff --git a/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9132 new file mode 100644
9133 index 00000000..14680adb
9134 --- /dev/null
9135 +++ b/arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
9136 @@ -0,0 +1,81 @@
9137 +/*
9138 + * QorIQ BMan Portals device tree
9139 + *
9140 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9141 + *
9142 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9143 + */
9144 +
9145 +&bportals {
9146 + #address-cells = <1>;
9147 + #size-cells = <1>;
9148 + compatible = "simple-bus";
9149 +
9150 + bman-portal@0 {
9151 + cell-index = <0>;
9152 + compatible = "fsl,bman-portal";
9153 + reg = <0x0 0x4000 0x4000000 0x4000>;
9154 + interrupts = <0 173 0x4>;
9155 + };
9156 +
9157 + bman-portal@10000 {
9158 + cell-index = <1>;
9159 + compatible = "fsl,bman-portal";
9160 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9161 + interrupts = <0 175 0x4>;
9162 + };
9163 +
9164 + bman-portal@20000 {
9165 + cell-index = <2>;
9166 + compatible = "fsl,bman-portal";
9167 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9168 + interrupts = <0 177 0x4>;
9169 + };
9170 +
9171 + bman-portal@30000 {
9172 + cell-index = <3>;
9173 + compatible = "fsl,bman-portal";
9174 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9175 + interrupts = <0 179 0x4>;
9176 + };
9177 +
9178 + bman-portal@40000 {
9179 + cell-index = <4>;
9180 + compatible = "fsl,bman-portal";
9181 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9182 + interrupts = <0 181 0x4>;
9183 + };
9184 +
9185 + bman-portal@50000 {
9186 + cell-index = <5>;
9187 + compatible = "fsl,bman-portal";
9188 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9189 + interrupts = <0 183 0x4>;
9190 + };
9191 +
9192 + bman-portal@60000 {
9193 + cell-index = <6>;
9194 + compatible = "fsl,bman-portal";
9195 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9196 + interrupts = <0 185 0x4>;
9197 + };
9198 +
9199 + bman-portal@70000 {
9200 + cell-index = <7>;
9201 + compatible = "fsl,bman-portal";
9202 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9203 + interrupts = <0 187 0x4>;
9204 + };
9205 +
9206 + bman-portal@80000 {
9207 + cell-index = <8>;
9208 + compatible = "fsl,bman-portal";
9209 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9210 + interrupts = <0 189 0x4>;
9211 + };
9212 +
9213 + bman-bpids@0 {
9214 + compatible = "fsl,bpid-range";
9215 + fsl,bpid-range = <32 32>;
9216 + };
9217 +};
9218 diff --git a/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9219 new file mode 100644
9220 index 00000000..eb5af912
9221 --- /dev/null
9222 +++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
9223 @@ -0,0 +1,66 @@
9224 +/*
9225 + * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
9226 + *
9227 + * Copyright 2012 - 2015 Freescale Semiconductor Inc.
9228 + *
9229 + * Redistribution and use in source and binary forms, with or without
9230 + * modification, are permitted provided that the following conditions are met:
9231 + * * Redistributions of source code must retain the above copyright
9232 + * notice, this list of conditions and the following disclaimer.
9233 + * * Redistributions in binary form must reproduce the above copyright
9234 + * notice, this list of conditions and the following disclaimer in the
9235 + * documentation and/or other materials provided with the distribution.
9236 + * * Neither the name of Freescale Semiconductor nor the
9237 + * names of its contributors may be used to endorse or promote products
9238 + * derived from this software without specific prior written permission.
9239 + *
9240 + *
9241 + * ALTERNATIVELY, this software may be distributed under the terms of the
9242 + * GNU General Public License ("GPL") as published by the Free Software
9243 + * Foundation, either version 2 of that License or (at your option) any
9244 + * later version.
9245 + *
9246 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9247 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9248 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9249 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9250 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9251 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9252 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9253 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9254 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9255 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9256 + */
9257 +
9258 +fsldpaa: fsl,dpaa {
9259 + compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa";
9260 + ethernet@0 {
9261 + compatible = "fsl,dpa-ethernet";
9262 + fsl,fman-mac = <&enet0>;
9263 + };
9264 + ethernet@1 {
9265 + compatible = "fsl,dpa-ethernet";
9266 + fsl,fman-mac = <&enet1>;
9267 + };
9268 + ethernet@2 {
9269 + compatible = "fsl,dpa-ethernet";
9270 + fsl,fman-mac = <&enet2>;
9271 + };
9272 + ethernet@3 {
9273 + compatible = "fsl,dpa-ethernet";
9274 + fsl,fman-mac = <&enet3>;
9275 + };
9276 + ethernet@4 {
9277 + compatible = "fsl,dpa-ethernet";
9278 + fsl,fman-mac = <&enet4>;
9279 + };
9280 + ethernet@5 {
9281 + compatible = "fsl,dpa-ethernet";
9282 + fsl,fman-mac = <&enet5>;
9283 + };
9284 + ethernet@8 {
9285 + compatible = "fsl,dpa-ethernet";
9286 + fsl,fman-mac = <&enet6>;
9287 + };
9288 +};
9289 +
9290 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9291 new file mode 100644
9292 index 00000000..474bff5e
9293 --- /dev/null
9294 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
9295 @@ -0,0 +1,43 @@
9296 +/*
9297 + * QorIQ FMan v3 10g port #0 device tree
9298 + *
9299 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9300 + *
9301 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9302 + */
9303 +
9304 +fman@1a00000 {
9305 + fman0_rx_0x10: port@90000 {
9306 + cell-index = <0x10>;
9307 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9308 + reg = <0x90000 0x1000>;
9309 + fsl,fman-10g-port;
9310 + };
9311 +
9312 + fman0_tx_0x30: port@b0000 {
9313 + cell-index = <0x30>;
9314 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9315 + reg = <0xb0000 0x1000>;
9316 + fsl,fman-10g-port;
9317 + fsl,qman-channel-id = <0x800>;
9318 + };
9319 +
9320 + ethernet@f0000 {
9321 + cell-index = <0x8>;
9322 + compatible = "fsl,fman-memac";
9323 + reg = <0xf0000 0x1000>;
9324 + fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
9325 + pcsphy-handle = <&pcsphy6>;
9326 + };
9327 +
9328 + mdio@f1000 {
9329 + #address-cells = <1>;
9330 + #size-cells = <0>;
9331 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9332 + reg = <0xf1000 0x1000>;
9333 +
9334 + pcsphy6: ethernet-phy@0 {
9335 + reg = <0x0>;
9336 + };
9337 + };
9338 +};
9339 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9340 new file mode 100644
9341 index 00000000..d4326f85
9342 --- /dev/null
9343 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
9344 @@ -0,0 +1,43 @@
9345 +/*
9346 + * QorIQ FMan v3 10g port #1 device tree
9347 + *
9348 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9349 + *
9350 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9351 + */
9352 +
9353 +fman@1a00000 {
9354 + fman0_rx_0x11: port@91000 {
9355 + cell-index = <0x11>;
9356 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
9357 + reg = <0x91000 0x1000>;
9358 + fsl,fman-10g-port;
9359 + };
9360 +
9361 + fman0_tx_0x31: port@b1000 {
9362 + cell-index = <0x31>;
9363 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
9364 + reg = <0xb1000 0x1000>;
9365 + fsl,fman-10g-port;
9366 + fsl,qman-channel-id = <0x801>;
9367 + };
9368 +
9369 + ethernet@f2000 {
9370 + cell-index = <0x9>;
9371 + compatible = "fsl,fman-memac";
9372 + reg = <0xf2000 0x1000>;
9373 + fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
9374 + pcsphy-handle = <&pcsphy7>;
9375 + };
9376 +
9377 + mdio@f3000 {
9378 + #address-cells = <1>;
9379 + #size-cells = <0>;
9380 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9381 + reg = <0xf3000 0x1000>;
9382 +
9383 + pcsphy7: ethernet-phy@0 {
9384 + reg = <0x0>;
9385 + };
9386 + };
9387 +};
9388 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9389 new file mode 100644
9390 index 00000000..7170cab9
9391 --- /dev/null
9392 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
9393 @@ -0,0 +1,42 @@
9394 +/*
9395 + * QorIQ FMan v3 1g port #0 device tree
9396 + *
9397 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9398 + *
9399 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9400 + */
9401 +
9402 +fman@1a00000 {
9403 + fman0_rx_0x08: port@88000 {
9404 + cell-index = <0x8>;
9405 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9406 + reg = <0x88000 0x1000>;
9407 + };
9408 +
9409 + fman0_tx_0x28: port@a8000 {
9410 + cell-index = <0x28>;
9411 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9412 + reg = <0xa8000 0x1000>;
9413 + fsl,qman-channel-id = <0x802>;
9414 + };
9415 +
9416 + ethernet@e0000 {
9417 + cell-index = <0>;
9418 + compatible = "fsl,fman-memac";
9419 + reg = <0xe0000 0x1000>;
9420 + fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
9421 + ptp-timer = <&ptp_timer0>;
9422 + pcsphy-handle = <&pcsphy0>;
9423 + };
9424 +
9425 + mdio@e1000 {
9426 + #address-cells = <1>;
9427 + #size-cells = <0>;
9428 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9429 + reg = <0xe1000 0x1000>;
9430 +
9431 + pcsphy0: ethernet-phy@0 {
9432 + reg = <0x0>;
9433 + };
9434 + };
9435 +};
9436 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9437 new file mode 100644
9438 index 00000000..c7eb8b6e
9439 --- /dev/null
9440 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
9441 @@ -0,0 +1,42 @@
9442 +/*
9443 + * QorIQ FMan v3 1g port #1 device tree
9444 + *
9445 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9446 + *
9447 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9448 + */
9449 +
9450 +fman@1a00000 {
9451 + fman0_rx_0x09: port@89000 {
9452 + cell-index = <0x9>;
9453 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9454 + reg = <0x89000 0x1000>;
9455 + };
9456 +
9457 + fman0_tx_0x29: port@a9000 {
9458 + cell-index = <0x29>;
9459 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9460 + reg = <0xa9000 0x1000>;
9461 + fsl,qman-channel-id = <0x803>;
9462 + };
9463 +
9464 + ethernet@e2000 {
9465 + cell-index = <1>;
9466 + compatible = "fsl,fman-memac";
9467 + reg = <0xe2000 0x1000>;
9468 + fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
9469 + ptp-timer = <&ptp_timer0>;
9470 + pcsphy-handle = <&pcsphy1>;
9471 + };
9472 +
9473 + mdio@e3000 {
9474 + #address-cells = <1>;
9475 + #size-cells = <0>;
9476 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9477 + reg = <0xe3000 0x1000>;
9478 +
9479 + pcsphy1: ethernet-phy@0 {
9480 + reg = <0x0>;
9481 + };
9482 + };
9483 +};
9484 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9485 new file mode 100644
9486 index 00000000..56f9f0dd
9487 --- /dev/null
9488 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
9489 @@ -0,0 +1,42 @@
9490 +/*
9491 + * QorIQ FMan v3 1g port #2 device tree
9492 + *
9493 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9494 + *
9495 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9496 + */
9497 +
9498 +fman@1a00000 {
9499 + fman0_rx_0x0a: port@8a000 {
9500 + cell-index = <0xa>;
9501 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9502 + reg = <0x8a000 0x1000>;
9503 + };
9504 +
9505 + fman0_tx_0x2a: port@aa000 {
9506 + cell-index = <0x2a>;
9507 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9508 + reg = <0xaa000 0x1000>;
9509 + fsl,qman-channel-id = <0x804>;
9510 + };
9511 +
9512 + ethernet@e4000 {
9513 + cell-index = <2>;
9514 + compatible = "fsl,fman-memac";
9515 + reg = <0xe4000 0x1000>;
9516 + fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
9517 + ptp-timer = <&ptp_timer0>;
9518 + pcsphy-handle = <&pcsphy2>;
9519 + };
9520 +
9521 + mdio@e5000 {
9522 + #address-cells = <1>;
9523 + #size-cells = <0>;
9524 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9525 + reg = <0xe5000 0x1000>;
9526 +
9527 + pcsphy2: ethernet-phy@0 {
9528 + reg = <0x0>;
9529 + };
9530 + };
9531 +};
9532 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9533 new file mode 100644
9534 index 00000000..bbe7dbaf
9535 --- /dev/null
9536 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
9537 @@ -0,0 +1,42 @@
9538 +/*
9539 + * QorIQ FMan v3 1g port #3 device tree
9540 + *
9541 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9542 + *
9543 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9544 + */
9545 +
9546 +fman@1a00000 {
9547 + fman0_rx_0x0b: port@8b000 {
9548 + cell-index = <0xb>;
9549 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9550 + reg = <0x8b000 0x1000>;
9551 + };
9552 +
9553 + fman0_tx_0x2b: port@ab000 {
9554 + cell-index = <0x2b>;
9555 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9556 + reg = <0xab000 0x1000>;
9557 + fsl,qman-channel-id = <0x805>;
9558 + };
9559 +
9560 + ethernet@e6000 {
9561 + cell-index = <3>;
9562 + compatible = "fsl,fman-memac";
9563 + reg = <0xe6000 0x1000>;
9564 + fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
9565 + ptp-timer = <&ptp_timer0>;
9566 + pcsphy-handle = <&pcsphy3>;
9567 + };
9568 +
9569 + mdio@e7000 {
9570 + #address-cells = <1>;
9571 + #size-cells = <0>;
9572 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9573 + reg = <0xe7000 0x1000>;
9574 +
9575 + pcsphy3: ethernet-phy@0 {
9576 + reg = <0x0>;
9577 + };
9578 + };
9579 +};
9580 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9581 new file mode 100644
9582 index 00000000..ead4f062
9583 --- /dev/null
9584 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
9585 @@ -0,0 +1,42 @@
9586 +/*
9587 + * QorIQ FMan v3 1g port #4 device tree
9588 + *
9589 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9590 + *
9591 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9592 + */
9593 +
9594 +fman@1a00000 {
9595 + fman0_rx_0x0c: port@8c000 {
9596 + cell-index = <0xc>;
9597 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9598 + reg = <0x8c000 0x1000>;
9599 + };
9600 +
9601 + fman0_tx_0x2c: port@ac000 {
9602 + cell-index = <0x2c>;
9603 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9604 + reg = <0xac000 0x1000>;
9605 + fsl,qman-channel-id = <0x806>;
9606 + };
9607 +
9608 + ethernet@e8000 {
9609 + cell-index = <4>;
9610 + compatible = "fsl,fman-memac";
9611 + reg = <0xe8000 0x1000>;
9612 + fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
9613 + ptp-timer = <&ptp_timer0>;
9614 + pcsphy-handle = <&pcsphy4>;
9615 + };
9616 +
9617 + mdio@e9000 {
9618 + #address-cells = <1>;
9619 + #size-cells = <0>;
9620 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9621 + reg = <0xe9000 0x1000>;
9622 +
9623 + pcsphy4: ethernet-phy@0 {
9624 + reg = <0x0>;
9625 + };
9626 + };
9627 +};
9628 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9629 new file mode 100644
9630 index 00000000..389eadaf
9631 --- /dev/null
9632 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
9633 @@ -0,0 +1,42 @@
9634 +/*
9635 + * QorIQ FMan v3 1g port #5 device tree
9636 + *
9637 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9638 + *
9639 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9640 + */
9641 +
9642 +fman@1a00000 {
9643 + fman0_rx_0x0d: port@8d000 {
9644 + cell-index = <0xd>;
9645 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx";
9646 + reg = <0x8d000 0x1000>;
9647 + };
9648 +
9649 + fman0_tx_0x2d: port@ad000 {
9650 + cell-index = <0x2d>;
9651 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx";
9652 + reg = <0xad000 0x1000>;
9653 + fsl,qman-channel-id = <0x807>;
9654 + };
9655 +
9656 + ethernet@ea000 {
9657 + cell-index = <5>;
9658 + compatible = "fsl,fman-memac";
9659 + reg = <0xea000 0x1000>;
9660 + fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
9661 + ptp-timer = <&ptp_timer0>;
9662 + pcsphy-handle = <&pcsphy5>;
9663 + };
9664 +
9665 + mdio@eb000 {
9666 + #address-cells = <1>;
9667 + #size-cells = <0>;
9668 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9669 + reg = <0xeb000 0x1000>;
9670 +
9671 + pcsphy5: ethernet-phy@0 {
9672 + reg = <0x0>;
9673 + };
9674 + };
9675 +};
9676 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
9677 new file mode 100644
9678 index 00000000..2d0df20d
9679 --- /dev/null
9680 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
9681 @@ -0,0 +1,47 @@
9682 +/*
9683 + * QorIQ FMan v3 OH ports device tree
9684 + *
9685 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9686 + *
9687 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9688 + */
9689 +
9690 +fman@1a00000 {
9691 +
9692 + fman0_oh1: port@82000 {
9693 + cell-index = <0>;
9694 + compatible = "fsl,fman-port-oh";
9695 + reg = <0x82000 0x1000>;
9696 + };
9697 +
9698 + fman0_oh2: port@83000 {
9699 + cell-index = <1>;
9700 + compatible = "fsl,fman-port-oh";
9701 + reg = <0x83000 0x1000>;
9702 + };
9703 +
9704 + fman0_oh3: port@84000 {
9705 + cell-index = <2>;
9706 + compatible = "fsl,fman-port-oh";
9707 + reg = <0x84000 0x1000>;
9708 + };
9709 +
9710 + fman0_oh4: port@85000 {
9711 + cell-index = <3>;
9712 + compatible = "fsl,fman-port-oh";
9713 + reg = <0x85000 0x1000>;
9714 + };
9715 +
9716 + fman0_oh5: port@86000 {
9717 + cell-index = <4>;
9718 + compatible = "fsl,fman-port-oh";
9719 + reg = <0x86000 0x1000>;
9720 + };
9721 +
9722 + fman0_oh6: port@87000 {
9723 + cell-index = <5>;
9724 + compatible = "fsl,fman-port-oh";
9725 + reg = <0x87000 0x1000>;
9726 + };
9727 +
9728 +};
9729 diff --git a/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
9730 new file mode 100644
9731 index 00000000..8e089f0c
9732 --- /dev/null
9733 +++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
9734 @@ -0,0 +1,130 @@
9735 +/*
9736 + * QorIQ FMan v3 device tree
9737 + *
9738 + * Copyright 2012-2015 Freescale Semiconductor Inc.
9739 + *
9740 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9741 + */
9742 +
9743 +fman0: fman@1a00000 {
9744 + #address-cells = <1>;
9745 + #size-cells = <1>;
9746 + cell-index = <0>;
9747 + compatible = "fsl,fman";
9748 + ranges = <0x0 0x00 0x1a00000 0x100000>;
9749 + reg = <0x0 0x1a00000 0x0 0x100000>;
9750 + interrupts = <0 44 0x4>, <0 45 0x4>;
9751 + clocks = <&clockgen 3 0>;
9752 + clock-names = "fmanclk";
9753 + fsl,qman-channel-range = <0x800 0x10>;
9754 +
9755 + cc {
9756 + compatible = "fsl,fman-cc";
9757 + };
9758 +
9759 + muram@0 {
9760 + compatible = "fsl,fman-muram";
9761 + reg = <0x0 0x60000>;
9762 + };
9763 +
9764 + bmi@80000 {
9765 + compatible = "fsl,fman-bmi";
9766 + reg = <0x80000 0x400>;
9767 + };
9768 +
9769 + qmi@80400 {
9770 + compatible = "fsl,fman-qmi";
9771 + reg = <0x80400 0x400>;
9772 + };
9773 +
9774 + fman0_oh_0x2: port@82000 {
9775 + cell-index = <0x2>;
9776 + compatible = "fsl,fman-v3-port-oh";
9777 + reg = <0x82000 0x1000>;
9778 + fsl,qman-channel-id = <0x809>;
9779 + };
9780 +
9781 + fman0_oh_0x3: port@83000 {
9782 + cell-index = <0x3>;
9783 + compatible = "fsl,fman-v3-port-oh";
9784 + reg = <0x83000 0x1000>;
9785 + fsl,qman-channel-id = <0x80a>;
9786 + };
9787 +
9788 + fman0_oh_0x4: port@84000 {
9789 + cell-index = <0x4>;
9790 + compatible = "fsl,fman-v3-port-oh";
9791 + reg = <0x84000 0x1000>;
9792 + fsl,qman-channel-id = <0x80b>;
9793 + };
9794 +
9795 + fman0_oh_0x5: port@85000 {
9796 + cell-index = <0x5>;
9797 + compatible = "fsl,fman-v3-port-oh";
9798 + reg = <0x85000 0x1000>;
9799 + fsl,qman-channel-id = <0x80c>;
9800 + };
9801 +
9802 + fman0_oh_0x6: port@86000 {
9803 + cell-index = <0x6>;
9804 + compatible = "fsl,fman-v3-port-oh";
9805 + reg = <0x86000 0x1000>;
9806 + fsl,qman-channel-id = <0x80d>;
9807 + };
9808 +
9809 + fman0_oh_0x7: port@87000 {
9810 + cell-index = <0x7>;
9811 + compatible = "fsl,fman-v3-port-oh";
9812 + reg = <0x87000 0x1000>;
9813 + fsl,qman-channel-id = <0x80e>;
9814 + };
9815 +
9816 + policer@c0000 {
9817 + compatible = "fsl,fman-policer";
9818 + reg = <0xc0000 0x1000>;
9819 + };
9820 +
9821 + keygen@c1000 {
9822 + compatible = "fsl,fman-keygen";
9823 + reg = <0xc1000 0x1000>;
9824 + };
9825 +
9826 + dma@c2000 {
9827 + compatible = "fsl,fman-dma";
9828 + reg = <0xc2000 0x1000>;
9829 + };
9830 +
9831 + fpm@c3000 {
9832 + compatible = "fsl,fman-fpm";
9833 + reg = <0xc3000 0x1000>;
9834 + };
9835 +
9836 + parser@c7000 {
9837 + compatible = "fsl,fman-parser";
9838 + reg = <0xc7000 0x1000>;
9839 + };
9840 +
9841 + vsps@dc000 {
9842 + compatible = "fsl,fman-vsps";
9843 + reg = <0xdc000 0x1000>;
9844 + };
9845 +
9846 + mdio0: mdio@fc000 {
9847 + #address-cells = <1>;
9848 + #size-cells = <0>;
9849 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9850 + reg = <0xfc000 0x1000>;
9851 + };
9852 +
9853 + xmdio0: mdio@fd000 {
9854 + #address-cells = <1>;
9855 + #size-cells = <0>;
9856 + compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
9857 + reg = <0xfd000 0x1000>;
9858 + };
9859 +
9860 + ptp_timer0: ptp-timer@fe000 {
9861 + compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc";
9862 + reg = <0xfe000 0x1000>;
9863 + };
9864 +};
9865 diff --git a/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
9866 new file mode 100644
9867 index 00000000..4f7edf48
9868 --- /dev/null
9869 +++ b/arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
9870 @@ -0,0 +1,104 @@
9871 +/*
9872 + * QorIQ QMan Portals device tree
9873 + *
9874 + * Copyright 2011-2016 Freescale Semiconductor Inc.
9875 + *
9876 + * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
9877 + */
9878 +
9879 +&qportals {
9880 + #address-cells = <1>;
9881 + #size-cells = <1>;
9882 + compatible = "simple-bus";
9883 +
9884 + qportal0: qman-portal@0 {
9885 + compatible = "fsl,qman-portal";
9886 + reg = <0x0 0x4000 0x4000000 0x4000>;
9887 + interrupts = <0 172 0x4>;
9888 + cell-index = <0>;
9889 + };
9890 +
9891 + qportal1: qman-portal@10000 {
9892 + compatible = "fsl,qman-portal";
9893 + reg = <0x10000 0x4000 0x4010000 0x4000>;
9894 + interrupts = <0 174 0x4>;
9895 + cell-index = <1>;
9896 + };
9897 +
9898 + qportal2: qman-portal@20000 {
9899 + compatible = "fsl,qman-portal";
9900 + reg = <0x20000 0x4000 0x4020000 0x4000>;
9901 + interrupts = <0 176 0x4>;
9902 + cell-index = <2>;
9903 + };
9904 +
9905 + qportal3: qman-portal@30000 {
9906 + compatible = "fsl,qman-portal";
9907 + reg = <0x30000 0x4000 0x4030000 0x4000>;
9908 + interrupts = <0 178 0x4>;
9909 + cell-index = <3>;
9910 + };
9911 +
9912 + qportal4: qman-portal@40000 {
9913 + compatible = "fsl,qman-portal";
9914 + reg = <0x40000 0x4000 0x4040000 0x4000>;
9915 + interrupts = <0 180 0x4>;
9916 + cell-index = <4>;
9917 + };
9918 +
9919 + qportal5: qman-portal@50000 {
9920 + compatible = "fsl,qman-portal";
9921 + reg = <0x50000 0x4000 0x4050000 0x4000>;
9922 + interrupts = <0 182 0x4>;
9923 + cell-index = <5>;
9924 + };
9925 +
9926 + qportal6: qman-portal@60000 {
9927 + compatible = "fsl,qman-portal";
9928 + reg = <0x60000 0x4000 0x4060000 0x4000>;
9929 + interrupts = <0 184 0x4>;
9930 + cell-index = <6>;
9931 + };
9932 +
9933 + qportal7: qman-portal@70000 {
9934 + compatible = "fsl,qman-portal";
9935 + reg = <0x70000 0x4000 0x4070000 0x4000>;
9936 + interrupts = <0 186 0x4>;
9937 + cell-index = <7>;
9938 + };
9939 +
9940 + qportal8: qman-portal@80000 {
9941 + compatible = "fsl,qman-portal";
9942 + reg = <0x80000 0x4000 0x4080000 0x4000>;
9943 + interrupts = <0 188 0x4>;
9944 + cell-index = <8>;
9945 + };
9946 +
9947 + qman-fqids@0 {
9948 + compatible = "fsl,fqid-range";
9949 + fsl,fqid-range = <256 256>;
9950 + };
9951 +
9952 + qman-fqids@1 {
9953 + compatible = "fsl,fqid-range";
9954 + fsl,fqid-range = <32768 32768>;
9955 + };
9956 +
9957 + qman-pools@0 {
9958 + compatible = "fsl,pool-channel-range";
9959 + fsl,pool-channel-range = <0x401 0xf>;
9960 + };
9961 +
9962 + qman-cgrids@0 {
9963 + compatible = "fsl,cgrid-range";
9964 + fsl,cgrid-range = <0 256>;
9965 + };
9966 +
9967 + qman-ceetm@0 {
9968 + compatible = "fsl,qman-ceetm";
9969 + fsl,ceetm-lfqid-range = <0xf00000 0x1000>;
9970 + fsl,ceetm-sp-range = <0 12>;
9971 + fsl,ceetm-lni-range = <0 8>;
9972 + fsl,ceetm-channel-range = <0 32>;
9973 + };
9974 +};
9975 diff --git a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
9976 index 5022432e..65701ada 100644
9977 --- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
9978 +++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi
9979 @@ -38,51 +38,61 @@
9980 compatible = "simple-bus";
9981
9982 bman-portal@0 {
9983 + cell-index = <0>;
9984 compatible = "fsl,bman-portal";
9985 reg = <0x0 0x4000>, <0x100000 0x1000>;
9986 interrupts = <105 2 0 0>;
9987 };
9988 bman-portal@4000 {
9989 + cell-index = <1>;
9990 compatible = "fsl,bman-portal";
9991 reg = <0x4000 0x4000>, <0x101000 0x1000>;
9992 interrupts = <107 2 0 0>;
9993 };
9994 bman-portal@8000 {
9995 + cell-index = <2>;
9996 compatible = "fsl,bman-portal";
9997 reg = <0x8000 0x4000>, <0x102000 0x1000>;
9998 interrupts = <109 2 0 0>;
9999 };
10000 bman-portal@c000 {
10001 + cell-index = <3>;
10002 compatible = "fsl,bman-portal";
10003 reg = <0xc000 0x4000>, <0x103000 0x1000>;
10004 interrupts = <111 2 0 0>;
10005 };
10006 bman-portal@10000 {
10007 + cell-index = <4>;
10008 compatible = "fsl,bman-portal";
10009 reg = <0x10000 0x4000>, <0x104000 0x1000>;
10010 interrupts = <113 2 0 0>;
10011 };
10012 bman-portal@14000 {
10013 + cell-index = <5>;
10014 compatible = "fsl,bman-portal";
10015 reg = <0x14000 0x4000>, <0x105000 0x1000>;
10016 interrupts = <115 2 0 0>;
10017 };
10018 bman-portal@18000 {
10019 + cell-index = <6>;
10020 compatible = "fsl,bman-portal";
10021 reg = <0x18000 0x4000>, <0x106000 0x1000>;
10022 interrupts = <117 2 0 0>;
10023 };
10024 bman-portal@1c000 {
10025 + cell-index = <7>;
10026 compatible = "fsl,bman-portal";
10027 reg = <0x1c000 0x4000>, <0x107000 0x1000>;
10028 interrupts = <119 2 0 0>;
10029 };
10030 bman-portal@20000 {
10031 + cell-index = <8>;
10032 compatible = "fsl,bman-portal";
10033 reg = <0x20000 0x4000>, <0x108000 0x1000>;
10034 interrupts = <121 2 0 0>;
10035 };
10036 bman-portal@24000 {
10037 + cell-index = <9>;
10038 compatible = "fsl,bman-portal";
10039 reg = <0x24000 0x4000>, <0x109000 0x1000>;
10040 interrupts = <123 2 0 0>;
10041 diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10042 index c288f3c6..dd200e28 100644
10043 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10044 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi
10045 @@ -35,14 +35,14 @@
10046 fman@400000 {
10047 fman0_rx_0x10: port@90000 {
10048 cell-index = <0x10>;
10049 - compatible = "fsl,fman-v3-port-rx";
10050 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10051 reg = <0x90000 0x1000>;
10052 fsl,fman-10g-port;
10053 };
10054
10055 fman0_tx_0x30: port@b0000 {
10056 cell-index = <0x30>;
10057 - compatible = "fsl,fman-v3-port-tx";
10058 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10059 reg = <0xb0000 0x1000>;
10060 fsl,fman-10g-port;
10061 };
10062 diff --git a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10063 index 94a76982..365770c9 100644
10064 --- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10065 +++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi
10066 @@ -35,14 +35,14 @@
10067 fman@400000 {
10068 fman0_rx_0x11: port@91000 {
10069 cell-index = <0x11>;
10070 - compatible = "fsl,fman-v3-port-rx";
10071 + compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx";
10072 reg = <0x91000 0x1000>;
10073 fsl,fman-10g-port;
10074 };
10075
10076 fman0_tx_0x31: port@b1000 {
10077 cell-index = <0x31>;
10078 - compatible = "fsl,fman-v3-port-tx";
10079 + compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx";
10080 reg = <0xb1000 0x1000>;
10081 fsl,fman-10g-port;
10082 };
10083 --
10084 2.14.1
10085
Staging tree of Zoltan Herpai