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layerscape: add linux 4.9 support
[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-4.9 / 401-mtd-spi-nor-support-layerscape.patch
1 From 120fa458ffe2250ea58578ccfc85e674005463dc Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 10:53:50 +0800
4 Subject: [PATCH] mtd: spi-nor: support layerscape
5
6 This is a integrated patch for layerscape qspi support.
7
8 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
9 Signed-off-by: Yunhui Cui <B56489@freescale.com>
10 Signed-off-by: mar.krzeminski <mar.krzeminski@gmail.com>
11 Signed-off-by: Alison Wang <b18965@freescale.com>
12 Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.kw@hitachi.com>
13 Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com>
14 Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
15 Signed-off-by: Alexander Kurz <akurz@blala.de>
16 Signed-off-by: L. D. Pinney <ldpinney@gmail.com>
17 Signed-off-by: Ash Benz <ash.benz@bk.ru>
18 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
19 ---
20 drivers/mtd/mtdchar.c | 2 +-
21 drivers/mtd/spi-nor/fsl-quadspi.c | 356 +++++++++++++++++++++++++++++++-------
22 drivers/mtd/spi-nor/spi-nor.c | 136 +++++++++++++--
23 include/linux/mtd/spi-nor.h | 14 +-
24 4 files changed, 432 insertions(+), 76 deletions(-)
25
26 diff --git a/drivers/mtd/mtdchar.c b/drivers/mtd/mtdchar.c
27 index 2a47a3f0..4f21401d 100644
28 --- a/drivers/mtd/mtdchar.c
29 +++ b/drivers/mtd/mtdchar.c
30 @@ -451,7 +451,7 @@ static int mtdchar_readoob(struct file *file, struct mtd_info *mtd,
31 * data. For our userspace tools it is important to dump areas
32 * with ECC errors!
33 * For kernel internal usage it also might return -EUCLEAN
34 - * to signal the caller that a bitflip has occured and has
35 + * to signal the caller that a bitflip has occurred and has
36 * been corrected by the ECC algorithm.
37 *
38 * Note: currently the standard NAND function, nand_read_oob_std,
39 diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c
40 index 5c82e4ef..8fb75532 100644
41 --- a/drivers/mtd/spi-nor/fsl-quadspi.c
42 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
43 @@ -41,6 +41,8 @@
44 #define QUADSPI_QUIRK_TKT253890 (1 << 2)
45 /* Controller cannot wake up from wait mode, TKT245618 */
46 #define QUADSPI_QUIRK_TKT245618 (1 << 3)
47 +/* QSPI_AMBA_BASE is internally added by SOC design */
48 +#define QUADSPI_AMBA_BASE_INTERNAL (0x10000)
49
50 /* The registers */
51 #define QUADSPI_MCR 0x00
52 @@ -193,7 +195,7 @@
53 #define QUADSPI_LUT_NUM 64
54
55 /* SEQID -- we can have 16 seqids at most. */
56 -#define SEQID_QUAD_READ 0
57 +#define SEQID_READ 0
58 #define SEQID_WREN 1
59 #define SEQID_WRDI 2
60 #define SEQID_RDSR 3
61 @@ -205,15 +207,22 @@
62 #define SEQID_RDCR 9
63 #define SEQID_EN4B 10
64 #define SEQID_BRWR 11
65 +#define SEQID_RDAR_OR_RD_EVCR 12
66 +#define SEQID_WRAR 13
67 +#define SEQID_WD_EVCR 14
68
69 #define QUADSPI_MIN_IOMAP SZ_4M
70
71 +#define FLASH_VENDOR_SPANSION_FS "s25fs"
72 +#define SPANSION_S25FS_FAMILY (1 << 1)
73 +
74 enum fsl_qspi_devtype {
75 FSL_QUADSPI_VYBRID,
76 FSL_QUADSPI_IMX6SX,
77 FSL_QUADSPI_IMX7D,
78 FSL_QUADSPI_IMX6UL,
79 FSL_QUADSPI_LS1021A,
80 + FSL_QUADSPI_LS2080A,
81 };
82
83 struct fsl_qspi_devtype_data {
84 @@ -224,7 +233,7 @@ struct fsl_qspi_devtype_data {
85 int driver_data;
86 };
87
88 -static struct fsl_qspi_devtype_data vybrid_data = {
89 +static const struct fsl_qspi_devtype_data vybrid_data = {
90 .devtype = FSL_QUADSPI_VYBRID,
91 .rxfifo = 128,
92 .txfifo = 64,
93 @@ -232,7 +241,7 @@ static struct fsl_qspi_devtype_data vybrid_data = {
94 .driver_data = QUADSPI_QUIRK_SWAP_ENDIAN,
95 };
96
97 -static struct fsl_qspi_devtype_data imx6sx_data = {
98 +static const struct fsl_qspi_devtype_data imx6sx_data = {
99 .devtype = FSL_QUADSPI_IMX6SX,
100 .rxfifo = 128,
101 .txfifo = 512,
102 @@ -241,7 +250,7 @@ static struct fsl_qspi_devtype_data imx6sx_data = {
103 | QUADSPI_QUIRK_TKT245618,
104 };
105
106 -static struct fsl_qspi_devtype_data imx7d_data = {
107 +static const struct fsl_qspi_devtype_data imx7d_data = {
108 .devtype = FSL_QUADSPI_IMX7D,
109 .rxfifo = 512,
110 .txfifo = 512,
111 @@ -250,7 +259,7 @@ static struct fsl_qspi_devtype_data imx7d_data = {
112 | QUADSPI_QUIRK_4X_INT_CLK,
113 };
114
115 -static struct fsl_qspi_devtype_data imx6ul_data = {
116 +static const struct fsl_qspi_devtype_data imx6ul_data = {
117 .devtype = FSL_QUADSPI_IMX6UL,
118 .rxfifo = 128,
119 .txfifo = 512,
120 @@ -267,6 +276,14 @@ static struct fsl_qspi_devtype_data ls1021a_data = {
121 .driver_data = 0,
122 };
123
124 +static struct fsl_qspi_devtype_data ls2080a_data = {
125 + .devtype = FSL_QUADSPI_LS2080A,
126 + .rxfifo = 128,
127 + .txfifo = 64,
128 + .ahb_buf_size = 1024,
129 + .driver_data = QUADSPI_AMBA_BASE_INTERNAL | QUADSPI_QUIRK_TKT253890,
130 +};
131 +
132 #define FSL_QSPI_MAX_CHIP 4
133 struct fsl_qspi {
134 struct spi_nor nor[FSL_QSPI_MAX_CHIP];
135 @@ -282,6 +299,7 @@ struct fsl_qspi {
136 u32 nor_size;
137 u32 nor_num;
138 u32 clk_rate;
139 + u32 ddr_smp;
140 unsigned int chip_base_addr; /* We may support two chips. */
141 bool has_second_chip;
142 bool big_endian;
143 @@ -309,6 +327,23 @@ static inline int needs_wakeup_wait_mode(struct fsl_qspi *q)
144 return q->devtype_data->driver_data & QUADSPI_QUIRK_TKT245618;
145 }
146
147 +static inline int has_added_amba_base_internal(struct fsl_qspi *q)
148 +{
149 + return q->devtype_data->driver_data & QUADSPI_AMBA_BASE_INTERNAL;
150 +}
151 +
152 +static u32 fsl_get_nor_vendor(struct spi_nor *nor)
153 +{
154 + u32 vendor_id;
155 +
156 + if (nor->vendor) {
157 + if (memcmp(nor->vendor, FLASH_VENDOR_SPANSION_FS,
158 + sizeof(FLASH_VENDOR_SPANSION_FS) - 1))
159 + vendor_id = SPANSION_S25FS_FAMILY;
160 + }
161 + return vendor_id;
162 +}
163 +
164 /*
165 * R/W functions for big- or little-endian registers:
166 * The qSPI controller's endian is independent of the CPU core's endian.
167 @@ -331,6 +366,31 @@ static u32 qspi_readl(struct fsl_qspi *q, void __iomem *addr)
168 return ioread32(addr);
169 }
170
171 +static inline u32 *u8tou32(u32 *dest, const u8 *src, size_t n)
172 +{
173 + size_t i;
174 + *dest = 0;
175 +
176 + n = n > 4 ? 4 : n;
177 + for (i = 0; i < n; i++)
178 + *dest |= *src++ << i * 8;
179 +
180 + return dest;
181 +
182 +}
183 +
184 +static inline u8 *u32tou8(u8 *dest, const u32 *src, size_t n)
185 +{
186 + size_t i;
187 + u8 *xdest = dest;
188 +
189 + n = n > 4 ? 4 : n;
190 + for (i = 0; i < n; i++)
191 + *xdest++ = *src >> i * 8;
192 +
193 + return dest;
194 +}
195 +
196 /*
197 * An IC bug makes us to re-arrange the 32-bit data.
198 * The following chips, such as IMX6SLX, have fixed this bug.
199 @@ -373,8 +433,15 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
200 void __iomem *base = q->iobase;
201 int rxfifo = q->devtype_data->rxfifo;
202 u32 lut_base;
203 - u8 cmd, addrlen, dummy;
204 int i;
205 + u32 vendor;
206 +
207 + struct spi_nor *nor = &q->nor[0];
208 + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT;
209 + u8 read_op = nor->read_opcode;
210 + u8 read_dm = nor->read_dummy;
211 +
212 + vendor = fsl_get_nor_vendor(nor);
213
214 fsl_qspi_unlock_lut(q);
215
216 @@ -382,25 +449,51 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
217 for (i = 0; i < QUADSPI_LUT_NUM; i++)
218 qspi_writel(q, 0, base + QUADSPI_LUT_BASE + i * 4);
219
220 - /* Quad Read */
221 - lut_base = SEQID_QUAD_READ * 4;
222 -
223 - if (q->nor_size <= SZ_16M) {
224 - cmd = SPINOR_OP_READ_1_1_4;
225 - addrlen = ADDR24BIT;
226 - dummy = 8;
227 - } else {
228 - /* use the 4-byte address */
229 - cmd = SPINOR_OP_READ_1_1_4;
230 - addrlen = ADDR32BIT;
231 - dummy = 8;
232 - }
233 -
234 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
235 + /* Read */
236 + lut_base = SEQID_READ * 4;
237 +
238 + if (nor->flash_read == SPI_NOR_FAST) {
239 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
240 + LUT1(ADDR, PAD1, addrlen),
241 + base + QUADSPI_LUT(lut_base));
242 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
243 + LUT1(FSL_READ, PAD1, rxfifo),
244 + base + QUADSPI_LUT(lut_base + 1));
245 + } else if (nor->flash_read == SPI_NOR_QUAD) {
246 + if (q->nor_size == 0x4000000) {
247 + read_op = 0xEC;
248 + qspi_writel(q,
249 + LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD4, addrlen),
250 + base + QUADSPI_LUT(lut_base));
251 + qspi_writel(q,
252 + LUT0(MODE, PAD4, 0xff) | LUT1(DUMMY, PAD4, read_dm),
253 + base + QUADSPI_LUT(lut_base + 1));
254 + qspi_writel(q,
255 + LUT0(FSL_READ, PAD4, rxfifo),
256 + base + QUADSPI_LUT(lut_base + 2));
257 + } else {
258 + qspi_writel(q, LUT0(CMD, PAD1, read_op) |
259 + LUT1(ADDR, PAD1, addrlen),
260 + base + QUADSPI_LUT(lut_base));
261 + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) |
262 + LUT1(FSL_READ, PAD4, rxfifo),
263 + base + QUADSPI_LUT(lut_base + 1));
264 + }
265 + } else if (nor->flash_read == SPI_NOR_DDR_QUAD) {
266 + /* read mode : 1-4-4, such as Spansion s25fl128s. */
267 + qspi_writel(q, LUT0(CMD, PAD1, read_op)
268 + | LUT1(ADDR_DDR, PAD4, addrlen),
269 base + QUADSPI_LUT(lut_base));
270 - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo),
271 +
272 + qspi_writel(q, LUT0(MODE_DDR, PAD4, 0xff)
273 + | LUT1(DUMMY, PAD1, read_dm),
274 base + QUADSPI_LUT(lut_base + 1));
275
276 + qspi_writel(q, LUT0(FSL_READ_DDR, PAD4, rxfifo)
277 + | LUT1(JMP_ON_CS, PAD1, 0),
278 + base + QUADSPI_LUT(lut_base + 2));
279 + }
280 +
281 /* Write enable */
282 lut_base = SEQID_WREN * 4;
283 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WREN),
284 @@ -409,16 +502,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
285 /* Page Program */
286 lut_base = SEQID_PP * 4;
287
288 - if (q->nor_size <= SZ_16M) {
289 - cmd = SPINOR_OP_PP;
290 - addrlen = ADDR24BIT;
291 - } else {
292 - /* use the 4-byte address */
293 - cmd = SPINOR_OP_PP;
294 - addrlen = ADDR32BIT;
295 - }
296 -
297 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
298 + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) |
299 + LUT1(ADDR, PAD1, addrlen),
300 base + QUADSPI_LUT(lut_base));
301 qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0),
302 base + QUADSPI_LUT(lut_base + 1));
303 @@ -432,10 +517,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
304 /* Erase a sector */
305 lut_base = SEQID_SE * 4;
306
307 - cmd = q->nor[0].erase_opcode;
308 - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT;
309 -
310 - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
311 + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) |
312 + LUT1(ADDR, PAD1, addrlen),
313 base + QUADSPI_LUT(lut_base));
314
315 /* Erase the whole chip */
316 @@ -476,6 +559,44 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
317 qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_BRWR),
318 base + QUADSPI_LUT(lut_base));
319
320 +
321 + /*
322 + * Flash Micron and Spansion command confilict
323 + * use the same value 0x65. But it indicates different meaning.
324 + */
325 + lut_base = SEQID_RDAR_OR_RD_EVCR * 4;
326 +
327 + if (vendor == SPANSION_S25FS_FAMILY) {
328 + /*
329 + * Read any device register.
330 + * Used for Spansion S25FS-S family flash only.
331 + */
332 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_RDAR) |
333 + LUT1(ADDR, PAD1, ADDR24BIT),
334 + base + QUADSPI_LUT(lut_base));
335 + qspi_writel(q, LUT0(DUMMY, PAD1, 8) | LUT1(FSL_READ, PAD1, 1),
336 + base + QUADSPI_LUT(lut_base + 1));
337 + } else {
338 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_RD_EVCR),
339 + base + QUADSPI_LUT(lut_base));
340 + }
341 +
342 + /*
343 + * Write any device register.
344 + * Used for Spansion S25FS-S family flash only.
345 + */
346 + lut_base = SEQID_WRAR * 4;
347 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_SPANSION_WRAR) |
348 + LUT1(ADDR, PAD1, ADDR24BIT),
349 + base + QUADSPI_LUT(lut_base));
350 + qspi_writel(q, LUT0(FSL_WRITE, PAD1, 1),
351 + base + QUADSPI_LUT(lut_base + 1));
352 +
353 + /* Write EVCR register */
354 + lut_base = SEQID_WD_EVCR * 4;
355 + qspi_writel(q, LUT0(CMD, PAD1, SPINOR_OP_WD_EVCR),
356 + base + QUADSPI_LUT(lut_base));
357 +
358 fsl_qspi_lock_lut(q);
359 }
360
361 @@ -483,8 +604,24 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q)
362 static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
363 {
364 switch (cmd) {
365 + case SPINOR_OP_READ_1_4_4_D:
366 + case SPINOR_OP_READ4_1_4_4_D:
367 + case SPINOR_OP_READ4_1_1_4:
368 case SPINOR_OP_READ_1_1_4:
369 - return SEQID_QUAD_READ;
370 + case SPINOR_OP_READ_FAST:
371 + case SPINOR_OP_READ4_FAST:
372 + return SEQID_READ;
373 + /*
374 + * Spansion & Micron use the same command value 0x65
375 + * Spansion: SPINOR_OP_SPANSION_RDAR, read any register.
376 + * Micron: SPINOR_OP_RD_EVCR,
377 + * read enhanced volatile configuration register.
378 + * case SPINOR_OP_RD_EVCR:
379 + */
380 + case SPINOR_OP_SPANSION_RDAR:
381 + return SEQID_RDAR_OR_RD_EVCR;
382 + case SPINOR_OP_SPANSION_WRAR:
383 + return SEQID_WRAR;
384 case SPINOR_OP_WREN:
385 return SEQID_WREN;
386 case SPINOR_OP_WRDI:
387 @@ -496,6 +633,7 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
388 case SPINOR_OP_CHIP_ERASE:
389 return SEQID_CHIP_ERASE;
390 case SPINOR_OP_PP:
391 + case SPINOR_OP_PP_4B:
392 return SEQID_PP;
393 case SPINOR_OP_RDID:
394 return SEQID_RDID;
395 @@ -507,6 +645,8 @@ static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
396 return SEQID_EN4B;
397 case SPINOR_OP_BRWR:
398 return SEQID_BRWR;
399 + case SPINOR_OP_WD_EVCR:
400 + return SEQID_WD_EVCR;
401 default:
402 if (cmd == q->nor[0].erase_opcode)
403 return SEQID_SE;
404 @@ -531,8 +671,11 @@ fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
405 /* save the reg */
406 reg = qspi_readl(q, base + QUADSPI_MCR);
407
408 - qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
409 - base + QUADSPI_SFAR);
410 + if (has_added_amba_base_internal(q))
411 + qspi_writel(q, q->chip_base_addr + addr, base + QUADSPI_SFAR);
412 + else
413 + qspi_writel(q, q->memmap_phy + q->chip_base_addr + addr,
414 + base + QUADSPI_SFAR);
415 qspi_writel(q, QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
416 base + QUADSPI_RBCT);
417 qspi_writel(q, reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
418 @@ -582,10 +725,10 @@ static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
419 q->chip_base_addr, tmp);
420
421 if (len >= 4) {
422 - *((u32 *)rxbuf) = tmp;
423 + u32tou8(rxbuf, &tmp, 4);
424 rxbuf += 4;
425 } else {
426 - memcpy(rxbuf, &tmp, len);
427 + u32tou8(rxbuf, &tmp, len);
428 break;
429 }
430
431 @@ -619,11 +762,12 @@ static inline void fsl_qspi_invalid(struct fsl_qspi *q)
432 }
433
434 static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
435 - u8 opcode, unsigned int to, u32 *txbuf,
436 + u8 opcode, unsigned int to, u8 *txbuf,
437 unsigned count)
438 {
439 int ret, i, j;
440 u32 tmp;
441 + u8 byts;
442
443 dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
444 q->chip_base_addr, to, count);
445 @@ -633,10 +777,13 @@ static ssize_t fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
446 qspi_writel(q, tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR);
447
448 /* fill the TX data to the FIFO */
449 + byts = count;
450 for (j = 0, i = ((count + 3) / 4); j < i; j++) {
451 - tmp = fsl_qspi_endian_xchg(q, *txbuf);
452 + u8tou32(&tmp, txbuf, byts);
453 + tmp = fsl_qspi_endian_xchg(q, tmp);
454 qspi_writel(q, tmp, q->iobase + QUADSPI_TBDR);
455 - txbuf++;
456 + txbuf += 4;
457 + byts -= 4;
458 }
459
460 /* fill the TXFIFO upto 16 bytes for i.MX7d */
461 @@ -657,11 +804,43 @@ static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
462 {
463 int nor_size = q->nor_size;
464 void __iomem *base = q->iobase;
465 + u32 mem_base;
466 +
467 + if (has_added_amba_base_internal(q))
468 + mem_base = 0x0;
469 + else
470 + mem_base = q->memmap_phy;
471 +
472 + qspi_writel(q, nor_size + mem_base, base + QUADSPI_SFA1AD);
473 + qspi_writel(q, nor_size * 2 + mem_base, base + QUADSPI_SFA2AD);
474 + qspi_writel(q, nor_size * 3 + mem_base, base + QUADSPI_SFB1AD);
475 + qspi_writel(q, nor_size * 4 + mem_base, base + QUADSPI_SFB2AD);
476 +}
477 +
478 +/*
479 + * enable controller ddr quad mode to support different
480 + * vender flashes ddr quad mode.
481 + */
482 +static void set_ddr_quad_mode(struct fsl_qspi *q)
483 +{
484 + u32 reg, reg2;
485 +
486 + reg = qspi_readl(q, q->iobase + QUADSPI_MCR);
487 +
488 + /* Firstly, disable the module */
489 + qspi_writel(q, reg | QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
490 +
491 + /* Set the Sampling Register for DDR */
492 + reg2 = qspi_readl(q, q->iobase + QUADSPI_SMPR);
493 + reg2 &= ~QUADSPI_SMPR_DDRSMP_MASK;
494 + reg2 |= (((q->ddr_smp) << QUADSPI_SMPR_DDRSMP_SHIFT) &
495 + QUADSPI_SMPR_DDRSMP_MASK);
496 + qspi_writel(q, reg2, q->iobase + QUADSPI_SMPR);
497 +
498 + /* Enable the module again (enable the DDR too) */
499 + reg |= QUADSPI_MCR_DDR_EN_MASK;
500 + qspi_writel(q, reg, q->iobase + QUADSPI_MCR);
501
502 - qspi_writel(q, nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
503 - qspi_writel(q, nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
504 - qspi_writel(q, nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
505 - qspi_writel(q, nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
506 }
507
508 /*
509 @@ -681,19 +860,36 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
510 {
511 void __iomem *base = q->iobase;
512 int seqid;
513 + const struct fsl_qspi_devtype_data *devtype_data = q->devtype_data;
514
515 /* AHB configuration for access buffer 0/1/2 .*/
516 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
517 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
518 qspi_writel(q, QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
519 +
520 /*
521 - * Set ADATSZ with the maximum AHB buffer size to improve the
522 - * read performance.
523 + * Errata: A-009282: QuadSPI data prefetch may result in incorrect data
524 + * Workaround: Keep the read data size to 64 bits (8 bytes).
525 + * This disables the prefetch on the AHB buffer and
526 + * prevents this issue from occurring.
527 */
528 - qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
529 - ((q->devtype_data->ahb_buf_size / 8)
530 - << QUADSPI_BUF3CR_ADATSZ_SHIFT),
531 - base + QUADSPI_BUF3CR);
532 + if (devtype_data->devtype == FSL_QUADSPI_LS2080A ||
533 + devtype_data->devtype == FSL_QUADSPI_LS1021A) {
534 +
535 + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
536 + (1 << QUADSPI_BUF3CR_ADATSZ_SHIFT),
537 + base + QUADSPI_BUF3CR);
538 +
539 + } else {
540 + /*
541 + * Set ADATSZ with the maximum AHB buffer size to improve the
542 + * read performance.
543 + */
544 + qspi_writel(q, QUADSPI_BUF3CR_ALLMST_MASK |
545 + ((q->devtype_data->ahb_buf_size / 8)
546 + << QUADSPI_BUF3CR_ADATSZ_SHIFT),
547 + base + QUADSPI_BUF3CR);
548 + }
549
550 /* We only use the buffer3 */
551 qspi_writel(q, 0, base + QUADSPI_BUF0IND);
552 @@ -704,6 +900,11 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
553 seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
554 qspi_writel(q, seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
555 q->iobase + QUADSPI_BFGENCR);
556 +
557 + /* enable the DDR quad read */
558 + if (q->nor->flash_read == SPI_NOR_DDR_QUAD)
559 + set_ddr_quad_mode(q);
560 +
561 }
562
563 /* This function was used to prepare and enable QSPI clock */
564 @@ -822,6 +1023,7 @@ static const struct of_device_id fsl_qspi_dt_ids[] = {
565 { .compatible = "fsl,imx7d-qspi", .data = (void *)&imx7d_data, },
566 { .compatible = "fsl,imx6ul-qspi", .data = (void *)&imx6ul_data, },
567 { .compatible = "fsl,ls1021a-qspi", .data = (void *)&ls1021a_data, },
568 + { .compatible = "fsl,ls2080a-qspi", .data = (void *)&ls2080a_data, },
569 { /* sentinel */ }
570 };
571 MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
572 @@ -835,8 +1037,12 @@ static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
573 {
574 int ret;
575 struct fsl_qspi *q = nor->priv;
576 + u32 to = 0;
577 +
578 + if (opcode == SPINOR_OP_SPANSION_RDAR)
579 + u8tou32(&to, nor->cmd_buf, 4);
580
581 - ret = fsl_qspi_runcmd(q, opcode, 0, len);
582 + ret = fsl_qspi_runcmd(q, opcode, to, len);
583 if (ret)
584 return ret;
585
586 @@ -848,9 +1054,13 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
587 {
588 struct fsl_qspi *q = nor->priv;
589 int ret;
590 + u32 to = 0;
591 +
592 + if (opcode == SPINOR_OP_SPANSION_WRAR)
593 + u8tou32(&to, nor->cmd_buf, 4);
594
595 if (!buf) {
596 - ret = fsl_qspi_runcmd(q, opcode, 0, 1);
597 + ret = fsl_qspi_runcmd(q, opcode, to, 1);
598 if (ret)
599 return ret;
600
601 @@ -859,7 +1069,7 @@ static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
602
603 } else if (len > 0) {
604 ret = fsl_qspi_nor_write(q, nor, opcode, 0,
605 - (u32 *)buf, len);
606 + buf, len);
607 if (ret > 0)
608 return 0;
609 } else {
610 @@ -875,7 +1085,7 @@ static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to,
611 {
612 struct fsl_qspi *q = nor->priv;
613 ssize_t ret = fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
614 - (u32 *)buf, len);
615 + (u8 *)buf, len);
616
617 /* invalid the data in the AHB buffer. */
618 fsl_qspi_invalid(q);
619 @@ -922,7 +1132,7 @@ static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from,
620 len);
621
622 /* Read out the data directly from the AHB buffer.*/
623 - memcpy(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
624 + memcpy_toio(buf, q->ahb_addr + q->chip_base_addr + from - q->memmap_offs,
625 len);
626
627 return len;
628 @@ -980,6 +1190,8 @@ static int fsl_qspi_probe(struct platform_device *pdev)
629 struct spi_nor *nor;
630 struct mtd_info *mtd;
631 int ret, i = 0;
632 + int find_node;
633 + enum read_mode mode = SPI_NOR_QUAD;
634
635 q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
636 if (!q)
637 @@ -1027,6 +1239,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
638 goto clk_failed;
639 }
640
641 + /* find ddrsmp value */
642 + ret = of_property_read_u32(dev->of_node, "fsl,ddr-sampling-point",
643 + &q->ddr_smp);
644 + if (ret)
645 + q->ddr_smp = 0;
646 +
647 /* find the irq */
648 ret = platform_get_irq(pdev, 0);
649 if (ret < 0) {
650 @@ -1050,6 +1268,7 @@ static int fsl_qspi_probe(struct platform_device *pdev)
651
652 mutex_init(&q->lock);
653
654 + find_node = 0;
655 /* iterate the subnodes. */
656 for_each_available_child_of_node(dev->of_node, np) {
657 /* skip the holes */
658 @@ -1076,18 +1295,25 @@ static int fsl_qspi_probe(struct platform_device *pdev)
659 ret = of_property_read_u32(np, "spi-max-frequency",
660 &q->clk_rate);
661 if (ret < 0)
662 - goto mutex_failed;
663 + continue;
664
665 /* set the chip address for READID */
666 fsl_qspi_set_base_addr(q, nor);
667
668 - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD);
669 + ret = of_property_read_bool(np, "m25p,fast-read");
670 + mode = (ret) ? SPI_NOR_FAST : SPI_NOR_QUAD;
671 + /* Can we enable the DDR Quad Read? */
672 + ret = of_property_read_bool(np, "ddr-quad-read");
673 if (ret)
674 - goto mutex_failed;
675 + mode = SPI_NOR_DDR_QUAD;
676 +
677 + ret = spi_nor_scan(nor, NULL, mode);
678 + if (ret)
679 + continue;
680
681 ret = mtd_device_register(mtd, NULL, 0);
682 if (ret)
683 - goto mutex_failed;
684 + continue;
685
686 /* Set the correct NOR size now. */
687 if (q->nor_size == 0) {
688 @@ -1110,8 +1336,12 @@ static int fsl_qspi_probe(struct platform_device *pdev)
689 nor->page_size = q->devtype_data->txfifo;
690
691 i++;
692 + find_node++;
693 }
694
695 + if (find_node == 0)
696 + goto mutex_failed;
697 +
698 /* finish the rest init. */
699 ret = fsl_qspi_nor_setup_last(q);
700 if (ret)
701 diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
702 index 793d321d..190e0e45 100644
703 --- a/drivers/mtd/spi-nor/spi-nor.c
704 +++ b/drivers/mtd/spi-nor/spi-nor.c
705 @@ -40,6 +40,13 @@
706 #define SPI_NOR_MAX_ID_LEN 6
707 #define SPI_NOR_MAX_ADDR_WIDTH 4
708
709 +#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f
710 +/* Added for S25FS-S family flash */
711 +#define SPINOR_CONFIG_REG3_OFFSET 0x800004
712 +#define CR3V_4KB_ERASE_UNABLE 0x8
713 +#define SPINOR_S25FS_FAMILY_ID 0x81
714 +
715 +
716 struct flash_info {
717 char *name;
718
719 @@ -68,7 +75,8 @@ struct flash_info {
720 #define SECT_4K_PMC BIT(4) /* SPINOR_OP_BE_4K_PMC works uniformly */
721 #define SPI_NOR_DUAL_READ BIT(5) /* Flash supports Dual Read */
722 #define SPI_NOR_QUAD_READ BIT(6) /* Flash supports Quad Read */
723 -#define USE_FSR BIT(7) /* use flag status register */
724 +#define USE_FSR BIT(13) /* use flag status register */
725 +#define SPI_NOR_DDR_QUAD_READ BIT(7) /* Flash supports DDR Quad Read */
726 #define SPI_NOR_HAS_LOCK BIT(8) /* Flash supports lock/unlock via SR */
727 #define SPI_NOR_HAS_TB BIT(9) /*
728 * Flash SR has Top/Bottom (TB) protect
729 @@ -85,9 +93,11 @@ struct flash_info {
730 * Use dedicated 4byte address op codes
731 * to support memory size above 128Mib.
732 */
733 +#define NO_CHIP_ERASE BIT(12) /* Chip does not support chip erase */
734 };
735
736 #define JEDEC_MFR(info) ((info)->id[0])
737 +#define EXT_ID(info) ((info)->id[5])
738
739 static const struct flash_info *spi_nor_match_id(const char *name);
740
741 @@ -132,7 +142,7 @@ static int read_fsr(struct spi_nor *nor)
742 /*
743 * Read configuration register, returning its value in the
744 * location. Return the configuration register value.
745 - * Returns negative if error occured.
746 + * Returns negative if error occurred.
747 */
748 static int read_cr(struct spi_nor *nor)
749 {
750 @@ -160,6 +170,8 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
751 case SPI_NOR_DUAL:
752 case SPI_NOR_QUAD:
753 return 8;
754 + case SPI_NOR_DDR_QUAD:
755 + return 6;
756 case SPI_NOR_NORMAL:
757 return 0;
758 }
759 @@ -961,6 +973,8 @@ static const struct flash_info spi_nor_ids[] = {
760
761 /* ESMT */
762 { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
763 + { "f25l32qa", INFO(0x8c4116, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
764 + { "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
765
766 /* Everspin */
767 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
768 @@ -1014,12 +1028,15 @@ static const struct flash_info spi_nor_ids[] = {
769 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
770 { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
771 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
772 + { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
773 + { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
774 + { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
775 { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64, 0) },
776 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
777 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
778 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
779 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
780 - { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_4B_OPCODES) },
781 + { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512, SECT_4K) },
782 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
783 { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
784 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
785 @@ -1033,10 +1050,11 @@ static const struct flash_info spi_nor_ids[] = {
786 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
787 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
788 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
789 + { "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
790 { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
791 { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
792 - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
793 - { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
794 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
795 + { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
796
797 /* PMC */
798 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
799 @@ -1054,8 +1072,11 @@ static const struct flash_info spi_nor_ids[] = {
800 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
801 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
802 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
803 - { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
804 + { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512, 0)},
805 + { "s25fl128s", INFO6(0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_QUAD_READ
806 + | SPI_NOR_DDR_QUAD_READ) },
807 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
808 + { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)},
809 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
810 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
811 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
812 @@ -1130,6 +1151,9 @@ static const struct flash_info spi_nor_ids[] = {
813 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
814 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
815 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
816 + { "w25q20cl", INFO(0xef4012, 0, 64 * 1024, 4, SECT_4K) },
817 + { "w25q20bw", INFO(0xef5012, 0, 64 * 1024, 4, SECT_4K) },
818 + { "w25q20ew", INFO(0xef6012, 0, 64 * 1024, 4, SECT_4K) },
819 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
820 {
821 "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
822 @@ -1192,6 +1216,53 @@ static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
823 id[0], id[1], id[2]);
824 return ERR_PTR(-ENODEV);
825 }
826 +/*
827 + * The S25FS-S family physical sectors may be configured as a
828 + * hybrid combination of eight 4-kB parameter sectors
829 + * at the top or bottom of the address space with all
830 + * but one of the remaining sectors being uniform size.
831 + * The Parameter Sector Erase commands (20h or 21h) must
832 + * be used to erase the 4-kB parameter sectors individually.
833 + * The Sector (uniform sector) Erase commands (D8h or DCh)
834 + * must be used to erase any of the remaining
835 + * sectors, including the portion of highest or lowest address
836 + * sector that is not overlaid by the parameter sectors.
837 + * The uniform sector erase command has no effect on parameter sectors.
838 + */
839 +static int spansion_s25fs_disable_4kb_erase(struct spi_nor *nor)
840 +{
841 + struct fsl_qspi *q;
842 + u32 cr3v_addr = SPINOR_CONFIG_REG3_OFFSET;
843 + u8 cr3v = 0x0;
844 + int ret = 0x0;
845 +
846 + q = nor->priv;
847 +
848 + nor->cmd_buf[2] = cr3v_addr >> 16;
849 + nor->cmd_buf[1] = cr3v_addr >> 8;
850 + nor->cmd_buf[0] = cr3v_addr >> 0;
851 +
852 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
853 + if (ret)
854 + return ret;
855 + if (cr3v & CR3V_4KB_ERASE_UNABLE)
856 + return 0;
857 + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
858 + if (ret)
859 + return ret;
860 + cr3v = CR3V_4KB_ERASE_UNABLE;
861 + nor->program_opcode = SPINOR_OP_SPANSION_WRAR;
862 + nor->write(nor, cr3v_addr, 1, &cr3v);
863 +
864 + ret = nor->read_reg(nor, SPINOR_OP_SPANSION_RDAR, &cr3v, 1);
865 + if (ret)
866 + return ret;
867 + if (!(cr3v & CR3V_4KB_ERASE_UNABLE))
868 + return -EPERM;
869 +
870 + return 0;
871 +}
872 +
873
874 static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
875 size_t *retlen, u_char *buf)
876 @@ -1411,7 +1482,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
877 * Write status Register and configuration register with 2 bytes
878 * The first byte will be written to the status register, while the
879 * second byte will be written to the configuration register.
880 - * Return negative if error occured.
881 + * Return negative if error occurred.
882 */
883 static int write_sr_cr(struct spi_nor *nor, u16 val)
884 {
885 @@ -1459,6 +1530,24 @@ static int spansion_quad_enable(struct spi_nor *nor)
886 return 0;
887 }
888
889 +static int set_ddr_quad_mode(struct spi_nor *nor, const struct flash_info *info)
890 +{
891 + int status;
892 +
893 + switch (JEDEC_MFR(info)) {
894 + case SNOR_MFR_SPANSION:
895 + status = spansion_quad_enable(nor);
896 + if (status) {
897 + dev_err(nor->dev, "Spansion DDR quad-read not enabled\n");
898 + return status;
899 + }
900 + return status;
901 + default:
902 + return -EINVAL;
903 + }
904 +}
905 +
906 +
907 static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
908 {
909 int status;
910 @@ -1604,9 +1693,25 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
911 write_sr(nor, 0);
912 spi_nor_wait_till_ready(nor);
913 }
914 + if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
915 + ret = read_sr(nor);
916 + ret &= SPI_NOR_MICRON_WRITE_ENABLE;
917 +
918 + write_enable(nor);
919 + write_sr(nor, ret);
920 + }
921 +
922 + if (EXT_ID(info) == SPINOR_S25FS_FAMILY_ID) {
923 + ret = spansion_s25fs_disable_4kb_erase(nor);
924 + if (ret)
925 + return ret;
926 + }
927 +
928
929 if (!mtd->name)
930 mtd->name = dev_name(dev);
931 + if (info->name)
932 + nor->vendor = info->name;
933 mtd->priv = nor;
934 mtd->type = MTD_NORFLASH;
935 mtd->writesize = 1;
936 @@ -1639,6 +1744,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
937 nor->flags |= SNOR_F_USE_FSR;
938 if (info->flags & SPI_NOR_HAS_TB)
939 nor->flags |= SNOR_F_HAS_SR_TB;
940 + if (info->flags & NO_CHIP_ERASE)
941 + nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
942
943 #ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
944 /* prefer "small sector" erase if possible */
945 @@ -1676,9 +1783,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
946 /* Some devices cannot do fast-read, no matter what DT tells us */
947 if (info->flags & SPI_NOR_NO_FR)
948 nor->flash_read = SPI_NOR_NORMAL;
949 -
950 - /* Quad/Dual-read mode takes precedence over fast/normal */
951 - if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
952 + /* DDR Quad/Quad/Dual-read mode takes precedence over fast/normal */
953 + if (mode == SPI_NOR_DDR_QUAD && info->flags & SPI_NOR_DDR_QUAD_READ) {
954 + ret = set_ddr_quad_mode(nor, info);
955 + if (ret) {
956 + dev_err(dev, "DDR quad mode not supported\n");
957 + return ret;
958 + }
959 + nor->flash_read = SPI_NOR_DDR_QUAD;
960 + } else if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
961 ret = set_quad_mode(nor, info);
962 if (ret) {
963 dev_err(dev, "quad mode not supported\n");
964 @@ -1691,6 +1804,9 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
965
966 /* Default commands */
967 switch (nor->flash_read) {
968 + case SPI_NOR_DDR_QUAD:
969 + nor->read_opcode = SPINOR_OP_READ4_1_4_4_D;
970 + break;
971 case SPI_NOR_QUAD:
972 nor->read_opcode = SPINOR_OP_READ_1_1_4;
973 break;
974 diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
975 index f2a71803..5003ff64 100644
976 --- a/include/linux/mtd/spi-nor.h
977 +++ b/include/linux/mtd/spi-nor.h
978 @@ -31,10 +31,10 @@
979
980 /*
981 * Note on opcode nomenclature: some opcodes have a format like
982 - * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
983 + * SPINOR_OP_FUNCTION{4,}_x_y_z{_D}. The numbers x, y,and z stand for the number
984 * of I/O lines used for the opcode, address, and data (respectively). The
985 * FUNCTION has an optional suffix of '4', to represent an opcode which
986 - * requires a 4-byte (32-bit) address.
987 + * requires a 4-byte (32-bit) address. The suffix of 'D' stands for the
988 */
989
990 /* Flash opcodes. */
991 @@ -46,7 +46,9 @@
992 #define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual Output SPI) */
993 #define SPINOR_OP_READ_1_2_2 0xbb /* Read data bytes (Dual I/O SPI) */
994 #define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad Output SPI) */
995 +#define SPINOR_OP_READ_1_4_4_D 0xed /* Read data bytes (DDR Quad SPI) */
996 #define SPINOR_OP_READ_1_4_4 0xeb /* Read data bytes (Quad I/O SPI) */
997 +#define SPINOR_OP_READ4_1_4_4_D 0xee /* Read data bytes (DDR Quad SPI) */
998 #define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
999 #define SPINOR_OP_PP_1_1_4 0x32 /* Quad page program */
1000 #define SPINOR_OP_PP_1_4_4 0x38 /* Quad page program */
1001 @@ -62,9 +64,11 @@
1002 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
1003 #define SPINOR_OP_READ_4B 0x13 /* Read data bytes (low frequency) */
1004 #define SPINOR_OP_READ_FAST_4B 0x0c /* Read data bytes (high frequency) */
1005 +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
1006 #define SPINOR_OP_READ_1_1_2_4B 0x3c /* Read data bytes (Dual Output SPI) */
1007 #define SPINOR_OP_READ_1_2_2_4B 0xbc /* Read data bytes (Dual I/O SPI) */
1008 #define SPINOR_OP_READ_1_1_4_4B 0x6c /* Read data bytes (Quad Output SPI) */
1009 +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
1010 #define SPINOR_OP_READ_1_4_4_4B 0xec /* Read data bytes (Quad I/O SPI) */
1011 #define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
1012 #define SPINOR_OP_PP_1_1_4_4B 0x34 /* Quad page program */
1013 @@ -94,6 +98,10 @@
1014 /* Used for Spansion flashes only. */
1015 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
1016
1017 +/* Used for Spansion S25FS-S family flash only. */
1018 +#define SPINOR_OP_SPANSION_RDAR 0x65 /* Read any device register */
1019 +#define SPINOR_OP_SPANSION_WRAR 0x71 /* Write any device register */
1020 +
1021 /* Used for Micron flashes only. */
1022 #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
1023 #define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
1024 @@ -124,6 +132,7 @@ enum read_mode {
1025 SPI_NOR_FAST,
1026 SPI_NOR_DUAL,
1027 SPI_NOR_QUAD,
1028 + SPI_NOR_DDR_QUAD,
1029 };
1030
1031 #define SPI_NOR_MAX_CMD_SIZE 8
1032 @@ -189,6 +198,7 @@ struct spi_nor {
1033 bool sst_write_second;
1034 u32 flags;
1035 u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
1036 + char *vendor;
1037
1038 int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
1039 void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
1040 --
1041 2.14.1
1042
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