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[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-4.9 / 704-fsl-mc-layerscape-support.patch
1 From 464b4d9b8282e0f1e5040e4914505f91ce4d3750 Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:06:25 +0800
4 Subject: [PATCH] fsl-mc: layerscape support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 This is a integrated patch for layerscape mc-bus support.
10
11 Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
12 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
13 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
14 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
15 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
16 Signed-off-by: Shiva Kerdel <shiva@exdev.nl>
17 Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
18 Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
19 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
20 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
21 ---
22 drivers/staging/fsl-mc/bus/Kconfig | 41 +-
23 drivers/staging/fsl-mc/bus/Makefile | 10 +-
24 drivers/staging/fsl-mc/bus/dpbp-cmd.h | 80 ++
25 drivers/staging/fsl-mc/bus/dpbp.c | 450 +--------
26 drivers/staging/fsl-mc/bus/dpcon-cmd.h | 85 ++
27 drivers/staging/fsl-mc/bus/dpcon.c | 317 ++++++
28 drivers/staging/fsl-mc/bus/dpio/Makefile | 11 +
29 .../{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} | 73 +-
30 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c | 296 ++++++
31 drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt | 135 +++
32 drivers/staging/fsl-mc/bus/dpio/dpio-service.c | 689 +++++++++++++
33 drivers/staging/fsl-mc/bus/dpio/dpio.c | 224 +++++
34 drivers/staging/fsl-mc/bus/dpio/dpio.h | 109 ++
35 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c | 1049 ++++++++++++++++++++
36 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h | 662 ++++++++++++
37 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c | 853 ++++++++++++++++
38 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h | 136 +++
39 drivers/staging/fsl-mc/bus/dpio/qbman_private.h | 171 ++++
40 drivers/staging/fsl-mc/bus/dpmcp-cmd.h | 112 +--
41 drivers/staging/fsl-mc/bus/dpmcp.c | 374 +------
42 drivers/staging/fsl-mc/bus/dpmcp.h | 127 +--
43 drivers/staging/fsl-mc/bus/dpmng-cmd.h | 14 +-
44 drivers/staging/fsl-mc/bus/dpmng.c | 37 +-
45 drivers/staging/fsl-mc/bus/dprc-cmd.h | 82 +-
46 drivers/staging/fsl-mc/bus/dprc-driver.c | 38 +-
47 drivers/staging/fsl-mc/bus/dprc.c | 629 +-----------
48 drivers/staging/fsl-mc/bus/fsl-mc-allocator.c | 78 +-
49 drivers/staging/fsl-mc/bus/fsl-mc-bus.c | 318 +++---
50 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c | 104 ++
51 drivers/staging/fsl-mc/bus/fsl-mc-msi.c | 3 +-
52 drivers/staging/fsl-mc/bus/fsl-mc-private.h | 6 +-
53 .../staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c | 11 +-
54 drivers/staging/fsl-mc/bus/mc-io.c | 4 +-
55 drivers/staging/fsl-mc/bus/mc-ioctl.h | 22 +
56 drivers/staging/fsl-mc/bus/mc-restool.c | 405 ++++++++
57 drivers/staging/fsl-mc/bus/mc-sys.c | 14 +-
58 drivers/staging/fsl-mc/include/dpaa2-fd.h | 706 +++++++++++++
59 drivers/staging/fsl-mc/include/dpaa2-global.h | 202 ++++
60 drivers/staging/fsl-mc/include/dpaa2-io.h | 190 ++++
61 drivers/staging/fsl-mc/include/dpbp-cmd.h | 185 ----
62 drivers/staging/fsl-mc/include/dpbp.h | 158 +--
63 drivers/staging/fsl-mc/include/dpcon.h | 115 +++
64 drivers/staging/fsl-mc/include/dpmng.h | 16 +-
65 drivers/staging/fsl-mc/include/dpopr.h | 110 ++
66 drivers/staging/fsl-mc/include/dprc.h | 470 +++------
67 drivers/staging/fsl-mc/include/mc-bus.h | 7 +-
68 drivers/staging/fsl-mc/include/mc-cmd.h | 44 +-
69 drivers/staging/fsl-mc/include/mc-sys.h | 3 +-
70 drivers/staging/fsl-mc/include/mc.h | 17 +-
71 49 files changed, 7380 insertions(+), 2612 deletions(-)
72 create mode 100644 drivers/staging/fsl-mc/bus/dpbp-cmd.h
73 create mode 100644 drivers/staging/fsl-mc/bus/dpcon-cmd.h
74 create mode 100644 drivers/staging/fsl-mc/bus/dpcon.c
75 create mode 100644 drivers/staging/fsl-mc/bus/dpio/Makefile
76 rename drivers/staging/fsl-mc/{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} (64%)
77 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
78 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt
79 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-service.c
80 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.c
81 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.h
82 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
83 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
84 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
85 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
86 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_private.h
87 create mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
88 create mode 100644 drivers/staging/fsl-mc/bus/mc-ioctl.h
89 create mode 100644 drivers/staging/fsl-mc/bus/mc-restool.c
90 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-fd.h
91 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-global.h
92 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-io.h
93 delete mode 100644 drivers/staging/fsl-mc/include/dpbp-cmd.h
94 create mode 100644 drivers/staging/fsl-mc/include/dpcon.h
95 create mode 100644 drivers/staging/fsl-mc/include/dpopr.h
96
97 --- a/drivers/staging/fsl-mc/bus/Kconfig
98 +++ b/drivers/staging/fsl-mc/bus/Kconfig
99 @@ -1,25 +1,40 @@
100 #
101 -# Freescale Management Complex (MC) bus drivers
102 +# DPAA2 fsl-mc bus
103 #
104 -# Copyright (C) 2014 Freescale Semiconductor, Inc.
105 +# Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
106 #
107 # This file is released under the GPLv2
108 #
109
110 config FSL_MC_BUS
111 - bool "Freescale Management Complex (MC) bus driver"
112 - depends on OF && ARM64
113 + bool "QorIQ DPAA2 fsl-mc bus driver"
114 + depends on OF && ARCH_LAYERSCAPE
115 select GENERIC_MSI_IRQ_DOMAIN
116 help
117 - Driver to enable the bus infrastructure for the Freescale
118 - QorIQ Management Complex (fsl-mc). The fsl-mc is a hardware
119 - module of the QorIQ LS2 SoCs, that does resource management
120 - for hardware building-blocks in the SoC that can be used
121 - to dynamically create networking hardware objects such as
122 - network interfaces (NICs), crypto accelerator instances,
123 - or L2 switches.
124 + Driver to enable the bus infrastructure for the QorIQ DPAA2
125 + architecture. The fsl-mc bus driver handles discovery of
126 + DPAA2 objects (which are represented as Linux devices) and
127 + binding objects to drivers.
128
129 - Only enable this option when building the kernel for
130 - Freescale QorQIQ LS2xxxx SoCs.
131 +config FSL_MC_DPIO
132 + tristate "QorIQ DPAA2 DPIO driver"
133 + depends on FSL_MC_BUS
134 + help
135 + Driver for the DPAA2 DPIO object. A DPIO provides queue and
136 + buffer management facilities for software to interact with
137 + other DPAA2 objects. This driver does not expose the DPIO
138 + objects individually, but groups them under a service layer
139 + API.
140
141 +config FSL_QBMAN_DEBUG
142 + tristate "Freescale QBMAN Debug APIs"
143 + depends on FSL_MC_DPIO
144 + help
145 + QBMan debug assistant APIs.
146
147 +config FSL_MC_RESTOOL
148 + tristate "Freescale Management Complex (MC) restool driver"
149 + depends on FSL_MC_BUS
150 + help
151 + Driver that provides kernel support for the Freescale Management
152 + Complex resource manager user-space tool.
153 --- a/drivers/staging/fsl-mc/bus/Makefile
154 +++ b/drivers/staging/fsl-mc/bus/Makefile
155 @@ -17,4 +17,12 @@ mc-bus-driver-objs := fsl-mc-bus.o \
156 fsl-mc-msi.o \
157 irq-gic-v3-its-fsl-mc-msi.o \
158 dpmcp.o \
159 - dpbp.o
160 + dpbp.o \
161 + dpcon.o \
162 + fsl-mc-iommu.o
163 +
164 +# MC DPIO driver
165 +obj-$(CONFIG_FSL_MC_DPIO) += dpio/
166 +
167 +# MC restool kernel support
168 +obj-$(CONFIG_FSL_MC_RESTOOL) += mc-restool.o
169 --- /dev/null
170 +++ b/drivers/staging/fsl-mc/bus/dpbp-cmd.h
171 @@ -0,0 +1,80 @@
172 +/*
173 + * Copyright 2013-2016 Freescale Semiconductor Inc.
174 + *
175 + * Redistribution and use in source and binary forms, with or without
176 + * modification, are permitted provided that the following conditions are met:
177 + * * Redistributions of source code must retain the above copyright
178 + * notice, this list of conditions and the following disclaimer.
179 + * * Redistributions in binary form must reproduce the above copyright
180 + * notice, this list of conditions and the following disclaimer in the
181 + * documentation and/or other materials provided with the distribution.
182 + * * Neither the name of the above-listed copyright holders nor the
183 + * names of any contributors may be used to endorse or promote products
184 + * derived from this software without specific prior written permission.
185 + *
186 + * ALTERNATIVELY, this software may be distributed under the terms of the
187 + * GNU General Public License ("GPL") as published by the Free Software
188 + * Foundation, either version 2 of that License or (at your option) any
189 + * later version.
190 + *
191 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
192 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
193 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
194 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
195 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
196 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
197 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
198 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
199 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
200 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
201 + * POSSIBILITY OF SUCH DAMAGE.
202 + */
203 +#ifndef _FSL_DPBP_CMD_H
204 +#define _FSL_DPBP_CMD_H
205 +
206 +/* DPBP Version */
207 +#define DPBP_VER_MAJOR 3
208 +#define DPBP_VER_MINOR 2
209 +
210 +/* Command versioning */
211 +#define DPBP_CMD_BASE_VERSION 1
212 +#define DPBP_CMD_ID_OFFSET 4
213 +
214 +#define DPBP_CMD(id) ((id << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION)
215 +
216 +/* Command IDs */
217 +#define DPBP_CMDID_CLOSE DPBP_CMD(0x800)
218 +#define DPBP_CMDID_OPEN DPBP_CMD(0x804)
219 +#define DPBP_CMDID_GET_API_VERSION DPBP_CMD(0xa04)
220 +
221 +#define DPBP_CMDID_ENABLE DPBP_CMD(0x002)
222 +#define DPBP_CMDID_DISABLE DPBP_CMD(0x003)
223 +#define DPBP_CMDID_GET_ATTR DPBP_CMD(0x004)
224 +#define DPBP_CMDID_RESET DPBP_CMD(0x005)
225 +#define DPBP_CMDID_IS_ENABLED DPBP_CMD(0x006)
226 +
227 +struct dpbp_cmd_open {
228 + __le32 dpbp_id;
229 +};
230 +
231 +struct dpbp_cmd_destroy {
232 + __le32 object_id;
233 +};
234 +
235 +#define DPBP_ENABLE 0x1
236 +
237 +struct dpbp_rsp_is_enabled {
238 + u8 enabled;
239 +};
240 +
241 +struct dpbp_rsp_get_attributes {
242 + /* response word 0 */
243 + __le16 pad;
244 + __le16 bpid;
245 + __le32 id;
246 + /* response word 1 */
247 + __le16 version_major;
248 + __le16 version_minor;
249 +};
250 +
251 +#endif /* _FSL_DPBP_CMD_H */
252 --- a/drivers/staging/fsl-mc/bus/dpbp.c
253 +++ b/drivers/staging/fsl-mc/bus/dpbp.c
254 @@ -1,4 +1,5 @@
255 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
256 +/*
257 + * Copyright 2013-2016 Freescale Semiconductor Inc.
258 *
259 * Redistribution and use in source and binary forms, with or without
260 * modification, are permitted provided that the following conditions are met:
261 @@ -11,7 +12,6 @@
262 * names of any contributors may be used to endorse or promote products
263 * derived from this software without specific prior written permission.
264 *
265 - *
266 * ALTERNATIVELY, this software may be distributed under the terms of the
267 * GNU General Public License ("GPL") as published by the Free Software
268 * Foundation, either version 2 of that License or (at your option) any
269 @@ -32,7 +32,8 @@
270 #include "../include/mc-sys.h"
271 #include "../include/mc-cmd.h"
272 #include "../include/dpbp.h"
273 -#include "../include/dpbp-cmd.h"
274 +
275 +#include "dpbp-cmd.h"
276
277 /**
278 * dpbp_open() - Open a control session for the specified object.
279 @@ -105,74 +106,6 @@ int dpbp_close(struct fsl_mc_io *mc_io,
280 EXPORT_SYMBOL(dpbp_close);
281
282 /**
283 - * dpbp_create() - Create the DPBP object.
284 - * @mc_io: Pointer to MC portal's I/O object
285 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
286 - * @cfg: Configuration structure
287 - * @token: Returned token; use in subsequent API calls
288 - *
289 - * Create the DPBP object, allocate required resources and
290 - * perform required initialization.
291 - *
292 - * The object can be created either by declaring it in the
293 - * DPL file, or by calling this function.
294 - * This function returns a unique authentication token,
295 - * associated with the specific object ID and the specific MC
296 - * portal; this token must be used in all subsequent calls to
297 - * this specific object. For objects that are created using the
298 - * DPL file, call dpbp_open function to get an authentication
299 - * token first.
300 - *
301 - * Return: '0' on Success; Error code otherwise.
302 - */
303 -int dpbp_create(struct fsl_mc_io *mc_io,
304 - u32 cmd_flags,
305 - const struct dpbp_cfg *cfg,
306 - u16 *token)
307 -{
308 - struct mc_command cmd = { 0 };
309 - int err;
310 -
311 - (void)(cfg); /* unused */
312 -
313 - /* prepare command */
314 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
315 - cmd_flags, 0);
316 -
317 - /* send command to mc*/
318 - err = mc_send_command(mc_io, &cmd);
319 - if (err)
320 - return err;
321 -
322 - /* retrieve response parameters */
323 - *token = mc_cmd_hdr_read_token(&cmd);
324 -
325 - return 0;
326 -}
327 -
328 -/**
329 - * dpbp_destroy() - Destroy the DPBP object and release all its resources.
330 - * @mc_io: Pointer to MC portal's I/O object
331 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
332 - * @token: Token of DPBP object
333 - *
334 - * Return: '0' on Success; error code otherwise.
335 - */
336 -int dpbp_destroy(struct fsl_mc_io *mc_io,
337 - u32 cmd_flags,
338 - u16 token)
339 -{
340 - struct mc_command cmd = { 0 };
341 -
342 - /* prepare command */
343 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
344 - cmd_flags, token);
345 -
346 - /* send command to mc*/
347 - return mc_send_command(mc_io, &cmd);
348 -}
349 -
350 -/**
351 * dpbp_enable() - Enable the DPBP.
352 * @mc_io: Pointer to MC portal's I/O object
353 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
354 @@ -250,6 +183,7 @@ int dpbp_is_enabled(struct fsl_mc_io *mc
355
356 return 0;
357 }
358 +EXPORT_SYMBOL(dpbp_is_enabled);
359
360 /**
361 * dpbp_reset() - Reset the DPBP, returns the object to initial state.
362 @@ -272,310 +206,7 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
363 /* send command to mc*/
364 return mc_send_command(mc_io, &cmd);
365 }
366 -
367 -/**
368 - * dpbp_set_irq() - Set IRQ information for the DPBP to trigger an interrupt.
369 - * @mc_io: Pointer to MC portal's I/O object
370 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
371 - * @token: Token of DPBP object
372 - * @irq_index: Identifies the interrupt index to configure
373 - * @irq_cfg: IRQ configuration
374 - *
375 - * Return: '0' on Success; Error code otherwise.
376 - */
377 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
378 - u32 cmd_flags,
379 - u16 token,
380 - u8 irq_index,
381 - struct dpbp_irq_cfg *irq_cfg)
382 -{
383 - struct mc_command cmd = { 0 };
384 - struct dpbp_cmd_set_irq *cmd_params;
385 -
386 - /* prepare command */
387 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ,
388 - cmd_flags, token);
389 - cmd_params = (struct dpbp_cmd_set_irq *)cmd.params;
390 - cmd_params->irq_index = irq_index;
391 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
392 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->addr);
393 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
394 -
395 - /* send command to mc*/
396 - return mc_send_command(mc_io, &cmd);
397 -}
398 -
399 -/**
400 - * dpbp_get_irq() - Get IRQ information from the DPBP.
401 - * @mc_io: Pointer to MC portal's I/O object
402 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
403 - * @token: Token of DPBP object
404 - * @irq_index: The interrupt index to configure
405 - * @type: Interrupt type: 0 represents message interrupt
406 - * type (both irq_addr and irq_val are valid)
407 - * @irq_cfg: IRQ attributes
408 - *
409 - * Return: '0' on Success; Error code otherwise.
410 - */
411 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
412 - u32 cmd_flags,
413 - u16 token,
414 - u8 irq_index,
415 - int *type,
416 - struct dpbp_irq_cfg *irq_cfg)
417 -{
418 - struct mc_command cmd = { 0 };
419 - struct dpbp_cmd_get_irq *cmd_params;
420 - struct dpbp_rsp_get_irq *rsp_params;
421 - int err;
422 -
423 - /* prepare command */
424 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ,
425 - cmd_flags, token);
426 - cmd_params = (struct dpbp_cmd_get_irq *)cmd.params;
427 - cmd_params->irq_index = irq_index;
428 -
429 - /* send command to mc*/
430 - err = mc_send_command(mc_io, &cmd);
431 - if (err)
432 - return err;
433 -
434 - /* retrieve response parameters */
435 - rsp_params = (struct dpbp_rsp_get_irq *)cmd.params;
436 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
437 - irq_cfg->addr = le64_to_cpu(rsp_params->irq_addr);
438 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
439 - *type = le32_to_cpu(rsp_params->type);
440 -
441 - return 0;
442 -}
443 -
444 -/**
445 - * dpbp_set_irq_enable() - Set overall interrupt state.
446 - * @mc_io: Pointer to MC portal's I/O object
447 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
448 - * @token: Token of DPBP object
449 - * @irq_index: The interrupt index to configure
450 - * @en: Interrupt state - enable = 1, disable = 0
451 - *
452 - * Allows GPP software to control when interrupts are generated.
453 - * Each interrupt can have up to 32 causes. The enable/disable control's the
454 - * overall interrupt state. if the interrupt is disabled no causes will cause
455 - * an interrupt.
456 - *
457 - * Return: '0' on Success; Error code otherwise.
458 - */
459 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
460 - u32 cmd_flags,
461 - u16 token,
462 - u8 irq_index,
463 - u8 en)
464 -{
465 - struct mc_command cmd = { 0 };
466 - struct dpbp_cmd_set_irq_enable *cmd_params;
467 -
468 - /* prepare command */
469 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_ENABLE,
470 - cmd_flags, token);
471 - cmd_params = (struct dpbp_cmd_set_irq_enable *)cmd.params;
472 - cmd_params->enable = en & DPBP_ENABLE;
473 - cmd_params->irq_index = irq_index;
474 -
475 - /* send command to mc*/
476 - return mc_send_command(mc_io, &cmd);
477 -}
478 -
479 -/**
480 - * dpbp_get_irq_enable() - Get overall interrupt state
481 - * @mc_io: Pointer to MC portal's I/O object
482 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
483 - * @token: Token of DPBP object
484 - * @irq_index: The interrupt index to configure
485 - * @en: Returned interrupt state - enable = 1, disable = 0
486 - *
487 - * Return: '0' on Success; Error code otherwise.
488 - */
489 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
490 - u32 cmd_flags,
491 - u16 token,
492 - u8 irq_index,
493 - u8 *en)
494 -{
495 - struct mc_command cmd = { 0 };
496 - struct dpbp_cmd_get_irq_enable *cmd_params;
497 - struct dpbp_rsp_get_irq_enable *rsp_params;
498 - int err;
499 -
500 - /* prepare command */
501 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_ENABLE,
502 - cmd_flags, token);
503 - cmd_params = (struct dpbp_cmd_get_irq_enable *)cmd.params;
504 - cmd_params->irq_index = irq_index;
505 -
506 - /* send command to mc*/
507 - err = mc_send_command(mc_io, &cmd);
508 - if (err)
509 - return err;
510 -
511 - /* retrieve response parameters */
512 - rsp_params = (struct dpbp_rsp_get_irq_enable *)cmd.params;
513 - *en = rsp_params->enabled & DPBP_ENABLE;
514 - return 0;
515 -}
516 -
517 -/**
518 - * dpbp_set_irq_mask() - Set interrupt mask.
519 - * @mc_io: Pointer to MC portal's I/O object
520 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
521 - * @token: Token of DPBP object
522 - * @irq_index: The interrupt index to configure
523 - * @mask: Event mask to trigger interrupt;
524 - * each bit:
525 - * 0 = ignore event
526 - * 1 = consider event for asserting IRQ
527 - *
528 - * Every interrupt can have up to 32 causes and the interrupt model supports
529 - * masking/unmasking each cause independently
530 - *
531 - * Return: '0' on Success; Error code otherwise.
532 - */
533 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
534 - u32 cmd_flags,
535 - u16 token,
536 - u8 irq_index,
537 - u32 mask)
538 -{
539 - struct mc_command cmd = { 0 };
540 - struct dpbp_cmd_set_irq_mask *cmd_params;
541 -
542 - /* prepare command */
543 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_MASK,
544 - cmd_flags, token);
545 - cmd_params = (struct dpbp_cmd_set_irq_mask *)cmd.params;
546 - cmd_params->mask = cpu_to_le32(mask);
547 - cmd_params->irq_index = irq_index;
548 -
549 - /* send command to mc*/
550 - return mc_send_command(mc_io, &cmd);
551 -}
552 -
553 -/**
554 - * dpbp_get_irq_mask() - Get interrupt mask.
555 - * @mc_io: Pointer to MC portal's I/O object
556 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
557 - * @token: Token of DPBP object
558 - * @irq_index: The interrupt index to configure
559 - * @mask: Returned event mask to trigger interrupt
560 - *
561 - * Every interrupt can have up to 32 causes and the interrupt model supports
562 - * masking/unmasking each cause independently
563 - *
564 - * Return: '0' on Success; Error code otherwise.
565 - */
566 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
567 - u32 cmd_flags,
568 - u16 token,
569 - u8 irq_index,
570 - u32 *mask)
571 -{
572 - struct mc_command cmd = { 0 };
573 - struct dpbp_cmd_get_irq_mask *cmd_params;
574 - struct dpbp_rsp_get_irq_mask *rsp_params;
575 - int err;
576 -
577 - /* prepare command */
578 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_MASK,
579 - cmd_flags, token);
580 - cmd_params = (struct dpbp_cmd_get_irq_mask *)cmd.params;
581 - cmd_params->irq_index = irq_index;
582 -
583 - /* send command to mc*/
584 - err = mc_send_command(mc_io, &cmd);
585 - if (err)
586 - return err;
587 -
588 - /* retrieve response parameters */
589 - rsp_params = (struct dpbp_rsp_get_irq_mask *)cmd.params;
590 - *mask = le32_to_cpu(rsp_params->mask);
591 -
592 - return 0;
593 -}
594 -
595 -/**
596 - * dpbp_get_irq_status() - Get the current status of any pending interrupts.
597 - *
598 - * @mc_io: Pointer to MC portal's I/O object
599 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
600 - * @token: Token of DPBP object
601 - * @irq_index: The interrupt index to configure
602 - * @status: Returned interrupts status - one bit per cause:
603 - * 0 = no interrupt pending
604 - * 1 = interrupt pending
605 - *
606 - * Return: '0' on Success; Error code otherwise.
607 - */
608 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
609 - u32 cmd_flags,
610 - u16 token,
611 - u8 irq_index,
612 - u32 *status)
613 -{
614 - struct mc_command cmd = { 0 };
615 - struct dpbp_cmd_get_irq_status *cmd_params;
616 - struct dpbp_rsp_get_irq_status *rsp_params;
617 - int err;
618 -
619 - /* prepare command */
620 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_STATUS,
621 - cmd_flags, token);
622 - cmd_params = (struct dpbp_cmd_get_irq_status *)cmd.params;
623 - cmd_params->status = cpu_to_le32(*status);
624 - cmd_params->irq_index = irq_index;
625 -
626 - /* send command to mc*/
627 - err = mc_send_command(mc_io, &cmd);
628 - if (err)
629 - return err;
630 -
631 - /* retrieve response parameters */
632 - rsp_params = (struct dpbp_rsp_get_irq_status *)cmd.params;
633 - *status = le32_to_cpu(rsp_params->status);
634 -
635 - return 0;
636 -}
637 -
638 -/**
639 - * dpbp_clear_irq_status() - Clear a pending interrupt's status
640 - *
641 - * @mc_io: Pointer to MC portal's I/O object
642 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
643 - * @token: Token of DPBP object
644 - * @irq_index: The interrupt index to configure
645 - * @status: Bits to clear (W1C) - one bit per cause:
646 - * 0 = don't change
647 - * 1 = clear status bit
648 - *
649 - * Return: '0' on Success; Error code otherwise.
650 - */
651 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
652 - u32 cmd_flags,
653 - u16 token,
654 - u8 irq_index,
655 - u32 status)
656 -{
657 - struct mc_command cmd = { 0 };
658 - struct dpbp_cmd_clear_irq_status *cmd_params;
659 -
660 - /* prepare command */
661 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLEAR_IRQ_STATUS,
662 - cmd_flags, token);
663 - cmd_params = (struct dpbp_cmd_clear_irq_status *)cmd.params;
664 - cmd_params->status = cpu_to_le32(status);
665 - cmd_params->irq_index = irq_index;
666 -
667 - /* send command to mc*/
668 - return mc_send_command(mc_io, &cmd);
669 -}
670 +EXPORT_SYMBOL(dpbp_reset);
671
672 /**
673 * dpbp_get_attributes - Retrieve DPBP attributes.
674 @@ -609,83 +240,40 @@ int dpbp_get_attributes(struct fsl_mc_io
675 rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params;
676 attr->bpid = le16_to_cpu(rsp_params->bpid);
677 attr->id = le32_to_cpu(rsp_params->id);
678 - attr->version.major = le16_to_cpu(rsp_params->version_major);
679 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
680
681 return 0;
682 }
683 EXPORT_SYMBOL(dpbp_get_attributes);
684
685 /**
686 - * dpbp_set_notifications() - Set notifications towards software
687 - * @mc_io: Pointer to MC portal's I/O object
688 + * dpbp_get_api_version - Get Data Path Buffer Pool API version
689 + * @mc_io: Pointer to Mc portal's I/O object
690 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
691 - * @token: Token of DPBP object
692 - * @cfg: notifications configuration
693 + * @major_ver: Major version of Buffer Pool API
694 + * @minor_ver: Minor version of Buffer Pool API
695 *
696 * Return: '0' on Success; Error code otherwise.
697 */
698 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
699 - u32 cmd_flags,
700 - u16 token,
701 - struct dpbp_notification_cfg *cfg)
702 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
703 + u32 cmd_flags,
704 + u16 *major_ver,
705 + u16 *minor_ver)
706 {
707 struct mc_command cmd = { 0 };
708 - struct dpbp_cmd_set_notifications *cmd_params;
709 -
710 - /* prepare command */
711 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS,
712 - cmd_flags, token);
713 - cmd_params = (struct dpbp_cmd_set_notifications *)cmd.params;
714 - cmd_params->depletion_entry = cpu_to_le32(cfg->depletion_entry);
715 - cmd_params->depletion_exit = cpu_to_le32(cfg->depletion_exit);
716 - cmd_params->surplus_entry = cpu_to_le32(cfg->surplus_entry);
717 - cmd_params->surplus_exit = cpu_to_le32(cfg->surplus_exit);
718 - cmd_params->options = cpu_to_le16(cfg->options);
719 - cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
720 - cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
721 -
722 - /* send command to mc*/
723 - return mc_send_command(mc_io, &cmd);
724 -}
725 -
726 -/**
727 - * dpbp_get_notifications() - Get the notifications configuration
728 - * @mc_io: Pointer to MC portal's I/O object
729 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
730 - * @token: Token of DPBP object
731 - * @cfg: notifications configuration
732 - *
733 - * Return: '0' on Success; Error code otherwise.
734 - */
735 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
736 - u32 cmd_flags,
737 - u16 token,
738 - struct dpbp_notification_cfg *cfg)
739 -{
740 - struct mc_command cmd = { 0 };
741 - struct dpbp_rsp_get_notifications *rsp_params;
742 int err;
743
744 /* prepare command */
745 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS,
746 - cmd_flags,
747 - token);
748 + cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_API_VERSION,
749 + cmd_flags, 0);
750
751 - /* send command to mc*/
752 + /* send command to mc */
753 err = mc_send_command(mc_io, &cmd);
754 if (err)
755 return err;
756
757 /* retrieve response parameters */
758 - rsp_params = (struct dpbp_rsp_get_notifications *)cmd.params;
759 - cfg->depletion_entry = le32_to_cpu(rsp_params->depletion_entry);
760 - cfg->depletion_exit = le32_to_cpu(rsp_params->depletion_exit);
761 - cfg->surplus_entry = le32_to_cpu(rsp_params->surplus_entry);
762 - cfg->surplus_exit = le32_to_cpu(rsp_params->surplus_exit);
763 - cfg->options = le16_to_cpu(rsp_params->options);
764 - cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
765 - cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
766 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
767
768 return 0;
769 }
770 +EXPORT_SYMBOL(dpbp_get_api_version);
771 --- /dev/null
772 +++ b/drivers/staging/fsl-mc/bus/dpcon-cmd.h
773 @@ -0,0 +1,85 @@
774 +/*
775 + * Copyright 2013-2016 Freescale Semiconductor Inc.
776 + *
777 + * Redistribution and use in source and binary forms, with or without
778 + * modification, are permitted provided that the following conditions are met:
779 + * * Redistributions of source code must retain the above copyright
780 + * notice, this list of conditions and the following disclaimer.
781 + * * Redistributions in binary form must reproduce the above copyright
782 + * notice, this list of conditions and the following disclaimer in the
783 + * documentation and/or other materials provided with the distribution.
784 + * * Neither the name of the above-listed copyright holders nor the
785 + * names of any contributors may be used to endorse or promote products
786 + * derived from this software without specific prior written permission.
787 + *
788 + * ALTERNATIVELY, this software may be distributed under the terms of the
789 + * GNU General Public License ("GPL") as published by the Free Software
790 + * Foundation, either version 2 of that License or (at your option) any
791 + * later version.
792 + *
793 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
794 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
795 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
796 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
797 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
798 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
799 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
800 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
801 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
802 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
803 + * POSSIBILITY OF SUCH DAMAGE.
804 + */
805 +#ifndef _FSL_DPCON_CMD_H
806 +#define _FSL_DPCON_CMD_H
807 +
808 +/* DPCON Version */
809 +#define DPCON_VER_MAJOR 3
810 +#define DPCON_VER_MINOR 2
811 +
812 +/* Command versioning */
813 +#define DPCON_CMD_BASE_VERSION 1
814 +#define DPCON_CMD_ID_OFFSET 4
815 +
816 +#define DPCON_CMD(id) (((id) << DPCON_CMD_ID_OFFSET) | DPCON_CMD_BASE_VERSION)
817 +
818 +/* Command IDs */
819 +#define DPCON_CMDID_CLOSE DPCON_CMD(0x800)
820 +#define DPCON_CMDID_OPEN DPCON_CMD(0x808)
821 +#define DPCON_CMDID_GET_API_VERSION DPCON_CMD(0xa08)
822 +
823 +#define DPCON_CMDID_ENABLE DPCON_CMD(0x002)
824 +#define DPCON_CMDID_DISABLE DPCON_CMD(0x003)
825 +#define DPCON_CMDID_GET_ATTR DPCON_CMD(0x004)
826 +#define DPCON_CMDID_RESET DPCON_CMD(0x005)
827 +#define DPCON_CMDID_IS_ENABLED DPCON_CMD(0x006)
828 +
829 +#define DPCON_CMDID_SET_NOTIFICATION DPCON_CMD(0x100)
830 +
831 +struct dpcon_cmd_open {
832 + __le32 dpcon_id;
833 +};
834 +
835 +#define DPCON_ENABLE 1
836 +
837 +struct dpcon_rsp_is_enabled {
838 + u8 enabled;
839 +};
840 +
841 +struct dpcon_rsp_get_attr {
842 + /* response word 0 */
843 + __le32 id;
844 + __le16 qbman_ch_id;
845 + u8 num_priorities;
846 + u8 pad;
847 +};
848 +
849 +struct dpcon_cmd_set_notification {
850 + /* cmd word 0 */
851 + __le32 dpio_id;
852 + u8 priority;
853 + u8 pad[3];
854 + /* cmd word 1 */
855 + __le64 user_ctx;
856 +};
857 +
858 +#endif /* _FSL_DPCON_CMD_H */
859 --- /dev/null
860 +++ b/drivers/staging/fsl-mc/bus/dpcon.c
861 @@ -0,0 +1,317 @@
862 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
863 + *
864 + * Redistribution and use in source and binary forms, with or without
865 + * modification, are permitted provided that the following conditions are met:
866 + * * Redistributions of source code must retain the above copyright
867 + * notice, this list of conditions and the following disclaimer.
868 + * * Redistributions in binary form must reproduce the above copyright
869 + * notice, this list of conditions and the following disclaimer in the
870 + * documentation and/or other materials provided with the distribution.
871 + * * Neither the name of the above-listed copyright holders nor the
872 + * names of any contributors may be used to endorse or promote products
873 + * derived from this software without specific prior written permission.
874 + *
875 + *
876 + * ALTERNATIVELY, this software may be distributed under the terms of the
877 + * GNU General Public License ("GPL") as published by the Free Software
878 + * Foundation, either version 2 of that License or (at your option) any
879 + * later version.
880 + *
881 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
882 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
883 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
884 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
885 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
886 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
887 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
888 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
889 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
890 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
891 + * POSSIBILITY OF SUCH DAMAGE.
892 + */
893 +#include "../include/mc-sys.h"
894 +#include "../include/mc-cmd.h"
895 +#include "../include/dpcon.h"
896 +
897 +#include "dpcon-cmd.h"
898 +
899 +/**
900 + * dpcon_open() - Open a control session for the specified object
901 + * @mc_io: Pointer to MC portal's I/O object
902 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
903 + * @dpcon_id: DPCON unique ID
904 + * @token: Returned token; use in subsequent API calls
905 + *
906 + * This function can be used to open a control session for an
907 + * already created object; an object may have been declared in
908 + * the DPL or by calling the dpcon_create() function.
909 + * This function returns a unique authentication token,
910 + * associated with the specific object ID and the specific MC
911 + * portal; this token must be used in all subsequent commands for
912 + * this specific object.
913 + *
914 + * Return: '0' on Success; Error code otherwise.
915 + */
916 +int dpcon_open(struct fsl_mc_io *mc_io,
917 + u32 cmd_flags,
918 + int dpcon_id,
919 + u16 *token)
920 +{
921 + struct mc_command cmd = { 0 };
922 + struct dpcon_cmd_open *dpcon_cmd;
923 + int err;
924 +
925 + /* prepare command */
926 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN,
927 + cmd_flags,
928 + 0);
929 + dpcon_cmd = (struct dpcon_cmd_open *)cmd.params;
930 + dpcon_cmd->dpcon_id = cpu_to_le32(dpcon_id);
931 +
932 + /* send command to mc*/
933 + err = mc_send_command(mc_io, &cmd);
934 + if (err)
935 + return err;
936 +
937 + /* retrieve response parameters */
938 + *token = mc_cmd_hdr_read_token(&cmd);
939 +
940 + return 0;
941 +}
942 +EXPORT_SYMBOL(dpcon_open);
943 +
944 +/**
945 + * dpcon_close() - Close the control session of the object
946 + * @mc_io: Pointer to MC portal's I/O object
947 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
948 + * @token: Token of DPCON object
949 + *
950 + * After this function is called, no further operations are
951 + * allowed on the object without opening a new control session.
952 + *
953 + * Return: '0' on Success; Error code otherwise.
954 + */
955 +int dpcon_close(struct fsl_mc_io *mc_io,
956 + u32 cmd_flags,
957 + u16 token)
958 +{
959 + struct mc_command cmd = { 0 };
960 +
961 + /* prepare command */
962 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE,
963 + cmd_flags,
964 + token);
965 +
966 + /* send command to mc*/
967 + return mc_send_command(mc_io, &cmd);
968 +}
969 +EXPORT_SYMBOL(dpcon_close);
970 +
971 +/**
972 + * dpcon_enable() - Enable the DPCON
973 + * @mc_io: Pointer to MC portal's I/O object
974 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
975 + * @token: Token of DPCON object
976 + *
977 + * Return: '0' on Success; Error code otherwise
978 + */
979 +int dpcon_enable(struct fsl_mc_io *mc_io,
980 + u32 cmd_flags,
981 + u16 token)
982 +{
983 + struct mc_command cmd = { 0 };
984 +
985 + /* prepare command */
986 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE,
987 + cmd_flags,
988 + token);
989 +
990 + /* send command to mc*/
991 + return mc_send_command(mc_io, &cmd);
992 +}
993 +EXPORT_SYMBOL(dpcon_enable);
994 +
995 +/**
996 + * dpcon_disable() - Disable the DPCON
997 + * @mc_io: Pointer to MC portal's I/O object
998 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
999 + * @token: Token of DPCON object
1000 + *
1001 + * Return: '0' on Success; Error code otherwise
1002 + */
1003 +int dpcon_disable(struct fsl_mc_io *mc_io,
1004 + u32 cmd_flags,
1005 + u16 token)
1006 +{
1007 + struct mc_command cmd = { 0 };
1008 +
1009 + /* prepare command */
1010 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE,
1011 + cmd_flags,
1012 + token);
1013 +
1014 + /* send command to mc*/
1015 + return mc_send_command(mc_io, &cmd);
1016 +}
1017 +EXPORT_SYMBOL(dpcon_disable);
1018 +
1019 +/**
1020 + * dpcon_is_enabled() - Check if the DPCON is enabled.
1021 + * @mc_io: Pointer to MC portal's I/O object
1022 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1023 + * @token: Token of DPCON object
1024 + * @en: Returns '1' if object is enabled; '0' otherwise
1025 + *
1026 + * Return: '0' on Success; Error code otherwise.
1027 + */
1028 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
1029 + u32 cmd_flags,
1030 + u16 token,
1031 + int *en)
1032 +{
1033 + struct mc_command cmd = { 0 };
1034 + struct dpcon_rsp_is_enabled *dpcon_rsp;
1035 + int err;
1036 +
1037 + /* prepare command */
1038 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED,
1039 + cmd_flags,
1040 + token);
1041 +
1042 + /* send command to mc*/
1043 + err = mc_send_command(mc_io, &cmd);
1044 + if (err)
1045 + return err;
1046 +
1047 + /* retrieve response parameters */
1048 + dpcon_rsp = (struct dpcon_rsp_is_enabled *)cmd.params;
1049 + *en = dpcon_rsp->enabled & DPCON_ENABLE;
1050 +
1051 + return 0;
1052 +}
1053 +EXPORT_SYMBOL(dpcon_is_enabled);
1054 +
1055 +/**
1056 + * dpcon_reset() - Reset the DPCON, returns the object to initial state.
1057 + * @mc_io: Pointer to MC portal's I/O object
1058 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1059 + * @token: Token of DPCON object
1060 + *
1061 + * Return: '0' on Success; Error code otherwise.
1062 + */
1063 +int dpcon_reset(struct fsl_mc_io *mc_io,
1064 + u32 cmd_flags,
1065 + u16 token)
1066 +{
1067 + struct mc_command cmd = { 0 };
1068 +
1069 + /* prepare command */
1070 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET,
1071 + cmd_flags, token);
1072 +
1073 + /* send command to mc*/
1074 + return mc_send_command(mc_io, &cmd);
1075 +}
1076 +EXPORT_SYMBOL(dpcon_reset);
1077 +
1078 +/**
1079 + * dpcon_get_attributes() - Retrieve DPCON attributes.
1080 + * @mc_io: Pointer to MC portal's I/O object
1081 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1082 + * @token: Token of DPCON object
1083 + * @attr: Object's attributes
1084 + *
1085 + * Return: '0' on Success; Error code otherwise.
1086 + */
1087 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
1088 + u32 cmd_flags,
1089 + u16 token,
1090 + struct dpcon_attr *attr)
1091 +{
1092 + struct mc_command cmd = { 0 };
1093 + struct dpcon_rsp_get_attr *dpcon_rsp;
1094 + int err;
1095 +
1096 + /* prepare command */
1097 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR,
1098 + cmd_flags,
1099 + token);
1100 +
1101 + /* send command to mc*/
1102 + err = mc_send_command(mc_io, &cmd);
1103 + if (err)
1104 + return err;
1105 +
1106 + /* retrieve response parameters */
1107 + dpcon_rsp = (struct dpcon_rsp_get_attr *)cmd.params;
1108 + attr->id = le32_to_cpu(dpcon_rsp->id);
1109 + attr->qbman_ch_id = le16_to_cpu(dpcon_rsp->qbman_ch_id);
1110 + attr->num_priorities = dpcon_rsp->num_priorities;
1111 +
1112 + return 0;
1113 +}
1114 +EXPORT_SYMBOL(dpcon_get_attributes);
1115 +
1116 +/**
1117 + * dpcon_set_notification() - Set DPCON notification destination
1118 + * @mc_io: Pointer to MC portal's I/O object
1119 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1120 + * @token: Token of DPCON object
1121 + * @cfg: Notification parameters
1122 + *
1123 + * Return: '0' on Success; Error code otherwise
1124 + */
1125 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
1126 + u32 cmd_flags,
1127 + u16 token,
1128 + struct dpcon_notification_cfg *cfg)
1129 +{
1130 + struct mc_command cmd = { 0 };
1131 + struct dpcon_cmd_set_notification *dpcon_cmd;
1132 +
1133 + /* prepare command */
1134 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION,
1135 + cmd_flags,
1136 + token);
1137 + dpcon_cmd = (struct dpcon_cmd_set_notification *)cmd.params;
1138 + dpcon_cmd->dpio_id = cpu_to_le32(cfg->dpio_id);
1139 + dpcon_cmd->priority = cfg->priority;
1140 + dpcon_cmd->user_ctx = cpu_to_le64(cfg->user_ctx);
1141 +
1142 + /* send command to mc*/
1143 + return mc_send_command(mc_io, &cmd);
1144 +}
1145 +EXPORT_SYMBOL(dpcon_set_notification);
1146 +
1147 +/**
1148 + * dpcon_get_api_version - Get Data Path Concentrator API version
1149 + * @mc_io: Pointer to MC portal's DPCON object
1150 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1151 + * @major_ver: Major version of DPCON API
1152 + * @minor_ver: Minor version of DPCON API
1153 + *
1154 + * Return: '0' on Success; Error code otherwise
1155 + */
1156 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
1157 + u32 cmd_flags,
1158 + u16 *major_ver,
1159 + u16 *minor_ver)
1160 +{
1161 + struct mc_command cmd = { 0 };
1162 + int err;
1163 +
1164 + /* prepare command */
1165 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_API_VERSION,
1166 + cmd_flags, 0);
1167 +
1168 + /* send command to mc */
1169 + err = mc_send_command(mc_io, &cmd);
1170 + if (err)
1171 + return err;
1172 +
1173 + /* retrieve response parameters */
1174 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
1175 +
1176 + return 0;
1177 +}
1178 +EXPORT_SYMBOL(dpcon_get_api_version);
1179 --- /dev/null
1180 +++ b/drivers/staging/fsl-mc/bus/dpio/Makefile
1181 @@ -0,0 +1,11 @@
1182 +#
1183 +# QorIQ DPAA2 DPIO driver
1184 +#
1185 +
1186 +subdir-ccflags-y := -Werror
1187 +
1188 +obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
1189 +
1190 +fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o
1191 +
1192 +obj-$(CONFIG_FSL_QBMAN_DEBUG) += qbman_debug.o
1193 --- a/drivers/staging/fsl-mc/include/dpcon-cmd.h
1194 +++ /dev/null
1195 @@ -1,62 +0,0 @@
1196 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
1197 - *
1198 - * Redistribution and use in source and binary forms, with or without
1199 - * modification, are permitted provided that the following conditions are met:
1200 - * * Redistributions of source code must retain the above copyright
1201 - * notice, this list of conditions and the following disclaimer.
1202 - * * Redistributions in binary form must reproduce the above copyright
1203 - * notice, this list of conditions and the following disclaimer in the
1204 - * documentation and/or other materials provided with the distribution.
1205 - * * Neither the name of the above-listed copyright holders nor the
1206 - * names of any contributors may be used to endorse or promote products
1207 - * derived from this software without specific prior written permission.
1208 - *
1209 - *
1210 - * ALTERNATIVELY, this software may be distributed under the terms of the
1211 - * GNU General Public License ("GPL") as published by the Free Software
1212 - * Foundation, either version 2 of that License or (at your option) any
1213 - * later version.
1214 - *
1215 - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1216 - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1217 - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1218 - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1219 - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1220 - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1221 - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1222 - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1223 - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1224 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1225 - * POSSIBILITY OF SUCH DAMAGE.
1226 - */
1227 -#ifndef _FSL_DPCON_CMD_H
1228 -#define _FSL_DPCON_CMD_H
1229 -
1230 -/* DPCON Version */
1231 -#define DPCON_VER_MAJOR 2
1232 -#define DPCON_VER_MINOR 1
1233 -
1234 -/* Command IDs */
1235 -#define DPCON_CMDID_CLOSE 0x800
1236 -#define DPCON_CMDID_OPEN 0x808
1237 -#define DPCON_CMDID_CREATE 0x908
1238 -#define DPCON_CMDID_DESTROY 0x900
1239 -
1240 -#define DPCON_CMDID_ENABLE 0x002
1241 -#define DPCON_CMDID_DISABLE 0x003
1242 -#define DPCON_CMDID_GET_ATTR 0x004
1243 -#define DPCON_CMDID_RESET 0x005
1244 -#define DPCON_CMDID_IS_ENABLED 0x006
1245 -
1246 -#define DPCON_CMDID_SET_IRQ 0x010
1247 -#define DPCON_CMDID_GET_IRQ 0x011
1248 -#define DPCON_CMDID_SET_IRQ_ENABLE 0x012
1249 -#define DPCON_CMDID_GET_IRQ_ENABLE 0x013
1250 -#define DPCON_CMDID_SET_IRQ_MASK 0x014
1251 -#define DPCON_CMDID_GET_IRQ_MASK 0x015
1252 -#define DPCON_CMDID_GET_IRQ_STATUS 0x016
1253 -#define DPCON_CMDID_CLEAR_IRQ_STATUS 0x017
1254 -
1255 -#define DPCON_CMDID_SET_NOTIFICATION 0x100
1256 -
1257 -#endif /* _FSL_DPCON_CMD_H */
1258 --- /dev/null
1259 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
1260 @@ -0,0 +1,75 @@
1261 +/*
1262 + * Copyright 2013-2016 Freescale Semiconductor Inc.
1263 + * Copyright 2016 NXP
1264 + *
1265 + * Redistribution and use in source and binary forms, with or without
1266 + * modification, are permitted provided that the following conditions are met:
1267 + * * Redistributions of source code must retain the above copyright
1268 + * notice, this list of conditions and the following disclaimer.
1269 + * * Redistributions in binary form must reproduce the above copyright
1270 + * notice, this list of conditions and the following disclaimer in the
1271 + * documentation and/or other materials provided with the distribution.
1272 + * * Neither the name of the above-listed copyright holders nor the
1273 + * names of any contributors may be used to endorse or promote products
1274 + * derived from this software without specific prior written permission.
1275 + *
1276 + * ALTERNATIVELY, this software may be distributed under the terms of the
1277 + * GNU General Public License ("GPL") as published by the Free Software
1278 + * Foundation, either version 2 of that License or (at your option) any
1279 + * later version.
1280 + *
1281 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1282 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1283 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1284 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1285 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1286 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1287 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1288 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1289 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1290 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1291 + * POSSIBILITY OF SUCH DAMAGE.
1292 + */
1293 +#ifndef _FSL_DPIO_CMD_H
1294 +#define _FSL_DPIO_CMD_H
1295 +
1296 +/* DPIO Version */
1297 +#define DPIO_VER_MAJOR 4
1298 +#define DPIO_VER_MINOR 2
1299 +
1300 +/* Command Versioning */
1301 +
1302 +#define DPIO_CMD_ID_OFFSET 4
1303 +#define DPIO_CMD_BASE_VERSION 1
1304 +
1305 +#define DPIO_CMD(id) (((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION)
1306 +
1307 +/* Command IDs */
1308 +#define DPIO_CMDID_CLOSE DPIO_CMD(0x800)
1309 +#define DPIO_CMDID_OPEN DPIO_CMD(0x803)
1310 +#define DPIO_CMDID_GET_API_VERSION DPIO_CMD(0xa03)
1311 +#define DPIO_CMDID_ENABLE DPIO_CMD(0x002)
1312 +#define DPIO_CMDID_DISABLE DPIO_CMD(0x003)
1313 +#define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004)
1314 +
1315 +struct dpio_cmd_open {
1316 + __le32 dpio_id;
1317 +};
1318 +
1319 +#define DPIO_CHANNEL_MODE_MASK 0x3
1320 +
1321 +struct dpio_rsp_get_attr {
1322 + /* cmd word 0 */
1323 + __le32 id;
1324 + __le16 qbman_portal_id;
1325 + u8 num_priorities;
1326 + u8 channel_mode;
1327 + /* cmd word 1 */
1328 + __le64 qbman_portal_ce_addr;
1329 + /* cmd word 2 */
1330 + __le64 qbman_portal_ci_addr;
1331 + /* cmd word 3 */
1332 + __le32 qbman_version;
1333 +};
1334 +
1335 +#endif /* _FSL_DPIO_CMD_H */
1336 --- /dev/null
1337 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
1338 @@ -0,0 +1,296 @@
1339 +/*
1340 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1341 + * Copyright 2016 NXP
1342 + *
1343 + * Redistribution and use in source and binary forms, with or without
1344 + * modification, are permitted provided that the following conditions are met:
1345 + * * Redistributions of source code must retain the above copyright
1346 + * notice, this list of conditions and the following disclaimer.
1347 + * * Redistributions in binary form must reproduce the above copyright
1348 + * notice, this list of conditions and the following disclaimer in the
1349 + * documentation and/or other materials provided with the distribution.
1350 + * * Neither the name of Freescale Semiconductor nor the
1351 + * names of its contributors may be used to endorse or promote products
1352 + * derived from this software without specific prior written permission.
1353 + *
1354 + * ALTERNATIVELY, this software may be distributed under the terms of the
1355 + * GNU General Public License ("GPL") as published by the Free Software
1356 + * Foundation, either version 2 of that License or (at your option) any
1357 + * later version.
1358 + *
1359 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1360 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1361 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1362 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1363 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1364 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1365 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1366 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1367 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1368 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1369 + */
1370 +
1371 +#include <linux/types.h>
1372 +#include <linux/init.h>
1373 +#include <linux/module.h>
1374 +#include <linux/platform_device.h>
1375 +#include <linux/interrupt.h>
1376 +#include <linux/msi.h>
1377 +#include <linux/dma-mapping.h>
1378 +#include <linux/delay.h>
1379 +
1380 +#include "../../include/mc.h"
1381 +#include "../../include/dpaa2-io.h"
1382 +
1383 +#include "qbman-portal.h"
1384 +#include "dpio.h"
1385 +#include "dpio-cmd.h"
1386 +
1387 +MODULE_LICENSE("Dual BSD/GPL");
1388 +MODULE_AUTHOR("Freescale Semiconductor, Inc");
1389 +MODULE_DESCRIPTION("DPIO Driver");
1390 +
1391 +struct dpio_priv {
1392 + struct dpaa2_io *io;
1393 +};
1394 +
1395 +static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
1396 +{
1397 + struct device *dev = (struct device *)arg;
1398 + struct dpio_priv *priv = dev_get_drvdata(dev);
1399 +
1400 + return dpaa2_io_irq(priv->io);
1401 +}
1402 +
1403 +static void unregister_dpio_irq_handlers(struct fsl_mc_device *dpio_dev)
1404 +{
1405 + struct fsl_mc_device_irq *irq;
1406 +
1407 + irq = dpio_dev->irqs[0];
1408 +
1409 + /* clear the affinity hint */
1410 + irq_set_affinity_hint(irq->msi_desc->irq, NULL);
1411 +}
1412 +
1413 +static int register_dpio_irq_handlers(struct fsl_mc_device *dpio_dev, int cpu)
1414 +{
1415 + struct dpio_priv *priv;
1416 + int error;
1417 + struct fsl_mc_device_irq *irq;
1418 + cpumask_t mask;
1419 +
1420 + priv = dev_get_drvdata(&dpio_dev->dev);
1421 +
1422 + irq = dpio_dev->irqs[0];
1423 + error = devm_request_irq(&dpio_dev->dev,
1424 + irq->msi_desc->irq,
1425 + dpio_irq_handler,
1426 + 0,
1427 + dev_name(&dpio_dev->dev),
1428 + &dpio_dev->dev);
1429 + if (error < 0) {
1430 + dev_err(&dpio_dev->dev,
1431 + "devm_request_irq() failed: %d\n",
1432 + error);
1433 + return error;
1434 + }
1435 +
1436 + /* set the affinity hint */
1437 + cpumask_clear(&mask);
1438 + cpumask_set_cpu(cpu, &mask);
1439 + if (irq_set_affinity_hint(irq->msi_desc->irq, &mask))
1440 + dev_err(&dpio_dev->dev,
1441 + "irq_set_affinity failed irq %d cpu %d\n",
1442 + irq->msi_desc->irq, cpu);
1443 +
1444 + return 0;
1445 +}
1446 +
1447 +static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
1448 +{
1449 + struct dpio_attr dpio_attrs;
1450 + struct dpaa2_io_desc desc;
1451 + struct dpio_priv *priv;
1452 + int err = -ENOMEM;
1453 + struct device *dev = &dpio_dev->dev;
1454 + static int next_cpu = -1;
1455 +
1456 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1457 + if (!priv)
1458 + goto err_priv_alloc;
1459 +
1460 + dev_set_drvdata(dev, priv);
1461 +
1462 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1463 + if (err) {
1464 + dev_dbg(dev, "MC portal allocation failed\n");
1465 + err = -EPROBE_DEFER;
1466 + goto err_mcportal;
1467 + }
1468 +
1469 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1470 + &dpio_dev->mc_handle);
1471 + if (err) {
1472 + dev_err(dev, "dpio_open() failed\n");
1473 + goto err_open;
1474 + }
1475 +
1476 + err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
1477 + &dpio_attrs);
1478 + if (err) {
1479 + dev_err(dev, "dpio_get_attributes() failed %d\n", err);
1480 + goto err_get_attr;
1481 + }
1482 + desc.qman_version = dpio_attrs.qbman_version;
1483 +
1484 + err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1485 + if (err) {
1486 + dev_err(dev, "dpio_enable() failed %d\n", err);
1487 + goto err_get_attr;
1488 + }
1489 +
1490 + /* initialize DPIO descriptor */
1491 + desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0;
1492 + desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0;
1493 + desc.dpio_id = dpio_dev->obj_desc.id;
1494 +
1495 + /* get the cpu to use for the affinity hint */
1496 + if (next_cpu == -1)
1497 + next_cpu = cpumask_first(cpu_online_mask);
1498 + else
1499 + next_cpu = cpumask_next(next_cpu, cpu_online_mask);
1500 +
1501 + if (!cpu_possible(next_cpu)) {
1502 + dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
1503 + err = -ERANGE;
1504 + goto err_allocate_irqs;
1505 + }
1506 + desc.cpu = next_cpu;
1507 +
1508 + /*
1509 + * Set the CENA regs to be the cache enabled area of the portal to
1510 + * achieve the best performance.
1511 + */
1512 + desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
1513 + resource_size(&dpio_dev->regions[0]));
1514 + desc.regs_cinh = ioremap(dpio_dev->regions[1].start,
1515 + resource_size(&dpio_dev->regions[1]));
1516 +
1517 + err = fsl_mc_allocate_irqs(dpio_dev);
1518 + if (err) {
1519 + dev_err(dev, "fsl_mc_allocate_irqs failed. err=%d\n", err);
1520 + goto err_allocate_irqs;
1521 + }
1522 +
1523 + err = register_dpio_irq_handlers(dpio_dev, desc.cpu);
1524 + if (err)
1525 + goto err_register_dpio_irq;
1526 +
1527 + priv->io = dpaa2_io_create(&desc);
1528 + if (!priv->io) {
1529 + dev_err(dev, "dpaa2_io_create failed\n");
1530 + goto err_dpaa2_io_create;
1531 + }
1532 +
1533 + dev_info(dev, "probed\n");
1534 + dev_dbg(dev, " receives_notifications = %d\n",
1535 + desc.receives_notifications);
1536 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1537 + fsl_mc_portal_free(dpio_dev->mc_io);
1538 +
1539 + return 0;
1540 +
1541 +err_dpaa2_io_create:
1542 + unregister_dpio_irq_handlers(dpio_dev);
1543 +err_register_dpio_irq:
1544 + fsl_mc_free_irqs(dpio_dev);
1545 +err_allocate_irqs:
1546 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1547 +err_get_attr:
1548 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1549 +err_open:
1550 + fsl_mc_portal_free(dpio_dev->mc_io);
1551 +err_mcportal:
1552 + dev_set_drvdata(dev, NULL);
1553 +err_priv_alloc:
1554 + return err;
1555 +}
1556 +
1557 +/* Tear down interrupts for a given DPIO object */
1558 +static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev)
1559 +{
1560 + unregister_dpio_irq_handlers(dpio_dev);
1561 + fsl_mc_free_irqs(dpio_dev);
1562 +}
1563 +
1564 +static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev)
1565 +{
1566 + struct device *dev;
1567 + struct dpio_priv *priv;
1568 + int err;
1569 +
1570 + dev = &dpio_dev->dev;
1571 + priv = dev_get_drvdata(dev);
1572 +
1573 + dpaa2_io_down(priv->io);
1574 +
1575 + dpio_teardown_irqs(dpio_dev);
1576 +
1577 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1578 + if (err) {
1579 + dev_err(dev, "MC portal allocation failed\n");
1580 + goto err_mcportal;
1581 + }
1582 +
1583 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1584 + &dpio_dev->mc_handle);
1585 + if (err) {
1586 + dev_err(dev, "dpio_open() failed\n");
1587 + goto err_open;
1588 + }
1589 +
1590 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1591 +
1592 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1593 +
1594 + fsl_mc_portal_free(dpio_dev->mc_io);
1595 +
1596 + dev_set_drvdata(dev, NULL);
1597 +
1598 + return 0;
1599 +
1600 +err_open:
1601 + fsl_mc_portal_free(dpio_dev->mc_io);
1602 +err_mcportal:
1603 + return err;
1604 +}
1605 +
1606 +static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = {
1607 + {
1608 + .vendor = FSL_MC_VENDOR_FREESCALE,
1609 + .obj_type = "dpio",
1610 + },
1611 + { .vendor = 0x0 }
1612 +};
1613 +
1614 +static struct fsl_mc_driver dpaa2_dpio_driver = {
1615 + .driver = {
1616 + .name = KBUILD_MODNAME,
1617 + .owner = THIS_MODULE,
1618 + },
1619 + .probe = dpaa2_dpio_probe,
1620 + .remove = dpaa2_dpio_remove,
1621 + .match_id_table = dpaa2_dpio_match_id_table
1622 +};
1623 +
1624 +static int dpio_driver_init(void)
1625 +{
1626 + return fsl_mc_driver_register(&dpaa2_dpio_driver);
1627 +}
1628 +
1629 +static void dpio_driver_exit(void)
1630 +{
1631 + fsl_mc_driver_unregister(&dpaa2_dpio_driver);
1632 +}
1633 +module_init(dpio_driver_init);
1634 +module_exit(dpio_driver_exit);
1635 --- /dev/null
1636 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt
1637 @@ -0,0 +1,135 @@
1638 +Copyright 2016 NXP
1639 +
1640 +Introduction
1641 +------------
1642 +
1643 +A DPAA2 DPIO (Data Path I/O) is a hardware object that provides
1644 +interfaces to enqueue and dequeue frames to/from network interfaces
1645 +and other accelerators. A DPIO also provides hardware buffer
1646 +pool management for network interfaces.
1647 +
1648 +This document provides an overview the Linux DPIO driver, its
1649 +subcomponents, and its APIs.
1650 +
1651 +See Documentation/dpaa2/overview.txt for a general overview of DPAA2
1652 +and the general DPAA2 driver architecture in Linux.
1653 +
1654 +Driver Overview
1655 +---------------
1656 +
1657 +The DPIO driver is bound to DPIO objects discovered on the fsl-mc bus and
1658 +provides services that:
1659 + A) allow other drivers, such as the Ethernet driver, to enqueue and dequeue
1660 + frames for their respective objects
1661 + B) allow drivers to register callbacks for data availability notifications
1662 + when data becomes available on a queue or channel
1663 + C) allow drivers to manage hardware buffer pools
1664 +
1665 +The Linux DPIO driver consists of 3 primary components--
1666 + DPIO object driver-- fsl-mc driver that manages the DPIO object
1667 + DPIO service-- provides APIs to other Linux drivers for services
1668 + QBman portal interface-- sends portal commands, gets responses
1669 +
1670 + fsl-mc other
1671 + bus drivers
1672 + | |
1673 + +---+----+ +------+-----+
1674 + |DPIO obj| |DPIO service|
1675 + | driver |---| (DPIO) |
1676 + +--------+ +------+-----+
1677 + |
1678 + +------+-----+
1679 + | QBman |
1680 + | portal i/f |
1681 + +------------+
1682 + |
1683 + hardware
1684 +
1685 +The diagram below shows how the DPIO driver components fit with the other
1686 +DPAA2 Linux driver components:
1687 + +------------+
1688 + | OS Network |
1689 + | Stack |
1690 + +------------+ +------------+
1691 + | Allocator |. . . . . . . | Ethernet |
1692 + |(DPMCP,DPBP)| | (DPNI) |
1693 + +-.----------+ +---+---+----+
1694 + . . ^ |
1695 + . . <data avail, | |<enqueue,
1696 + . . tx confirm> | | dequeue>
1697 + +-------------+ . | |
1698 + | DPRC driver | . +--------+ +------------+
1699 + | (DPRC) | . . |DPIO obj| |DPIO service|
1700 + +----------+--+ | driver |-| (DPIO) |
1701 + | +--------+ +------+-----+
1702 + |<dev add/remove> +------|-----+
1703 + | | QBman |
1704 + +----+--------------+ | portal i/f |
1705 + | MC-bus driver | +------------+
1706 + | | |
1707 + | /soc/fsl-mc | |
1708 + +-------------------+ |
1709 + |
1710 + =========================================|=========|========================
1711 + +-+--DPIO---|-----------+
1712 + | | |
1713 + | QBman Portal |
1714 + +-----------------------+
1715 +
1716 + ============================================================================
1717 +
1718 +
1719 +DPIO Object Driver (dpio-driver.c)
1720 +----------------------------------
1721 +
1722 + The dpio-driver component registers with the fsl-mc bus to handle objects of
1723 + type "dpio". The implementation of probe() handles basic initialization
1724 + of the DPIO including mapping of the DPIO regions (the QBman SW portal)
1725 + and initializing interrupts and registering irq handlers. The dpio-driver
1726 + registers the probed DPIO with dpio-service.
1727 +
1728 +DPIO service (dpio-service.c, dpaa2-io.h)
1729 +------------------------------------------
1730 +
1731 + The dpio service component provides queuing, notification, and buffers
1732 + management services to DPAA2 drivers, such as the Ethernet driver. A system
1733 + will typically allocate 1 DPIO object per CPU to allow queuing operations
1734 + to happen simultaneously across all CPUs.
1735 +
1736 + Notification handling
1737 + dpaa2_io_service_register()
1738 + dpaa2_io_service_deregister()
1739 + dpaa2_io_service_rearm()
1740 +
1741 + Queuing
1742 + dpaa2_io_service_pull_fq()
1743 + dpaa2_io_service_pull_channel()
1744 + dpaa2_io_service_enqueue_fq()
1745 + dpaa2_io_service_enqueue_qd()
1746 + dpaa2_io_store_create()
1747 + dpaa2_io_store_destroy()
1748 + dpaa2_io_store_next()
1749 +
1750 + Buffer pool management
1751 + dpaa2_io_service_release()
1752 + dpaa2_io_service_acquire()
1753 +
1754 +QBman portal interface (qbman-portal.c)
1755 +---------------------------------------
1756 +
1757 + The qbman-portal component provides APIs to do the low level hardware
1758 + bit twiddling for operations such as:
1759 + -initializing Qman software portals
1760 + -building and sending portal commands
1761 + -portal interrupt configuration and processing
1762 +
1763 + The qbman-portal APIs are not public to other drivers, and are
1764 + only used by dpio-service.
1765 +
1766 +Other (dpaa2-fd.h, dpaa2-global.h)
1767 +----------------------------------
1768 +
1769 + Frame descriptor and scatter-gather definitions and the APIs used to
1770 + manipulate them are defined in dpaa2-fd.h.
1771 +
1772 + Dequeue result struct and parsing APIs are defined in dpaa2-global.h.
1773 --- /dev/null
1774 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
1775 @@ -0,0 +1,689 @@
1776 +/*
1777 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1778 + * Copyright 2016 NXP
1779 + *
1780 + * Redistribution and use in source and binary forms, with or without
1781 + * modification, are permitted provided that the following conditions are met:
1782 + * * Redistributions of source code must retain the above copyright
1783 + * notice, this list of conditions and the following disclaimer.
1784 + * * Redistributions in binary form must reproduce the above copyright
1785 + * notice, this list of conditions and the following disclaimer in the
1786 + * documentation and/or other materials provided with the distribution.
1787 + * * Neither the name of Freescale Semiconductor nor the
1788 + * names of its contributors may be used to endorse or promote products
1789 + * derived from this software without specific prior written permission.
1790 + *
1791 + * ALTERNATIVELY, this software may be distributed under the terms of the
1792 + * GNU General Public License ("GPL") as published by the Free Software
1793 + * Foundation, either version 2 of that License or (at your option) any
1794 + * later version.
1795 + *
1796 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1797 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1798 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1799 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1800 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1801 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1802 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1803 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1804 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1805 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1806 + */
1807 +#include <linux/types.h>
1808 +#include "../../include/mc.h"
1809 +#include "../../include/dpaa2-io.h"
1810 +#include <linux/init.h>
1811 +#include <linux/module.h>
1812 +#include <linux/platform_device.h>
1813 +#include <linux/interrupt.h>
1814 +#include <linux/dma-mapping.h>
1815 +#include <linux/slab.h>
1816 +
1817 +#include "dpio.h"
1818 +#include "qbman-portal.h"
1819 +#include "qbman_debug.h"
1820 +
1821 +struct dpaa2_io {
1822 + atomic_t refs;
1823 + struct dpaa2_io_desc dpio_desc;
1824 + struct qbman_swp_desc swp_desc;
1825 + struct qbman_swp *swp;
1826 + struct list_head node;
1827 + /* protect against multiple management commands */
1828 + spinlock_t lock_mgmt_cmd;
1829 + /* protect notifications list */
1830 + spinlock_t lock_notifications;
1831 + struct list_head notifications;
1832 +};
1833 +
1834 +struct dpaa2_io_store {
1835 + unsigned int max;
1836 + dma_addr_t paddr;
1837 + struct dpaa2_dq *vaddr;
1838 + void *alloced_addr; /* unaligned value from kmalloc() */
1839 + unsigned int idx; /* position of the next-to-be-returned entry */
1840 + struct qbman_swp *swp; /* portal used to issue VDQCR */
1841 + struct device *dev; /* device used for DMA mapping */
1842 +};
1843 +
1844 +/* keep a per cpu array of DPIOs for fast access */
1845 +static struct dpaa2_io *dpio_by_cpu[NR_CPUS];
1846 +static struct list_head dpio_list = LIST_HEAD_INIT(dpio_list);
1847 +static DEFINE_SPINLOCK(dpio_list_lock);
1848 +
1849 +static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d,
1850 + int cpu)
1851 +{
1852 + if (d)
1853 + return d;
1854 +
1855 + if (unlikely(cpu >= num_possible_cpus()))
1856 + return NULL;
1857 +
1858 + /*
1859 + * If cpu == -1, choose the current cpu, with no guarantees about
1860 + * potentially being migrated away.
1861 + */
1862 + if (unlikely(cpu < 0))
1863 + cpu = smp_processor_id();
1864 +
1865 + /* If a specific cpu was requested, pick it up immediately */
1866 + return dpio_by_cpu[cpu];
1867 +}
1868 +
1869 +static inline struct dpaa2_io *service_select(struct dpaa2_io *d)
1870 +{
1871 + if (d)
1872 + return d;
1873 +
1874 + spin_lock(&dpio_list_lock);
1875 + d = list_entry(dpio_list.next, struct dpaa2_io, node);
1876 + list_del(&d->node);
1877 + list_add_tail(&d->node, &dpio_list);
1878 + spin_unlock(&dpio_list_lock);
1879 +
1880 + return d;
1881 +}
1882 +
1883 +/**
1884 + * dpaa2_io_create() - create a dpaa2_io object.
1885 + * @desc: the dpaa2_io descriptor
1886 + *
1887 + * Activates a "struct dpaa2_io" corresponding to the given config of an actual
1888 + * DPIO object.
1889 + *
1890 + * Return a valid dpaa2_io object for success, or NULL for failure.
1891 + */
1892 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc)
1893 +{
1894 + struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL);
1895 +
1896 + if (!obj)
1897 + return NULL;
1898 +
1899 + /* check if CPU is out of range (-1 means any cpu) */
1900 + if (desc->cpu >= num_possible_cpus()) {
1901 + kfree(obj);
1902 + return NULL;
1903 + }
1904 +
1905 + atomic_set(&obj->refs, 1);
1906 + obj->dpio_desc = *desc;
1907 + obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
1908 + obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
1909 + obj->swp_desc.qman_version = obj->dpio_desc.qman_version;
1910 + obj->swp = qbman_swp_init(&obj->swp_desc);
1911 +
1912 + if (!obj->swp) {
1913 + kfree(obj);
1914 + return NULL;
1915 + }
1916 +
1917 + INIT_LIST_HEAD(&obj->node);
1918 + spin_lock_init(&obj->lock_mgmt_cmd);
1919 + spin_lock_init(&obj->lock_notifications);
1920 + INIT_LIST_HEAD(&obj->notifications);
1921 +
1922 + /* For now only enable DQRR interrupts */
1923 + qbman_swp_interrupt_set_trigger(obj->swp,
1924 + QBMAN_SWP_INTERRUPT_DQRI);
1925 + qbman_swp_interrupt_clear_status(obj->swp, 0xffffffff);
1926 + if (obj->dpio_desc.receives_notifications)
1927 + qbman_swp_push_set(obj->swp, 0, 1);
1928 +
1929 + spin_lock(&dpio_list_lock);
1930 + list_add_tail(&obj->node, &dpio_list);
1931 + if (desc->cpu >= 0 && !dpio_by_cpu[desc->cpu])
1932 + dpio_by_cpu[desc->cpu] = obj;
1933 + spin_unlock(&dpio_list_lock);
1934 +
1935 + return obj;
1936 +}
1937 +EXPORT_SYMBOL(dpaa2_io_create);
1938 +
1939 +/**
1940 + * dpaa2_io_down() - release the dpaa2_io object.
1941 + * @d: the dpaa2_io object to be released.
1942 + *
1943 + * The "struct dpaa2_io" type can represent an individual DPIO object (as
1944 + * described by "struct dpaa2_io_desc") or an instance of a "DPIO service",
1945 + * which can be used to group/encapsulate multiple DPIO objects. In all cases,
1946 + * each handle obtained should be released using this function.
1947 + */
1948 +void dpaa2_io_down(struct dpaa2_io *d)
1949 +{
1950 + if (!atomic_dec_and_test(&d->refs))
1951 + return;
1952 + kfree(d);
1953 +}
1954 +EXPORT_SYMBOL(dpaa2_io_down);
1955 +
1956 +#define DPAA_POLL_MAX 32
1957 +
1958 +/**
1959 + * dpaa2_io_irq() - ISR for DPIO interrupts
1960 + *
1961 + * @obj: the given DPIO object.
1962 + *
1963 + * Return IRQ_HANDLED for success or IRQ_NONE if there
1964 + * were no pending interrupts.
1965 + */
1966 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj)
1967 +{
1968 + const struct dpaa2_dq *dq;
1969 + int max = 0;
1970 + struct qbman_swp *swp;
1971 + u32 status;
1972 +
1973 + swp = obj->swp;
1974 + status = qbman_swp_interrupt_read_status(swp);
1975 + if (!status)
1976 + return IRQ_NONE;
1977 +
1978 + dq = qbman_swp_dqrr_next(swp);
1979 + while (dq) {
1980 + if (qbman_result_is_SCN(dq)) {
1981 + struct dpaa2_io_notification_ctx *ctx;
1982 + u64 q64;
1983 +
1984 + q64 = qbman_result_SCN_ctx(dq);
1985 + ctx = (void *)q64;
1986 + ctx->cb(ctx);
1987 + } else {
1988 + pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
1989 + }
1990 + qbman_swp_dqrr_consume(swp, dq);
1991 + ++max;
1992 + if (max > DPAA_POLL_MAX)
1993 + goto done;
1994 + dq = qbman_swp_dqrr_next(swp);
1995 + }
1996 +done:
1997 + qbman_swp_interrupt_clear_status(swp, status);
1998 + qbman_swp_interrupt_set_inhibit(swp, 0);
1999 + return IRQ_HANDLED;
2000 +}
2001 +EXPORT_SYMBOL(dpaa2_io_irq);
2002 +
2003 +/**
2004 + * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
2005 + * notifications on the given DPIO service.
2006 + * @d: the given DPIO service.
2007 + * @ctx: the notification context.
2008 + *
2009 + * The caller should make the MC command to attach a DPAA2 object to
2010 + * a DPIO after this function completes successfully. In that way:
2011 + * (a) The DPIO service is "ready" to handle a notification arrival
2012 + * (which might happen before the "attach" command to MC has
2013 + * returned control of execution back to the caller)
2014 + * (b) The DPIO service can provide back to the caller the 'dpio_id' and
2015 + * 'qman64' parameters that it should pass along in the MC command
2016 + * in order for the object to be configured to produce the right
2017 + * notification fields to the DPIO service.
2018 + *
2019 + * Return 0 for success, or -ENODEV for failure.
2020 + */
2021 +int dpaa2_io_service_register(struct dpaa2_io *d,
2022 + struct dpaa2_io_notification_ctx *ctx)
2023 +{
2024 + unsigned long irqflags;
2025 +
2026 + d = service_select_by_cpu(d, ctx->desired_cpu);
2027 + if (!d)
2028 + return -ENODEV;
2029 +
2030 + ctx->dpio_id = d->dpio_desc.dpio_id;
2031 + ctx->qman64 = (u64)ctx;
2032 + ctx->dpio_private = d;
2033 + spin_lock_irqsave(&d->lock_notifications, irqflags);
2034 + list_add(&ctx->node, &d->notifications);
2035 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
2036 +
2037 + /* Enable the generation of CDAN notifications */
2038 + if (ctx->is_cdan)
2039 + qbman_swp_CDAN_set_context_enable(d->swp,
2040 + (u16)ctx->id,
2041 + ctx->qman64);
2042 + return 0;
2043 +}
2044 +EXPORT_SYMBOL(dpaa2_io_service_register);
2045 +
2046 +/**
2047 + * dpaa2_io_service_deregister - The opposite of 'register'.
2048 + * @service: the given DPIO service.
2049 + * @ctx: the notification context.
2050 + *
2051 + * This function should be called only after sending the MC command to
2052 + * to detach the notification-producing device from the DPIO.
2053 + */
2054 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
2055 + struct dpaa2_io_notification_ctx *ctx)
2056 +{
2057 + struct dpaa2_io *d = ctx->dpio_private;
2058 + unsigned long irqflags;
2059 +
2060 + if (ctx->is_cdan)
2061 + qbman_swp_CDAN_disable(d->swp, (u16)ctx->id);
2062 +
2063 + spin_lock_irqsave(&d->lock_notifications, irqflags);
2064 + list_del(&ctx->node);
2065 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
2066 +}
2067 +EXPORT_SYMBOL(dpaa2_io_service_deregister);
2068 +
2069 +/**
2070 + * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
2071 + * @d: the given DPIO service.
2072 + * @ctx: the notification context.
2073 + *
2074 + * Once a FQDAN/CDAN has been produced, the corresponding FQ/channel is
2075 + * considered "disarmed". Ie. the user can issue pull dequeue operations on that
2076 + * traffic source for as long as it likes. Eventually it may wish to "rearm"
2077 + * that source to allow it to produce another FQDAN/CDAN, that's what this
2078 + * function achieves.
2079 + *
2080 + * Return 0 for success.
2081 + */
2082 +int dpaa2_io_service_rearm(struct dpaa2_io *d,
2083 + struct dpaa2_io_notification_ctx *ctx)
2084 +{
2085 + unsigned long irqflags;
2086 + int err;
2087 +
2088 + d = service_select_by_cpu(d, ctx->desired_cpu);
2089 + if (!unlikely(d))
2090 + return -ENODEV;
2091 +
2092 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2093 + if (ctx->is_cdan)
2094 + err = qbman_swp_CDAN_enable(d->swp, (u16)ctx->id);
2095 + else
2096 + err = qbman_swp_fq_schedule(d->swp, ctx->id);
2097 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2098 +
2099 + return err;
2100 +}
2101 +EXPORT_SYMBOL(dpaa2_io_service_rearm);
2102 +
2103 +/**
2104 + * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq.
2105 + * @d: the given DPIO service.
2106 + * @fqid: the given frame queue id.
2107 + * @s: the dpaa2_io_store object for the result.
2108 + *
2109 + * Return 0 for success, or error code for failure.
2110 + */
2111 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
2112 + struct dpaa2_io_store *s)
2113 +{
2114 + struct qbman_pull_desc pd;
2115 + int err;
2116 +
2117 + qbman_pull_desc_clear(&pd);
2118 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
2119 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
2120 + qbman_pull_desc_set_fq(&pd, fqid);
2121 +
2122 + d = service_select(d);
2123 + if (!d)
2124 + return -ENODEV;
2125 + s->swp = d->swp;
2126 + err = qbman_swp_pull(d->swp, &pd);
2127 + if (err)
2128 + s->swp = NULL;
2129 +
2130 + return err;
2131 +}
2132 +EXPORT_SYMBOL(dpaa2_io_service_pull_fq);
2133 +
2134 +/**
2135 + * dpaa2_io_service_pull_channel() - pull dequeue functions from a channel.
2136 + * @d: the given DPIO service.
2137 + * @channelid: the given channel id.
2138 + * @s: the dpaa2_io_store object for the result.
2139 + *
2140 + * Return 0 for success, or error code for failure.
2141 + */
2142 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
2143 + struct dpaa2_io_store *s)
2144 +{
2145 + struct qbman_pull_desc pd;
2146 + int err;
2147 +
2148 + qbman_pull_desc_clear(&pd);
2149 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
2150 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
2151 + qbman_pull_desc_set_channel(&pd, channelid, qbman_pull_type_prio);
2152 +
2153 + d = service_select(d);
2154 + if (!d)
2155 + return -ENODEV;
2156 +
2157 + s->swp = d->swp;
2158 + err = qbman_swp_pull(d->swp, &pd);
2159 + if (err)
2160 + s->swp = NULL;
2161 +
2162 + return err;
2163 +}
2164 +EXPORT_SYMBOL(dpaa2_io_service_pull_channel);
2165 +
2166 +/**
2167 + * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue.
2168 + * @d: the given DPIO service.
2169 + * @fqid: the given frame queue id.
2170 + * @fd: the frame descriptor which is enqueued.
2171 + *
2172 + * Return 0 for successful enqueue, -EBUSY if the enqueue ring is not ready,
2173 + * or -ENODEV if there is no dpio service.
2174 + */
2175 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d,
2176 + u32 fqid,
2177 + const struct dpaa2_fd *fd)
2178 +{
2179 + struct qbman_eq_desc ed;
2180 +
2181 + d = service_select(d);
2182 + if (!d)
2183 + return -ENODEV;
2184 +
2185 + qbman_eq_desc_clear(&ed);
2186 + qbman_eq_desc_set_no_orp(&ed, 0);
2187 + qbman_eq_desc_set_fq(&ed, fqid);
2188 +
2189 + return qbman_swp_enqueue(d->swp, &ed, fd);
2190 +}
2191 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_fq);
2192 +
2193 +/**
2194 + * dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD.
2195 + * @d: the given DPIO service.
2196 + * @qdid: the given queuing destination id.
2197 + * @prio: the given queuing priority.
2198 + * @qdbin: the given queuing destination bin.
2199 + * @fd: the frame descriptor which is enqueued.
2200 + *
2201 + * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
2202 + * or -ENODEV if there is no dpio service.
2203 + */
2204 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d,
2205 + u32 qdid, u8 prio, u16 qdbin,
2206 + const struct dpaa2_fd *fd)
2207 +{
2208 + struct qbman_eq_desc ed;
2209 +
2210 + d = service_select(d);
2211 + if (!d)
2212 + return -ENODEV;
2213 +
2214 + qbman_eq_desc_clear(&ed);
2215 + qbman_eq_desc_set_no_orp(&ed, 0);
2216 + qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
2217 +
2218 + return qbman_swp_enqueue(d->swp, &ed, fd);
2219 +}
2220 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_qd);
2221 +
2222 +/**
2223 + * dpaa2_io_service_release() - Release buffers to a buffer pool.
2224 + * @d: the given DPIO object.
2225 + * @bpid: the buffer pool id.
2226 + * @buffers: the buffers to be released.
2227 + * @num_buffers: the number of the buffers to be released.
2228 + *
2229 + * Return 0 for success, and negative error code for failure.
2230 + */
2231 +int dpaa2_io_service_release(struct dpaa2_io *d,
2232 + u32 bpid,
2233 + const u64 *buffers,
2234 + unsigned int num_buffers)
2235 +{
2236 + struct qbman_release_desc rd;
2237 +
2238 + d = service_select(d);
2239 + if (!d)
2240 + return -ENODEV;
2241 +
2242 + qbman_release_desc_clear(&rd);
2243 + qbman_release_desc_set_bpid(&rd, bpid);
2244 +
2245 + return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
2246 +}
2247 +EXPORT_SYMBOL(dpaa2_io_service_release);
2248 +
2249 +/**
2250 + * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
2251 + * @d: the given DPIO object.
2252 + * @bpid: the buffer pool id.
2253 + * @buffers: the buffer addresses for acquired buffers.
2254 + * @num_buffers: the expected number of the buffers to acquire.
2255 + *
2256 + * Return a negative error code if the command failed, otherwise it returns
2257 + * the number of buffers acquired, which may be less than the number requested.
2258 + * Eg. if the buffer pool is empty, this will return zero.
2259 + */
2260 +int dpaa2_io_service_acquire(struct dpaa2_io *d,
2261 + u32 bpid,
2262 + u64 *buffers,
2263 + unsigned int num_buffers)
2264 +{
2265 + unsigned long irqflags;
2266 + int err;
2267 +
2268 + d = service_select(d);
2269 + if (!d)
2270 + return -ENODEV;
2271 +
2272 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2273 + err = qbman_swp_acquire(d->swp, bpid, buffers, num_buffers);
2274 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2275 +
2276 + return err;
2277 +}
2278 +EXPORT_SYMBOL(dpaa2_io_service_acquire);
2279 +
2280 +/*
2281 + * 'Stores' are reusable memory blocks for holding dequeue results, and to
2282 + * assist with parsing those results.
2283 + */
2284 +
2285 +/**
2286 + * dpaa2_io_store_create() - Create the dma memory storage for dequeue result.
2287 + * @max_frames: the maximum number of dequeued result for frames, must be <= 16.
2288 + * @dev: the device to allow mapping/unmapping the DMAable region.
2289 + *
2290 + * The size of the storage is "max_frames*sizeof(struct dpaa2_dq)".
2291 + * The 'dpaa2_io_store' returned is a DPIO service managed object.
2292 + *
2293 + * Return pointer to dpaa2_io_store struct for successfuly created storage
2294 + * memory, or NULL on error.
2295 + */
2296 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
2297 + struct device *dev)
2298 +{
2299 + struct dpaa2_io_store *ret;
2300 + size_t size;
2301 +
2302 + if (!max_frames || (max_frames > 16))
2303 + return NULL;
2304 +
2305 + ret = kmalloc(sizeof(*ret), GFP_KERNEL);
2306 + if (!ret)
2307 + return NULL;
2308 +
2309 + ret->max = max_frames;
2310 + size = max_frames * sizeof(struct dpaa2_dq) + 64;
2311 + ret->alloced_addr = kzalloc(size, GFP_KERNEL);
2312 + if (!ret->alloced_addr) {
2313 + kfree(ret);
2314 + return NULL;
2315 + }
2316 +
2317 + ret->vaddr = PTR_ALIGN(ret->alloced_addr, 64);
2318 + ret->paddr = dma_map_single(dev, ret->vaddr,
2319 + sizeof(struct dpaa2_dq) * max_frames,
2320 + DMA_FROM_DEVICE);
2321 + if (dma_mapping_error(dev, ret->paddr)) {
2322 + kfree(ret->alloced_addr);
2323 + kfree(ret);
2324 + return NULL;
2325 + }
2326 +
2327 + ret->idx = 0;
2328 + ret->dev = dev;
2329 +
2330 + return ret;
2331 +}
2332 +EXPORT_SYMBOL(dpaa2_io_store_create);
2333 +
2334 +/**
2335 + * dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
2336 + * result.
2337 + * @s: the storage memory to be destroyed.
2338 + */
2339 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s)
2340 +{
2341 + dma_unmap_single(s->dev, s->paddr, sizeof(struct dpaa2_dq) * s->max,
2342 + DMA_FROM_DEVICE);
2343 + kfree(s->alloced_addr);
2344 + kfree(s);
2345 +}
2346 +EXPORT_SYMBOL(dpaa2_io_store_destroy);
2347 +
2348 +/**
2349 + * dpaa2_io_store_next() - Determine when the next dequeue result is available.
2350 + * @s: the dpaa2_io_store object.
2351 + * @is_last: indicate whether this is the last frame in the pull command.
2352 + *
2353 + * When an object driver performs dequeues to a dpaa2_io_store, this function
2354 + * can be used to determine when the next frame result is available. Once
2355 + * this function returns non-NULL, a subsequent call to it will try to find
2356 + * the next dequeue result.
2357 + *
2358 + * Note that if a pull-dequeue has a NULL result because the target FQ/channel
2359 + * was empty, then this function will also return NULL (rather than expecting
2360 + * the caller to always check for this. As such, "is_last" can be used to
2361 + * differentiate between "end-of-empty-dequeue" and "still-waiting".
2362 + *
2363 + * Return dequeue result for a valid dequeue result, or NULL for empty dequeue.
2364 + */
2365 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last)
2366 +{
2367 + int match;
2368 + struct dpaa2_dq *ret = &s->vaddr[s->idx];
2369 +
2370 + match = qbman_result_has_new_result(s->swp, ret);
2371 + if (!match) {
2372 + *is_last = 0;
2373 + return NULL;
2374 + }
2375 +
2376 + s->idx++;
2377 +
2378 + if (dpaa2_dq_is_pull_complete(ret)) {
2379 + *is_last = 1;
2380 + s->idx = 0;
2381 + /*
2382 + * If we get an empty dequeue result to terminate a zero-results
2383 + * vdqcr, return NULL to the caller rather than expecting him to
2384 + * check non-NULL results every time.
2385 + */
2386 + if (!(dpaa2_dq_flags(ret) & DPAA2_DQ_STAT_VALIDFRAME))
2387 + ret = NULL;
2388 + } else {
2389 + *is_last = 0;
2390 + }
2391 +
2392 + return ret;
2393 +}
2394 +EXPORT_SYMBOL(dpaa2_io_store_next);
2395 +
2396 +#ifdef CONFIG_FSL_QBMAN_DEBUG
2397 +/**
2398 + * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq.
2399 + * @d: the given DPIO object.
2400 + * @fqid: the id of frame queue to be queried.
2401 + * @fcnt: the queried frame count.
2402 + * @bcnt: the queried byte count.
2403 + *
2404 + * Knowing the FQ count at run-time can be useful in debugging situations.
2405 + * The instantaneous frame- and byte-count are hereby returned.
2406 + *
2407 + * Return 0 for a successful query, and negative error code if query fails.
2408 + */
2409 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
2410 + u32 *fcnt, u32 *bcnt)
2411 +{
2412 + struct qbman_attr state;
2413 + struct qbman_swp *swp;
2414 + unsigned long irqflags;
2415 + int ret;
2416 +
2417 + d = service_select(d);
2418 + if (!d)
2419 + return -ENODEV;
2420 +
2421 + swp = d->swp;
2422 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2423 + ret = qbman_fq_query_state(swp, fqid, &state);
2424 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2425 + if (ret)
2426 + return ret;
2427 + *fcnt = qbman_fq_state_frame_count(&state);
2428 + *bcnt = qbman_fq_state_byte_count(&state);
2429 +
2430 + return 0;
2431 +}
2432 +EXPORT_SYMBOL(dpaa2_io_query_fq_count);
2433 +
2434 +/**
2435 + * dpaa2_io_query_bp_count() - Query the number of buffers currenty in a
2436 + * buffer pool.
2437 + * @d: the given DPIO object.
2438 + * @bpid: the index of buffer pool to be queried.
2439 + * @num: the queried number of buffers in the buffer pool.
2440 + *
2441 + * Return 0 for a sucessful query, and negative error code if query fails.
2442 + */
2443 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid, u32 *num)
2444 +{
2445 + struct qbman_attr state;
2446 + struct qbman_swp *swp;
2447 + unsigned long irqflags;
2448 + int ret;
2449 +
2450 + d = service_select(d);
2451 + if (!d)
2452 + return -ENODEV;
2453 +
2454 + swp = d->swp;
2455 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2456 + ret = qbman_bp_query(swp, bpid, &state);
2457 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2458 + if (ret)
2459 + return ret;
2460 + *num = qbman_bp_info_num_free_bufs(&state);
2461 + return 0;
2462 +}
2463 +EXPORT_SYMBOL(dpaa2_io_query_bp_count);
2464 +#endif
2465 --- /dev/null
2466 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
2467 @@ -0,0 +1,224 @@
2468 +/*
2469 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2470 + * Copyright 2016 NXP
2471 + *
2472 + * Redistribution and use in source and binary forms, with or without
2473 + * modification, are permitted provided that the following conditions are met:
2474 + * * Redistributions of source code must retain the above copyright
2475 + * notice, this list of conditions and the following disclaimer.
2476 + * * Redistributions in binary form must reproduce the above copyright
2477 + * notice, this list of conditions and the following disclaimer in the
2478 + * documentation and/or other materials provided with the distribution.
2479 + * * Neither the name of the above-listed copyright holders nor the
2480 + * names of any contributors may be used to endorse or promote products
2481 + * derived from this software without specific prior written permission.
2482 + *
2483 + * ALTERNATIVELY, this software may be distributed under the terms of the
2484 + * GNU General Public License ("GPL") as published by the Free Software
2485 + * Foundation, either version 2 of that License or (at your option) any
2486 + * later version.
2487 + *
2488 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2489 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2490 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2491 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2492 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2493 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2494 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2495 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2496 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2497 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2498 + * POSSIBILITY OF SUCH DAMAGE.
2499 + */
2500 +#include "../../include/mc-sys.h"
2501 +#include "../../include/mc-cmd.h"
2502 +
2503 +#include "dpio.h"
2504 +#include "dpio-cmd.h"
2505 +
2506 +/*
2507 + * Data Path I/O Portal API
2508 + * Contains initialization APIs and runtime control APIs for DPIO
2509 + */
2510 +
2511 +/**
2512 + * dpio_open() - Open a control session for the specified object
2513 + * @mc_io: Pointer to MC portal's I/O object
2514 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2515 + * @dpio_id: DPIO unique ID
2516 + * @token: Returned token; use in subsequent API calls
2517 + *
2518 + * This function can be used to open a control session for an
2519 + * already created object; an object may have been declared in
2520 + * the DPL or by calling the dpio_create() function.
2521 + * This function returns a unique authentication token,
2522 + * associated with the specific object ID and the specific MC
2523 + * portal; this token must be used in all subsequent commands for
2524 + * this specific object.
2525 + *
2526 + * Return: '0' on Success; Error code otherwise.
2527 + */
2528 +int dpio_open(struct fsl_mc_io *mc_io,
2529 + u32 cmd_flags,
2530 + int dpio_id,
2531 + u16 *token)
2532 +{
2533 + struct mc_command cmd = { 0 };
2534 + struct dpio_cmd_open *dpio_cmd;
2535 + int err;
2536 +
2537 + /* prepare command */
2538 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
2539 + cmd_flags,
2540 + 0);
2541 + dpio_cmd = (struct dpio_cmd_open *)cmd.params;
2542 + dpio_cmd->dpio_id = cpu_to_le32(dpio_id);
2543 +
2544 + err = mc_send_command(mc_io, &cmd);
2545 + if (err)
2546 + return err;
2547 +
2548 + /* retrieve response parameters */
2549 + *token = mc_cmd_hdr_read_token(&cmd);
2550 +
2551 + return 0;
2552 +}
2553 +
2554 +/**
2555 + * dpio_close() - Close the control session of the object
2556 + * @mc_io: Pointer to MC portal's I/O object
2557 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2558 + * @token: Token of DPIO object
2559 + *
2560 + * Return: '0' on Success; Error code otherwise.
2561 + */
2562 +int dpio_close(struct fsl_mc_io *mc_io,
2563 + u32 cmd_flags,
2564 + u16 token)
2565 +{
2566 + struct mc_command cmd = { 0 };
2567 +
2568 + /* prepare command */
2569 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
2570 + cmd_flags,
2571 + token);
2572 +
2573 + return mc_send_command(mc_io, &cmd);
2574 +}
2575 +
2576 +/**
2577 + * dpio_enable() - Enable the DPIO, allow I/O portal operations.
2578 + * @mc_io: Pointer to MC portal's I/O object
2579 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2580 + * @token: Token of DPIO object
2581 + *
2582 + * Return: '0' on Success; Error code otherwise
2583 + */
2584 +int dpio_enable(struct fsl_mc_io *mc_io,
2585 + u32 cmd_flags,
2586 + u16 token)
2587 +{
2588 + struct mc_command cmd = { 0 };
2589 +
2590 + /* prepare command */
2591 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
2592 + cmd_flags,
2593 + token);
2594 +
2595 + return mc_send_command(mc_io, &cmd);
2596 +}
2597 +
2598 +/**
2599 + * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
2600 + * @mc_io: Pointer to MC portal's I/O object
2601 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2602 + * @token: Token of DPIO object
2603 + *
2604 + * Return: '0' on Success; Error code otherwise
2605 + */
2606 +int dpio_disable(struct fsl_mc_io *mc_io,
2607 + u32 cmd_flags,
2608 + u16 token)
2609 +{
2610 + struct mc_command cmd = { 0 };
2611 +
2612 + /* prepare command */
2613 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
2614 + cmd_flags,
2615 + token);
2616 +
2617 + return mc_send_command(mc_io, &cmd);
2618 +}
2619 +
2620 +/**
2621 + * dpio_get_attributes() - Retrieve DPIO attributes
2622 + * @mc_io: Pointer to MC portal's I/O object
2623 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2624 + * @token: Token of DPIO object
2625 + * @attr: Returned object's attributes
2626 + *
2627 + * Return: '0' on Success; Error code otherwise
2628 + */
2629 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2630 + u32 cmd_flags,
2631 + u16 token,
2632 + struct dpio_attr *attr)
2633 +{
2634 + struct mc_command cmd = { 0 };
2635 + struct dpio_rsp_get_attr *dpio_rsp;
2636 + int err;
2637 +
2638 + /* prepare command */
2639 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
2640 + cmd_flags,
2641 + token);
2642 +
2643 + err = mc_send_command(mc_io, &cmd);
2644 + if (err)
2645 + return err;
2646 +
2647 + /* retrieve response parameters */
2648 + dpio_rsp = (struct dpio_rsp_get_attr *)cmd.params;
2649 + attr->id = le32_to_cpu(dpio_rsp->id);
2650 + attr->qbman_portal_id = le16_to_cpu(dpio_rsp->qbman_portal_id);
2651 + attr->num_priorities = dpio_rsp->num_priorities;
2652 + attr->channel_mode = dpio_rsp->channel_mode & DPIO_CHANNEL_MODE_MASK;
2653 + attr->qbman_portal_ce_offset =
2654 + le64_to_cpu(dpio_rsp->qbman_portal_ce_addr);
2655 + attr->qbman_portal_ci_offset =
2656 + le64_to_cpu(dpio_rsp->qbman_portal_ci_addr);
2657 + attr->qbman_version = le32_to_cpu(dpio_rsp->qbman_version);
2658 +
2659 + return 0;
2660 +}
2661 +
2662 +/**
2663 + * dpio_get_api_version - Get Data Path I/O API version
2664 + * @mc_io: Pointer to MC portal's DPIO object
2665 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2666 + * @major_ver: Major version of DPIO API
2667 + * @minor_ver: Minor version of DPIO API
2668 + *
2669 + * Return: '0' on Success; Error code otherwise
2670 + */
2671 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2672 + u32 cmd_flags,
2673 + u16 *major_ver,
2674 + u16 *minor_ver)
2675 +{
2676 + struct mc_command cmd = { 0 };
2677 + int err;
2678 +
2679 + /* prepare command */
2680 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
2681 + cmd_flags, 0);
2682 +
2683 + err = mc_send_command(mc_io, &cmd);
2684 + if (err)
2685 + return err;
2686 +
2687 + /* retrieve response parameters */
2688 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
2689 +
2690 + return 0;
2691 +}
2692 --- /dev/null
2693 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.h
2694 @@ -0,0 +1,109 @@
2695 +/*
2696 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2697 + * Copyright 2016 NXP
2698 + *
2699 + * Redistribution and use in source and binary forms, with or without
2700 + * modification, are permitted provided that the following conditions are met:
2701 + * * Redistributions of source code must retain the above copyright
2702 + * notice, this list of conditions and the following disclaimer.
2703 + * * Redistributions in binary form must reproduce the above copyright
2704 + * notice, this list of conditions and the following disclaimer in the
2705 + * documentation and/or other materials provided with the distribution.
2706 + * * Neither the name of the above-listed copyright holders nor the
2707 + * names of any contributors may be used to endorse or promote products
2708 + * derived from this software without specific prior written permission.
2709 + *
2710 + * ALTERNATIVELY, this software may be distributed under the terms of the
2711 + * GNU General Public License ("GPL") as published by the Free Software
2712 + * Foundation, either version 2 of that License or (at your option) any
2713 + * later version.
2714 + *
2715 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2716 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2717 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2718 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2719 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2720 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2721 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2722 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2723 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2724 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2725 + * POSSIBILITY OF SUCH DAMAGE.
2726 + */
2727 +#ifndef __FSL_DPIO_H
2728 +#define __FSL_DPIO_H
2729 +
2730 +struct fsl_mc_io;
2731 +
2732 +int dpio_open(struct fsl_mc_io *mc_io,
2733 + u32 cmd_flags,
2734 + int dpio_id,
2735 + u16 *token);
2736 +
2737 +int dpio_close(struct fsl_mc_io *mc_io,
2738 + u32 cmd_flags,
2739 + u16 token);
2740 +
2741 +/**
2742 + * enum dpio_channel_mode - DPIO notification channel mode
2743 + * @DPIO_NO_CHANNEL: No support for notification channel
2744 + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
2745 + * dedicated channel in the DPIO; user should point the queue's
2746 + * destination in the relevant interface to this DPIO
2747 + */
2748 +enum dpio_channel_mode {
2749 + DPIO_NO_CHANNEL = 0,
2750 + DPIO_LOCAL_CHANNEL = 1,
2751 +};
2752 +
2753 +/**
2754 + * struct dpio_cfg - Structure representing DPIO configuration
2755 + * @channel_mode: Notification channel mode
2756 + * @num_priorities: Number of priorities for the notification channel (1-8);
2757 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2758 + */
2759 +struct dpio_cfg {
2760 + enum dpio_channel_mode channel_mode;
2761 + u8 num_priorities;
2762 +};
2763 +
2764 +int dpio_enable(struct fsl_mc_io *mc_io,
2765 + u32 cmd_flags,
2766 + u16 token);
2767 +
2768 +int dpio_disable(struct fsl_mc_io *mc_io,
2769 + u32 cmd_flags,
2770 + u16 token);
2771 +
2772 +/**
2773 + * struct dpio_attr - Structure representing DPIO attributes
2774 + * @id: DPIO object ID
2775 + * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
2776 + * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
2777 + * @qbman_portal_id: Software portal ID
2778 + * @channel_mode: Notification channel mode
2779 + * @num_priorities: Number of priorities for the notification channel (1-8);
2780 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2781 + * @qbman_version: QBMAN version
2782 + */
2783 +struct dpio_attr {
2784 + int id;
2785 + u64 qbman_portal_ce_offset;
2786 + u64 qbman_portal_ci_offset;
2787 + u16 qbman_portal_id;
2788 + enum dpio_channel_mode channel_mode;
2789 + u8 num_priorities;
2790 + u32 qbman_version;
2791 +};
2792 +
2793 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2794 + u32 cmd_flags,
2795 + u16 token,
2796 + struct dpio_attr *attr);
2797 +
2798 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2799 + u32 cmd_flags,
2800 + u16 *major_ver,
2801 + u16 *minor_ver);
2802 +
2803 +#endif /* __FSL_DPIO_H */
2804 --- /dev/null
2805 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
2806 @@ -0,0 +1,1049 @@
2807 +/*
2808 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
2809 + * Copyright 2016 NXP
2810 + *
2811 + * Redistribution and use in source and binary forms, with or without
2812 + * modification, are permitted provided that the following conditions are met:
2813 + * * Redistributions of source code must retain the above copyright
2814 + * notice, this list of conditions and the following disclaimer.
2815 + * * Redistributions in binary form must reproduce the above copyright
2816 + * notice, this list of conditions and the following disclaimer in the
2817 + * documentation and/or other materials provided with the distribution.
2818 + * * Neither the name of Freescale Semiconductor nor the
2819 + * names of its contributors may be used to endorse or promote products
2820 + * derived from this software without specific prior written permission.
2821 + *
2822 + * ALTERNATIVELY, this software may be distributed under the terms of the
2823 + * GNU General Public License ("GPL") as published by the Free Software
2824 + * Foundation, either version 2 of that License or (at your option) any
2825 + * later version.
2826 + *
2827 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
2828 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2829 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
2830 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
2831 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2832 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2833 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
2834 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2835 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
2836 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2837 + */
2838 +
2839 +#include <asm/cacheflush.h>
2840 +#include <linux/io.h>
2841 +#include <linux/slab.h>
2842 +#include "../../include/dpaa2-global.h"
2843 +
2844 +#include "qbman-portal.h"
2845 +
2846 +struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7);
2847 +struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8);
2848 +
2849 +#define QMAN_REV_4000 0x04000000
2850 +#define QMAN_REV_4100 0x04010000
2851 +#define QMAN_REV_4101 0x04010001
2852 +#define QMAN_REV_MASK 0xffff0000
2853 +
2854 +/* All QBMan command and result structures use this "valid bit" encoding */
2855 +#define QB_VALID_BIT ((u32)0x80)
2856 +
2857 +/* QBMan portal management command codes */
2858 +#define QBMAN_MC_ACQUIRE 0x30
2859 +#define QBMAN_WQCHAN_CONFIGURE 0x46
2860 +
2861 +/* CINH register offsets */
2862 +#define QBMAN_CINH_SWP_EQAR 0x8c0
2863 +#define QBMAN_CINH_SWP_DQPI 0xa00
2864 +#define QBMAN_CINH_SWP_DCAP 0xac0
2865 +#define QBMAN_CINH_SWP_SDQCR 0xb00
2866 +#define QBMAN_CINH_SWP_RAR 0xcc0
2867 +#define QBMAN_CINH_SWP_ISR 0xe00
2868 +#define QBMAN_CINH_SWP_IER 0xe40
2869 +#define QBMAN_CINH_SWP_ISDR 0xe80
2870 +#define QBMAN_CINH_SWP_IIR 0xec0
2871 +
2872 +/* CENA register offsets */
2873 +#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6))
2874 +#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((u32)(n) << 6))
2875 +#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((u32)(n) << 6))
2876 +#define QBMAN_CENA_SWP_CR 0x600
2877 +#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((u32)(vb) >> 1))
2878 +#define QBMAN_CENA_SWP_VDQCR 0x780
2879 +
2880 +/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
2881 +#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)(p) & 0x1ff) >> 6)
2882 +
2883 +/* Define token used to determine if response written to memory is valid */
2884 +#define QMAN_DQ_TOKEN_VALID 1
2885 +
2886 +/* SDQCR attribute codes */
2887 +#define QB_SDQCR_FC_SHIFT 29
2888 +#define QB_SDQCR_FC_MASK 0x1
2889 +#define QB_SDQCR_DCT_SHIFT 24
2890 +#define QB_SDQCR_DCT_MASK 0x3
2891 +#define QB_SDQCR_TOK_SHIFT 16
2892 +#define QB_SDQCR_TOK_MASK 0xff
2893 +#define QB_SDQCR_SRC_SHIFT 0
2894 +#define QB_SDQCR_SRC_MASK 0xffff
2895 +
2896 +/* opaque token for static dequeues */
2897 +#define QMAN_SDQCR_TOKEN 0xbb
2898 +
2899 +enum qbman_sdqcr_dct {
2900 + qbman_sdqcr_dct_null = 0,
2901 + qbman_sdqcr_dct_prio_ics,
2902 + qbman_sdqcr_dct_active_ics,
2903 + qbman_sdqcr_dct_active
2904 +};
2905 +
2906 +enum qbman_sdqcr_fc {
2907 + qbman_sdqcr_fc_one = 0,
2908 + qbman_sdqcr_fc_up_to_3 = 1
2909 +};
2910 +
2911 +#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
2912 +#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
2913 +static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
2914 +{
2915 + dcivac(p->addr_cena + offset);
2916 + prefetch(p->addr_cena + offset);
2917 +}
2918 +
2919 +/* Portal Access */
2920 +
2921 +static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
2922 +{
2923 + return readl_relaxed(p->addr_cinh + offset);
2924 +}
2925 +
2926 +static inline void qbman_write_register(struct qbman_swp *p, u32 offset,
2927 + u32 value)
2928 +{
2929 + writel_relaxed(value, p->addr_cinh + offset);
2930 +}
2931 +
2932 +static inline void *qbman_get_cmd(struct qbman_swp *p, u32 offset)
2933 +{
2934 + return p->addr_cena + offset;
2935 +}
2936 +
2937 +#define QBMAN_CINH_SWP_CFG 0xd00
2938 +
2939 +#define SWP_CFG_DQRR_MF_SHIFT 20
2940 +#define SWP_CFG_EST_SHIFT 16
2941 +#define SWP_CFG_WN_SHIFT 14
2942 +#define SWP_CFG_RPM_SHIFT 12
2943 +#define SWP_CFG_DCM_SHIFT 10
2944 +#define SWP_CFG_EPM_SHIFT 8
2945 +#define SWP_CFG_SD_SHIFT 5
2946 +#define SWP_CFG_SP_SHIFT 4
2947 +#define SWP_CFG_SE_SHIFT 3
2948 +#define SWP_CFG_DP_SHIFT 2
2949 +#define SWP_CFG_DE_SHIFT 1
2950 +#define SWP_CFG_EP_SHIFT 0
2951 +
2952 +static inline u32 qbman_set_swp_cfg(u8 max_fill, u8 wn, u8 est, u8 rpm, u8 dcm,
2953 + u8 epm, int sd, int sp, int se,
2954 + int dp, int de, int ep)
2955 +{
2956 + return cpu_to_le32 (max_fill << SWP_CFG_DQRR_MF_SHIFT |
2957 + est << SWP_CFG_EST_SHIFT |
2958 + wn << SWP_CFG_WN_SHIFT |
2959 + rpm << SWP_CFG_RPM_SHIFT |
2960 + dcm << SWP_CFG_DCM_SHIFT |
2961 + epm << SWP_CFG_EPM_SHIFT |
2962 + sd << SWP_CFG_SD_SHIFT |
2963 + sp << SWP_CFG_SP_SHIFT |
2964 + se << SWP_CFG_SE_SHIFT |
2965 + dp << SWP_CFG_DP_SHIFT |
2966 + de << SWP_CFG_DE_SHIFT |
2967 + ep << SWP_CFG_EP_SHIFT);
2968 +}
2969 +
2970 +/**
2971 + * qbman_swp_init() - Create a functional object representing the given
2972 + * QBMan portal descriptor.
2973 + * @d: the given qbman swp descriptor
2974 + *
2975 + * Return qbman_swp portal for success, NULL if the object cannot
2976 + * be created.
2977 + */
2978 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
2979 +{
2980 + struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
2981 + u32 reg;
2982 +
2983 + if (!p)
2984 + return NULL;
2985 + p->desc = d;
2986 + p->mc.valid_bit = QB_VALID_BIT;
2987 + p->sdq = 0;
2988 + p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
2989 + p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
2990 + p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
2991 +
2992 + atomic_set(&p->vdq.available, 1);
2993 + p->vdq.valid_bit = QB_VALID_BIT;
2994 + p->dqrr.next_idx = 0;
2995 + p->dqrr.valid_bit = QB_VALID_BIT;
2996 +
2997 + if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_4100) {
2998 + p->dqrr.dqrr_size = 4;
2999 + p->dqrr.reset_bug = 1;
3000 + } else {
3001 + p->dqrr.dqrr_size = 8;
3002 + p->dqrr.reset_bug = 0;
3003 + }
3004 +
3005 + p->addr_cena = d->cena_bar;
3006 + p->addr_cinh = d->cinh_bar;
3007 +
3008 + reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
3009 + 0, /* Writes cacheable */
3010 + 0, /* EQCR_CI stashing threshold */
3011 + 3, /* RPM: Valid bit mode, RCR in array mode */
3012 + 2, /* DCM: Discrete consumption ack mode */
3013 + 3, /* EPM: Valid bit mode, EQCR in array mode */
3014 + 0, /* mem stashing drop enable == FALSE */
3015 + 1, /* mem stashing priority == TRUE */
3016 + 0, /* mem stashing enable == FALSE */
3017 + 1, /* dequeue stashing priority == TRUE */
3018 + 0, /* dequeue stashing enable == FALSE */
3019 + 0); /* EQCR_CI stashing priority == FALSE */
3020 +
3021 + qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg);
3022 + reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG);
3023 + if (!reg) {
3024 + pr_err("qbman: the portal is not enabled!\n");
3025 + return NULL;
3026 + }
3027 +
3028 + /*
3029 + * SDQCR needs to be initialized to 0 when no channels are
3030 + * being dequeued from or else the QMan HW will indicate an
3031 + * error. The values that were calculated above will be
3032 + * applied when dequeues from a specific channel are enabled.
3033 + */
3034 + qbman_write_register(p, QBMAN_CINH_SWP_SDQCR, 0);
3035 + return p;
3036 +}
3037 +
3038 +/**
3039 + * qbman_swp_finish() - Create and destroy a functional object representing
3040 + * the given QBMan portal descriptor.
3041 + * @p: the qbman_swp object to be destroyed
3042 + */
3043 +void qbman_swp_finish(struct qbman_swp *p)
3044 +{
3045 + kfree(p);
3046 +}
3047 +
3048 +/**
3049 + * qbman_swp_interrupt_read_status()
3050 + * @p: the given software portal
3051 + *
3052 + * Return the value in the SWP_ISR register.
3053 + */
3054 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p)
3055 +{
3056 + return qbman_read_register(p, QBMAN_CINH_SWP_ISR);
3057 +}
3058 +
3059 +/**
3060 + * qbman_swp_interrupt_clear_status()
3061 + * @p: the given software portal
3062 + * @mask: The mask to clear in SWP_ISR register
3063 + */
3064 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask)
3065 +{
3066 + qbman_write_register(p, QBMAN_CINH_SWP_ISR, mask);
3067 +}
3068 +
3069 +/**
3070 + * qbman_swp_interrupt_get_trigger() - read interrupt enable register
3071 + * @p: the given software portal
3072 + *
3073 + * Return the value in the SWP_IER register.
3074 + */
3075 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
3076 +{
3077 + return qbman_read_register(p, QBMAN_CINH_SWP_IER);
3078 +}
3079 +
3080 +/**
3081 + * qbman_swp_interrupt_set_trigger() - enable interrupts for a swp
3082 + * @p: the given software portal
3083 + * @mask: The mask of bits to enable in SWP_IER
3084 + */
3085 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask)
3086 +{
3087 + qbman_write_register(p, QBMAN_CINH_SWP_IER, mask);
3088 +}
3089 +
3090 +/**
3091 + * qbman_swp_interrupt_get_inhibit() - read interrupt mask register
3092 + * @p: the given software portal object
3093 + *
3094 + * Return the value in the SWP_IIR register.
3095 + */
3096 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
3097 +{
3098 + return qbman_read_register(p, QBMAN_CINH_SWP_IIR);
3099 +}
3100 +
3101 +/**
3102 + * qbman_swp_interrupt_set_inhibit() - write interrupt mask register
3103 + * @p: the given software portal object
3104 + * @mask: The mask to set in SWP_IIR register
3105 + */
3106 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
3107 +{
3108 + qbman_write_register(p, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
3109 +}
3110 +
3111 +/*
3112 + * Different management commands all use this common base layer of code to issue
3113 + * commands and poll for results.
3114 + */
3115 +
3116 +/*
3117 + * Returns a pointer to where the caller should fill in their management command
3118 + * (caller should ignore the verb byte)
3119 + */
3120 +void *qbman_swp_mc_start(struct qbman_swp *p)
3121 +{
3122 + return qbman_get_cmd(p, QBMAN_CENA_SWP_CR);
3123 +}
3124 +
3125 +/*
3126 + * Commits merges in the caller-supplied command verb (which should not include
3127 + * the valid-bit) and submits the command to hardware
3128 + */
3129 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb)
3130 +{
3131 + u8 *v = cmd;
3132 +
3133 + dma_wmb();
3134 + *v = cmd_verb | p->mc.valid_bit;
3135 + dccvac(cmd);
3136 +}
3137 +
3138 +/*
3139 + * Checks for a completed response (returns non-NULL if only if the response
3140 + * is complete).
3141 + */
3142 +void *qbman_swp_mc_result(struct qbman_swp *p)
3143 +{
3144 + u32 *ret, verb;
3145 +
3146 + qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3147 + ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3148 +
3149 + /* Remove the valid-bit - command completed if the rest is non-zero */
3150 + verb = ret[0] & ~QB_VALID_BIT;
3151 + if (!verb)
3152 + return NULL;
3153 + p->mc.valid_bit ^= QB_VALID_BIT;
3154 + return ret;
3155 +}
3156 +
3157 +#define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0
3158 +enum qb_enqueue_commands {
3159 + enqueue_empty = 0,
3160 + enqueue_response_always = 1,
3161 + enqueue_rejects_to_fq = 2
3162 +};
3163 +
3164 +#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
3165 +#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
3166 +#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
3167 +
3168 +/**
3169 + * qbman_eq_desc_clear() - Clear the contents of a descriptor to
3170 + * default/starting state.
3171 + */
3172 +void qbman_eq_desc_clear(struct qbman_eq_desc *d)
3173 +{
3174 + memset(d, 0, sizeof(*d));
3175 +}
3176 +
3177 +/**
3178 + * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp
3179 + * @d: the enqueue descriptor.
3180 + * @response_success: 1 = enqueue with response always; 0 = enqueue with
3181 + * rejections returned on a FQ.
3182 + */
3183 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
3184 +{
3185 + d->verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
3186 + if (respond_success)
3187 + d->verb |= enqueue_response_always;
3188 + else
3189 + d->verb |= enqueue_rejects_to_fq;
3190 +}
3191 +
3192 +/*
3193 + * Exactly one of the following descriptor "targets" should be set. (Calling any
3194 + * one of these will replace the effect of any prior call to one of these.)
3195 + * -enqueue to a frame queue
3196 + * -enqueue to a queuing destination
3197 + */
3198 +
3199 +/**
3200 + * qbman_eq_desc_set_fq() - set the FQ for the enqueue command
3201 + * @d: the enqueue descriptor
3202 + * @fqid: the id of the frame queue to be enqueued
3203 + */
3204 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid)
3205 +{
3206 + d->verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
3207 + d->tgtid = cpu_to_le32(fqid);
3208 +}
3209 +
3210 +/**
3211 + * qbman_eq_desc_set_qd() - Set Queuing Destination for the enqueue command
3212 + * @d: the enqueue descriptor
3213 + * @qdid: the id of the queuing destination to be enqueued
3214 + * @qd_bin: the queuing destination bin
3215 + * @qd_prio: the queuing destination priority
3216 + */
3217 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
3218 + u32 qd_bin, u32 qd_prio)
3219 +{
3220 + d->verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
3221 + d->tgtid = cpu_to_le32(qdid);
3222 + d->qdbin = cpu_to_le16(qd_bin);
3223 + d->qpri = qd_prio;
3224 +}
3225 +
3226 +#define EQAR_IDX(eqar) ((eqar) & 0x7)
3227 +#define EQAR_VB(eqar) ((eqar) & 0x80)
3228 +#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
3229 +
3230 +/**
3231 + * qbman_swp_enqueue() - Issue an enqueue command
3232 + * @s: the software portal used for enqueue
3233 + * @d: the enqueue descriptor
3234 + * @fd: the frame descriptor to be enqueued
3235 + *
3236 + * Please note that 'fd' should only be NULL if the "action" of the
3237 + * descriptor is "orp_hole" or "orp_nesn".
3238 + *
3239 + * Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
3240 + */
3241 +int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
3242 + const struct dpaa2_fd *fd)
3243 +{
3244 + struct qbman_eq_desc *p;
3245 + u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
3246 +
3247 + if (!EQAR_SUCCESS(eqar))
3248 + return -EBUSY;
3249 +
3250 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
3251 + memcpy(&p->dca, &d->dca, 31);
3252 + memcpy(&p->fd, fd, sizeof(*fd));
3253 +
3254 + /* Set the verb byte, have to substitute in the valid-bit */
3255 + dma_wmb();
3256 + p->verb = d->verb | EQAR_VB(eqar);
3257 + dccvac(p);
3258 +
3259 + return 0;
3260 +}
3261 +
3262 +/* Static (push) dequeue */
3263 +
3264 +/**
3265 + * qbman_swp_push_get() - Get the push dequeue setup
3266 + * @p: the software portal object
3267 + * @channel_idx: the channel index to query
3268 + * @enabled: returned boolean to show whether the push dequeue is enabled
3269 + * for the given channel
3270 + */
3271 +void qbman_swp_push_get(struct qbman_swp *s, u8 channel_idx, int *enabled)
3272 +{
3273 + u16 src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3274 +
3275 + WARN_ON(channel_idx > 15);
3276 + *enabled = src | (1 << channel_idx);
3277 +}
3278 +
3279 +/**
3280 + * qbman_swp_push_set() - Enable or disable push dequeue
3281 + * @p: the software portal object
3282 + * @channel_idx: the channel index (0 to 15)
3283 + * @enable: enable or disable push dequeue
3284 + */
3285 +void qbman_swp_push_set(struct qbman_swp *s, u8 channel_idx, int enable)
3286 +{
3287 + u16 dqsrc;
3288 +
3289 + WARN_ON(channel_idx > 15);
3290 + if (enable)
3291 + s->sdq |= 1 << channel_idx;
3292 + else
3293 + s->sdq &= ~(1 << channel_idx);
3294 +
3295 + /* Read make the complete src map. If no channels are enabled
3296 + * the SDQCR must be 0 or else QMan will assert errors
3297 + */
3298 + dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3299 + if (dqsrc != 0)
3300 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, s->sdq);
3301 + else
3302 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, 0);
3303 +}
3304 +
3305 +#define QB_VDQCR_VERB_DCT_SHIFT 0
3306 +#define QB_VDQCR_VERB_DT_SHIFT 2
3307 +#define QB_VDQCR_VERB_RLS_SHIFT 4
3308 +#define QB_VDQCR_VERB_WAE_SHIFT 5
3309 +
3310 +enum qb_pull_dt_e {
3311 + qb_pull_dt_channel,
3312 + qb_pull_dt_workqueue,
3313 + qb_pull_dt_framequeue
3314 +};
3315 +
3316 +/**
3317 + * qbman_pull_desc_clear() - Clear the contents of a descriptor to
3318 + * default/starting state
3319 + * @d: the pull dequeue descriptor to be cleared
3320 + */
3321 +void qbman_pull_desc_clear(struct qbman_pull_desc *d)
3322 +{
3323 + memset(d, 0, sizeof(*d));
3324 +}
3325 +
3326 +/**
3327 + * qbman_pull_desc_set_storage()- Set the pull dequeue storage
3328 + * @d: the pull dequeue descriptor to be set
3329 + * @storage: the pointer of the memory to store the dequeue result
3330 + * @storage_phys: the physical address of the storage memory
3331 + * @stash: to indicate whether write allocate is enabled
3332 + *
3333 + * If not called, or if called with 'storage' as NULL, the result pull dequeues
3334 + * will produce results to DQRR. If 'storage' is non-NULL, then results are
3335 + * produced to the given memory location (using the DMA address which
3336 + * the caller provides in 'storage_phys'), and 'stash' controls whether or not
3337 + * those writes to main-memory express a cache-warming attribute.
3338 + */
3339 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
3340 + struct dpaa2_dq *storage,
3341 + dma_addr_t storage_phys,
3342 + int stash)
3343 +{
3344 + /* save the virtual address */
3345 + d->rsp_addr_virt = (u64)storage;
3346 +
3347 + if (!storage) {
3348 + d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
3349 + return;
3350 + }
3351 + d->verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
3352 + if (stash)
3353 + d->verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
3354 + else
3355 + d->verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
3356 +
3357 + d->rsp_addr = cpu_to_le64(storage_phys);
3358 +}
3359 +
3360 +/**
3361 + * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued
3362 + * @d: the pull dequeue descriptor to be set
3363 + * @numframes: number of frames to be set, must be between 1 and 16, inclusive
3364 + */
3365 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes)
3366 +{
3367 + d->numf = numframes - 1;
3368 +}
3369 +
3370 +void qbman_pull_desc_set_token(struct qbman_pull_desc *d, u8 token)
3371 +{
3372 + d->tok = token;
3373 +}
3374 +
3375 +/*
3376 + * Exactly one of the following descriptor "actions" should be set. (Calling any
3377 + * one of these will replace the effect of any prior call to one of these.)
3378 + * - pull dequeue from the given frame queue (FQ)
3379 + * - pull dequeue from any FQ in the given work queue (WQ)
3380 + * - pull dequeue from any FQ in any WQ in the given channel
3381 + */
3382 +
3383 +/**
3384 + * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues
3385 + * @fqid: the frame queue index of the given FQ
3386 + */
3387 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid)
3388 +{
3389 + d->verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
3390 + d->verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
3391 + d->dq_src = cpu_to_le32(fqid);
3392 +}
3393 +
3394 +/**
3395 + * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues
3396 + * @wqid: composed of channel id and wqid within the channel
3397 + * @dct: the dequeue command type
3398 + */
3399 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
3400 + enum qbman_pull_type_e dct)
3401 +{
3402 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3403 + d->verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
3404 + d->dq_src = cpu_to_le32(wqid);
3405 +}
3406 +
3407 +/**
3408 + * qbman_pull_desc_set_channel() - Set channelid from which the dequeue command
3409 + * dequeues
3410 + * @chid: the channel id to be dequeued
3411 + * @dct: the dequeue command type
3412 + */
3413 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
3414 + enum qbman_pull_type_e dct)
3415 +{
3416 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3417 + d->verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
3418 + d->dq_src = cpu_to_le32(chid);
3419 +}
3420 +
3421 +/**
3422 + * qbman_swp_pull() - Issue the pull dequeue command
3423 + * @s: the software portal object
3424 + * @d: the software portal descriptor which has been configured with
3425 + * the set of qbman_pull_desc_set_*() calls
3426 + *
3427 + * Return 0 for success, and -EBUSY if the software portal is not ready
3428 + * to do pull dequeue.
3429 + */
3430 +int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
3431 +{
3432 + struct qbman_pull_desc *p;
3433 +
3434 + if (!atomic_dec_and_test(&s->vdq.available)) {
3435 + atomic_inc(&s->vdq.available);
3436 + return -EBUSY;
3437 + }
3438 + s->vdq.storage = (void *)d->rsp_addr_virt;
3439 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
3440 + p->numf = d->numf;
3441 + p->tok = QMAN_DQ_TOKEN_VALID;
3442 + p->dq_src = d->dq_src;
3443 + p->rsp_addr = d->rsp_addr;
3444 + p->rsp_addr_virt = d->rsp_addr_virt;
3445 + dma_wmb();
3446 +
3447 + /* Set the verb byte, have to substitute in the valid-bit */
3448 + p->verb = d->verb | s->vdq.valid_bit;
3449 + s->vdq.valid_bit ^= QB_VALID_BIT;
3450 + dccvac(p);
3451 +
3452 + return 0;
3453 +}
3454 +
3455 +#define QMAN_DQRR_PI_MASK 0xf
3456 +
3457 +/**
3458 + * qbman_swp_dqrr_next() - Get an valid DQRR entry
3459 + * @s: the software portal object
3460 + *
3461 + * Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry
3462 + * only once, so repeated calls can return a sequence of DQRR entries, without
3463 + * requiring they be consumed immediately or in any particular order.
3464 + */
3465 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
3466 +{
3467 + u32 verb;
3468 + u32 response_verb;
3469 + u32 flags;
3470 + struct dpaa2_dq *p;
3471 +
3472 + /* Before using valid-bit to detect if something is there, we have to
3473 + * handle the case of the DQRR reset bug...
3474 + */
3475 + if (unlikely(s->dqrr.reset_bug)) {
3476 + /*
3477 + * We pick up new entries by cache-inhibited producer index,
3478 + * which means that a non-coherent mapping would require us to
3479 + * invalidate and read *only* once that PI has indicated that
3480 + * there's an entry here. The first trip around the DQRR ring
3481 + * will be much less efficient than all subsequent trips around
3482 + * it...
3483 + */
3484 + u8 pi = qbman_read_register(s, QBMAN_CINH_SWP_DQPI) &
3485 + QMAN_DQRR_PI_MASK;
3486 +
3487 + /* there are new entries if pi != next_idx */
3488 + if (pi == s->dqrr.next_idx)
3489 + return NULL;
3490 +
3491 + /*
3492 + * if next_idx is/was the last ring index, and 'pi' is
3493 + * different, we can disable the workaround as all the ring
3494 + * entries have now been DMA'd to so valid-bit checking is
3495 + * repaired. Note: this logic needs to be based on next_idx
3496 + * (which increments one at a time), rather than on pi (which
3497 + * can burst and wrap-around between our snapshots of it).
3498 + */
3499 + if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
3500 + pr_debug("next_idx=%d, pi=%d, clear reset bug\n",
3501 + s->dqrr.next_idx, pi);
3502 + s->dqrr.reset_bug = 0;
3503 + }
3504 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3505 + }
3506 +
3507 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3508 + verb = p->dq.verb;
3509 +
3510 + /*
3511 + * If the valid-bit isn't of the expected polarity, nothing there. Note,
3512 + * in the DQRR reset bug workaround, we shouldn't need to skip these
3513 + * check, because we've already determined that a new entry is available
3514 + * and we've invalidated the cacheline before reading it, so the
3515 + * valid-bit behaviour is repaired and should tell us what we already
3516 + * knew from reading PI.
3517 + */
3518 + if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
3519 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3520 + return NULL;
3521 + }
3522 + /*
3523 + * There's something there. Move "next_idx" attention to the next ring
3524 + * entry (and prefetch it) before returning what we found.
3525 + */
3526 + s->dqrr.next_idx++;
3527 + s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */
3528 + if (!s->dqrr.next_idx)
3529 + s->dqrr.valid_bit ^= QB_VALID_BIT;
3530 +
3531 + /*
3532 + * If this is the final response to a volatile dequeue command
3533 + * indicate that the vdq is available
3534 + */
3535 + flags = p->dq.stat;
3536 + response_verb = verb & QBMAN_RESULT_MASK;
3537 + if ((response_verb == QBMAN_RESULT_DQ) &&
3538 + (flags & DPAA2_DQ_STAT_VOLATILE) &&
3539 + (flags & DPAA2_DQ_STAT_EXPIRED))
3540 + atomic_inc(&s->vdq.available);
3541 +
3542 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3543 +
3544 + return p;
3545 +}
3546 +
3547 +/**
3548 + * qbman_swp_dqrr_consume() - Consume DQRR entries previously returned from
3549 + * qbman_swp_dqrr_next().
3550 + * @s: the software portal object
3551 + * @dq: the DQRR entry to be consumed
3552 + */
3553 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq)
3554 +{
3555 + qbman_write_register(s, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
3556 +}
3557 +
3558 +/**
3559 + * qbman_result_has_new_result() - Check and get the dequeue response from the
3560 + * dq storage memory set in pull dequeue command
3561 + * @s: the software portal object
3562 + * @dq: the dequeue result read from the memory
3563 + *
3564 + * Return 1 for getting a valid dequeue result, or 0 for not getting a valid
3565 + * dequeue result.
3566 + *
3567 + * Only used for user-provided storage of dequeue results, not DQRR. For
3568 + * efficiency purposes, the driver will perform any required endianness
3569 + * conversion to ensure that the user's dequeue result storage is in host-endian
3570 + * format. As such, once the user has called qbman_result_has_new_result() and
3571 + * been returned a valid dequeue result, they should not call it again on
3572 + * the same memory location (except of course if another dequeue command has
3573 + * been executed to produce a new result to that location).
3574 + */
3575 +int qbman_result_has_new_result(struct qbman_swp *s, const struct dpaa2_dq *dq)
3576 +{
3577 + if (dq->dq.tok != QMAN_DQ_TOKEN_VALID)
3578 + return 0;
3579 +
3580 + /*
3581 + * Set token to be 0 so we will detect change back to 1
3582 + * next time the looping is traversed. Const is cast away here
3583 + * as we want users to treat the dequeue responses as read only.
3584 + */
3585 + ((struct dpaa2_dq *)dq)->dq.tok = 0;
3586 +
3587 + /*
3588 + * Determine whether VDQCR is available based on whether the
3589 + * current result is sitting in the first storage location of
3590 + * the busy command.
3591 + */
3592 + if (s->vdq.storage == dq) {
3593 + s->vdq.storage = NULL;
3594 + atomic_inc(&s->vdq.available);
3595 + }
3596 +
3597 + return 1;
3598 +}
3599 +
3600 +/**
3601 + * qbman_release_desc_clear() - Clear the contents of a descriptor to
3602 + * default/starting state.
3603 + */
3604 +void qbman_release_desc_clear(struct qbman_release_desc *d)
3605 +{
3606 + memset(d, 0, sizeof(*d));
3607 + d->verb = 1 << 5; /* Release Command Valid */
3608 +}
3609 +
3610 +/**
3611 + * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to
3612 + */
3613 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid)
3614 +{
3615 + d->bpid = cpu_to_le16(bpid);
3616 +}
3617 +
3618 +/**
3619 + * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI
3620 + * interrupt source should be asserted after the release command is completed.
3621 + */
3622 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
3623 +{
3624 + if (enable)
3625 + d->verb |= 1 << 6;
3626 + else
3627 + d->verb &= ~(1 << 6);
3628 +}
3629 +
3630 +#define RAR_IDX(rar) ((rar) & 0x7)
3631 +#define RAR_VB(rar) ((rar) & 0x80)
3632 +#define RAR_SUCCESS(rar) ((rar) & 0x100)
3633 +
3634 +/**
3635 + * qbman_swp_release() - Issue a buffer release command
3636 + * @s: the software portal object
3637 + * @d: the release descriptor
3638 + * @buffers: a pointer pointing to the buffer address to be released
3639 + * @num_buffers: number of buffers to be released, must be less than 8
3640 + *
3641 + * Return 0 for success, -EBUSY if the release command ring is not ready.
3642 + */
3643 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
3644 + const u64 *buffers, unsigned int num_buffers)
3645 +{
3646 + int i;
3647 + struct qbman_release_desc *p;
3648 + u32 rar;
3649 +
3650 + if (!num_buffers || (num_buffers > 7))
3651 + return -EINVAL;
3652 +
3653 + rar = qbman_read_register(s, QBMAN_CINH_SWP_RAR);
3654 + if (!RAR_SUCCESS(rar))
3655 + return -EBUSY;
3656 +
3657 + /* Start the release command */
3658 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
3659 + /* Copy the caller's buffer pointers to the command */
3660 + for (i = 0; i < num_buffers; i++)
3661 + p->buf[i] = cpu_to_le64(buffers[i]);
3662 + p->bpid = d->bpid;
3663 +
3664 + /*
3665 + * Set the verb byte, have to substitute in the valid-bit and the number
3666 + * of buffers.
3667 + */
3668 + dma_wmb();
3669 + p->verb = d->verb | RAR_VB(rar) | num_buffers;
3670 + dccvac(p);
3671 +
3672 + return 0;
3673 +}
3674 +
3675 +struct qbman_acquire_desc {
3676 + u8 verb;
3677 + u8 reserved;
3678 + u16 bpid;
3679 + u8 num;
3680 + u8 reserved2[59];
3681 +};
3682 +
3683 +struct qbman_acquire_rslt {
3684 + u8 verb;
3685 + u8 rslt;
3686 + u16 reserved;
3687 + u8 num;
3688 + u8 reserved2[3];
3689 + u64 buf[7];
3690 +};
3691 +
3692 +/**
3693 + * qbman_swp_acquire() - Issue a buffer acquire command
3694 + * @s: the software portal object
3695 + * @bpid: the buffer pool index
3696 + * @buffers: a pointer pointing to the acquired buffer addresses
3697 + * @num_buffers: number of buffers to be acquired, must be less than 8
3698 + *
3699 + * Return 0 for success, or negative error code if the acquire command
3700 + * fails.
3701 + */
3702 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
3703 + unsigned int num_buffers)
3704 +{
3705 + struct qbman_acquire_desc *p;
3706 + struct qbman_acquire_rslt *r;
3707 + int i;
3708 +
3709 + if (!num_buffers || (num_buffers > 7))
3710 + return -EINVAL;
3711 +
3712 + /* Start the management command */
3713 + p = qbman_swp_mc_start(s);
3714 +
3715 + if (!p)
3716 + return -EBUSY;
3717 +
3718 + /* Encode the caller-provided attributes */
3719 + p->bpid = cpu_to_le16(bpid);
3720 + p->num = num_buffers;
3721 +
3722 + /* Complete the management command */
3723 + r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
3724 + if (unlikely(!r)) {
3725 + pr_err("qbman: acquire from BPID %d failed, no response\n",
3726 + bpid);
3727 + return -EIO;
3728 + }
3729 +
3730 + /* Decode the outcome */
3731 + WARN_ON((r->verb & 0x7f) != QBMAN_MC_ACQUIRE);
3732 +
3733 + /* Determine success or failure */
3734 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3735 + pr_err("qbman: acquire from BPID 0x%x failed, code=0x%02x\n",
3736 + bpid, r->rslt);
3737 + return -EIO;
3738 + }
3739 +
3740 + WARN_ON(r->num > num_buffers);
3741 +
3742 + /* Copy the acquired buffers to the caller's array */
3743 + for (i = 0; i < r->num; i++)
3744 + buffers[i] = le64_to_cpu(r->buf[i]);
3745 +
3746 + return (int)r->num;
3747 +}
3748 +
3749 +struct qbman_alt_fq_state_desc {
3750 + u8 verb;
3751 + u8 reserved[3];
3752 + u32 fqid;
3753 + u8 reserved2[56];
3754 +};
3755 +
3756 +struct qbman_alt_fq_state_rslt {
3757 + u8 verb;
3758 + u8 rslt;
3759 + u8 reserved[62];
3760 +};
3761 +
3762 +#define ALT_FQ_FQID_MASK 0x00FFFFFF
3763 +
3764 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
3765 + u8 alt_fq_verb)
3766 +{
3767 + struct qbman_alt_fq_state_desc *p;
3768 + struct qbman_alt_fq_state_rslt *r;
3769 +
3770 + /* Start the management command */
3771 + p = qbman_swp_mc_start(s);
3772 + if (!p)
3773 + return -EBUSY;
3774 +
3775 + p->fqid = cpu_to_le32(fqid) & ALT_FQ_FQID_MASK;
3776 +
3777 + /* Complete the management command */
3778 + r = qbman_swp_mc_complete(s, p, alt_fq_verb);
3779 + if (unlikely(!r)) {
3780 + pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
3781 + alt_fq_verb);
3782 + return -EIO;
3783 + }
3784 +
3785 + /* Decode the outcome */
3786 + WARN_ON((r->verb & QBMAN_RESULT_MASK) != alt_fq_verb);
3787 +
3788 + /* Determine success or failure */
3789 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3790 + pr_err("qbman: ALT FQID %d failed: verb = 0x%08x code = 0x%02x\n",
3791 + fqid, r->verb, r->rslt);
3792 + return -EIO;
3793 + }
3794 +
3795 + return 0;
3796 +}
3797 +
3798 +struct qbman_cdan_ctrl_desc {
3799 + u8 verb;
3800 + u8 reserved;
3801 + u16 ch;
3802 + u8 we;
3803 + u8 ctrl;
3804 + u16 reserved2;
3805 + u64 cdan_ctx;
3806 + u8 reserved3[48];
3807 +
3808 +};
3809 +
3810 +struct qbman_cdan_ctrl_rslt {
3811 + u8 verb;
3812 + u8 rslt;
3813 + u16 ch;
3814 + u8 reserved[60];
3815 +};
3816 +
3817 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
3818 + u8 we_mask, u8 cdan_en,
3819 + u64 ctx)
3820 +{
3821 + struct qbman_cdan_ctrl_desc *p = NULL;
3822 + struct qbman_cdan_ctrl_rslt *r = NULL;
3823 +
3824 + /* Start the management command */
3825 + p = qbman_swp_mc_start(s);
3826 + if (!p)
3827 + return -EBUSY;
3828 +
3829 + /* Encode the caller-provided attributes */
3830 + p->ch = cpu_to_le16(channelid);
3831 + p->we = we_mask;
3832 + if (cdan_en)
3833 + p->ctrl = 1;
3834 + else
3835 + p->ctrl = 0;
3836 + p->cdan_ctx = cpu_to_le64(ctx);
3837 +
3838 + /* Complete the management command */
3839 + r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
3840 + if (unlikely(!r)) {
3841 + pr_err("qbman: wqchan config failed, no response\n");
3842 + return -EIO;
3843 + }
3844 +
3845 + WARN_ON((r->verb & 0x7f) != QBMAN_WQCHAN_CONFIGURE);
3846 +
3847 + /* Determine success or failure */
3848 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3849 + pr_err("qbman: CDAN cQID %d failed: code = 0x%02x\n",
3850 + channelid, r->rslt);
3851 + return -EIO;
3852 + }
3853 +
3854 + return 0;
3855 +}
3856 --- /dev/null
3857 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
3858 @@ -0,0 +1,662 @@
3859 +/*
3860 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3861 + * Copyright 2016 NXP
3862 + *
3863 + * Redistribution and use in source and binary forms, with or without
3864 + * modification, are permitted provided that the following conditions are met:
3865 + * * Redistributions of source code must retain the above copyright
3866 + * notice, this list of conditions and the following disclaimer.
3867 + * * Redistributions in binary form must reproduce the above copyright
3868 + * notice, this list of conditions and the following disclaimer in the
3869 + * documentation and/or other materials provided with the distribution.
3870 + * * Neither the name of Freescale Semiconductor nor the
3871 + * names of its contributors may be used to endorse or promote products
3872 + * derived from this software without specific prior written permission.
3873 + *
3874 + * ALTERNATIVELY, this software may be distributed under the terms of the
3875 + * GNU General Public License ("GPL") as published by the Free Software
3876 + * Foundation, either version 2 of that License or (at your option) any
3877 + * later version.
3878 + *
3879 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
3880 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
3881 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
3882 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
3883 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3884 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3885 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3886 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3887 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
3888 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3889 + */
3890 +#ifndef __FSL_QBMAN_PORTAL_H
3891 +#define __FSL_QBMAN_PORTAL_H
3892 +
3893 +#include "qbman_private.h"
3894 +#include "../../include/dpaa2-fd.h"
3895 +
3896 +struct dpaa2_dq;
3897 +struct qbman_swp;
3898 +
3899 +/* qbman software portal descriptor structure */
3900 +struct qbman_swp_desc {
3901 + void *cena_bar; /* Cache-enabled portal base address */
3902 + void *cinh_bar; /* Cache-inhibited portal base address */
3903 + u32 qman_version;
3904 +};
3905 +
3906 +#define QBMAN_SWP_INTERRUPT_EQRI 0x01
3907 +#define QBMAN_SWP_INTERRUPT_EQDI 0x02
3908 +#define QBMAN_SWP_INTERRUPT_DQRI 0x04
3909 +#define QBMAN_SWP_INTERRUPT_RCRI 0x08
3910 +#define QBMAN_SWP_INTERRUPT_RCDI 0x10
3911 +#define QBMAN_SWP_INTERRUPT_VDCI 0x20
3912 +
3913 +/* the structure for pull dequeue descriptor */
3914 +struct qbman_pull_desc {
3915 + u8 verb;
3916 + u8 numf;
3917 + u8 tok;
3918 + u8 reserved;
3919 + u32 dq_src;
3920 + u64 rsp_addr;
3921 + u64 rsp_addr_virt;
3922 + u8 padding[40];
3923 +};
3924 +
3925 +enum qbman_pull_type_e {
3926 + /* dequeue with priority precedence, respect intra-class scheduling */
3927 + qbman_pull_type_prio = 1,
3928 + /* dequeue with active FQ precedence, respect ICS */
3929 + qbman_pull_type_active,
3930 + /* dequeue with active FQ precedence, no ICS */
3931 + qbman_pull_type_active_noics
3932 +};
3933 +
3934 +/* Definitions for parsing dequeue entries */
3935 +#define QBMAN_RESULT_MASK 0x7f
3936 +#define QBMAN_RESULT_DQ 0x60
3937 +#define QBMAN_RESULT_FQRN 0x21
3938 +#define QBMAN_RESULT_FQRNI 0x22
3939 +#define QBMAN_RESULT_FQPN 0x24
3940 +#define QBMAN_RESULT_FQDAN 0x25
3941 +#define QBMAN_RESULT_CDAN 0x26
3942 +#define QBMAN_RESULT_CSCN_MEM 0x27
3943 +#define QBMAN_RESULT_CGCU 0x28
3944 +#define QBMAN_RESULT_BPSCN 0x29
3945 +#define QBMAN_RESULT_CSCN_WQ 0x2a
3946 +
3947 +/* QBMan FQ management command codes */
3948 +#define QBMAN_FQ_SCHEDULE 0x48
3949 +#define QBMAN_FQ_FORCE 0x49
3950 +#define QBMAN_FQ_XON 0x4d
3951 +#define QBMAN_FQ_XOFF 0x4e
3952 +
3953 +/* structure of enqueue descriptor */
3954 +struct qbman_eq_desc {
3955 + u8 verb;
3956 + u8 dca;
3957 + u16 seqnum;
3958 + u16 orpid;
3959 + u16 reserved1;
3960 + u32 tgtid;
3961 + u32 tag;
3962 + u16 qdbin;
3963 + u8 qpri;
3964 + u8 reserved[3];
3965 + u8 wae;
3966 + u8 rspid;
3967 + u64 rsp_addr;
3968 + u8 fd[32];
3969 +};
3970 +
3971 +/* buffer release descriptor */
3972 +struct qbman_release_desc {
3973 + u8 verb;
3974 + u8 reserved;
3975 + u16 bpid;
3976 + u32 reserved2;
3977 + u64 buf[7];
3978 +};
3979 +
3980 +/* Management command result codes */
3981 +#define QBMAN_MC_RSLT_OK 0xf0
3982 +
3983 +#define CODE_CDAN_WE_EN 0x1
3984 +#define CODE_CDAN_WE_CTX 0x4
3985 +
3986 +/* portal data structure */
3987 +struct qbman_swp {
3988 + const struct qbman_swp_desc *desc;
3989 + void __iomem *addr_cena;
3990 + void __iomem *addr_cinh;
3991 +
3992 + /* Management commands */
3993 + struct {
3994 + u32 valid_bit; /* 0x00 or 0x80 */
3995 + } mc;
3996 +
3997 + /* Push dequeues */
3998 + u32 sdq;
3999 +
4000 + /* Volatile dequeues */
4001 + struct {
4002 + atomic_t available; /* indicates if a command can be sent */
4003 + u32 valid_bit; /* 0x00 or 0x80 */
4004 + struct dpaa2_dq *storage; /* NULL if DQRR */
4005 + } vdq;
4006 +
4007 + /* DQRR */
4008 + struct {
4009 + u32 next_idx;
4010 + u32 valid_bit;
4011 + u8 dqrr_size;
4012 + int reset_bug; /* indicates dqrr reset workaround is needed */
4013 + } dqrr;
4014 +};
4015 +
4016 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
4017 +void qbman_swp_finish(struct qbman_swp *p);
4018 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p);
4019 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask);
4020 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p);
4021 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask);
4022 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p);
4023 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit);
4024 +
4025 +void qbman_swp_push_get(struct qbman_swp *p, u8 channel_idx, int *enabled);
4026 +void qbman_swp_push_set(struct qbman_swp *p, u8 channel_idx, int enable);
4027 +
4028 +void qbman_pull_desc_clear(struct qbman_pull_desc *d);
4029 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
4030 + struct dpaa2_dq *storage,
4031 + dma_addr_t storage_phys,
4032 + int stash);
4033 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes);
4034 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid);
4035 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
4036 + enum qbman_pull_type_e dct);
4037 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
4038 + enum qbman_pull_type_e dct);
4039 +
4040 +int qbman_swp_pull(struct qbman_swp *p, struct qbman_pull_desc *d);
4041 +
4042 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s);
4043 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq);
4044 +
4045 +int qbman_result_has_new_result(struct qbman_swp *p, const struct dpaa2_dq *dq);
4046 +
4047 +void qbman_eq_desc_clear(struct qbman_eq_desc *d);
4048 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
4049 +void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
4050 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
4051 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
4052 + u32 qd_bin, u32 qd_prio);
4053 +
4054 +int qbman_swp_enqueue(struct qbman_swp *p, const struct qbman_eq_desc *d,
4055 + const struct dpaa2_fd *fd);
4056 +
4057 +void qbman_release_desc_clear(struct qbman_release_desc *d);
4058 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid);
4059 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
4060 +
4061 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
4062 + const u64 *buffers, unsigned int num_buffers);
4063 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
4064 + unsigned int num_buffers);
4065 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
4066 + u8 alt_fq_verb);
4067 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
4068 + u8 we_mask, u8 cdan_en,
4069 + u64 ctx);
4070 +
4071 +void *qbman_swp_mc_start(struct qbman_swp *p);
4072 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb);
4073 +void *qbman_swp_mc_result(struct qbman_swp *p);
4074 +
4075 +/**
4076 + * qbman_result_is_DQ() - check if the dequeue result is a dequeue response
4077 + * @dq: the dequeue result to be checked
4078 + *
4079 + * DQRR entries may contain non-dequeue results, ie. notifications
4080 + */
4081 +static inline int qbman_result_is_DQ(const struct dpaa2_dq *dq)
4082 +{
4083 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_DQ);
4084 +}
4085 +
4086 +/**
4087 + * qbman_result_is_SCN() - Check the dequeue result is notification or not
4088 + * @dq: the dequeue result to be checked
4089 + *
4090 + */
4091 +static inline int qbman_result_is_SCN(const struct dpaa2_dq *dq)
4092 +{
4093 + return !qbman_result_is_DQ(dq);
4094 +}
4095 +
4096 +/* FQ Data Availability */
4097 +static inline int qbman_result_is_FQDAN(const struct dpaa2_dq *dq)
4098 +{
4099 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQDAN);
4100 +}
4101 +
4102 +/* Channel Data Availability */
4103 +static inline int qbman_result_is_CDAN(const struct dpaa2_dq *dq)
4104 +{
4105 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CDAN);
4106 +}
4107 +
4108 +/* Congestion State Change */
4109 +static inline int qbman_result_is_CSCN(const struct dpaa2_dq *dq)
4110 +{
4111 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CSCN_WQ);
4112 +}
4113 +
4114 +/* Buffer Pool State Change */
4115 +static inline int qbman_result_is_BPSCN(const struct dpaa2_dq *dq)
4116 +{
4117 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_BPSCN);
4118 +}
4119 +
4120 +/* Congestion Group Count Update */
4121 +static inline int qbman_result_is_CGCU(const struct dpaa2_dq *dq)
4122 +{
4123 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CGCU);
4124 +}
4125 +
4126 +/* Retirement */
4127 +static inline int qbman_result_is_FQRN(const struct dpaa2_dq *dq)
4128 +{
4129 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRN);
4130 +}
4131 +
4132 +/* Retirement Immediate */
4133 +static inline int qbman_result_is_FQRNI(const struct dpaa2_dq *dq)
4134 +{
4135 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRNI);
4136 +}
4137 +
4138 + /* Park */
4139 +static inline int qbman_result_is_FQPN(const struct dpaa2_dq *dq)
4140 +{
4141 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQPN);
4142 +}
4143 +
4144 +/**
4145 + * qbman_result_SCN_state() - Get the state field in State-change notification
4146 + */
4147 +static inline u8 qbman_result_SCN_state(const struct dpaa2_dq *scn)
4148 +{
4149 + return scn->scn.state;
4150 +}
4151 +
4152 +#define SCN_RID_MASK 0x00FFFFFF
4153 +
4154 +/**
4155 + * qbman_result_SCN_rid() - Get the resource id in State-change notification
4156 + */
4157 +static inline u32 qbman_result_SCN_rid(const struct dpaa2_dq *scn)
4158 +{
4159 + return le32_to_cpu(scn->scn.rid_tok) & SCN_RID_MASK;
4160 +}
4161 +
4162 +/**
4163 + * qbman_result_SCN_ctx() - Get the context data in State-change notification
4164 + */
4165 +static inline u64 qbman_result_SCN_ctx(const struct dpaa2_dq *scn)
4166 +{
4167 + return le64_to_cpu(scn->scn.ctx);
4168 +}
4169 +
4170 +/**
4171 + * qbman_swp_fq_schedule() - Move the fq to the scheduled state
4172 + * @s: the software portal object
4173 + * @fqid: the index of frame queue to be scheduled
4174 + *
4175 + * There are a couple of different ways that a FQ can end up parked state,
4176 + * This schedules it.
4177 + *
4178 + * Return 0 for success, or negative error code for failure.
4179 + */
4180 +static inline int qbman_swp_fq_schedule(struct qbman_swp *s, u32 fqid)
4181 +{
4182 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
4183 +}
4184 +
4185 +/**
4186 + * qbman_swp_fq_force() - Force the FQ to fully scheduled state
4187 + * @s: the software portal object
4188 + * @fqid: the index of frame queue to be forced
4189 + *
4190 + * Force eligible will force a tentatively-scheduled FQ to be fully-scheduled
4191 + * and thus be available for selection by any channel-dequeuing behaviour (push
4192 + * or pull). If the FQ is subsequently "dequeued" from the channel and is still
4193 + * empty at the time this happens, the resulting dq_entry will have no FD.
4194 + * (qbman_result_DQ_fd() will return NULL.)
4195 + *
4196 + * Return 0 for success, or negative error code for failure.
4197 + */
4198 +static inline int qbman_swp_fq_force(struct qbman_swp *s, u32 fqid)
4199 +{
4200 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
4201 +}
4202 +
4203 +/**
4204 + * qbman_swp_fq_xon() - sets FQ flow-control to XON
4205 + * @s: the software portal object
4206 + * @fqid: the index of frame queue
4207 + *
4208 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4209 + *
4210 + * Return 0 for success, or negative error code for failure.
4211 + */
4212 +static inline int qbman_swp_fq_xon(struct qbman_swp *s, u32 fqid)
4213 +{
4214 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
4215 +}
4216 +
4217 +/**
4218 + * qbman_swp_fq_xoff() - sets FQ flow-control to XOFF
4219 + * @s: the software portal object
4220 + * @fqid: the index of frame queue
4221 + *
4222 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4223 + * XOFF FQs will remain in the tenatively-scheduled state, even when
4224 + * non-empty, meaning they won't be selected for scheduled dequeuing.
4225 + * If a FQ is changed to XOFF after it had already become truly-scheduled
4226 + * to a channel, and a pull dequeue of that channel occurs that selects
4227 + * that FQ for dequeuing, then the resulting dq_entry will have no FD.
4228 + * (qbman_result_DQ_fd() will return NULL.)
4229 + *
4230 + * Return 0 for success, or negative error code for failure.
4231 + */
4232 +static inline int qbman_swp_fq_xoff(struct qbman_swp *s, u32 fqid)
4233 +{
4234 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
4235 +}
4236 +
4237 +/* If the user has been allocated a channel object that is going to generate
4238 + * CDANs to another channel, then the qbman_swp_CDAN* functions will be
4239 + * necessary.
4240 + *
4241 + * CDAN-enabled channels only generate a single CDAN notification, after which
4242 + * they need to be reenabled before they'll generate another. The idea is
4243 + * that pull dequeuing will occur in reaction to the CDAN, followed by a
4244 + * reenable step. Each function generates a distinct command to hardware, so a
4245 + * combination function is provided if the user wishes to modify the "context"
4246 + * (which shows up in each CDAN message) each time they reenable, as a single
4247 + * command to hardware.
4248 + */
4249 +
4250 +/**
4251 + * qbman_swp_CDAN_set_context() - Set CDAN context
4252 + * @s: the software portal object
4253 + * @channelid: the channel index
4254 + * @ctx: the context to be set in CDAN
4255 + *
4256 + * Return 0 for success, or negative error code for failure.
4257 + */
4258 +static inline int qbman_swp_CDAN_set_context(struct qbman_swp *s, u16 channelid,
4259 + u64 ctx)
4260 +{
4261 + return qbman_swp_CDAN_set(s, channelid,
4262 + CODE_CDAN_WE_CTX,
4263 + 0, ctx);
4264 +}
4265 +
4266 +/**
4267 + * qbman_swp_CDAN_enable() - Enable CDAN for the channel
4268 + * @s: the software portal object
4269 + * @channelid: the index of the channel to generate CDAN
4270 + *
4271 + * Return 0 for success, or negative error code for failure.
4272 + */
4273 +static inline int qbman_swp_CDAN_enable(struct qbman_swp *s, u16 channelid)
4274 +{
4275 + return qbman_swp_CDAN_set(s, channelid,
4276 + CODE_CDAN_WE_EN,
4277 + 1, 0);
4278 +}
4279 +
4280 +/**
4281 + * qbman_swp_CDAN_disable() - disable CDAN for the channel
4282 + * @s: the software portal object
4283 + * @channelid: the index of the channel to generate CDAN
4284 + *
4285 + * Return 0 for success, or negative error code for failure.
4286 + */
4287 +static inline int qbman_swp_CDAN_disable(struct qbman_swp *s, u16 channelid)
4288 +{
4289 + return qbman_swp_CDAN_set(s, channelid,
4290 + CODE_CDAN_WE_EN,
4291 + 0, 0);
4292 +}
4293 +
4294 +/**
4295 + * qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN
4296 + * @s: the software portal object
4297 + * @channelid: the index of the channel to generate CDAN
4298 + * @ctx:i the context set in CDAN
4299 + *
4300 + * Return 0 for success, or negative error code for failure.
4301 + */
4302 +static inline int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s,
4303 + u16 channelid,
4304 + u64 ctx)
4305 +{
4306 + return qbman_swp_CDAN_set(s, channelid,
4307 + CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
4308 + 1, ctx);
4309 +}
4310 +
4311 +/* Wraps up submit + poll-for-result */
4312 +static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
4313 + u8 cmd_verb)
4314 +{
4315 + int loopvar = 1000;
4316 +
4317 + qbman_swp_mc_submit(swp, cmd, cmd_verb);
4318 +
4319 + do {
4320 + cmd = qbman_swp_mc_result(swp);
4321 + } while (!cmd && loopvar--);
4322 +
4323 + WARN_ON(!loopvar);
4324 +
4325 + return cmd;
4326 +}
4327 +
4328 +/* ------------ */
4329 +/* qb_attr_code */
4330 +/* ------------ */
4331 +
4332 +/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
4333 + * is either serving as a configuration command or a query result. The
4334 + * representation is inherently little-endian, as the indexing of the words is
4335 + * itself little-endian in nature and layerscape is little endian for anything
4336 + * that crosses a word boundary too (64-bit fields are the obvious examples).
4337 + */
4338 +struct qb_attr_code {
4339 + unsigned int word; /* which u32[] array member encodes the field */
4340 + unsigned int lsoffset; /* encoding offset from ls-bit */
4341 + unsigned int width; /* encoding width. (bool must be 1.) */
4342 +};
4343 +
4344 +/* Some pre-defined codes */
4345 +extern struct qb_attr_code code_generic_verb;
4346 +extern struct qb_attr_code code_generic_rslt;
4347 +
4348 +/* Macros to define codes */
4349 +#define QB_CODE(a, b, c) { a, b, c}
4350 +#define QB_CODE_NULL \
4351 + QB_CODE((unsigned int)-1, (unsigned int)-1, (unsigned int)-1)
4352 +
4353 +/* Rotate a code "ms", meaning that it moves from less-significant bytes to
4354 + * more-significant, from less-significant words to more-significant, etc. The
4355 + * "ls" version does the inverse, from more-significant towards
4356 + * less-significant.
4357 + */
4358 +static inline void qb_attr_code_rotate_ms(struct qb_attr_code *code,
4359 + unsigned int bits)
4360 +{
4361 + code->lsoffset += bits;
4362 + while (code->lsoffset > 31) {
4363 + code->word++;
4364 + code->lsoffset -= 32;
4365 + }
4366 +}
4367 +
4368 +static inline void qb_attr_code_rotate_ls(struct qb_attr_code *code,
4369 + unsigned int bits)
4370 +{
4371 + /* Don't be fooled, this trick should work because the types are
4372 + * unsigned. So the case that interests the while loop (the rotate has
4373 + * gone too far and the word count needs to compensate for it), is
4374 + * manifested when lsoffset is negative. But that equates to a really
4375 + * large unsigned value, starting with lots of "F"s. As such, we can
4376 + * continue adding 32 back to it until it wraps back round above zero,
4377 + * to a value of 31 or less...
4378 + */
4379 + code->lsoffset -= bits;
4380 + while (code->lsoffset > 31) {
4381 + code->word--;
4382 + code->lsoffset += 32;
4383 + }
4384 +}
4385 +
4386 +/* Implement a loop of code rotations until 'expr' evaluates to FALSE (0). */
4387 +#define qb_attr_code_for_ms(code, bits, expr) \
4388 + for (; expr; qb_attr_code_rotate_ms(code, bits))
4389 +#define qb_attr_code_for_ls(code, bits, expr) \
4390 + for (; expr; qb_attr_code_rotate_ls(code, bits))
4391 +
4392 +static inline void word_copy(void *d, const void *s, unsigned int cnt)
4393 +{
4394 + u32 *dd = d;
4395 + const u32 *ss = s;
4396 +
4397 + while (cnt--)
4398 + *(dd++) = *(ss++);
4399 +}
4400 +
4401 +/*
4402 + * Currently, the CENA support code expects each 32-bit word to be written in
4403 + * host order, and these are converted to hardware (little-endian) order on
4404 + * command submission. However, 64-bit quantities are must be written (and read)
4405 + * as two 32-bit words with the least-significant word first, irrespective of
4406 + * host endianness.
4407 + */
4408 +static inline void u64_to_le32_copy(void *d, const u64 *s,
4409 + unsigned int cnt)
4410 +{
4411 + u32 *dd = d;
4412 + const u32 *ss = (const u32 *)s;
4413 +
4414 + while (cnt--) {
4415 + /*
4416 + * TBD: the toolchain was choking on the use of 64-bit types up
4417 + * until recently so this works entirely with 32-bit variables.
4418 + * When 64-bit types become usable again, investigate better
4419 + * ways of doing this.
4420 + */
4421 +#if defined(__BIG_ENDIAN)
4422 + *(dd++) = ss[1];
4423 + *(dd++) = ss[0];
4424 + ss += 2;
4425 +#else
4426 + *(dd++) = *(ss++);
4427 + *(dd++) = *(ss++);
4428 +#endif
4429 + }
4430 +}
4431 +
4432 +static inline void u64_from_le32_copy(u64 *d, const void *s,
4433 + unsigned int cnt)
4434 +{
4435 + const u32 *ss = s;
4436 + u32 *dd = (u32 *)d;
4437 +
4438 + while (cnt--) {
4439 +#if defined(__BIG_ENDIAN)
4440 + dd[1] = *(ss++);
4441 + dd[0] = *(ss++);
4442 + dd += 2;
4443 +#else
4444 + *(dd++) = *(ss++);
4445 + *(dd++) = *(ss++);
4446 +#endif
4447 + }
4448 +}
4449 +
4450 +/* decode a field from a cacheline */
4451 +static inline u32 qb_attr_code_decode(const struct qb_attr_code *code,
4452 + const u32 *cacheline)
4453 +{
4454 + return d32_u32(code->lsoffset, code->width, cacheline[code->word]);
4455 +}
4456 +
4457 +static inline u64 qb_attr_code_decode_64(const struct qb_attr_code *code,
4458 + const u64 *cacheline)
4459 +{
4460 + u64 res;
4461 +
4462 + u64_from_le32_copy(&res, &cacheline[code->word / 2], 1);
4463 + return res;
4464 +}
4465 +
4466 +/* encode a field to a cacheline */
4467 +static inline void qb_attr_code_encode(const struct qb_attr_code *code,
4468 + u32 *cacheline, u32 val)
4469 +{
4470 + cacheline[code->word] =
4471 + r32_u32(code->lsoffset, code->width, cacheline[code->word])
4472 + | e32_u32(code->lsoffset, code->width, val);
4473 +}
4474 +
4475 +static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
4476 + u64 *cacheline, u64 val)
4477 +{
4478 + u64_to_le32_copy(&cacheline[code->word / 2], &val, 1);
4479 +}
4480 +
4481 +/* Small-width signed values (two's-complement) will decode into medium-width
4482 + * positives. (Eg. for an 8-bit signed field, which stores values from -128 to
4483 + * +127, a setting of -7 would appear to decode to the 32-bit unsigned value
4484 + * 249. Likewise -120 would decode as 136.) This function allows the caller to
4485 + * "re-sign" such fields to 32-bit signed. (Eg. -7, which was 249 with an 8-bit
4486 + * encoding, will become 0xfffffff9 if you cast the return value to u32).
4487 + */
4488 +static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code,
4489 + u32 val)
4490 +{
4491 + WARN_ON(val >= (1 << code->width));
4492 + /* If the high bit was set, it was encoding a negative */
4493 + if (val >= (1 << (code->width - 1)))
4494 + return (int32_t)0 - (int32_t)(((u32)1 << code->width) -
4495 + val);
4496 + /* Otherwise, it was encoding a positive */
4497 + return (int32_t)val;
4498 +}
4499 +
4500 +/* ---------------------- */
4501 +/* Descriptors/cachelines */
4502 +/* ---------------------- */
4503 +
4504 +/* To avoid needless dynamic allocation, the driver API often gives the caller
4505 + * a "descriptor" type that the caller can instantiate however they like.
4506 + * Ultimately though, it is just a cacheline of binary storage (or something
4507 + * smaller when it is known that the descriptor doesn't need all 64 bytes) for
4508 + * holding pre-formatted pieces of hardware commands. The performance-critical
4509 + * code can then copy these descriptors directly into hardware command
4510 + * registers more efficiently than trying to construct/format commands
4511 + * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
4512 + * order for the compiler to know its size, but the internal details are not
4513 + * exposed. The following macro is used within the driver for converting *any*
4514 + * descriptor pointer to a usable array pointer. The use of a macro (instead of
4515 + * an inline) is necessary to work with different descriptor types and to work
4516 + * correctly with const and non-const inputs (and similarly-qualified outputs).
4517 + */
4518 +#define qb_cl(d) (&(d)->dont_manipulate_directly[0])
4519 +
4520 +#endif /* __FSL_QBMAN_PORTAL_H */
4521 --- /dev/null
4522 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
4523 @@ -0,0 +1,853 @@
4524 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
4525 + *
4526 + * Redistribution and use in source and binary forms, with or without
4527 + * modification, are permitted provided that the following conditions are met:
4528 + * * Redistributions of source code must retain the above copyright
4529 + * notice, this list of conditions and the following disclaimer.
4530 + * * Redistributions in binary form must reproduce the above copyright
4531 + * notice, this list of conditions and the following disclaimer in the
4532 + * documentation and/or other materials provided with the distribution.
4533 + * * Neither the name of Freescale Semiconductor nor the
4534 + * names of its contributors may be used to endorse or promote products
4535 + * derived from this software without specific prior written permission.
4536 + *
4537 + *
4538 + * ALTERNATIVELY, this software may be distributed under the terms of the
4539 + * GNU General Public License ("GPL") as published by the Free Software
4540 + * Foundation, either version 2 of that License or (at your option) any
4541 + * later version.
4542 + *
4543 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
4544 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
4545 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
4546 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
4547 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4548 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
4549 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
4550 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4551 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
4552 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4553 + */
4554 +
4555 +#include <linux/errno.h>
4556 +
4557 +#include "../../include/dpaa2-global.h"
4558 +#include "qbman-portal.h"
4559 +#include "qbman_debug.h"
4560 +
4561 +/* QBMan portal management command code */
4562 +#define QBMAN_BP_QUERY 0x32
4563 +#define QBMAN_FQ_QUERY 0x44
4564 +#define QBMAN_FQ_QUERY_NP 0x45
4565 +#define QBMAN_CGR_QUERY 0x51
4566 +#define QBMAN_WRED_QUERY 0x54
4567 +#define QBMAN_CGR_STAT_QUERY 0x55
4568 +#define QBMAN_CGR_STAT_QUERY_CLR 0x56
4569 +
4570 +enum qbman_attr_usage_e {
4571 + qbman_attr_usage_fq,
4572 + qbman_attr_usage_bpool,
4573 + qbman_attr_usage_cgr,
4574 +};
4575 +
4576 +struct int_qbman_attr {
4577 + u32 words[32];
4578 + enum qbman_attr_usage_e usage;
4579 +};
4580 +
4581 +#define attr_type_set(a, e) \
4582 +{ \
4583 + struct qbman_attr *__attr = a; \
4584 + enum qbman_attr_usage_e __usage = e; \
4585 + ((struct int_qbman_attr *)__attr)->usage = __usage; \
4586 +}
4587 +
4588 +#define ATTR32(d) (&(d)->dont_manipulate_directly[0])
4589 +#define ATTR32_1(d) (&(d)->dont_manipulate_directly[16])
4590 +
4591 +static struct qb_attr_code code_bp_bpid = QB_CODE(0, 16, 16);
4592 +static struct qb_attr_code code_bp_bdi = QB_CODE(1, 16, 1);
4593 +static struct qb_attr_code code_bp_va = QB_CODE(1, 17, 1);
4594 +static struct qb_attr_code code_bp_wae = QB_CODE(1, 18, 1);
4595 +static struct qb_attr_code code_bp_swdet = QB_CODE(4, 0, 16);
4596 +static struct qb_attr_code code_bp_swdxt = QB_CODE(4, 16, 16);
4597 +static struct qb_attr_code code_bp_hwdet = QB_CODE(5, 0, 16);
4598 +static struct qb_attr_code code_bp_hwdxt = QB_CODE(5, 16, 16);
4599 +static struct qb_attr_code code_bp_swset = QB_CODE(6, 0, 16);
4600 +static struct qb_attr_code code_bp_swsxt = QB_CODE(6, 16, 16);
4601 +static struct qb_attr_code code_bp_vbpid = QB_CODE(7, 0, 14);
4602 +static struct qb_attr_code code_bp_icid = QB_CODE(7, 16, 15);
4603 +static struct qb_attr_code code_bp_pl = QB_CODE(7, 31, 1);
4604 +static struct qb_attr_code code_bp_bpscn_addr_lo = QB_CODE(8, 0, 32);
4605 +static struct qb_attr_code code_bp_bpscn_addr_hi = QB_CODE(9, 0, 32);
4606 +static struct qb_attr_code code_bp_bpscn_ctx_lo = QB_CODE(10, 0, 32);
4607 +static struct qb_attr_code code_bp_bpscn_ctx_hi = QB_CODE(11, 0, 32);
4608 +static struct qb_attr_code code_bp_hw_targ = QB_CODE(12, 0, 16);
4609 +static struct qb_attr_code code_bp_state = QB_CODE(1, 24, 3);
4610 +static struct qb_attr_code code_bp_fill = QB_CODE(2, 0, 32);
4611 +static struct qb_attr_code code_bp_hdptr = QB_CODE(3, 0, 32);
4612 +static struct qb_attr_code code_bp_sdcnt = QB_CODE(13, 0, 8);
4613 +static struct qb_attr_code code_bp_hdcnt = QB_CODE(13, 1, 8);
4614 +static struct qb_attr_code code_bp_sscnt = QB_CODE(13, 2, 8);
4615 +
4616 +void qbman_bp_attr_clear(struct qbman_attr *a)
4617 +{
4618 + memset(a, 0, sizeof(*a));
4619 + attr_type_set(a, qbman_attr_usage_bpool);
4620 +}
4621 +
4622 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
4623 + struct qbman_attr *a)
4624 +{
4625 + u32 *p;
4626 + u32 verb, rslt;
4627 + u32 *attr = ATTR32(a);
4628 +
4629 + qbman_bp_attr_clear(a);
4630 +
4631 + /* Start the management command */
4632 + p = qbman_swp_mc_start(s);
4633 + if (!p)
4634 + return -EBUSY;
4635 +
4636 + /* Encode the caller-provided attributes */
4637 + qb_attr_code_encode(&code_bp_bpid, p, bpid);
4638 +
4639 + /* Complete the management command */
4640 + p = qbman_swp_mc_complete(s, p, QBMAN_BP_QUERY);
4641 +
4642 + /* Decode the outcome */
4643 + verb = qb_attr_code_decode(&code_generic_verb, p);
4644 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4645 + WARN_ON(verb != QBMAN_BP_QUERY);
4646 +
4647 + /* Determine success or failure */
4648 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4649 + pr_err("Query of BPID 0x%x failed, code=0x%02x\n", bpid, rslt);
4650 + return -EIO;
4651 + }
4652 +
4653 + /* For the query, word[0] of the result contains only the
4654 + * verb/rslt fields, so skip word[0].
4655 + */
4656 + word_copy(&attr[1], &p[1], 15);
4657 + return 0;
4658 +}
4659 +
4660 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae)
4661 +{
4662 + u32 *p = ATTR32(a);
4663 +
4664 + *bdi = !!qb_attr_code_decode(&code_bp_bdi, p);
4665 + *va = !!qb_attr_code_decode(&code_bp_va, p);
4666 + *wae = !!qb_attr_code_decode(&code_bp_wae, p);
4667 +}
4668 +
4669 +static u32 qbman_bp_thresh_to_value(u32 val)
4670 +{
4671 + return (val & 0xff) << ((val & 0xf00) >> 8);
4672 +}
4673 +
4674 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet)
4675 +{
4676 + u32 *p = ATTR32(a);
4677 +
4678 + *swdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdet,
4679 + p));
4680 +}
4681 +
4682 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt)
4683 +{
4684 + u32 *p = ATTR32(a);
4685 +
4686 + *swdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdxt,
4687 + p));
4688 +}
4689 +
4690 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet)
4691 +{
4692 + u32 *p = ATTR32(a);
4693 +
4694 + *hwdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdet,
4695 + p));
4696 +}
4697 +
4698 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt)
4699 +{
4700 + u32 *p = ATTR32(a);
4701 +
4702 + *hwdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdxt,
4703 + p));
4704 +}
4705 +
4706 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset)
4707 +{
4708 + u32 *p = ATTR32(a);
4709 +
4710 + *swset = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swset,
4711 + p));
4712 +}
4713 +
4714 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt)
4715 +{
4716 + u32 *p = ATTR32(a);
4717 +
4718 + *swsxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swsxt,
4719 + p));
4720 +}
4721 +
4722 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid)
4723 +{
4724 + u32 *p = ATTR32(a);
4725 +
4726 + *vbpid = qb_attr_code_decode(&code_bp_vbpid, p);
4727 +}
4728 +
4729 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl)
4730 +{
4731 + u32 *p = ATTR32(a);
4732 +
4733 + *icid = qb_attr_code_decode(&code_bp_icid, p);
4734 + *pl = !!qb_attr_code_decode(&code_bp_pl, p);
4735 +}
4736 +
4737 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr)
4738 +{
4739 + u32 *p = ATTR32(a);
4740 +
4741 + *bpscn_addr = ((u64)qb_attr_code_decode(&code_bp_bpscn_addr_hi,
4742 + p) << 32) |
4743 + (u64)qb_attr_code_decode(&code_bp_bpscn_addr_lo,
4744 + p);
4745 +}
4746 +
4747 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx)
4748 +{
4749 + u32 *p = ATTR32(a);
4750 +
4751 + *bpscn_ctx = ((u64)qb_attr_code_decode(&code_bp_bpscn_ctx_hi, p)
4752 + << 32) |
4753 + (u64)qb_attr_code_decode(&code_bp_bpscn_ctx_lo,
4754 + p);
4755 +}
4756 +
4757 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ)
4758 +{
4759 + u32 *p = ATTR32(a);
4760 +
4761 + *hw_targ = qb_attr_code_decode(&code_bp_hw_targ, p);
4762 +}
4763 +
4764 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a)
4765 +{
4766 + u32 *p = ATTR32(a);
4767 +
4768 + return !(int)(qb_attr_code_decode(&code_bp_state, p) & 0x1);
4769 +}
4770 +
4771 +int qbman_bp_info_is_depleted(struct qbman_attr *a)
4772 +{
4773 + u32 *p = ATTR32(a);
4774 +
4775 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x2);
4776 +}
4777 +
4778 +int qbman_bp_info_is_surplus(struct qbman_attr *a)
4779 +{
4780 + u32 *p = ATTR32(a);
4781 +
4782 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x4);
4783 +}
4784 +
4785 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a)
4786 +{
4787 + u32 *p = ATTR32(a);
4788 +
4789 + return qb_attr_code_decode(&code_bp_fill, p);
4790 +}
4791 +
4792 +u32 qbman_bp_info_hdptr(struct qbman_attr *a)
4793 +{
4794 + u32 *p = ATTR32(a);
4795 +
4796 + return qb_attr_code_decode(&code_bp_hdptr, p);
4797 +}
4798 +
4799 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a)
4800 +{
4801 + u32 *p = ATTR32(a);
4802 +
4803 + return qb_attr_code_decode(&code_bp_sdcnt, p);
4804 +}
4805 +
4806 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a)
4807 +{
4808 + u32 *p = ATTR32(a);
4809 +
4810 + return qb_attr_code_decode(&code_bp_hdcnt, p);
4811 +}
4812 +
4813 +u32 qbman_bp_info_sscnt(struct qbman_attr *a)
4814 +{
4815 + u32 *p = ATTR32(a);
4816 +
4817 + return qb_attr_code_decode(&code_bp_sscnt, p);
4818 +}
4819 +
4820 +static struct qb_attr_code code_fq_fqid = QB_CODE(1, 0, 24);
4821 +static struct qb_attr_code code_fq_cgrid = QB_CODE(2, 16, 16);
4822 +static struct qb_attr_code code_fq_destwq = QB_CODE(3, 0, 15);
4823 +static struct qb_attr_code code_fq_fqctrl = QB_CODE(3, 24, 8);
4824 +static struct qb_attr_code code_fq_icscred = QB_CODE(4, 0, 15);
4825 +static struct qb_attr_code code_fq_tdthresh = QB_CODE(4, 16, 13);
4826 +static struct qb_attr_code code_fq_oa_len = QB_CODE(5, 0, 12);
4827 +static struct qb_attr_code code_fq_oa_ics = QB_CODE(5, 14, 1);
4828 +static struct qb_attr_code code_fq_oa_cgr = QB_CODE(5, 15, 1);
4829 +static struct qb_attr_code code_fq_mctl_bdi = QB_CODE(5, 24, 1);
4830 +static struct qb_attr_code code_fq_mctl_ff = QB_CODE(5, 25, 1);
4831 +static struct qb_attr_code code_fq_mctl_va = QB_CODE(5, 26, 1);
4832 +static struct qb_attr_code code_fq_mctl_ps = QB_CODE(5, 27, 1);
4833 +static struct qb_attr_code code_fq_ctx_lower32 = QB_CODE(6, 0, 32);
4834 +static struct qb_attr_code code_fq_ctx_upper32 = QB_CODE(7, 0, 32);
4835 +static struct qb_attr_code code_fq_icid = QB_CODE(8, 0, 15);
4836 +static struct qb_attr_code code_fq_pl = QB_CODE(8, 15, 1);
4837 +static struct qb_attr_code code_fq_vfqid = QB_CODE(9, 0, 24);
4838 +static struct qb_attr_code code_fq_erfqid = QB_CODE(10, 0, 24);
4839 +
4840 +void qbman_fq_attr_clear(struct qbman_attr *a)
4841 +{
4842 + memset(a, 0, sizeof(*a));
4843 + attr_type_set(a, qbman_attr_usage_fq);
4844 +}
4845 +
4846 +/* FQ query function for programmable fields */
4847 +int qbman_fq_query(struct qbman_swp *s, u32 fqid, struct qbman_attr *desc)
4848 +{
4849 + u32 *p;
4850 + u32 verb, rslt;
4851 + u32 *d = ATTR32(desc);
4852 +
4853 + qbman_fq_attr_clear(desc);
4854 +
4855 + p = qbman_swp_mc_start(s);
4856 + if (!p)
4857 + return -EBUSY;
4858 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
4859 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY);
4860 +
4861 + /* Decode the outcome */
4862 + verb = qb_attr_code_decode(&code_generic_verb, p);
4863 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4864 + WARN_ON(verb != QBMAN_FQ_QUERY);
4865 +
4866 + /* Determine success or failure */
4867 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4868 + pr_err("Query of FQID 0x%x failed, code=0x%02x\n",
4869 + fqid, rslt);
4870 + return -EIO;
4871 + }
4872 + /*
4873 + * For the configure, word[0] of the command contains only the WE-mask.
4874 + * For the query, word[0] of the result contains only the verb/rslt
4875 + * fields. Skip word[0] in the latter case.
4876 + */
4877 + word_copy(&d[1], &p[1], 15);
4878 + return 0;
4879 +}
4880 +
4881 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl)
4882 +{
4883 + u32 *p = ATTR32(d);
4884 +
4885 + *fqctrl = qb_attr_code_decode(&code_fq_fqctrl, p);
4886 +}
4887 +
4888 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid)
4889 +{
4890 + u32 *p = ATTR32(d);
4891 +
4892 + *cgrid = qb_attr_code_decode(&code_fq_cgrid, p);
4893 +}
4894 +
4895 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq)
4896 +{
4897 + u32 *p = ATTR32(d);
4898 +
4899 + *destwq = qb_attr_code_decode(&code_fq_destwq, p);
4900 +}
4901 +
4902 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred)
4903 +{
4904 + u32 *p = ATTR32(d);
4905 +
4906 + *icscred = qb_attr_code_decode(&code_fq_icscred, p);
4907 +}
4908 +
4909 +static struct qb_attr_code code_tdthresh_exp = QB_CODE(0, 0, 5);
4910 +static struct qb_attr_code code_tdthresh_mant = QB_CODE(0, 5, 8);
4911 +static u32 qbman_thresh_to_value(u32 val)
4912 +{
4913 + u32 m, e;
4914 +
4915 + m = qb_attr_code_decode(&code_tdthresh_mant, &val);
4916 + e = qb_attr_code_decode(&code_tdthresh_exp, &val);
4917 + return m << e;
4918 +}
4919 +
4920 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh)
4921 +{
4922 + u32 *p = ATTR32(d);
4923 +
4924 + *tdthresh = qbman_thresh_to_value(qb_attr_code_decode(&code_fq_tdthresh,
4925 + p));
4926 +}
4927 +
4928 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
4929 + int *oa_ics, int *oa_cgr, int32_t *oa_len)
4930 +{
4931 + u32 *p = ATTR32(d);
4932 +
4933 + *oa_ics = !!qb_attr_code_decode(&code_fq_oa_ics, p);
4934 + *oa_cgr = !!qb_attr_code_decode(&code_fq_oa_cgr, p);
4935 + *oa_len = qb_attr_code_makesigned(&code_fq_oa_len,
4936 + qb_attr_code_decode(&code_fq_oa_len, p));
4937 +}
4938 +
4939 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
4940 + int *bdi, int *ff, int *va, int *ps)
4941 +{
4942 + u32 *p = ATTR32(d);
4943 +
4944 + *bdi = !!qb_attr_code_decode(&code_fq_mctl_bdi, p);
4945 + *ff = !!qb_attr_code_decode(&code_fq_mctl_ff, p);
4946 + *va = !!qb_attr_code_decode(&code_fq_mctl_va, p);
4947 + *ps = !!qb_attr_code_decode(&code_fq_mctl_ps, p);
4948 +}
4949 +
4950 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo)
4951 +{
4952 + u32 *p = ATTR32(d);
4953 +
4954 + *hi = qb_attr_code_decode(&code_fq_ctx_upper32, p);
4955 + *lo = qb_attr_code_decode(&code_fq_ctx_lower32, p);
4956 +}
4957 +
4958 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl)
4959 +{
4960 + u32 *p = ATTR32(d);
4961 +
4962 + *icid = qb_attr_code_decode(&code_fq_icid, p);
4963 + *pl = !!qb_attr_code_decode(&code_fq_pl, p);
4964 +}
4965 +
4966 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid)
4967 +{
4968 + u32 *p = ATTR32(d);
4969 +
4970 + *vfqid = qb_attr_code_decode(&code_fq_vfqid, p);
4971 +}
4972 +
4973 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid)
4974 +{
4975 + u32 *p = ATTR32(d);
4976 +
4977 + *erfqid = qb_attr_code_decode(&code_fq_erfqid, p);
4978 +}
4979 +
4980 +/* Query FQ Non-Programmalbe Fields */
4981 +static struct qb_attr_code code_fq_np_state = QB_CODE(0, 16, 3);
4982 +static struct qb_attr_code code_fq_np_fe = QB_CODE(0, 19, 1);
4983 +static struct qb_attr_code code_fq_np_x = QB_CODE(0, 20, 1);
4984 +static struct qb_attr_code code_fq_np_r = QB_CODE(0, 21, 1);
4985 +static struct qb_attr_code code_fq_np_oe = QB_CODE(0, 22, 1);
4986 +static struct qb_attr_code code_fq_np_frm_cnt = QB_CODE(6, 0, 24);
4987 +static struct qb_attr_code code_fq_np_byte_cnt = QB_CODE(7, 0, 32);
4988 +
4989 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
4990 + struct qbman_attr *state)
4991 +{
4992 + u32 *p;
4993 + u32 verb, rslt;
4994 + u32 *d = ATTR32(state);
4995 +
4996 + qbman_fq_attr_clear(state);
4997 +
4998 + p = qbman_swp_mc_start(s);
4999 + if (!p)
5000 + return -EBUSY;
5001 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
5002 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
5003 +
5004 + /* Decode the outcome */
5005 + verb = qb_attr_code_decode(&code_generic_verb, p);
5006 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5007 + WARN_ON(verb != QBMAN_FQ_QUERY_NP);
5008 +
5009 + /* Determine success or failure */
5010 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5011 + pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
5012 + fqid, rslt);
5013 + return -EIO;
5014 + }
5015 + word_copy(&d[0], &p[0], 16);
5016 + return 0;
5017 +}
5018 +
5019 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state)
5020 +{
5021 + const u32 *p = ATTR32(state);
5022 +
5023 + return qb_attr_code_decode(&code_fq_np_state, p);
5024 +}
5025 +
5026 +int qbman_fq_state_force_eligible(const struct qbman_attr *state)
5027 +{
5028 + const u32 *p = ATTR32(state);
5029 +
5030 + return !!qb_attr_code_decode(&code_fq_np_fe, p);
5031 +}
5032 +
5033 +int qbman_fq_state_xoff(const struct qbman_attr *state)
5034 +{
5035 + const u32 *p = ATTR32(state);
5036 +
5037 + return !!qb_attr_code_decode(&code_fq_np_x, p);
5038 +}
5039 +
5040 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state)
5041 +{
5042 + const u32 *p = ATTR32(state);
5043 +
5044 + return !!qb_attr_code_decode(&code_fq_np_r, p);
5045 +}
5046 +
5047 +int qbman_fq_state_overflow_error(const struct qbman_attr *state)
5048 +{
5049 + const u32 *p = ATTR32(state);
5050 +
5051 + return !!qb_attr_code_decode(&code_fq_np_oe, p);
5052 +}
5053 +
5054 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state)
5055 +{
5056 + const u32 *p = ATTR32(state);
5057 +
5058 + return qb_attr_code_decode(&code_fq_np_frm_cnt, p);
5059 +}
5060 +
5061 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state)
5062 +{
5063 + const u32 *p = ATTR32(state);
5064 +
5065 + return qb_attr_code_decode(&code_fq_np_byte_cnt, p);
5066 +}
5067 +
5068 +/* Query CGR */
5069 +static struct qb_attr_code code_cgr_cgid = QB_CODE(0, 16, 16);
5070 +static struct qb_attr_code code_cgr_cscn_wq_en_enter = QB_CODE(2, 0, 1);
5071 +static struct qb_attr_code code_cgr_cscn_wq_en_exit = QB_CODE(2, 1, 1);
5072 +static struct qb_attr_code code_cgr_cscn_wq_icd = QB_CODE(2, 2, 1);
5073 +static struct qb_attr_code code_cgr_mode = QB_CODE(3, 16, 2);
5074 +static struct qb_attr_code code_cgr_rej_cnt_mode = QB_CODE(3, 18, 1);
5075 +static struct qb_attr_code code_cgr_cscn_bdi = QB_CODE(3, 19, 1);
5076 +static struct qb_attr_code code_cgr_cscn_wr_en_enter = QB_CODE(3, 24, 1);
5077 +static struct qb_attr_code code_cgr_cscn_wr_en_exit = QB_CODE(3, 25, 1);
5078 +static struct qb_attr_code code_cgr_cg_wr_ae = QB_CODE(3, 26, 1);
5079 +static struct qb_attr_code code_cgr_cscn_dcp_en = QB_CODE(3, 27, 1);
5080 +static struct qb_attr_code code_cgr_cg_wr_va = QB_CODE(3, 28, 1);
5081 +static struct qb_attr_code code_cgr_i_cnt_wr_en = QB_CODE(4, 0, 1);
5082 +static struct qb_attr_code code_cgr_i_cnt_wr_bnd = QB_CODE(4, 1, 5);
5083 +static struct qb_attr_code code_cgr_td_en = QB_CODE(4, 8, 1);
5084 +static struct qb_attr_code code_cgr_cs_thres = QB_CODE(4, 16, 13);
5085 +static struct qb_attr_code code_cgr_cs_thres_x = QB_CODE(5, 0, 13);
5086 +static struct qb_attr_code code_cgr_td_thres = QB_CODE(5, 16, 13);
5087 +static struct qb_attr_code code_cgr_cscn_tdcp = QB_CODE(6, 0, 16);
5088 +static struct qb_attr_code code_cgr_cscn_wqid = QB_CODE(6, 16, 16);
5089 +static struct qb_attr_code code_cgr_cscn_vcgid = QB_CODE(7, 0, 16);
5090 +static struct qb_attr_code code_cgr_cg_icid = QB_CODE(7, 16, 15);
5091 +static struct qb_attr_code code_cgr_cg_pl = QB_CODE(7, 31, 1);
5092 +static struct qb_attr_code code_cgr_cg_wr_addr_lo = QB_CODE(8, 0, 32);
5093 +static struct qb_attr_code code_cgr_cg_wr_addr_hi = QB_CODE(9, 0, 32);
5094 +static struct qb_attr_code code_cgr_cscn_ctx_lo = QB_CODE(10, 0, 32);
5095 +static struct qb_attr_code code_cgr_cscn_ctx_hi = QB_CODE(11, 0, 32);
5096 +
5097 +void qbman_cgr_attr_clear(struct qbman_attr *a)
5098 +{
5099 + memset(a, 0, sizeof(*a));
5100 + attr_type_set(a, qbman_attr_usage_cgr);
5101 +}
5102 +
5103 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid, struct qbman_attr *attr)
5104 +{
5105 + u32 *p;
5106 + u32 verb, rslt;
5107 + u32 *d[2];
5108 + int i;
5109 + u32 query_verb;
5110 +
5111 + d[0] = ATTR32(attr);
5112 + d[1] = ATTR32_1(attr);
5113 +
5114 + qbman_cgr_attr_clear(attr);
5115 +
5116 + for (i = 0; i < 2; i++) {
5117 + p = qbman_swp_mc_start(s);
5118 + if (!p)
5119 + return -EBUSY;
5120 + query_verb = i ? QBMAN_WRED_QUERY : QBMAN_CGR_QUERY;
5121 +
5122 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
5123 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
5124 +
5125 + /* Decode the outcome */
5126 + verb = qb_attr_code_decode(&code_generic_verb, p);
5127 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5128 + WARN_ON(verb != query_verb);
5129 +
5130 + /* Determine success or failure */
5131 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5132 + pr_err("Query CGID 0x%x failed,", cgid);
5133 + pr_err(" verb=0x%02x, code=0x%02x\n", verb, rslt);
5134 + return -EIO;
5135 + }
5136 + /* For the configure, word[0] of the command contains only the
5137 + * verb/cgid. For the query, word[0] of the result contains
5138 + * only the verb/rslt fields. Skip word[0] in the latter case.
5139 + */
5140 + word_copy(&d[i][1], &p[1], 15);
5141 + }
5142 + return 0;
5143 +}
5144 +
5145 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5146 + int *cscn_wq_en_exit, int *cscn_wq_icd)
5147 + {
5148 + u32 *p = ATTR32(d);
5149 + *cscn_wq_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_enter,
5150 + p);
5151 + *cscn_wq_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_exit, p);
5152 + *cscn_wq_icd = !!qb_attr_code_decode(&code_cgr_cscn_wq_icd, p);
5153 +}
5154 +
5155 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5156 + int *rej_cnt_mode, int *cscn_bdi)
5157 +{
5158 + u32 *p = ATTR32(d);
5159 + *mode = qb_attr_code_decode(&code_cgr_mode, p);
5160 + *rej_cnt_mode = !!qb_attr_code_decode(&code_cgr_rej_cnt_mode, p);
5161 + *cscn_bdi = !!qb_attr_code_decode(&code_cgr_cscn_bdi, p);
5162 +}
5163 +
5164 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5165 + int *cscn_wr_en_exit, int *cg_wr_ae,
5166 + int *cscn_dcp_en, int *cg_wr_va)
5167 +{
5168 + u32 *p = ATTR32(d);
5169 + *cscn_wr_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_enter,
5170 + p);
5171 + *cscn_wr_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_exit, p);
5172 + *cg_wr_ae = !!qb_attr_code_decode(&code_cgr_cg_wr_ae, p);
5173 + *cscn_dcp_en = !!qb_attr_code_decode(&code_cgr_cscn_dcp_en, p);
5174 + *cg_wr_va = !!qb_attr_code_decode(&code_cgr_cg_wr_va, p);
5175 +}
5176 +
5177 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5178 + u32 *i_cnt_wr_bnd)
5179 +{
5180 + u32 *p = ATTR32(d);
5181 + *i_cnt_wr_en = !!qb_attr_code_decode(&code_cgr_i_cnt_wr_en, p);
5182 + *i_cnt_wr_bnd = qb_attr_code_decode(&code_cgr_i_cnt_wr_bnd, p);
5183 +}
5184 +
5185 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en)
5186 +{
5187 + u32 *p = ATTR32(d);
5188 + *td_en = !!qb_attr_code_decode(&code_cgr_td_en, p);
5189 +}
5190 +
5191 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres)
5192 +{
5193 + u32 *p = ATTR32(d);
5194 + *cs_thres = qbman_thresh_to_value(qb_attr_code_decode(
5195 + &code_cgr_cs_thres, p));
5196 +}
5197 +
5198 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5199 + u32 *cs_thres_x)
5200 +{
5201 + u32 *p = ATTR32(d);
5202 + *cs_thres_x = qbman_thresh_to_value(qb_attr_code_decode(
5203 + &code_cgr_cs_thres_x, p));
5204 +}
5205 +
5206 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres)
5207 +{
5208 + u32 *p = ATTR32(d);
5209 + *td_thres = qbman_thresh_to_value(qb_attr_code_decode(
5210 + &code_cgr_td_thres, p));
5211 +}
5212 +
5213 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp)
5214 +{
5215 + u32 *p = ATTR32(d);
5216 + *cscn_tdcp = qb_attr_code_decode(&code_cgr_cscn_tdcp, p);
5217 +}
5218 +
5219 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid)
5220 +{
5221 + u32 *p = ATTR32(d);
5222 + *cscn_wqid = qb_attr_code_decode(&code_cgr_cscn_wqid, p);
5223 +}
5224 +
5225 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5226 + u32 *cscn_vcgid)
5227 +{
5228 + u32 *p = ATTR32(d);
5229 + *cscn_vcgid = qb_attr_code_decode(&code_cgr_cscn_vcgid, p);
5230 +}
5231 +
5232 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5233 + int *pl)
5234 +{
5235 + u32 *p = ATTR32(d);
5236 + *icid = qb_attr_code_decode(&code_cgr_cg_icid, p);
5237 + *pl = !!qb_attr_code_decode(&code_cgr_cg_pl, p);
5238 +}
5239 +
5240 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5241 + u64 *cg_wr_addr)
5242 +{
5243 + u32 *p = ATTR32(d);
5244 + *cg_wr_addr = ((u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_hi,
5245 + p) << 32) |
5246 + (u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_lo,
5247 + p);
5248 +}
5249 +
5250 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx)
5251 +{
5252 + u32 *p = ATTR32(d);
5253 + *cscn_ctx = ((u64)qb_attr_code_decode(&code_cgr_cscn_ctx_hi, p)
5254 + << 32) |
5255 + (u64)qb_attr_code_decode(&code_cgr_cscn_ctx_lo, p);
5256 +}
5257 +
5258 +#define WRED_EDP_WORD(n) (18 + (n) / 4)
5259 +#define WRED_EDP_OFFSET(n) (8 * ((n) % 4))
5260 +#define WRED_PARM_DP_WORD(n) ((n) + 20)
5261 +#define WRED_WE_EDP(n) (16 + (n) * 2)
5262 +#define WRED_WE_PARM_DP(n) (17 + (n) * 2)
5263 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5264 + int *edp)
5265 +{
5266 + u32 *p = ATTR32(d);
5267 + struct qb_attr_code code_wred_edp = QB_CODE(WRED_EDP_WORD(idx),
5268 + WRED_EDP_OFFSET(idx), 8);
5269 + *edp = (int)qb_attr_code_decode(&code_wred_edp, p);
5270 +}
5271 +
5272 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5273 + u64 *maxth, u8 *maxp)
5274 +{
5275 + u8 ma, mn, step_i, step_s, pn;
5276 +
5277 + ma = (u8)(dp >> 24);
5278 + mn = (u8)(dp >> 19) & 0x1f;
5279 + step_i = (u8)(dp >> 11);
5280 + step_s = (u8)(dp >> 6) & 0x1f;
5281 + pn = (u8)dp & 0x3f;
5282 +
5283 + *maxp = ((pn << 2) * 100) / 256;
5284 +
5285 + if (mn == 0)
5286 + *maxth = ma;
5287 + else
5288 + *maxth = ((ma + 256) * (1 << (mn - 1)));
5289 +
5290 + if (step_s == 0)
5291 + *minth = *maxth - step_i;
5292 + else
5293 + *minth = *maxth - (256 + step_i) * (1 << (step_s - 1));
5294 +}
5295 +
5296 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5297 + u32 *dp)
5298 +{
5299 + u32 *p = ATTR32(d);
5300 + struct qb_attr_code code_wred_parm_dp = QB_CODE(WRED_PARM_DP_WORD(idx),
5301 + 0, 8);
5302 + *dp = qb_attr_code_decode(&code_wred_parm_dp, p);
5303 +}
5304 +
5305 +/* Query CGR/CCGR/CQ statistics */
5306 +static struct qb_attr_code code_cgr_stat_ct = QB_CODE(4, 0, 32);
5307 +static struct qb_attr_code code_cgr_stat_frame_cnt_lo = QB_CODE(4, 0, 32);
5308 +static struct qb_attr_code code_cgr_stat_frame_cnt_hi = QB_CODE(5, 0, 8);
5309 +static struct qb_attr_code code_cgr_stat_byte_cnt_lo = QB_CODE(6, 0, 32);
5310 +static struct qb_attr_code code_cgr_stat_byte_cnt_hi = QB_CODE(7, 0, 16);
5311 +static int qbman_cgr_statistics_query(struct qbman_swp *s, u32 cgid,
5312 + int clear, u32 command_type,
5313 + u64 *frame_cnt, u64 *byte_cnt)
5314 +{
5315 + u32 *p;
5316 + u32 verb, rslt;
5317 + u32 query_verb;
5318 + u32 hi, lo;
5319 +
5320 + p = qbman_swp_mc_start(s);
5321 + if (!p)
5322 + return -EBUSY;
5323 +
5324 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
5325 + if (command_type < 2)
5326 + qb_attr_code_encode(&code_cgr_stat_ct, p, command_type);
5327 + query_verb = clear ?
5328 + QBMAN_CGR_STAT_QUERY_CLR : QBMAN_CGR_STAT_QUERY;
5329 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
5330 +
5331 + /* Decode the outcome */
5332 + verb = qb_attr_code_decode(&code_generic_verb, p);
5333 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5334 + WARN_ON(verb != query_verb);
5335 +
5336 + /* Determine success or failure */
5337 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5338 + pr_err("Query statistics of CGID 0x%x failed,", cgid);
5339 + pr_err(" verb=0x%02x code=0x%02x\n", verb, rslt);
5340 + return -EIO;
5341 + }
5342 +
5343 + if (*frame_cnt) {
5344 + hi = qb_attr_code_decode(&code_cgr_stat_frame_cnt_hi, p);
5345 + lo = qb_attr_code_decode(&code_cgr_stat_frame_cnt_lo, p);
5346 + *frame_cnt = ((u64)hi << 32) | (u64)lo;
5347 + }
5348 + if (*byte_cnt) {
5349 + hi = qb_attr_code_decode(&code_cgr_stat_byte_cnt_hi, p);
5350 + lo = qb_attr_code_decode(&code_cgr_stat_byte_cnt_lo, p);
5351 + *byte_cnt = ((u64)hi << 32) | (u64)lo;
5352 + }
5353 +
5354 + return 0;
5355 +}
5356 +
5357 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5358 + u64 *frame_cnt, u64 *byte_cnt)
5359 +{
5360 + return qbman_cgr_statistics_query(s, cgid, clear, 0xff,
5361 + frame_cnt, byte_cnt);
5362 +}
5363 +
5364 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5365 + u64 *frame_cnt, u64 *byte_cnt)
5366 +{
5367 + return qbman_cgr_statistics_query(s, cgid, clear, 1,
5368 + frame_cnt, byte_cnt);
5369 +}
5370 +
5371 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5372 + u64 *frame_cnt, u64 *byte_cnt)
5373 +{
5374 + return qbman_cgr_statistics_query(s, cgid, clear, 0,
5375 + frame_cnt, byte_cnt);
5376 +}
5377 --- /dev/null
5378 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
5379 @@ -0,0 +1,136 @@
5380 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
5381 + *
5382 + * Redistribution and use in source and binary forms, with or without
5383 + * modification, are permitted provided that the following conditions are met:
5384 + * * Redistributions of source code must retain the above copyright
5385 + * notice, this list of conditions and the following disclaimer.
5386 + * * Redistributions in binary form must reproduce the above copyright
5387 + * notice, this list of conditions and the following disclaimer in the
5388 + * documentation and/or other materials provided with the distribution.
5389 + * * Neither the name of Freescale Semiconductor nor the
5390 + * names of its contributors may be used to endorse or promote products
5391 + * derived from this software without specific prior written permission.
5392 + *
5393 + *
5394 + * ALTERNATIVELY, this software may be distributed under the terms of the
5395 + * GNU General Public License ("GPL") as published by the Free Software
5396 + * Foundation, either version 2 of that License or (at your option) any
5397 + * later version.
5398 + *
5399 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5400 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5401 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5402 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5403 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5404 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5405 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5406 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5407 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5408 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5409 + */
5410 +
5411 +struct qbman_attr {
5412 + u32 dont_manipulate_directly[40];
5413 +};
5414 +
5415 +/* Buffer pool query commands */
5416 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
5417 + struct qbman_attr *a);
5418 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae);
5419 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet);
5420 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt);
5421 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet);
5422 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt);
5423 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset);
5424 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt);
5425 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid);
5426 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl);
5427 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr);
5428 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx);
5429 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ);
5430 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a);
5431 +int qbman_bp_info_is_depleted(struct qbman_attr *a);
5432 +int qbman_bp_info_is_surplus(struct qbman_attr *a);
5433 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a);
5434 +u32 qbman_bp_info_hdptr(struct qbman_attr *a);
5435 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a);
5436 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a);
5437 +u32 qbman_bp_info_sscnt(struct qbman_attr *a);
5438 +
5439 +/* FQ query function for programmable fields */
5440 +int qbman_fq_query(struct qbman_swp *s, u32 fqid,
5441 + struct qbman_attr *desc);
5442 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl);
5443 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid);
5444 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq);
5445 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred);
5446 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh);
5447 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
5448 + int *oa_ics, int *oa_cgr, int32_t *oa_len);
5449 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
5450 + int *bdi, int *ff, int *va, int *ps);
5451 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo);
5452 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl);
5453 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid);
5454 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid);
5455 +
5456 +/* FQ query command for non-programmable fields*/
5457 +enum qbman_fq_schedstate_e {
5458 + qbman_fq_schedstate_oos = 0,
5459 + qbman_fq_schedstate_retired,
5460 + qbman_fq_schedstate_tentatively_scheduled,
5461 + qbman_fq_schedstate_truly_scheduled,
5462 + qbman_fq_schedstate_parked,
5463 + qbman_fq_schedstate_held_active,
5464 +};
5465 +
5466 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
5467 + struct qbman_attr *state);
5468 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state);
5469 +int qbman_fq_state_force_eligible(const struct qbman_attr *state);
5470 +int qbman_fq_state_xoff(const struct qbman_attr *state);
5471 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state);
5472 +int qbman_fq_state_overflow_error(const struct qbman_attr *state);
5473 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state);
5474 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state);
5475 +
5476 +/* CGR query */
5477 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid,
5478 + struct qbman_attr *attr);
5479 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5480 + int *cscn_wq_en_exit, int *cscn_wq_icd);
5481 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5482 + int *rej_cnt_mode, int *cscn_bdi);
5483 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5484 + int *cscn_wr_en_exit, int *cg_wr_ae,
5485 + int *cscn_dcp_en, int *cg_wr_va);
5486 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5487 + u32 *i_cnt_wr_bnd);
5488 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en);
5489 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres);
5490 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5491 + u32 *cs_thres_x);
5492 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres);
5493 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp);
5494 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid);
5495 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5496 + u32 *cscn_vcgid);
5497 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5498 + int *pl);
5499 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5500 + u64 *cg_wr_addr);
5501 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx);
5502 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5503 + int *edp);
5504 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5505 + u64 *maxth, u8 *maxp);
5506 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5507 + u32 *dp);
5508 +
5509 +/* CGR/CCGR/CQ statistics query */
5510 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5511 + u64 *frame_cnt, u64 *byte_cnt);
5512 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5513 + u64 *frame_cnt, u64 *byte_cnt);
5514 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5515 + u64 *frame_cnt, u64 *byte_cnt);
5516 --- /dev/null
5517 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_private.h
5518 @@ -0,0 +1,171 @@
5519 +/* Copyright (C) 2014 Freescale Semiconductor, Inc.
5520 + *
5521 + * Redistribution and use in source and binary forms, with or without
5522 + * modification, are permitted provided that the following conditions are met:
5523 + * * Redistributions of source code must retain the above copyright
5524 + * notice, this list of conditions and the following disclaimer.
5525 + * * Redistributions in binary form must reproduce the above copyright
5526 + * notice, this list of conditions and the following disclaimer in the
5527 + * documentation and/or other materials provided with the distribution.
5528 + * * Neither the name of Freescale Semiconductor nor the
5529 + * names of its contributors may be used to endorse or promote products
5530 + * derived from this software without specific prior written permission.
5531 + *
5532 + *
5533 + * ALTERNATIVELY, this software may be distributed under the terms of the
5534 + * GNU General Public License ("GPL") as published by the Free Software
5535 + * Foundation, either version 2 of that License or (at your option) any
5536 + * later version.
5537 + *
5538 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5539 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5540 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5541 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5542 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5543 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5544 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5545 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5546 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5547 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5548 + */
5549 +
5550 +/* Perform extra checking */
5551 +#define QBMAN_CHECKING
5552 +
5553 +/* To maximise the amount of logic that is common between the Linux driver and
5554 + * other targets (such as the embedded MC firmware), we pivot here between the
5555 + * inclusion of two platform-specific headers.
5556 + *
5557 + * The first, qbman_sys_decl.h, includes any and all required system headers as
5558 + * well as providing any definitions for the purposes of compatibility. The
5559 + * second, qbman_sys.h, is where platform-specific routines go.
5560 + *
5561 + * The point of the split is that the platform-independent code (including this
5562 + * header) may depend on platform-specific declarations, yet other
5563 + * platform-specific routines may depend on platform-independent definitions.
5564 + */
5565 +
5566 +#define QMAN_REV_4000 0x04000000
5567 +#define QMAN_REV_4100 0x04010000
5568 +#define QMAN_REV_4101 0x04010001
5569 +
5570 +/* When things go wrong, it is a convenient trick to insert a few FOO()
5571 + * statements in the code to trace progress. TODO: remove this once we are
5572 + * hacking the code less actively.
5573 + */
5574 +#define FOO() fsl_os_print("FOO: %s:%d\n", __FILE__, __LINE__)
5575 +
5576 +/* Any time there is a register interface which we poll on, this provides a
5577 + * "break after x iterations" scheme for it. It's handy for debugging, eg.
5578 + * where you don't want millions of lines of log output from a polling loop
5579 + * that won't, because such things tend to drown out the earlier log output
5580 + * that might explain what caused the problem. (NB: put ";" after each macro!)
5581 + * TODO: we should probably remove this once we're done sanitising the
5582 + * simulator...
5583 + */
5584 +#define DBG_POLL_START(loopvar) (loopvar = 1000)
5585 +#define DBG_POLL_CHECK(loopvar) \
5586 + do {if (!((loopvar)--)) WARN_ON(1); } while (0)
5587 +
5588 +/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets
5589 + * and widths, these macro-generated encode/decode/isolate/remove inlines can
5590 + * be used.
5591 + *
5592 + * Eg. to "d"ecode a 14-bit field out of a register (into a "u16" type),
5593 + * where the field is located 3 bits "up" from the least-significant bit of the
5594 + * register (ie. the field location within the 32-bit register corresponds to a
5595 + * mask of 0x0001fff8), you would do;
5596 + * u16 field = d32_u16(3, 14, reg_value);
5597 + *
5598 + * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE,
5599 + * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!"
5600 + * operator) into a register at bit location 0x00080000 (19 bits "in" from the
5601 + * LS bit), do;
5602 + * reg_value |= e32_int(19, 1, !!field);
5603 + *
5604 + * If you wish to read-modify-write a register, such that you leave the 14-bit
5605 + * field as-is but have all other fields set to zero, then "i"solate the 14-bit
5606 + * value using;
5607 + * reg_value = i32_u16(3, 14, reg_value);
5608 + *
5609 + * Alternatively, you could "r"emove the 1-bit boolean field (setting it to
5610 + * zero) but leaving all other fields as-is;
5611 + * reg_val = r32_int(19, 1, reg_value);
5612 + *
5613 + */
5614 +#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \
5615 + (u32)((1 << width) - 1))
5616 +#define DECLARE_CODEC32(t) \
5617 +static inline u32 e32_##t(u32 lsoffset, u32 width, t val) \
5618 +{ \
5619 + WARN_ON(width > (sizeof(t) * 8)); \
5620 + return ((u32)val & MAKE_MASK32(width)) << lsoffset; \
5621 +} \
5622 +static inline t d32_##t(u32 lsoffset, u32 width, u32 val) \
5623 +{ \
5624 + WARN_ON(width > (sizeof(t) * 8)); \
5625 + return (t)((val >> lsoffset) & MAKE_MASK32(width)); \
5626 +} \
5627 +static inline u32 i32_##t(u32 lsoffset, u32 width, \
5628 + u32 val) \
5629 +{ \
5630 + WARN_ON(width > (sizeof(t) * 8)); \
5631 + return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \
5632 +} \
5633 +static inline u32 r32_##t(u32 lsoffset, u32 width, \
5634 + u32 val) \
5635 +{ \
5636 + WARN_ON(width > (sizeof(t) * 8)); \
5637 + return ~(MAKE_MASK32(width) << lsoffset) & val; \
5638 +}
5639 +DECLARE_CODEC32(u32)
5640 +DECLARE_CODEC32(u16)
5641 +DECLARE_CODEC32(u8)
5642 +DECLARE_CODEC32(int)
5643 +
5644 + /*********************/
5645 + /* Debugging assists */
5646 + /*********************/
5647 +
5648 +static inline void __hexdump(unsigned long start, unsigned long end,
5649 + unsigned long p, size_t sz,
5650 + const unsigned char *c)
5651 +{
5652 + while (start < end) {
5653 + unsigned int pos = 0;
5654 + char buf[64];
5655 + int nl = 0;
5656 +
5657 + pos += sprintf(buf + pos, "%08lx: ", start);
5658 + do {
5659 + if ((start < p) || (start >= (p + sz)))
5660 + pos += sprintf(buf + pos, "..");
5661 + else
5662 + pos += sprintf(buf + pos, "%02x", *(c++));
5663 + if (!(++start & 15)) {
5664 + buf[pos++] = '\n';
5665 + nl = 1;
5666 + } else {
5667 + nl = 0;
5668 + if (!(start & 1))
5669 + buf[pos++] = ' ';
5670 + if (!(start & 3))
5671 + buf[pos++] = ' ';
5672 + }
5673 + } while (start & 15);
5674 + if (!nl)
5675 + buf[pos++] = '\n';
5676 + buf[pos] = '\0';
5677 + pr_info("%s", buf);
5678 + }
5679 +}
5680 +
5681 +static inline void hexdump(const void *ptr, size_t sz)
5682 +{
5683 + unsigned long p = (unsigned long)ptr;
5684 + unsigned long start = p & ~15ul;
5685 + unsigned long end = (p + sz + 15) & ~15ul;
5686 + const unsigned char *c = ptr;
5687 +
5688 + __hexdump(start, end, p, sz, c);
5689 +}
5690 --- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5691 +++ b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5692 @@ -1,4 +1,5 @@
5693 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5694 +/*
5695 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5696 *
5697 * Redistribution and use in source and binary forms, with or without
5698 * modification, are permitted provided that the following conditions are met:
5699 @@ -11,7 +12,6 @@
5700 * names of any contributors may be used to endorse or promote products
5701 * derived from this software without specific prior written permission.
5702 *
5703 - *
5704 * ALTERNATIVELY, this software may be distributed under the terms of the
5705 * GNU General Public License ("GPL") as published by the Free Software
5706 * Foundation, either version 2 of that License or (at your option) any
5707 @@ -33,108 +33,24 @@
5708 #define _FSL_DPMCP_CMD_H
5709
5710 /* Minimal supported DPMCP Version */
5711 -#define DPMCP_MIN_VER_MAJOR 3
5712 -#define DPMCP_MIN_VER_MINOR 0
5713 -
5714 -/* Command IDs */
5715 -#define DPMCP_CMDID_CLOSE 0x800
5716 -#define DPMCP_CMDID_OPEN 0x80b
5717 -#define DPMCP_CMDID_CREATE 0x90b
5718 -#define DPMCP_CMDID_DESTROY 0x900
5719 -
5720 -#define DPMCP_CMDID_GET_ATTR 0x004
5721 -#define DPMCP_CMDID_RESET 0x005
5722 -
5723 -#define DPMCP_CMDID_SET_IRQ 0x010
5724 -#define DPMCP_CMDID_GET_IRQ 0x011
5725 -#define DPMCP_CMDID_SET_IRQ_ENABLE 0x012
5726 -#define DPMCP_CMDID_GET_IRQ_ENABLE 0x013
5727 -#define DPMCP_CMDID_SET_IRQ_MASK 0x014
5728 -#define DPMCP_CMDID_GET_IRQ_MASK 0x015
5729 -#define DPMCP_CMDID_GET_IRQ_STATUS 0x016
5730 -
5731 -struct dpmcp_cmd_open {
5732 - __le32 dpmcp_id;
5733 -};
5734 -
5735 -struct dpmcp_cmd_create {
5736 - __le32 portal_id;
5737 -};
5738 -
5739 -struct dpmcp_cmd_set_irq {
5740 - /* cmd word 0 */
5741 - u8 irq_index;
5742 - u8 pad[3];
5743 - __le32 irq_val;
5744 - /* cmd word 1 */
5745 - __le64 irq_addr;
5746 - /* cmd word 2 */
5747 - __le32 irq_num;
5748 -};
5749 -
5750 -struct dpmcp_cmd_get_irq {
5751 - __le32 pad;
5752 - u8 irq_index;
5753 -};
5754 -
5755 -struct dpmcp_rsp_get_irq {
5756 - /* cmd word 0 */
5757 - __le32 irq_val;
5758 - __le32 pad;
5759 - /* cmd word 1 */
5760 - __le64 irq_paddr;
5761 - /* cmd word 2 */
5762 - __le32 irq_num;
5763 - __le32 type;
5764 -};
5765 +#define DPMCP_MIN_VER_MAJOR 3
5766 +#define DPMCP_MIN_VER_MINOR 0
5767
5768 -#define DPMCP_ENABLE 0x1
5769 +/* Command versioning */
5770 +#define DPMCP_CMD_BASE_VERSION 1
5771 +#define DPMCP_CMD_ID_OFFSET 4
5772
5773 -struct dpmcp_cmd_set_irq_enable {
5774 - u8 enable;
5775 - u8 pad[3];
5776 - u8 irq_index;
5777 -};
5778 +#define DPMCP_CMD(id) ((id << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION)
5779
5780 -struct dpmcp_cmd_get_irq_enable {
5781 - __le32 pad;
5782 - u8 irq_index;
5783 -};
5784 -
5785 -struct dpmcp_rsp_get_irq_enable {
5786 - u8 enabled;
5787 -};
5788 -
5789 -struct dpmcp_cmd_set_irq_mask {
5790 - __le32 mask;
5791 - u8 irq_index;
5792 -};
5793 -
5794 -struct dpmcp_cmd_get_irq_mask {
5795 - __le32 pad;
5796 - u8 irq_index;
5797 -};
5798 -
5799 -struct dpmcp_rsp_get_irq_mask {
5800 - __le32 mask;
5801 -};
5802 +/* Command IDs */
5803 +#define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800)
5804 +#define DPMCP_CMDID_OPEN DPMCP_CMD(0x80b)
5805 +#define DPMCP_CMDID_GET_API_VERSION DPMCP_CMD(0xa0b)
5806
5807 -struct dpmcp_cmd_get_irq_status {
5808 - __le32 status;
5809 - u8 irq_index;
5810 -};
5811 +#define DPMCP_CMDID_RESET DPMCP_CMD(0x005)
5812
5813 -struct dpmcp_rsp_get_irq_status {
5814 - __le32 status;
5815 -};
5816 -
5817 -struct dpmcp_rsp_get_attributes {
5818 - /* response word 0 */
5819 - __le32 pad;
5820 - __le32 id;
5821 - /* response word 1 */
5822 - __le16 version_major;
5823 - __le16 version_minor;
5824 +struct dpmcp_cmd_open {
5825 + __le32 dpmcp_id;
5826 };
5827
5828 #endif /* _FSL_DPMCP_CMD_H */
5829 --- a/drivers/staging/fsl-mc/bus/dpmcp.c
5830 +++ b/drivers/staging/fsl-mc/bus/dpmcp.c
5831 @@ -1,4 +1,5 @@
5832 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5833 +/*
5834 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5835 *
5836 * Redistribution and use in source and binary forms, with or without
5837 * modification, are permitted provided that the following conditions are met:
5838 @@ -11,7 +12,6 @@
5839 * names of any contributors may be used to endorse or promote products
5840 * derived from this software without specific prior written permission.
5841 *
5842 - *
5843 * ALTERNATIVELY, this software may be distributed under the terms of the
5844 * GNU General Public License ("GPL") as published by the Free Software
5845 * Foundation, either version 2 of that License or (at your option) any
5846 @@ -104,76 +104,6 @@ int dpmcp_close(struct fsl_mc_io *mc_io,
5847 }
5848
5849 /**
5850 - * dpmcp_create() - Create the DPMCP object.
5851 - * @mc_io: Pointer to MC portal's I/O object
5852 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5853 - * @cfg: Configuration structure
5854 - * @token: Returned token; use in subsequent API calls
5855 - *
5856 - * Create the DPMCP object, allocate required resources and
5857 - * perform required initialization.
5858 - *
5859 - * The object can be created either by declaring it in the
5860 - * DPL file, or by calling this function.
5861 - * This function returns a unique authentication token,
5862 - * associated with the specific object ID and the specific MC
5863 - * portal; this token must be used in all subsequent calls to
5864 - * this specific object. For objects that are created using the
5865 - * DPL file, call dpmcp_open function to get an authentication
5866 - * token first.
5867 - *
5868 - * Return: '0' on Success; Error code otherwise.
5869 - */
5870 -int dpmcp_create(struct fsl_mc_io *mc_io,
5871 - u32 cmd_flags,
5872 - const struct dpmcp_cfg *cfg,
5873 - u16 *token)
5874 -{
5875 - struct mc_command cmd = { 0 };
5876 - struct dpmcp_cmd_create *cmd_params;
5877 -
5878 - int err;
5879 -
5880 - /* prepare command */
5881 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CREATE,
5882 - cmd_flags, 0);
5883 - cmd_params = (struct dpmcp_cmd_create *)cmd.params;
5884 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
5885 -
5886 - /* send command to mc*/
5887 - err = mc_send_command(mc_io, &cmd);
5888 - if (err)
5889 - return err;
5890 -
5891 - /* retrieve response parameters */
5892 - *token = mc_cmd_hdr_read_token(&cmd);
5893 -
5894 - return 0;
5895 -}
5896 -
5897 -/**
5898 - * dpmcp_destroy() - Destroy the DPMCP object and release all its resources.
5899 - * @mc_io: Pointer to MC portal's I/O object
5900 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5901 - * @token: Token of DPMCP object
5902 - *
5903 - * Return: '0' on Success; error code otherwise.
5904 - */
5905 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
5906 - u32 cmd_flags,
5907 - u16 token)
5908 -{
5909 - struct mc_command cmd = { 0 };
5910 -
5911 - /* prepare command */
5912 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_DESTROY,
5913 - cmd_flags, token);
5914 -
5915 - /* send command to mc*/
5916 - return mc_send_command(mc_io, &cmd);
5917 -}
5918 -
5919 -/**
5920 * dpmcp_reset() - Reset the DPMCP, returns the object to initial state.
5921 * @mc_io: Pointer to MC portal's I/O object
5922 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5923 @@ -196,309 +126,33 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,
5924 }
5925
5926 /**
5927 - * dpmcp_set_irq() - Set IRQ information for the DPMCP to trigger an interrupt.
5928 - * @mc_io: Pointer to MC portal's I/O object
5929 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5930 - * @token: Token of DPMCP object
5931 - * @irq_index: Identifies the interrupt index to configure
5932 - * @irq_cfg: IRQ configuration
5933 - *
5934 - * Return: '0' on Success; Error code otherwise.
5935 - */
5936 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
5937 - u32 cmd_flags,
5938 - u16 token,
5939 - u8 irq_index,
5940 - struct dpmcp_irq_cfg *irq_cfg)
5941 -{
5942 - struct mc_command cmd = { 0 };
5943 - struct dpmcp_cmd_set_irq *cmd_params;
5944 -
5945 - /* prepare command */
5946 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ,
5947 - cmd_flags, token);
5948 - cmd_params = (struct dpmcp_cmd_set_irq *)cmd.params;
5949 - cmd_params->irq_index = irq_index;
5950 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
5951 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
5952 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
5953 -
5954 - /* send command to mc*/
5955 - return mc_send_command(mc_io, &cmd);
5956 -}
5957 -
5958 -/**
5959 - * dpmcp_get_irq() - Get IRQ information from the DPMCP.
5960 - * @mc_io: Pointer to MC portal's I/O object
5961 + * dpmcp_get_api_version - Get Data Path Management Command Portal API version
5962 + * @mc_io: Pointer to Mc portal's I/O object
5963 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5964 - * @token: Token of DPMCP object
5965 - * @irq_index: The interrupt index to configure
5966 - * @type: Interrupt type: 0 represents message interrupt
5967 - * type (both irq_addr and irq_val are valid)
5968 - * @irq_cfg: IRQ attributes
5969 + * @major_ver: Major version of Data Path Management Command Portal API
5970 + * @minor_ver: Minor version of Data Path Management Command Portal API
5971 *
5972 * Return: '0' on Success; Error code otherwise.
5973 */
5974 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
5975 - u32 cmd_flags,
5976 - u16 token,
5977 - u8 irq_index,
5978 - int *type,
5979 - struct dpmcp_irq_cfg *irq_cfg)
5980 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
5981 + u32 cmd_flags,
5982 + u16 *major_ver,
5983 + u16 *minor_ver)
5984 {
5985 struct mc_command cmd = { 0 };
5986 - struct dpmcp_cmd_get_irq *cmd_params;
5987 - struct dpmcp_rsp_get_irq *rsp_params;
5988 int err;
5989
5990 /* prepare command */
5991 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ,
5992 - cmd_flags, token);
5993 - cmd_params = (struct dpmcp_cmd_get_irq *)cmd.params;
5994 - cmd_params->irq_index = irq_index;
5995 -
5996 - /* send command to mc*/
5997 - err = mc_send_command(mc_io, &cmd);
5998 - if (err)
5999 - return err;
6000 -
6001 - /* retrieve response parameters */
6002 - rsp_params = (struct dpmcp_rsp_get_irq *)cmd.params;
6003 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
6004 - irq_cfg->paddr = le64_to_cpu(rsp_params->irq_paddr);
6005 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
6006 - *type = le32_to_cpu(rsp_params->type);
6007 - return 0;
6008 -}
6009 -
6010 -/**
6011 - * dpmcp_set_irq_enable() - Set overall interrupt state.
6012 - * @mc_io: Pointer to MC portal's I/O object
6013 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6014 - * @token: Token of DPMCP object
6015 - * @irq_index: The interrupt index to configure
6016 - * @en: Interrupt state - enable = 1, disable = 0
6017 - *
6018 - * Allows GPP software to control when interrupts are generated.
6019 - * Each interrupt can have up to 32 causes. The enable/disable control's the
6020 - * overall interrupt state. if the interrupt is disabled no causes will cause
6021 - * an interrupt.
6022 - *
6023 - * Return: '0' on Success; Error code otherwise.
6024 - */
6025 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
6026 - u32 cmd_flags,
6027 - u16 token,
6028 - u8 irq_index,
6029 - u8 en)
6030 -{
6031 - struct mc_command cmd = { 0 };
6032 - struct dpmcp_cmd_set_irq_enable *cmd_params;
6033 -
6034 - /* prepare command */
6035 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_ENABLE,
6036 - cmd_flags, token);
6037 - cmd_params = (struct dpmcp_cmd_set_irq_enable *)cmd.params;
6038 - cmd_params->enable = en & DPMCP_ENABLE;
6039 - cmd_params->irq_index = irq_index;
6040 -
6041 - /* send command to mc*/
6042 - return mc_send_command(mc_io, &cmd);
6043 -}
6044 -
6045 -/**
6046 - * dpmcp_get_irq_enable() - Get overall interrupt state
6047 - * @mc_io: Pointer to MC portal's I/O object
6048 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6049 - * @token: Token of DPMCP object
6050 - * @irq_index: The interrupt index to configure
6051 - * @en: Returned interrupt state - enable = 1, disable = 0
6052 - *
6053 - * Return: '0' on Success; Error code otherwise.
6054 - */
6055 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
6056 - u32 cmd_flags,
6057 - u16 token,
6058 - u8 irq_index,
6059 - u8 *en)
6060 -{
6061 - struct mc_command cmd = { 0 };
6062 - struct dpmcp_cmd_get_irq_enable *cmd_params;
6063 - struct dpmcp_rsp_get_irq_enable *rsp_params;
6064 - int err;
6065 -
6066 - /* prepare command */
6067 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_ENABLE,
6068 - cmd_flags, token);
6069 - cmd_params = (struct dpmcp_cmd_get_irq_enable *)cmd.params;
6070 - cmd_params->irq_index = irq_index;
6071 -
6072 - /* send command to mc*/
6073 - err = mc_send_command(mc_io, &cmd);
6074 - if (err)
6075 - return err;
6076 -
6077 - /* retrieve response parameters */
6078 - rsp_params = (struct dpmcp_rsp_get_irq_enable *)cmd.params;
6079 - *en = rsp_params->enabled & DPMCP_ENABLE;
6080 - return 0;
6081 -}
6082 -
6083 -/**
6084 - * dpmcp_set_irq_mask() - Set interrupt mask.
6085 - * @mc_io: Pointer to MC portal's I/O object
6086 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6087 - * @token: Token of DPMCP object
6088 - * @irq_index: The interrupt index to configure
6089 - * @mask: Event mask to trigger interrupt;
6090 - * each bit:
6091 - * 0 = ignore event
6092 - * 1 = consider event for asserting IRQ
6093 - *
6094 - * Every interrupt can have up to 32 causes and the interrupt model supports
6095 - * masking/unmasking each cause independently
6096 - *
6097 - * Return: '0' on Success; Error code otherwise.
6098 - */
6099 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
6100 - u32 cmd_flags,
6101 - u16 token,
6102 - u8 irq_index,
6103 - u32 mask)
6104 -{
6105 - struct mc_command cmd = { 0 };
6106 - struct dpmcp_cmd_set_irq_mask *cmd_params;
6107 -
6108 - /* prepare command */
6109 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_MASK,
6110 - cmd_flags, token);
6111 - cmd_params = (struct dpmcp_cmd_set_irq_mask *)cmd.params;
6112 - cmd_params->mask = cpu_to_le32(mask);
6113 - cmd_params->irq_index = irq_index;
6114 -
6115 - /* send command to mc*/
6116 - return mc_send_command(mc_io, &cmd);
6117 -}
6118 -
6119 -/**
6120 - * dpmcp_get_irq_mask() - Get interrupt mask.
6121 - * @mc_io: Pointer to MC portal's I/O object
6122 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6123 - * @token: Token of DPMCP object
6124 - * @irq_index: The interrupt index to configure
6125 - * @mask: Returned event mask to trigger interrupt
6126 - *
6127 - * Every interrupt can have up to 32 causes and the interrupt model supports
6128 - * masking/unmasking each cause independently
6129 - *
6130 - * Return: '0' on Success; Error code otherwise.
6131 - */
6132 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
6133 - u32 cmd_flags,
6134 - u16 token,
6135 - u8 irq_index,
6136 - u32 *mask)
6137 -{
6138 - struct mc_command cmd = { 0 };
6139 - struct dpmcp_cmd_get_irq_mask *cmd_params;
6140 - struct dpmcp_rsp_get_irq_mask *rsp_params;
6141 -
6142 - int err;
6143 -
6144 - /* prepare command */
6145 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_MASK,
6146 - cmd_flags, token);
6147 - cmd_params = (struct dpmcp_cmd_get_irq_mask *)cmd.params;
6148 - cmd_params->irq_index = irq_index;
6149 -
6150 - /* send command to mc*/
6151 - err = mc_send_command(mc_io, &cmd);
6152 - if (err)
6153 - return err;
6154 -
6155 - /* retrieve response parameters */
6156 - rsp_params = (struct dpmcp_rsp_get_irq_mask *)cmd.params;
6157 - *mask = le32_to_cpu(rsp_params->mask);
6158 -
6159 - return 0;
6160 -}
6161 -
6162 -/**
6163 - * dpmcp_get_irq_status() - Get the current status of any pending interrupts.
6164 - *
6165 - * @mc_io: Pointer to MC portal's I/O object
6166 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6167 - * @token: Token of DPMCP object
6168 - * @irq_index: The interrupt index to configure
6169 - * @status: Returned interrupts status - one bit per cause:
6170 - * 0 = no interrupt pending
6171 - * 1 = interrupt pending
6172 - *
6173 - * Return: '0' on Success; Error code otherwise.
6174 - */
6175 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6176 - u32 cmd_flags,
6177 - u16 token,
6178 - u8 irq_index,
6179 - u32 *status)
6180 -{
6181 - struct mc_command cmd = { 0 };
6182 - struct dpmcp_cmd_get_irq_status *cmd_params;
6183 - struct dpmcp_rsp_get_irq_status *rsp_params;
6184 - int err;
6185 -
6186 - /* prepare command */
6187 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_STATUS,
6188 - cmd_flags, token);
6189 - cmd_params = (struct dpmcp_cmd_get_irq_status *)cmd.params;
6190 - cmd_params->status = cpu_to_le32(*status);
6191 - cmd_params->irq_index = irq_index;
6192 -
6193 - /* send command to mc*/
6194 - err = mc_send_command(mc_io, &cmd);
6195 - if (err)
6196 - return err;
6197 -
6198 - /* retrieve response parameters */
6199 - rsp_params = (struct dpmcp_rsp_get_irq_status *)cmd.params;
6200 - *status = le32_to_cpu(rsp_params->status);
6201 -
6202 - return 0;
6203 -}
6204 -
6205 -/**
6206 - * dpmcp_get_attributes - Retrieve DPMCP attributes.
6207 - *
6208 - * @mc_io: Pointer to MC portal's I/O object
6209 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6210 - * @token: Token of DPMCP object
6211 - * @attr: Returned object's attributes
6212 - *
6213 - * Return: '0' on Success; Error code otherwise.
6214 - */
6215 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6216 - u32 cmd_flags,
6217 - u16 token,
6218 - struct dpmcp_attr *attr)
6219 -{
6220 - struct mc_command cmd = { 0 };
6221 - struct dpmcp_rsp_get_attributes *rsp_params;
6222 - int err;
6223 -
6224 - /* prepare command */
6225 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_ATTR,
6226 - cmd_flags, token);
6227 + cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_API_VERSION,
6228 + cmd_flags, 0);
6229
6230 - /* send command to mc*/
6231 + /* send command to mc */
6232 err = mc_send_command(mc_io, &cmd);
6233 if (err)
6234 return err;
6235
6236 /* retrieve response parameters */
6237 - rsp_params = (struct dpmcp_rsp_get_attributes *)cmd.params;
6238 - attr->id = le32_to_cpu(rsp_params->id);
6239 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6240 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6241 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
6242
6243 return 0;
6244 }
6245 --- a/drivers/staging/fsl-mc/bus/dpmcp.h
6246 +++ b/drivers/staging/fsl-mc/bus/dpmcp.h
6247 @@ -1,4 +1,5 @@
6248 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
6249 +/*
6250 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6251 *
6252 * Redistribution and use in source and binary forms, with or without
6253 * modification, are permitted provided that the following conditions are met:
6254 @@ -11,7 +12,6 @@
6255 * names of any contributors may be used to endorse or promote products
6256 * derived from this software without specific prior written permission.
6257 *
6258 - *
6259 * ALTERNATIVELY, this software may be distributed under the terms of the
6260 * GNU General Public License ("GPL") as published by the Free Software
6261 * Foundation, either version 2 of that License or (at your option) any
6262 @@ -32,128 +32,29 @@
6263 #ifndef __FSL_DPMCP_H
6264 #define __FSL_DPMCP_H
6265
6266 -/* Data Path Management Command Portal API
6267 +/*
6268 + * Data Path Management Command Portal API
6269 * Contains initialization APIs and runtime control APIs for DPMCP
6270 */
6271
6272 struct fsl_mc_io;
6273
6274 int dpmcp_open(struct fsl_mc_io *mc_io,
6275 - uint32_t cmd_flags,
6276 + u32 cmd_flags,
6277 int dpmcp_id,
6278 - uint16_t *token);
6279 -
6280 -/* Get portal ID from pool */
6281 -#define DPMCP_GET_PORTAL_ID_FROM_POOL (-1)
6282 + u16 *token);
6283
6284 int dpmcp_close(struct fsl_mc_io *mc_io,
6285 - uint32_t cmd_flags,
6286 - uint16_t token);
6287 + u32 cmd_flags,
6288 + u16 token);
6289
6290 -/**
6291 - * struct dpmcp_cfg - Structure representing DPMCP configuration
6292 - * @portal_id: Portal ID; 'DPMCP_GET_PORTAL_ID_FROM_POOL' to get the portal ID
6293 - * from pool
6294 - */
6295 -struct dpmcp_cfg {
6296 - int portal_id;
6297 -};
6298 -
6299 -int dpmcp_create(struct fsl_mc_io *mc_io,
6300 - uint32_t cmd_flags,
6301 - const struct dpmcp_cfg *cfg,
6302 - uint16_t *token);
6303 -
6304 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
6305 - uint32_t cmd_flags,
6306 - uint16_t token);
6307 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
6308 + u32 cmd_flags,
6309 + u16 *major_ver,
6310 + u16 *minor_ver);
6311
6312 int dpmcp_reset(struct fsl_mc_io *mc_io,
6313 - uint32_t cmd_flags,
6314 - uint16_t token);
6315 -
6316 -/* IRQ */
6317 -/* IRQ Index */
6318 -#define DPMCP_IRQ_INDEX 0
6319 -/* irq event - Indicates that the link state changed */
6320 -#define DPMCP_IRQ_EVENT_CMD_DONE 0x00000001
6321 -
6322 -/**
6323 - * struct dpmcp_irq_cfg - IRQ configuration
6324 - * @paddr: Address that must be written to signal a message-based interrupt
6325 - * @val: Value to write into irq_addr address
6326 - * @irq_num: A user defined number associated with this IRQ
6327 - */
6328 -struct dpmcp_irq_cfg {
6329 - uint64_t paddr;
6330 - uint32_t val;
6331 - int irq_num;
6332 -};
6333 -
6334 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
6335 - uint32_t cmd_flags,
6336 - uint16_t token,
6337 - uint8_t irq_index,
6338 - struct dpmcp_irq_cfg *irq_cfg);
6339 -
6340 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
6341 - uint32_t cmd_flags,
6342 - uint16_t token,
6343 - uint8_t irq_index,
6344 - int *type,
6345 - struct dpmcp_irq_cfg *irq_cfg);
6346 -
6347 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
6348 - uint32_t cmd_flags,
6349 - uint16_t token,
6350 - uint8_t irq_index,
6351 - uint8_t en);
6352 -
6353 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
6354 - uint32_t cmd_flags,
6355 - uint16_t token,
6356 - uint8_t irq_index,
6357 - uint8_t *en);
6358 -
6359 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
6360 - uint32_t cmd_flags,
6361 - uint16_t token,
6362 - uint8_t irq_index,
6363 - uint32_t mask);
6364 -
6365 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
6366 - uint32_t cmd_flags,
6367 - uint16_t token,
6368 - uint8_t irq_index,
6369 - uint32_t *mask);
6370 -
6371 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6372 - uint32_t cmd_flags,
6373 - uint16_t token,
6374 - uint8_t irq_index,
6375 - uint32_t *status);
6376 -
6377 -/**
6378 - * struct dpmcp_attr - Structure representing DPMCP attributes
6379 - * @id: DPMCP object ID
6380 - * @version: DPMCP version
6381 - */
6382 -struct dpmcp_attr {
6383 - int id;
6384 - /**
6385 - * struct version - Structure representing DPMCP version
6386 - * @major: DPMCP major version
6387 - * @minor: DPMCP minor version
6388 - */
6389 - struct {
6390 - uint16_t major;
6391 - uint16_t minor;
6392 - } version;
6393 -};
6394 -
6395 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6396 - uint32_t cmd_flags,
6397 - uint16_t token,
6398 - struct dpmcp_attr *attr);
6399 + u32 cmd_flags,
6400 + u16 token);
6401
6402 #endif /* __FSL_DPMCP_H */
6403 --- a/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6404 +++ b/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6405 @@ -12,7 +12,6 @@
6406 * names of any contributors may be used to endorse or promote products
6407 * derived from this software without specific prior written permission.
6408 *
6409 - *
6410 * ALTERNATIVELY, this software may be distributed under the terms of the
6411 * GNU General Public License ("GPL") as published by the Free Software
6412 * Foundation, either version 2 of that License or (at your option) any
6413 @@ -41,13 +40,14 @@
6414 #ifndef __FSL_DPMNG_CMD_H
6415 #define __FSL_DPMNG_CMD_H
6416
6417 -/* Command IDs */
6418 -#define DPMNG_CMDID_GET_CONT_ID 0x830
6419 -#define DPMNG_CMDID_GET_VERSION 0x831
6420 +/* Command versioning */
6421 +#define DPMNG_CMD_BASE_VERSION 1
6422 +#define DPMNG_CMD_ID_OFFSET 4
6423
6424 -struct dpmng_rsp_get_container_id {
6425 - __le32 container_id;
6426 -};
6427 +#define DPMNG_CMD(id) ((id << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION)
6428 +
6429 +/* Command IDs */
6430 +#define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831)
6431
6432 struct dpmng_rsp_get_version {
6433 __le32 revision;
6434 --- a/drivers/staging/fsl-mc/bus/dpmng.c
6435 +++ b/drivers/staging/fsl-mc/bus/dpmng.c
6436 @@ -1,4 +1,5 @@
6437 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6438 +/*
6439 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6440 *
6441 * Redistribution and use in source and binary forms, with or without
6442 * modification, are permitted provided that the following conditions are met:
6443 @@ -11,7 +12,6 @@
6444 * names of any contributors may be used to endorse or promote products
6445 * derived from this software without specific prior written permission.
6446 *
6447 - *
6448 * ALTERNATIVELY, this software may be distributed under the terms of the
6449 * GNU General Public License ("GPL") as published by the Free Software
6450 * Foundation, either version 2 of that License or (at your option) any
6451 @@ -72,36 +72,3 @@ int mc_get_version(struct fsl_mc_io *mc_
6452 }
6453 EXPORT_SYMBOL(mc_get_version);
6454
6455 -/**
6456 - * dpmng_get_container_id() - Get container ID associated with a given portal.
6457 - * @mc_io: Pointer to MC portal's I/O object
6458 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6459 - * @container_id: Requested container ID
6460 - *
6461 - * Return: '0' on Success; Error code otherwise.
6462 - */
6463 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
6464 - u32 cmd_flags,
6465 - int *container_id)
6466 -{
6467 - struct mc_command cmd = { 0 };
6468 - struct dpmng_rsp_get_container_id *rsp_params;
6469 - int err;
6470 -
6471 - /* prepare command */
6472 - cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_CONT_ID,
6473 - cmd_flags,
6474 - 0);
6475 -
6476 - /* send command to mc*/
6477 - err = mc_send_command(mc_io, &cmd);
6478 - if (err)
6479 - return err;
6480 -
6481 - /* retrieve response parameters */
6482 - rsp_params = (struct dpmng_rsp_get_container_id *)cmd.params;
6483 - *container_id = le32_to_cpu(rsp_params->container_id);
6484 -
6485 - return 0;
6486 -}
6487 -
6488 --- a/drivers/staging/fsl-mc/bus/dprc-cmd.h
6489 +++ b/drivers/staging/fsl-mc/bus/dprc-cmd.h
6490 @@ -12,7 +12,6 @@
6491 * names of any contributors may be used to endorse or promote products
6492 * derived from this software without specific prior written permission.
6493 *
6494 - *
6495 * ALTERNATIVELY, this software may be distributed under the terms of the
6496 * GNU General Public License ("GPL") as published by the Free Software
6497 * Foundation, either version 2 of that License or (at your option) any
6498 @@ -42,48 +41,39 @@
6499 #define _FSL_DPRC_CMD_H
6500
6501 /* Minimal supported DPRC Version */
6502 -#define DPRC_MIN_VER_MAJOR 5
6503 +#define DPRC_MIN_VER_MAJOR 6
6504 #define DPRC_MIN_VER_MINOR 0
6505
6506 -/* Command IDs */
6507 -#define DPRC_CMDID_CLOSE 0x800
6508 -#define DPRC_CMDID_OPEN 0x805
6509 -#define DPRC_CMDID_CREATE 0x905
6510 -
6511 -#define DPRC_CMDID_GET_ATTR 0x004
6512 -#define DPRC_CMDID_RESET_CONT 0x005
6513 -
6514 -#define DPRC_CMDID_SET_IRQ 0x010
6515 -#define DPRC_CMDID_GET_IRQ 0x011
6516 -#define DPRC_CMDID_SET_IRQ_ENABLE 0x012
6517 -#define DPRC_CMDID_GET_IRQ_ENABLE 0x013
6518 -#define DPRC_CMDID_SET_IRQ_MASK 0x014
6519 -#define DPRC_CMDID_GET_IRQ_MASK 0x015
6520 -#define DPRC_CMDID_GET_IRQ_STATUS 0x016
6521 -#define DPRC_CMDID_CLEAR_IRQ_STATUS 0x017
6522 -
6523 -#define DPRC_CMDID_CREATE_CONT 0x151
6524 -#define DPRC_CMDID_DESTROY_CONT 0x152
6525 -#define DPRC_CMDID_SET_RES_QUOTA 0x155
6526 -#define DPRC_CMDID_GET_RES_QUOTA 0x156
6527 -#define DPRC_CMDID_ASSIGN 0x157
6528 -#define DPRC_CMDID_UNASSIGN 0x158
6529 -#define DPRC_CMDID_GET_OBJ_COUNT 0x159
6530 -#define DPRC_CMDID_GET_OBJ 0x15A
6531 -#define DPRC_CMDID_GET_RES_COUNT 0x15B
6532 -#define DPRC_CMDID_GET_RES_IDS 0x15C
6533 -#define DPRC_CMDID_GET_OBJ_REG 0x15E
6534 -#define DPRC_CMDID_SET_OBJ_IRQ 0x15F
6535 -#define DPRC_CMDID_GET_OBJ_IRQ 0x160
6536 -#define DPRC_CMDID_SET_OBJ_LABEL 0x161
6537 -#define DPRC_CMDID_GET_OBJ_DESC 0x162
6538 -
6539 -#define DPRC_CMDID_CONNECT 0x167
6540 -#define DPRC_CMDID_DISCONNECT 0x168
6541 -#define DPRC_CMDID_GET_POOL 0x169
6542 -#define DPRC_CMDID_GET_POOL_COUNT 0x16A
6543 +/* Command versioning */
6544 +#define DPRC_CMD_BASE_VERSION 1
6545 +#define DPRC_CMD_ID_OFFSET 4
6546
6547 -#define DPRC_CMDID_GET_CONNECTION 0x16C
6548 +#define DPRC_CMD(id) ((id << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION)
6549 +
6550 +/* Command IDs */
6551 +#define DPRC_CMDID_CLOSE DPRC_CMD(0x800)
6552 +#define DPRC_CMDID_OPEN DPRC_CMD(0x805)
6553 +#define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05)
6554 +
6555 +#define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004)
6556 +#define DPRC_CMDID_RESET_CONT DPRC_CMD(0x005)
6557 +
6558 +#define DPRC_CMDID_SET_IRQ DPRC_CMD(0x010)
6559 +#define DPRC_CMDID_GET_IRQ DPRC_CMD(0x011)
6560 +#define DPRC_CMDID_SET_IRQ_ENABLE DPRC_CMD(0x012)
6561 +#define DPRC_CMDID_GET_IRQ_ENABLE DPRC_CMD(0x013)
6562 +#define DPRC_CMDID_SET_IRQ_MASK DPRC_CMD(0x014)
6563 +#define DPRC_CMDID_GET_IRQ_MASK DPRC_CMD(0x015)
6564 +#define DPRC_CMDID_GET_IRQ_STATUS DPRC_CMD(0x016)
6565 +#define DPRC_CMDID_CLEAR_IRQ_STATUS DPRC_CMD(0x017)
6566 +
6567 +#define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830)
6568 +#define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159)
6569 +#define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A)
6570 +#define DPRC_CMDID_GET_RES_COUNT DPRC_CMD(0x15B)
6571 +#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E)
6572 +#define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F)
6573 +#define DPRC_CMDID_GET_OBJ_IRQ DPRC_CMD(0x160)
6574
6575 struct dprc_cmd_open {
6576 __le32 container_id;
6577 @@ -199,9 +189,6 @@ struct dprc_rsp_get_attributes {
6578 /* response word 1 */
6579 __le32 options;
6580 __le32 portal_id;
6581 - /* response word 2 */
6582 - __le16 version_major;
6583 - __le16 version_minor;
6584 };
6585
6586 struct dprc_cmd_set_res_quota {
6587 @@ -367,11 +354,16 @@ struct dprc_cmd_get_obj_region {
6588
6589 struct dprc_rsp_get_obj_region {
6590 /* response word 0 */
6591 - __le64 pad;
6592 + __le64 pad0;
6593 /* response word 1 */
6594 - __le64 base_addr;
6595 + __le32 base_addr;
6596 + __le32 pad1;
6597 /* response word 2 */
6598 __le32 size;
6599 + u8 type;
6600 + u8 pad2[3];
6601 + /* response word 3 */
6602 + __le32 flags;
6603 };
6604
6605 struct dprc_cmd_set_obj_label {
6606 --- a/drivers/staging/fsl-mc/bus/dprc-driver.c
6607 +++ b/drivers/staging/fsl-mc/bus/dprc-driver.c
6608 @@ -1,7 +1,7 @@
6609 /*
6610 * Freescale data path resource container (DPRC) driver
6611 *
6612 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
6613 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6614 * Author: German Rivera <German.Rivera@freescale.com>
6615 *
6616 * This file is licensed under the terms of the GNU General Public
6617 @@ -160,6 +160,8 @@ static void check_plugged_state_change(s
6618 * dprc_add_new_devices - Adds devices to the logical bus for a DPRC
6619 *
6620 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6621 + * @driver_override: driver override to apply to new objects found in the
6622 + * DPRC, or NULL, if none.
6623 * @obj_desc_array: array of device descriptors for child devices currently
6624 * present in the physical DPRC.
6625 * @num_child_objects_in_mc: number of entries in obj_desc_array
6626 @@ -169,6 +171,7 @@ static void check_plugged_state_change(s
6627 * in the physical DPRC.
6628 */
6629 static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
6630 + const char *driver_override,
6631 struct dprc_obj_desc *obj_desc_array,
6632 int num_child_objects_in_mc)
6633 {
6634 @@ -188,11 +191,12 @@ static void dprc_add_new_devices(struct
6635 child_dev = fsl_mc_device_lookup(obj_desc, mc_bus_dev);
6636 if (child_dev) {
6637 check_plugged_state_change(child_dev, obj_desc);
6638 + put_device(&child_dev->dev);
6639 continue;
6640 }
6641
6642 error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev,
6643 - &child_dev);
6644 + driver_override, &child_dev);
6645 if (error < 0)
6646 continue;
6647 }
6648 @@ -202,6 +206,8 @@ static void dprc_add_new_devices(struct
6649 * dprc_scan_objects - Discover objects in a DPRC
6650 *
6651 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6652 + * @driver_override: driver override to apply to new objects found in the
6653 + * DPRC, or NULL, if none.
6654 * @total_irq_count: total number of IRQs needed by objects in the DPRC.
6655 *
6656 * Detects objects added and removed from a DPRC and synchronizes the
6657 @@ -217,6 +223,7 @@ static void dprc_add_new_devices(struct
6658 * of the device drivers for the non-allocatable devices.
6659 */
6660 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
6661 + const char *driver_override,
6662 unsigned int *total_irq_count)
6663 {
6664 int num_child_objects;
6665 @@ -297,7 +304,7 @@ int dprc_scan_objects(struct fsl_mc_devi
6666 dprc_remove_devices(mc_bus_dev, child_obj_desc_array,
6667 num_child_objects);
6668
6669 - dprc_add_new_devices(mc_bus_dev, child_obj_desc_array,
6670 + dprc_add_new_devices(mc_bus_dev, driver_override, child_obj_desc_array,
6671 num_child_objects);
6672
6673 if (child_obj_desc_array)
6674 @@ -328,7 +335,7 @@ int dprc_scan_container(struct fsl_mc_de
6675 * Discover objects in the DPRC:
6676 */
6677 mutex_lock(&mc_bus->scan_mutex);
6678 - error = dprc_scan_objects(mc_bus_dev, &irq_count);
6679 + error = dprc_scan_objects(mc_bus_dev, NULL, &irq_count);
6680 mutex_unlock(&mc_bus->scan_mutex);
6681 if (error < 0)
6682 goto error;
6683 @@ -415,7 +422,7 @@ static irqreturn_t dprc_irq0_handler_thr
6684 DPRC_IRQ_EVENT_OBJ_CREATED)) {
6685 unsigned int irq_count;
6686
6687 - error = dprc_scan_objects(mc_dev, &irq_count);
6688 + error = dprc_scan_objects(mc_dev, NULL, &irq_count);
6689 if (error < 0) {
6690 /*
6691 * If the error is -ENXIO, we ignore it, as it indicates
6692 @@ -505,7 +512,7 @@ static int register_dprc_irq_handler(str
6693 dprc_irq0_handler,
6694 dprc_irq0_handler_thread,
6695 IRQF_NO_SUSPEND | IRQF_ONESHOT,
6696 - "FSL MC DPRC irq0",
6697 + dev_name(&mc_dev->dev),
6698 &mc_dev->dev);
6699 if (error < 0) {
6700 dev_err(&mc_dev->dev,
6701 @@ -597,6 +604,7 @@ static int dprc_probe(struct fsl_mc_devi
6702 struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev);
6703 bool mc_io_created = false;
6704 bool msi_domain_set = false;
6705 + u16 major_ver, minor_ver;
6706
6707 if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0))
6708 return -EINVAL;
6709 @@ -669,13 +677,21 @@ static int dprc_probe(struct fsl_mc_devi
6710 goto error_cleanup_open;
6711 }
6712
6713 - if (mc_bus->dprc_attr.version.major < DPRC_MIN_VER_MAJOR ||
6714 - (mc_bus->dprc_attr.version.major == DPRC_MIN_VER_MAJOR &&
6715 - mc_bus->dprc_attr.version.minor < DPRC_MIN_VER_MINOR)) {
6716 + error = dprc_get_api_version(mc_dev->mc_io, 0,
6717 + &major_ver,
6718 + &minor_ver);
6719 + if (error < 0) {
6720 + dev_err(&mc_dev->dev, "dprc_get_api_version() failed: %d\n",
6721 + error);
6722 + goto error_cleanup_open;
6723 + }
6724 +
6725 + if (major_ver < DPRC_MIN_VER_MAJOR ||
6726 + (major_ver == DPRC_MIN_VER_MAJOR &&
6727 + minor_ver < DPRC_MIN_VER_MINOR)) {
6728 dev_err(&mc_dev->dev,
6729 "ERROR: DPRC version %d.%d not supported\n",
6730 - mc_bus->dprc_attr.version.major,
6731 - mc_bus->dprc_attr.version.minor);
6732 + major_ver, minor_ver);
6733 error = -ENOTSUPP;
6734 goto error_cleanup_open;
6735 }
6736 --- a/drivers/staging/fsl-mc/bus/dprc.c
6737 +++ b/drivers/staging/fsl-mc/bus/dprc.c
6738 @@ -1,4 +1,5 @@
6739 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6740 +/*
6741 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6742 *
6743 * Redistribution and use in source and binary forms, with or without
6744 * modification, are permitted provided that the following conditions are met:
6745 @@ -11,7 +12,6 @@
6746 * names of any contributors may be used to endorse or promote products
6747 * derived from this software without specific prior written permission.
6748 *
6749 - *
6750 * ALTERNATIVELY, this software may be distributed under the terms of the
6751 * GNU General Public License ("GPL") as published by the Free Software
6752 * Foundation, either version 2 of that License or (at your option) any
6753 @@ -100,93 +100,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
6754 EXPORT_SYMBOL(dprc_close);
6755
6756 /**
6757 - * dprc_create_container() - Create child container
6758 - * @mc_io: Pointer to MC portal's I/O object
6759 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6760 - * @token: Token of DPRC object
6761 - * @cfg: Child container configuration
6762 - * @child_container_id: Returned child container ID
6763 - * @child_portal_offset: Returned child portal offset from MC portal base
6764 - *
6765 - * Return: '0' on Success; Error code otherwise.
6766 - */
6767 -int dprc_create_container(struct fsl_mc_io *mc_io,
6768 - u32 cmd_flags,
6769 - u16 token,
6770 - struct dprc_cfg *cfg,
6771 - int *child_container_id,
6772 - u64 *child_portal_offset)
6773 -{
6774 - struct mc_command cmd = { 0 };
6775 - struct dprc_cmd_create_container *cmd_params;
6776 - struct dprc_rsp_create_container *rsp_params;
6777 - int err;
6778 -
6779 - /* prepare command */
6780 - cmd_params = (struct dprc_cmd_create_container *)cmd.params;
6781 - cmd_params->options = cpu_to_le32(cfg->options);
6782 - cmd_params->icid = cpu_to_le16(cfg->icid);
6783 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
6784 - strncpy(cmd_params->label, cfg->label, 16);
6785 - cmd_params->label[15] = '\0';
6786 -
6787 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
6788 - cmd_flags, token);
6789 -
6790 - /* send command to mc*/
6791 - err = mc_send_command(mc_io, &cmd);
6792 - if (err)
6793 - return err;
6794 -
6795 - /* retrieve response parameters */
6796 - rsp_params = (struct dprc_rsp_create_container *)cmd.params;
6797 - *child_container_id = le32_to_cpu(rsp_params->child_container_id);
6798 - *child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr);
6799 -
6800 - return 0;
6801 -}
6802 -
6803 -/**
6804 - * dprc_destroy_container() - Destroy child container.
6805 - * @mc_io: Pointer to MC portal's I/O object
6806 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6807 - * @token: Token of DPRC object
6808 - * @child_container_id: ID of the container to destroy
6809 - *
6810 - * This function terminates the child container, so following this call the
6811 - * child container ID becomes invalid.
6812 - *
6813 - * Notes:
6814 - * - All resources and objects of the destroyed container are returned to the
6815 - * parent container or destroyed if were created be the destroyed container.
6816 - * - This function destroy all the child containers of the specified
6817 - * container prior to destroying the container itself.
6818 - *
6819 - * warning: Only the parent container is allowed to destroy a child policy
6820 - * Container 0 can't be destroyed
6821 - *
6822 - * Return: '0' on Success; Error code otherwise.
6823 - *
6824 - */
6825 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
6826 - u32 cmd_flags,
6827 - u16 token,
6828 - int child_container_id)
6829 -{
6830 - struct mc_command cmd = { 0 };
6831 - struct dprc_cmd_destroy_container *cmd_params;
6832 -
6833 - /* prepare command */
6834 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
6835 - cmd_flags, token);
6836 - cmd_params = (struct dprc_cmd_destroy_container *)cmd.params;
6837 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6838 -
6839 - /* send command to mc*/
6840 - return mc_send_command(mc_io, &cmd);
6841 -}
6842 -
6843 -/**
6844 * dprc_reset_container - Reset child container.
6845 * @mc_io: Pointer to MC portal's I/O object
6846 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6847 @@ -565,279 +478,6 @@ int dprc_get_attributes(struct fsl_mc_io
6848 attr->icid = le16_to_cpu(rsp_params->icid);
6849 attr->options = le32_to_cpu(rsp_params->options);
6850 attr->portal_id = le32_to_cpu(rsp_params->portal_id);
6851 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6852 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6853 -
6854 - return 0;
6855 -}
6856 -
6857 -/**
6858 - * dprc_set_res_quota() - Set allocation policy for a specific resource/object
6859 - * type in a child container
6860 - * @mc_io: Pointer to MC portal's I/O object
6861 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6862 - * @token: Token of DPRC object
6863 - * @child_container_id: ID of the child container
6864 - * @type: Resource/object type
6865 - * @quota: Sets the maximum number of resources of the selected type
6866 - * that the child container is allowed to allocate from its parent;
6867 - * when quota is set to -1, the policy is the same as container's
6868 - * general policy.
6869 - *
6870 - * Allocation policy determines whether or not a container may allocate
6871 - * resources from its parent. Each container has a 'global' allocation policy
6872 - * that is set when the container is created.
6873 - *
6874 - * This function sets allocation policy for a specific resource type.
6875 - * The default policy for all resource types matches the container's 'global'
6876 - * allocation policy.
6877 - *
6878 - * Return: '0' on Success; Error code otherwise.
6879 - *
6880 - * @warning Only the parent container is allowed to change a child policy.
6881 - */
6882 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
6883 - u32 cmd_flags,
6884 - u16 token,
6885 - int child_container_id,
6886 - char *type,
6887 - u16 quota)
6888 -{
6889 - struct mc_command cmd = { 0 };
6890 - struct dprc_cmd_set_res_quota *cmd_params;
6891 -
6892 - /* prepare command */
6893 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_RES_QUOTA,
6894 - cmd_flags, token);
6895 - cmd_params = (struct dprc_cmd_set_res_quota *)cmd.params;
6896 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6897 - cmd_params->quota = cpu_to_le16(quota);
6898 - strncpy(cmd_params->type, type, 16);
6899 - cmd_params->type[15] = '\0';
6900 -
6901 - /* send command to mc*/
6902 - return mc_send_command(mc_io, &cmd);
6903 -}
6904 -
6905 -/**
6906 - * dprc_get_res_quota() - Gets the allocation policy of a specific
6907 - * resource/object type in a child container
6908 - * @mc_io: Pointer to MC portal's I/O object
6909 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6910 - * @token: Token of DPRC object
6911 - * @child_container_id; ID of the child container
6912 - * @type: resource/object type
6913 - * @quota: Returnes the maximum number of resources of the selected type
6914 - * that the child container is allowed to allocate from the parent;
6915 - * when quota is set to -1, the policy is the same as container's
6916 - * general policy.
6917 - *
6918 - * Return: '0' on Success; Error code otherwise.
6919 - */
6920 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
6921 - u32 cmd_flags,
6922 - u16 token,
6923 - int child_container_id,
6924 - char *type,
6925 - u16 *quota)
6926 -{
6927 - struct mc_command cmd = { 0 };
6928 - struct dprc_cmd_get_res_quota *cmd_params;
6929 - struct dprc_rsp_get_res_quota *rsp_params;
6930 - int err;
6931 -
6932 - /* prepare command */
6933 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_QUOTA,
6934 - cmd_flags, token);
6935 - cmd_params = (struct dprc_cmd_get_res_quota *)cmd.params;
6936 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6937 - strncpy(cmd_params->type, type, 16);
6938 - cmd_params->type[15] = '\0';
6939 -
6940 - /* send command to mc*/
6941 - err = mc_send_command(mc_io, &cmd);
6942 - if (err)
6943 - return err;
6944 -
6945 - /* retrieve response parameters */
6946 - rsp_params = (struct dprc_rsp_get_res_quota *)cmd.params;
6947 - *quota = le16_to_cpu(rsp_params->quota);
6948 -
6949 - return 0;
6950 -}
6951 -
6952 -/**
6953 - * dprc_assign() - Assigns objects or resource to a child container.
6954 - * @mc_io: Pointer to MC portal's I/O object
6955 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6956 - * @token: Token of DPRC object
6957 - * @container_id: ID of the child container
6958 - * @res_req: Describes the type and amount of resources to
6959 - * assign to the given container
6960 - *
6961 - * Assignment is usually done by a parent (this DPRC) to one of its child
6962 - * containers.
6963 - *
6964 - * According to the DPRC allocation policy, the assigned resources may be taken
6965 - * (allocated) from the container's ancestors, if not enough resources are
6966 - * available in the container itself.
6967 - *
6968 - * The type of assignment depends on the dprc_res_req options, as follows:
6969 - * - DPRC_RES_REQ_OPT_EXPLICIT: indicates that assigned resources should have
6970 - * the explicit base ID specified at the id_base_align field of res_req.
6971 - * - DPRC_RES_REQ_OPT_ALIGNED: indicates that the assigned resources should be
6972 - * aligned to the value given at id_base_align field of res_req.
6973 - * - DPRC_RES_REQ_OPT_PLUGGED: Relevant only for object assignment,
6974 - * and indicates that the object must be set to the plugged state.
6975 - *
6976 - * A container may use this function with its own ID in order to change a
6977 - * object state to plugged or unplugged.
6978 - *
6979 - * If IRQ information has been set in the child DPRC, it will signal an
6980 - * interrupt following every change in its object assignment.
6981 - *
6982 - * Return: '0' on Success; Error code otherwise.
6983 - */
6984 -int dprc_assign(struct fsl_mc_io *mc_io,
6985 - u32 cmd_flags,
6986 - u16 token,
6987 - int container_id,
6988 - struct dprc_res_req *res_req)
6989 -{
6990 - struct mc_command cmd = { 0 };
6991 - struct dprc_cmd_assign *cmd_params;
6992 -
6993 - /* prepare command */
6994 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_ASSIGN,
6995 - cmd_flags, token);
6996 - cmd_params = (struct dprc_cmd_assign *)cmd.params;
6997 - cmd_params->container_id = cpu_to_le32(container_id);
6998 - cmd_params->options = cpu_to_le32(res_req->options);
6999 - cmd_params->num = cpu_to_le32(res_req->num);
7000 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
7001 - strncpy(cmd_params->type, res_req->type, 16);
7002 - cmd_params->type[15] = '\0';
7003 -
7004 - /* send command to mc*/
7005 - return mc_send_command(mc_io, &cmd);
7006 -}
7007 -
7008 -/**
7009 - * dprc_unassign() - Un-assigns objects or resources from a child container
7010 - * and moves them into this (parent) DPRC.
7011 - * @mc_io: Pointer to MC portal's I/O object
7012 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7013 - * @token: Token of DPRC object
7014 - * @child_container_id: ID of the child container
7015 - * @res_req: Describes the type and amount of resources to un-assign from
7016 - * the child container
7017 - *
7018 - * Un-assignment of objects can succeed only if the object is not in the
7019 - * plugged or opened state.
7020 - *
7021 - * Return: '0' on Success; Error code otherwise.
7022 - */
7023 -int dprc_unassign(struct fsl_mc_io *mc_io,
7024 - u32 cmd_flags,
7025 - u16 token,
7026 - int child_container_id,
7027 - struct dprc_res_req *res_req)
7028 -{
7029 - struct mc_command cmd = { 0 };
7030 - struct dprc_cmd_unassign *cmd_params;
7031 -
7032 - /* prepare command */
7033 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_UNASSIGN,
7034 - cmd_flags,
7035 - token);
7036 - cmd_params = (struct dprc_cmd_unassign *)cmd.params;
7037 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
7038 - cmd_params->options = cpu_to_le32(res_req->options);
7039 - cmd_params->num = cpu_to_le32(res_req->num);
7040 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
7041 - strncpy(cmd_params->type, res_req->type, 16);
7042 - cmd_params->type[15] = '\0';
7043 -
7044 - /* send command to mc*/
7045 - return mc_send_command(mc_io, &cmd);
7046 -}
7047 -
7048 -/**
7049 - * dprc_get_pool_count() - Get the number of dprc's pools
7050 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7051 - * @mc_io: Pointer to MC portal's I/O object
7052 - * @token: Token of DPRC object
7053 - * @pool_count: Returned number of resource pools in the dprc
7054 - *
7055 - * Return: '0' on Success; Error code otherwise.
7056 - */
7057 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
7058 - u32 cmd_flags,
7059 - u16 token,
7060 - int *pool_count)
7061 -{
7062 - struct mc_command cmd = { 0 };
7063 - struct dprc_rsp_get_pool_count *rsp_params;
7064 - int err;
7065 -
7066 - /* prepare command */
7067 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL_COUNT,
7068 - cmd_flags, token);
7069 -
7070 - /* send command to mc*/
7071 - err = mc_send_command(mc_io, &cmd);
7072 - if (err)
7073 - return err;
7074 -
7075 - /* retrieve response parameters */
7076 - rsp_params = (struct dprc_rsp_get_pool_count *)cmd.params;
7077 - *pool_count = le32_to_cpu(rsp_params->pool_count);
7078 -
7079 - return 0;
7080 -}
7081 -
7082 -/**
7083 - * dprc_get_pool() - Get the type (string) of a certain dprc's pool
7084 - * @mc_io: Pointer to MC portal's I/O object
7085 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7086 - * @token: Token of DPRC object
7087 - * @pool_index; Index of the pool to be queried (< pool_count)
7088 - * @type: The type of the pool
7089 - *
7090 - * The pool types retrieved one by one by incrementing
7091 - * pool_index up to (not including) the value of pool_count returned
7092 - * from dprc_get_pool_count(). dprc_get_pool_count() must
7093 - * be called prior to dprc_get_pool().
7094 - *
7095 - * Return: '0' on Success; Error code otherwise.
7096 - */
7097 -int dprc_get_pool(struct fsl_mc_io *mc_io,
7098 - u32 cmd_flags,
7099 - u16 token,
7100 - int pool_index,
7101 - char *type)
7102 -{
7103 - struct mc_command cmd = { 0 };
7104 - struct dprc_cmd_get_pool *cmd_params;
7105 - struct dprc_rsp_get_pool *rsp_params;
7106 - int err;
7107 -
7108 - /* prepare command */
7109 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL,
7110 - cmd_flags,
7111 - token);
7112 - cmd_params = (struct dprc_cmd_get_pool *)cmd.params;
7113 - cmd_params->pool_index = cpu_to_le32(pool_index);
7114 -
7115 - /* send command to mc*/
7116 - err = mc_send_command(mc_io, &cmd);
7117 - if (err)
7118 - return err;
7119 -
7120 - /* retrieve response parameters */
7121 - rsp_params = (struct dprc_rsp_get_pool *)cmd.params;
7122 - strncpy(type, rsp_params->type, 16);
7123 - type[15] = '\0';
7124
7125 return 0;
7126 }
7127 @@ -934,64 +574,6 @@ int dprc_get_obj(struct fsl_mc_io *mc_io
7128 EXPORT_SYMBOL(dprc_get_obj);
7129
7130 /**
7131 - * dprc_get_obj_desc() - Get object descriptor.
7132 - *
7133 - * @mc_io: Pointer to MC portal's I/O object
7134 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7135 - * @token: Token of DPRC object
7136 - * @obj_type: The type of the object to get its descriptor.
7137 - * @obj_id: The id of the object to get its descriptor
7138 - * @obj_desc: The returned descriptor to fill and return to the user
7139 - *
7140 - * Return: '0' on Success; Error code otherwise.
7141 - *
7142 - */
7143 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
7144 - u32 cmd_flags,
7145 - u16 token,
7146 - char *obj_type,
7147 - int obj_id,
7148 - struct dprc_obj_desc *obj_desc)
7149 -{
7150 - struct mc_command cmd = { 0 };
7151 - struct dprc_cmd_get_obj_desc *cmd_params;
7152 - struct dprc_rsp_get_obj_desc *rsp_params;
7153 - int err;
7154 -
7155 - /* prepare command */
7156 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_DESC,
7157 - cmd_flags,
7158 - token);
7159 - cmd_params = (struct dprc_cmd_get_obj_desc *)cmd.params;
7160 - cmd_params->obj_id = cpu_to_le32(obj_id);
7161 - strncpy(cmd_params->type, obj_type, 16);
7162 - cmd_params->type[15] = '\0';
7163 -
7164 - /* send command to mc*/
7165 - err = mc_send_command(mc_io, &cmd);
7166 - if (err)
7167 - return err;
7168 -
7169 - /* retrieve response parameters */
7170 - rsp_params = (struct dprc_rsp_get_obj_desc *)cmd.params;
7171 - obj_desc->id = le32_to_cpu(rsp_params->id);
7172 - obj_desc->vendor = le16_to_cpu(rsp_params->vendor);
7173 - obj_desc->irq_count = rsp_params->irq_count;
7174 - obj_desc->region_count = rsp_params->region_count;
7175 - obj_desc->state = le32_to_cpu(rsp_params->state);
7176 - obj_desc->ver_major = le16_to_cpu(rsp_params->version_major);
7177 - obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor);
7178 - obj_desc->flags = le16_to_cpu(rsp_params->flags);
7179 - strncpy(obj_desc->type, rsp_params->type, 16);
7180 - obj_desc->type[15] = '\0';
7181 - strncpy(obj_desc->label, rsp_params->label, 16);
7182 - obj_desc->label[15] = '\0';
7183 -
7184 - return 0;
7185 -}
7186 -EXPORT_SYMBOL(dprc_get_obj_desc);
7187 -
7188 -/**
7189 * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt.
7190 * @mc_io: Pointer to MC portal's I/O object
7191 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7192 @@ -1130,52 +712,6 @@ int dprc_get_res_count(struct fsl_mc_io
7193 EXPORT_SYMBOL(dprc_get_res_count);
7194
7195 /**
7196 - * dprc_get_res_ids() - Obtains IDs of free resources in the container
7197 - * @mc_io: Pointer to MC portal's I/O object
7198 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7199 - * @token: Token of DPRC object
7200 - * @type: pool type
7201 - * @range_desc: range descriptor
7202 - *
7203 - * Return: '0' on Success; Error code otherwise.
7204 - */
7205 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
7206 - u32 cmd_flags,
7207 - u16 token,
7208 - char *type,
7209 - struct dprc_res_ids_range_desc *range_desc)
7210 -{
7211 - struct mc_command cmd = { 0 };
7212 - struct dprc_cmd_get_res_ids *cmd_params;
7213 - struct dprc_rsp_get_res_ids *rsp_params;
7214 - int err;
7215 -
7216 - /* prepare command */
7217 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
7218 - cmd_flags, token);
7219 - cmd_params = (struct dprc_cmd_get_res_ids *)cmd.params;
7220 - cmd_params->iter_status = range_desc->iter_status;
7221 - cmd_params->base_id = cpu_to_le32(range_desc->base_id);
7222 - cmd_params->last_id = cpu_to_le32(range_desc->last_id);
7223 - strncpy(cmd_params->type, type, 16);
7224 - cmd_params->type[15] = '\0';
7225 -
7226 - /* send command to mc*/
7227 - err = mc_send_command(mc_io, &cmd);
7228 - if (err)
7229 - return err;
7230 -
7231 - /* retrieve response parameters */
7232 - rsp_params = (struct dprc_rsp_get_res_ids *)cmd.params;
7233 - range_desc->iter_status = rsp_params->iter_status;
7234 - range_desc->base_id = le32_to_cpu(rsp_params->base_id);
7235 - range_desc->last_id = le32_to_cpu(rsp_params->last_id);
7236 -
7237 - return 0;
7238 -}
7239 -EXPORT_SYMBOL(dprc_get_res_ids);
7240 -
7241 -/**
7242 * dprc_get_obj_region() - Get region information for a specified object.
7243 * @mc_io: Pointer to MC portal's I/O object
7244 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7245 @@ -1216,160 +752,66 @@ int dprc_get_obj_region(struct fsl_mc_io
7246
7247 /* retrieve response parameters */
7248 rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params;
7249 - region_desc->base_offset = le64_to_cpu(rsp_params->base_addr);
7250 + region_desc->base_offset = le32_to_cpu(rsp_params->base_addr);
7251 region_desc->size = le32_to_cpu(rsp_params->size);
7252 + region_desc->type = rsp_params->type;
7253 + region_desc->flags = le32_to_cpu(rsp_params->flags);
7254
7255 return 0;
7256 }
7257 EXPORT_SYMBOL(dprc_get_obj_region);
7258
7259 /**
7260 - * dprc_set_obj_label() - Set object label.
7261 - * @mc_io: Pointer to MC portal's I/O object
7262 + * dprc_get_api_version - Get Data Path Resource Container API version
7263 + * @mc_io: Pointer to Mc portal's I/O object
7264 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7265 - * @token: Token of DPRC object
7266 - * @obj_type: Object's type
7267 - * @obj_id: Object's ID
7268 - * @label: The required label. The maximum length is 16 chars.
7269 + * @major_ver: Major version of Data Path Resource Container API
7270 + * @minor_ver: Minor version of Data Path Resource Container API
7271 *
7272 * Return: '0' on Success; Error code otherwise.
7273 */
7274 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
7275 - u32 cmd_flags,
7276 - u16 token,
7277 - char *obj_type,
7278 - int obj_id,
7279 - char *label)
7280 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
7281 + u32 cmd_flags,
7282 + u16 *major_ver,
7283 + u16 *minor_ver)
7284 {
7285 struct mc_command cmd = { 0 };
7286 - struct dprc_cmd_set_obj_label *cmd_params;
7287 + int err;
7288
7289 /* prepare command */
7290 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_LABEL,
7291 - cmd_flags,
7292 - token);
7293 - cmd_params = (struct dprc_cmd_set_obj_label *)cmd.params;
7294 - cmd_params->obj_id = cpu_to_le32(obj_id);
7295 - strncpy(cmd_params->label, label, 16);
7296 - cmd_params->label[15] = '\0';
7297 - strncpy(cmd_params->obj_type, obj_type, 16);
7298 - cmd_params->obj_type[15] = '\0';
7299 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION,
7300 + cmd_flags, 0);
7301
7302 - /* send command to mc*/
7303 - return mc_send_command(mc_io, &cmd);
7304 -}
7305 -EXPORT_SYMBOL(dprc_set_obj_label);
7306 -
7307 -/**
7308 - * dprc_connect() - Connect two endpoints to create a network link between them
7309 - * @mc_io: Pointer to MC portal's I/O object
7310 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7311 - * @token: Token of DPRC object
7312 - * @endpoint1: Endpoint 1 configuration parameters
7313 - * @endpoint2: Endpoint 2 configuration parameters
7314 - * @cfg: Connection configuration. The connection configuration is ignored for
7315 - * connections made to DPMAC objects, where rate is retrieved from the
7316 - * MAC configuration.
7317 - *
7318 - * Return: '0' on Success; Error code otherwise.
7319 - */
7320 -int dprc_connect(struct fsl_mc_io *mc_io,
7321 - u32 cmd_flags,
7322 - u16 token,
7323 - const struct dprc_endpoint *endpoint1,
7324 - const struct dprc_endpoint *endpoint2,
7325 - const struct dprc_connection_cfg *cfg)
7326 -{
7327 - struct mc_command cmd = { 0 };
7328 - struct dprc_cmd_connect *cmd_params;
7329 + /* send command to mc */
7330 + err = mc_send_command(mc_io, &cmd);
7331 + if (err)
7332 + return err;
7333
7334 - /* prepare command */
7335 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
7336 - cmd_flags,
7337 - token);
7338 - cmd_params = (struct dprc_cmd_connect *)cmd.params;
7339 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7340 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7341 - cmd_params->ep2_id = cpu_to_le32(endpoint2->id);
7342 - cmd_params->ep2_interface_id = cpu_to_le32(endpoint2->if_id);
7343 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7344 - cmd_params->ep1_type[15] = '\0';
7345 - cmd_params->max_rate = cpu_to_le32(cfg->max_rate);
7346 - cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate);
7347 - strncpy(cmd_params->ep2_type, endpoint2->type, 16);
7348 - cmd_params->ep2_type[15] = '\0';
7349 + /* retrieve response parameters */
7350 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
7351
7352 - /* send command to mc*/
7353 - return mc_send_command(mc_io, &cmd);
7354 + return 0;
7355 }
7356
7357 /**
7358 - * dprc_disconnect() - Disconnect one endpoint to remove its network connection
7359 - * @mc_io: Pointer to MC portal's I/O object
7360 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7361 - * @token: Token of DPRC object
7362 - * @endpoint: Endpoint configuration parameters
7363 + * dprc_get_container_id - Get container ID associated with a given portal.
7364 + * @mc_io: Pointer to Mc portal's I/O object
7365 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7366 + * @container_id: Requested container id
7367 *
7368 * Return: '0' on Success; Error code otherwise.
7369 */
7370 -int dprc_disconnect(struct fsl_mc_io *mc_io,
7371 - u32 cmd_flags,
7372 - u16 token,
7373 - const struct dprc_endpoint *endpoint)
7374 -{
7375 - struct mc_command cmd = { 0 };
7376 - struct dprc_cmd_disconnect *cmd_params;
7377 -
7378 - /* prepare command */
7379 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
7380 - cmd_flags,
7381 - token);
7382 - cmd_params = (struct dprc_cmd_disconnect *)cmd.params;
7383 - cmd_params->id = cpu_to_le32(endpoint->id);
7384 - cmd_params->interface_id = cpu_to_le32(endpoint->if_id);
7385 - strncpy(cmd_params->type, endpoint->type, 16);
7386 - cmd_params->type[15] = '\0';
7387 -
7388 - /* send command to mc*/
7389 - return mc_send_command(mc_io, &cmd);
7390 -}
7391 -
7392 -/**
7393 - * dprc_get_connection() - Get connected endpoint and link status if connection
7394 - * exists.
7395 - * @mc_io: Pointer to MC portal's I/O object
7396 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7397 - * @token: Token of DPRC object
7398 - * @endpoint1: Endpoint 1 configuration parameters
7399 - * @endpoint2: Returned endpoint 2 configuration parameters
7400 - * @state: Returned link state:
7401 - * 1 - link is up;
7402 - * 0 - link is down;
7403 - * -1 - no connection (endpoint2 information is irrelevant)
7404 - *
7405 - * Return: '0' on Success; -ENAVAIL if connection does not exist.
7406 - */
7407 -int dprc_get_connection(struct fsl_mc_io *mc_io,
7408 - u32 cmd_flags,
7409 - u16 token,
7410 - const struct dprc_endpoint *endpoint1,
7411 - struct dprc_endpoint *endpoint2,
7412 - int *state)
7413 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
7414 + u32 cmd_flags,
7415 + int *container_id)
7416 {
7417 struct mc_command cmd = { 0 };
7418 - struct dprc_cmd_get_connection *cmd_params;
7419 - struct dprc_rsp_get_connection *rsp_params;
7420 int err;
7421
7422 /* prepare command */
7423 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
7424 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
7425 cmd_flags,
7426 - token);
7427 - cmd_params = (struct dprc_cmd_get_connection *)cmd.params;
7428 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7429 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7430 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7431 - cmd_params->ep1_type[15] = '\0';
7432 + 0);
7433
7434 /* send command to mc*/
7435 err = mc_send_command(mc_io, &cmd);
7436 @@ -1377,12 +819,7 @@ int dprc_get_connection(struct fsl_mc_io
7437 return err;
7438
7439 /* retrieve response parameters */
7440 - rsp_params = (struct dprc_rsp_get_connection *)cmd.params;
7441 - endpoint2->id = le32_to_cpu(rsp_params->ep2_id);
7442 - endpoint2->if_id = le32_to_cpu(rsp_params->ep2_interface_id);
7443 - strncpy(endpoint2->type, rsp_params->ep2_type, 16);
7444 - endpoint2->type[15] = '\0';
7445 - *state = le32_to_cpu(rsp_params->state);
7446 + *container_id = (int)mc_cmd_read_object_id(&cmd);
7447
7448 return 0;
7449 }
7450 --- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7451 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7452 @@ -1,7 +1,7 @@
7453 /*
7454 - * Freescale MC object device allocator driver
7455 + * fsl-mc object allocator driver
7456 *
7457 - * Copyright (C) 2013 Freescale Semiconductor, Inc.
7458 + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
7459 *
7460 * This file is licensed under the terms of the GNU General Public
7461 * License version 2. This program is licensed "as is" without any
7462 @@ -12,9 +12,9 @@
7463 #include <linux/msi.h>
7464 #include "../include/mc-bus.h"
7465 #include "../include/mc-sys.h"
7466 -#include "../include/dpbp-cmd.h"
7467 -#include "../include/dpcon-cmd.h"
7468
7469 +#include "dpbp-cmd.h"
7470 +#include "dpcon-cmd.h"
7471 #include "fsl-mc-private.h"
7472
7473 #define FSL_MC_IS_ALLOCATABLE(_obj_type) \
7474 @@ -23,15 +23,12 @@
7475 strcmp(_obj_type, "dpcon") == 0)
7476
7477 /**
7478 - * fsl_mc_resource_pool_add_device - add allocatable device to a resource
7479 - * pool of a given MC bus
7480 + * fsl_mc_resource_pool_add_device - add allocatable object to a resource
7481 + * pool of a given fsl-mc bus
7482 *
7483 - * @mc_bus: pointer to the MC bus
7484 - * @pool_type: MC bus pool type
7485 - * @mc_dev: Pointer to allocatable MC object device
7486 - *
7487 - * It adds an allocatable MC object device to a container's resource pool of
7488 - * the given resource type
7489 + * @mc_bus: pointer to the fsl-mc bus
7490 + * @pool_type: pool type
7491 + * @mc_dev: pointer to allocatable fsl-mc device
7492 */
7493 static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus
7494 *mc_bus,
7495 @@ -95,10 +92,10 @@ out:
7496 * fsl_mc_resource_pool_remove_device - remove an allocatable device from a
7497 * resource pool
7498 *
7499 - * @mc_dev: Pointer to allocatable MC object device
7500 + * @mc_dev: pointer to allocatable fsl-mc device
7501 *
7502 - * It permanently removes an allocatable MC object device from the resource
7503 - * pool, the device is currently in, as long as it is in the pool's free list.
7504 + * It permanently removes an allocatable fsl-mc device from the resource
7505 + * pool. It's an error if the device is in use.
7506 */
7507 static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device
7508 *mc_dev)
7509 @@ -255,17 +252,18 @@ out_unlock:
7510 EXPORT_SYMBOL_GPL(fsl_mc_resource_free);
7511
7512 /**
7513 - * fsl_mc_object_allocate - Allocates a MC object device of the given
7514 - * pool type from a given MC bus
7515 + * fsl_mc_object_allocate - Allocates an fsl-mc object of the given
7516 + * pool type from a given fsl-mc bus instance
7517 *
7518 - * @mc_dev: MC device for which the MC object device is to be allocated
7519 - * @pool_type: MC bus resource pool type
7520 - * @new_mc_dev: Pointer to area where the pointer to the allocated
7521 - * MC object device is to be returned
7522 + * @mc_dev: fsl-mc device which is used in conjunction with the
7523 + * allocated object
7524 + * @pool_type: pool type
7525 + * @new_mc_dev: pointer to area where the pointer to the allocated device
7526 + * is to be returned
7527 *
7528 - * This function allocates a MC object device from the device's parent DPRC,
7529 - * from the corresponding MC bus' pool of allocatable MC object devices of
7530 - * the given resource type. mc_dev cannot be a DPRC itself.
7531 + * Allocatable objects are always used in conjunction with some functional
7532 + * device. This function allocates an object of the specified type from
7533 + * the DPRC containing the functional device.
7534 *
7535 * NOTE: pool_type must be different from FSL_MC_POOL_MCP, since MC
7536 * portals are allocated using fsl_mc_portal_allocate(), instead of
7537 @@ -312,10 +310,9 @@ error:
7538 EXPORT_SYMBOL_GPL(fsl_mc_object_allocate);
7539
7540 /**
7541 - * fsl_mc_object_free - Returns an allocatable MC object device to the
7542 - * corresponding resource pool of a given MC bus.
7543 - *
7544 - * @mc_adev: Pointer to the MC object device
7545 + * fsl_mc_object_free - Returns an fsl-mc object to the resource
7546 + * pool where it came from.
7547 + * @mc_adev: Pointer to the fsl-mc device
7548 */
7549 void fsl_mc_object_free(struct fsl_mc_device *mc_adev)
7550 {
7551 @@ -332,8 +329,14 @@ void fsl_mc_object_free(struct fsl_mc_de
7552 EXPORT_SYMBOL_GPL(fsl_mc_object_free);
7553
7554 /*
7555 - * Initialize the interrupt pool associated with a MC bus.
7556 - * It allocates a block of IRQs from the GIC-ITS
7557 + * A DPRC and the devices in the DPRC all share the same GIC-ITS device
7558 + * ID. A block of IRQs is pre-allocated and maintained in a pool
7559 + * from which devices can allocate them when needed.
7560 + */
7561 +
7562 +/*
7563 + * Initialize the interrupt pool associated with an fsl-mc bus.
7564 + * It allocates a block of IRQs from the GIC-ITS.
7565 */
7566 int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus,
7567 unsigned int irq_count)
7568 @@ -395,7 +398,7 @@ cleanup_msi_irqs:
7569 EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool);
7570
7571 /**
7572 - * Teardown the interrupt pool associated with an MC bus.
7573 + * Teardown the interrupt pool associated with an fsl-mc bus.
7574 * It frees the IRQs that were allocated to the pool, back to the GIC-ITS.
7575 */
7576 void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus)
7577 @@ -422,11 +425,7 @@ void fsl_mc_cleanup_irq_pool(struct fsl_
7578 EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool);
7579
7580 /**
7581 - * It allocates the IRQs required by a given MC object device. The
7582 - * IRQs are allocated from the interrupt pool associated with the
7583 - * MC bus that contains the device, if the device is not a DPRC device.
7584 - * Otherwise, the IRQs are allocated from the interrupt pool associated
7585 - * with the MC bus that represents the DPRC device itself.
7586 + * Allocate the IRQs required by a given fsl-mc device.
7587 */
7588 int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev)
7589 {
7590 @@ -495,8 +494,7 @@ error_resource_alloc:
7591 EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs);
7592
7593 /*
7594 - * It frees the IRQs that were allocated for a MC object device, by
7595 - * returning them to the corresponding interrupt pool.
7596 + * Frees the IRQs that were allocated for an fsl-mc device.
7597 */
7598 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev)
7599 {
7600 @@ -605,7 +603,7 @@ static int fsl_mc_allocator_probe(struct
7601 return error;
7602
7603 dev_dbg(&mc_dev->dev,
7604 - "Allocatable MC object device bound to fsl_mc_allocator driver");
7605 + "Allocatable fsl-mc device bound to fsl_mc_allocator driver");
7606 return 0;
7607 }
7608
7609 @@ -627,7 +625,7 @@ static int fsl_mc_allocator_remove(struc
7610 }
7611
7612 dev_dbg(&mc_dev->dev,
7613 - "Allocatable MC object device unbound from fsl_mc_allocator driver");
7614 + "Allocatable fsl-mc device unbound from fsl_mc_allocator driver");
7615 return 0;
7616 }
7617
7618 --- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7619 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7620 @@ -1,7 +1,7 @@
7621 /*
7622 * Freescale Management Complex (MC) bus driver
7623 *
7624 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
7625 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
7626 * Author: German Rivera <German.Rivera@freescale.com>
7627 *
7628 * This file is licensed under the terms of the GNU General Public
7629 @@ -9,6 +9,8 @@
7630 * warranty of any kind, whether express or implied.
7631 */
7632
7633 +#define pr_fmt(fmt) "fsl-mc: " fmt
7634 +
7635 #include <linux/module.h>
7636 #include <linux/of_device.h>
7637 #include <linux/of_address.h>
7638 @@ -25,8 +27,6 @@
7639 #include "fsl-mc-private.h"
7640 #include "dprc-cmd.h"
7641
7642 -static struct kmem_cache *mc_dev_cache;
7643 -
7644 /**
7645 * Default DMA mask for devices on a fsl-mc bus
7646 */
7647 @@ -34,7 +34,7 @@ static struct kmem_cache *mc_dev_cache;
7648
7649 /**
7650 * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
7651 - * @root_mc_bus_dev: MC object device representing the root DPRC
7652 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
7653 * @num_translation_ranges: number of entries in addr_translation_ranges
7654 * @translation_ranges: array of bus to system address translation ranges
7655 */
7656 @@ -62,8 +62,8 @@ struct fsl_mc_addr_translation_range {
7657
7658 /**
7659 * fsl_mc_bus_match - device to driver matching callback
7660 - * @dev: the MC object device structure to match against
7661 - * @drv: the device driver to search for matching MC object device id
7662 + * @dev: the fsl-mc device to match against
7663 + * @drv: the device driver to search for matching fsl-mc object type
7664 * structures
7665 *
7666 * Returns 1 on success, 0 otherwise.
7667 @@ -75,8 +75,11 @@ static int fsl_mc_bus_match(struct devic
7668 struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv);
7669 bool found = false;
7670
7671 - if (WARN_ON(!fsl_mc_bus_exists()))
7672 + /* When driver_override is set, only bind to the matching driver */
7673 + if (mc_dev->driver_override) {
7674 + found = !strcmp(mc_dev->driver_override, mc_drv->driver.name);
7675 goto out;
7676 + }
7677
7678 if (!mc_drv->match_id_table)
7679 goto out;
7680 @@ -91,7 +94,7 @@ static int fsl_mc_bus_match(struct devic
7681
7682 /*
7683 * Traverse the match_id table of the given driver, trying to find
7684 - * a matching for the given MC object device.
7685 + * a matching for the given device.
7686 */
7687 for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) {
7688 if (id->vendor == mc_dev->obj_desc.vendor &&
7689 @@ -132,23 +135,141 @@ static ssize_t modalias_show(struct devi
7690 }
7691 static DEVICE_ATTR_RO(modalias);
7692
7693 +static ssize_t rescan_store(struct device *dev,
7694 + struct device_attribute *attr,
7695 + const char *buf, size_t count)
7696 +{
7697 + unsigned long val;
7698 + unsigned int irq_count;
7699 + struct fsl_mc_device *root_mc_dev;
7700 + struct fsl_mc_bus *root_mc_bus;
7701 +
7702 + if (!fsl_mc_is_root_dprc(dev))
7703 + return -EINVAL;
7704 +
7705 + root_mc_dev = to_fsl_mc_device(dev);
7706 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7707 +
7708 + if (kstrtoul(buf, 0, &val) < 0)
7709 + return -EINVAL;
7710 +
7711 + if (val) {
7712 + mutex_lock(&root_mc_bus->scan_mutex);
7713 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7714 + mutex_unlock(&root_mc_bus->scan_mutex);
7715 + }
7716 +
7717 + return count;
7718 +}
7719 +static DEVICE_ATTR_WO(rescan);
7720 +
7721 +static ssize_t driver_override_store(struct device *dev,
7722 + struct device_attribute *attr,
7723 + const char *buf, size_t count)
7724 +{
7725 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7726 + const char *driver_override, *old = mc_dev->driver_override;
7727 + char *cp;
7728 +
7729 + if (WARN_ON(dev->bus != &fsl_mc_bus_type))
7730 + return -EINVAL;
7731 +
7732 + if (count >= (PAGE_SIZE - 1))
7733 + return -EINVAL;
7734 +
7735 + driver_override = kstrndup(buf, count, GFP_KERNEL);
7736 + if (!driver_override)
7737 + return -ENOMEM;
7738 +
7739 + cp = strchr(driver_override, '\n');
7740 + if (cp)
7741 + *cp = '\0';
7742 +
7743 + if (strlen(driver_override)) {
7744 + mc_dev->driver_override = driver_override;
7745 + } else {
7746 + kfree(driver_override);
7747 + mc_dev->driver_override = NULL;
7748 + }
7749 +
7750 + kfree(old);
7751 +
7752 + return count;
7753 +}
7754 +
7755 +static ssize_t driver_override_show(struct device *dev,
7756 + struct device_attribute *attr, char *buf)
7757 +{
7758 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7759 +
7760 + return snprintf(buf, PAGE_SIZE, "%s\n", mc_dev->driver_override);
7761 +}
7762 +static DEVICE_ATTR_RW(driver_override);
7763 +
7764 static struct attribute *fsl_mc_dev_attrs[] = {
7765 &dev_attr_modalias.attr,
7766 + &dev_attr_rescan.attr,
7767 + &dev_attr_driver_override.attr,
7768 NULL,
7769 };
7770
7771 ATTRIBUTE_GROUPS(fsl_mc_dev);
7772
7773 +static int scan_fsl_mc_bus(struct device *dev, void *data)
7774 +{
7775 + unsigned int irq_count;
7776 + struct fsl_mc_device *root_mc_dev;
7777 + struct fsl_mc_bus *root_mc_bus;
7778 +
7779 + if (fsl_mc_is_root_dprc(dev)) {
7780 + root_mc_dev = to_fsl_mc_device(dev);
7781 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7782 + mutex_lock(&root_mc_bus->scan_mutex);
7783 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7784 + mutex_unlock(&root_mc_bus->scan_mutex);
7785 + }
7786 +
7787 + return 0;
7788 +}
7789 +
7790 +static ssize_t bus_rescan_store(struct bus_type *bus,
7791 + const char *buf, size_t count)
7792 +{
7793 + unsigned long val;
7794 +
7795 + if (kstrtoul(buf, 0, &val) < 0)
7796 + return -EINVAL;
7797 +
7798 + if (val)
7799 + bus_for_each_dev(bus, NULL, NULL, scan_fsl_mc_bus);
7800 +
7801 + return count;
7802 +}
7803 +static BUS_ATTR(rescan, (S_IWUSR | S_IWGRP), NULL, bus_rescan_store);
7804 +
7805 +static struct attribute *fsl_mc_bus_attrs[] = {
7806 + &bus_attr_rescan.attr,
7807 + NULL,
7808 +};
7809 +
7810 +static const struct attribute_group fsl_mc_bus_group = {
7811 + .attrs = fsl_mc_bus_attrs,
7812 +};
7813 +
7814 +static const struct attribute_group *fsl_mc_bus_groups[] = {
7815 + &fsl_mc_bus_group,
7816 + NULL,
7817 +};
7818 +
7819 struct bus_type fsl_mc_bus_type = {
7820 .name = "fsl-mc",
7821 .match = fsl_mc_bus_match,
7822 .uevent = fsl_mc_bus_uevent,
7823 .dev_groups = fsl_mc_dev_groups,
7824 + .bus_groups = fsl_mc_bus_groups,
7825 };
7826 EXPORT_SYMBOL_GPL(fsl_mc_bus_type);
7827
7828 -static atomic_t root_dprc_count = ATOMIC_INIT(0);
7829 -
7830 static int fsl_mc_driver_probe(struct device *dev)
7831 {
7832 struct fsl_mc_driver *mc_drv;
7833 @@ -164,8 +285,7 @@ static int fsl_mc_driver_probe(struct de
7834
7835 error = mc_drv->probe(mc_dev);
7836 if (error < 0) {
7837 - dev_err(dev, "MC object device probe callback failed: %d\n",
7838 - error);
7839 + dev_err(dev, "%s failed: %d\n", __func__, error);
7840 return error;
7841 }
7842
7843 @@ -183,9 +303,7 @@ static int fsl_mc_driver_remove(struct d
7844
7845 error = mc_drv->remove(mc_dev);
7846 if (error < 0) {
7847 - dev_err(dev,
7848 - "MC object device remove callback failed: %d\n",
7849 - error);
7850 + dev_err(dev, "%s failed: %d\n", __func__, error);
7851 return error;
7852 }
7853
7854 @@ -232,8 +350,6 @@ int __fsl_mc_driver_register(struct fsl_
7855 return error;
7856 }
7857
7858 - pr_info("MC object device driver %s registered\n",
7859 - mc_driver->driver.name);
7860 return 0;
7861 }
7862 EXPORT_SYMBOL_GPL(__fsl_mc_driver_register);
7863 @@ -249,15 +365,6 @@ void fsl_mc_driver_unregister(struct fsl
7864 EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister);
7865
7866 /**
7867 - * fsl_mc_bus_exists - check if a root dprc exists
7868 - */
7869 -bool fsl_mc_bus_exists(void)
7870 -{
7871 - return atomic_read(&root_dprc_count) > 0;
7872 -}
7873 -EXPORT_SYMBOL_GPL(fsl_mc_bus_exists);
7874 -
7875 -/**
7876 * fsl_mc_get_root_dprc - function to traverse to the root dprc
7877 */
7878 void fsl_mc_get_root_dprc(struct device *dev,
7879 @@ -315,21 +422,6 @@ static int get_dprc_icid(struct fsl_mc_i
7880 return error;
7881 }
7882
7883 -static int get_dprc_version(struct fsl_mc_io *mc_io,
7884 - int container_id, u16 *major, u16 *minor)
7885 -{
7886 - struct dprc_attributes attr;
7887 - int error;
7888 -
7889 - error = get_dprc_attr(mc_io, container_id, &attr);
7890 - if (error == 0) {
7891 - *major = attr.version.major;
7892 - *minor = attr.version.minor;
7893 - }
7894 -
7895 - return error;
7896 -}
7897 -
7898 static int translate_mc_addr(struct fsl_mc_device *mc_dev,
7899 enum dprc_region_type mc_region_type,
7900 u64 mc_offset, phys_addr_t *phys_addr)
7901 @@ -451,18 +543,37 @@ bool fsl_mc_is_root_dprc(struct device *
7902 return dev == root_dprc_dev;
7903 }
7904
7905 +static void fsl_mc_device_release(struct device *dev)
7906 +{
7907 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7908 + struct fsl_mc_bus *mc_bus = NULL;
7909 +
7910 + kfree(mc_dev->regions);
7911 +
7912 + if (strcmp(mc_dev->obj_desc.type, "dprc") == 0)
7913 + mc_bus = to_fsl_mc_bus(mc_dev);
7914 +
7915 + if (mc_bus)
7916 + kfree(mc_bus);
7917 + else
7918 + kfree(mc_dev);
7919 +}
7920 +
7921 /**
7922 - * Add a newly discovered MC object device to be visible in Linux
7923 + * Add a newly discovered fsl-mc device to be visible in Linux
7924 */
7925 int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
7926 struct fsl_mc_io *mc_io,
7927 struct device *parent_dev,
7928 + const char *driver_override,
7929 struct fsl_mc_device **new_mc_dev)
7930 {
7931 int error;
7932 struct fsl_mc_device *mc_dev = NULL;
7933 struct fsl_mc_bus *mc_bus = NULL;
7934 struct fsl_mc_device *parent_mc_dev;
7935 + struct device *fsl_mc_platform_dev;
7936 + struct device_node *fsl_mc_platform_node;
7937
7938 if (dev_is_fsl_mc(parent_dev))
7939 parent_mc_dev = to_fsl_mc_device(parent_dev);
7940 @@ -473,7 +584,7 @@ int fsl_mc_device_add(struct dprc_obj_de
7941 /*
7942 * Allocate an MC bus device object:
7943 */
7944 - mc_bus = devm_kzalloc(parent_dev, sizeof(*mc_bus), GFP_KERNEL);
7945 + mc_bus = kzalloc(sizeof(*mc_bus), GFP_KERNEL);
7946 if (!mc_bus)
7947 return -ENOMEM;
7948
7949 @@ -482,16 +593,30 @@ int fsl_mc_device_add(struct dprc_obj_de
7950 /*
7951 * Allocate a regular fsl_mc_device object:
7952 */
7953 - mc_dev = kmem_cache_zalloc(mc_dev_cache, GFP_KERNEL);
7954 + mc_dev = kzalloc(sizeof(*mc_dev), GFP_KERNEL);
7955 if (!mc_dev)
7956 return -ENOMEM;
7957 }
7958
7959 mc_dev->obj_desc = *obj_desc;
7960 mc_dev->mc_io = mc_io;
7961 +
7962 + if (driver_override) {
7963 + /*
7964 + * We trust driver_override, so we don't need to use
7965 + * kstrndup() here
7966 + */
7967 + mc_dev->driver_override = kstrdup(driver_override, GFP_KERNEL);
7968 + if (!mc_dev->driver_override) {
7969 + error = -ENOMEM;
7970 + goto error_cleanup_dev;
7971 + }
7972 + }
7973 +
7974 device_initialize(&mc_dev->dev);
7975 mc_dev->dev.parent = parent_dev;
7976 mc_dev->dev.bus = &fsl_mc_bus_type;
7977 + mc_dev->dev.release = fsl_mc_device_release;
7978 dev_set_name(&mc_dev->dev, "%s.%d", obj_desc->type, obj_desc->id);
7979
7980 if (strcmp(obj_desc->type, "dprc") == 0) {
7981 @@ -524,8 +649,6 @@ int fsl_mc_device_add(struct dprc_obj_de
7982 }
7983
7984 mc_io2 = mc_io;
7985 -
7986 - atomic_inc(&root_dprc_count);
7987 }
7988
7989 error = get_dprc_icid(mc_io2, obj_desc->id, &mc_dev->icid);
7990 @@ -533,8 +656,8 @@ int fsl_mc_device_add(struct dprc_obj_de
7991 goto error_cleanup_dev;
7992 } else {
7993 /*
7994 - * A non-DPRC MC object device has to be a child of another
7995 - * MC object (specifically a DPRC object)
7996 + * A non-DPRC object has to be a child of a DPRC, use the
7997 + * parent's ICID and interrupt domain.
7998 */
7999 mc_dev->icid = parent_mc_dev->icid;
8000 mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK;
8001 @@ -556,9 +679,14 @@ int fsl_mc_device_add(struct dprc_obj_de
8002 goto error_cleanup_dev;
8003 }
8004
8005 - /* Objects are coherent, unless 'no shareability' flag set. */
8006 - if (!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY))
8007 - arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true);
8008 + fsl_mc_platform_dev = &mc_dev->dev;
8009 + while (dev_is_fsl_mc(fsl_mc_platform_dev))
8010 + fsl_mc_platform_dev = fsl_mc_platform_dev->parent;
8011 + fsl_mc_platform_node = fsl_mc_platform_dev->of_node;
8012 +
8013 + /* Set up the iommu configuration for the devices. */
8014 + fsl_mc_dma_configure(mc_dev, fsl_mc_platform_node,
8015 + !(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY));
8016
8017 /*
8018 * The device-specific probe callback will get invoked by device_add()
8019 @@ -571,9 +699,7 @@ int fsl_mc_device_add(struct dprc_obj_de
8020 goto error_cleanup_dev;
8021 }
8022
8023 - (void)get_device(&mc_dev->dev);
8024 - dev_dbg(parent_dev, "Added MC object device %s\n",
8025 - dev_name(&mc_dev->dev));
8026 + dev_dbg(parent_dev, "added %s\n", dev_name(&mc_dev->dev));
8027
8028 *new_mc_dev = mc_dev;
8029 return 0;
8030 @@ -581,47 +707,34 @@ int fsl_mc_device_add(struct dprc_obj_de
8031 error_cleanup_dev:
8032 kfree(mc_dev->regions);
8033 if (mc_bus)
8034 - devm_kfree(parent_dev, mc_bus);
8035 + kfree(mc_bus);
8036 else
8037 - kmem_cache_free(mc_dev_cache, mc_dev);
8038 + kfree(mc_dev);
8039
8040 return error;
8041 }
8042 EXPORT_SYMBOL_GPL(fsl_mc_device_add);
8043
8044 /**
8045 - * fsl_mc_device_remove - Remove a MC object device from being visible to
8046 + * fsl_mc_device_remove - Remove an fsl-mc device from being visible to
8047 * Linux
8048 *
8049 - * @mc_dev: Pointer to a MC object device object
8050 + * @mc_dev: Pointer to an fsl-mc device
8051 */
8052 void fsl_mc_device_remove(struct fsl_mc_device *mc_dev)
8053 {
8054 - struct fsl_mc_bus *mc_bus = NULL;
8055 -
8056 - kfree(mc_dev->regions);
8057 + kfree(mc_dev->driver_override);
8058 + mc_dev->driver_override = NULL;
8059
8060 /*
8061 * The device-specific remove callback will get invoked by device_del()
8062 */
8063 device_del(&mc_dev->dev);
8064 - put_device(&mc_dev->dev);
8065
8066 - if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) {
8067 - mc_bus = to_fsl_mc_bus(mc_dev);
8068 -
8069 - if (fsl_mc_is_root_dprc(&mc_dev->dev)) {
8070 - if (atomic_read(&root_dprc_count) > 0)
8071 - atomic_dec(&root_dprc_count);
8072 - else
8073 - WARN_ON(1);
8074 - }
8075 - }
8076 + if (strcmp(mc_dev->obj_desc.type, "dprc") != 0)
8077 + mc_dev->dev.iommu_fwspec = NULL;
8078
8079 - if (mc_bus)
8080 - devm_kfree(mc_dev->dev.parent, mc_bus);
8081 - else
8082 - kmem_cache_free(mc_dev_cache, mc_dev);
8083 + put_device(&mc_dev->dev);
8084 }
8085 EXPORT_SYMBOL_GPL(fsl_mc_device_remove);
8086
8087 @@ -629,8 +742,7 @@ static int parse_mc_ranges(struct device
8088 int *paddr_cells,
8089 int *mc_addr_cells,
8090 int *mc_size_cells,
8091 - const __be32 **ranges_start,
8092 - u8 *num_ranges)
8093 + const __be32 **ranges_start)
8094 {
8095 const __be32 *prop;
8096 int range_tuple_cell_count;
8097 @@ -643,8 +755,6 @@ static int parse_mc_ranges(struct device
8098 dev_warn(dev,
8099 "missing or empty ranges property for device tree node '%s'\n",
8100 mc_node->name);
8101 -
8102 - *num_ranges = 0;
8103 return 0;
8104 }
8105
8106 @@ -671,8 +781,7 @@ static int parse_mc_ranges(struct device
8107 return -EINVAL;
8108 }
8109
8110 - *num_ranges = ranges_len / tuple_len;
8111 - return 0;
8112 + return ranges_len / tuple_len;
8113 }
8114
8115 static int get_mc_addr_translation_ranges(struct device *dev,
8116 @@ -680,7 +789,7 @@ static int get_mc_addr_translation_range
8117 **ranges,
8118 u8 *num_ranges)
8119 {
8120 - int error;
8121 + int ret;
8122 int paddr_cells;
8123 int mc_addr_cells;
8124 int mc_size_cells;
8125 @@ -688,16 +797,16 @@ static int get_mc_addr_translation_range
8126 const __be32 *ranges_start;
8127 const __be32 *cell;
8128
8129 - error = parse_mc_ranges(dev,
8130 + ret = parse_mc_ranges(dev,
8131 &paddr_cells,
8132 &mc_addr_cells,
8133 &mc_size_cells,
8134 - &ranges_start,
8135 - num_ranges);
8136 - if (error < 0)
8137 - return error;
8138 + &ranges_start);
8139 + if (ret < 0)
8140 + return ret;
8141
8142 - if (!(*num_ranges)) {
8143 + *num_ranges = ret;
8144 + if (!ret) {
8145 /*
8146 * Missing or empty ranges property ("ranges;") for the
8147 * 'fsl,qoriq-mc' node. In this case, identity mapping
8148 @@ -749,8 +858,6 @@ static int fsl_mc_bus_probe(struct platf
8149 struct mc_version mc_version;
8150 struct resource res;
8151
8152 - dev_info(&pdev->dev, "Root MC bus device probed");
8153 -
8154 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
8155 if (!mc)
8156 return -ENOMEM;
8157 @@ -783,8 +890,7 @@ static int fsl_mc_bus_probe(struct platf
8158 goto error_cleanup_mc_io;
8159 }
8160
8161 - dev_info(&pdev->dev,
8162 - "Freescale Management Complex Firmware version: %u.%u.%u\n",
8163 + dev_info(&pdev->dev, "MC firmware version: %u.%u.%u\n",
8164 mc_version.major, mc_version.minor, mc_version.revision);
8165
8166 error = get_mc_addr_translation_ranges(&pdev->dev,
8167 @@ -793,16 +899,17 @@ static int fsl_mc_bus_probe(struct platf
8168 if (error < 0)
8169 goto error_cleanup_mc_io;
8170
8171 - error = dpmng_get_container_id(mc_io, 0, &container_id);
8172 + error = dprc_get_container_id(mc_io, 0, &container_id);
8173 if (error < 0) {
8174 dev_err(&pdev->dev,
8175 - "dpmng_get_container_id() failed: %d\n", error);
8176 + "dprc_get_container_id() failed: %d\n", error);
8177 goto error_cleanup_mc_io;
8178 }
8179
8180 memset(&obj_desc, 0, sizeof(struct dprc_obj_desc));
8181 - error = get_dprc_version(mc_io, container_id,
8182 - &obj_desc.ver_major, &obj_desc.ver_minor);
8183 + error = dprc_get_api_version(mc_io, 0,
8184 + &obj_desc.ver_major,
8185 + &obj_desc.ver_minor);
8186 if (error < 0)
8187 goto error_cleanup_mc_io;
8188
8189 @@ -812,7 +919,8 @@ static int fsl_mc_bus_probe(struct platf
8190 obj_desc.irq_count = 1;
8191 obj_desc.region_count = 0;
8192
8193 - error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev);
8194 + error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, NULL,
8195 + &mc_bus_dev);
8196 if (error < 0)
8197 goto error_cleanup_mc_io;
8198
8199 @@ -840,7 +948,6 @@ static int fsl_mc_bus_remove(struct plat
8200 fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io);
8201 mc->root_mc_bus_dev->mc_io = NULL;
8202
8203 - dev_info(&pdev->dev, "Root MC bus device removed");
8204 return 0;
8205 }
8206
8207 @@ -865,22 +972,12 @@ static int __init fsl_mc_bus_driver_init
8208 {
8209 int error;
8210
8211 - mc_dev_cache = kmem_cache_create("fsl_mc_device",
8212 - sizeof(struct fsl_mc_device), 0, 0,
8213 - NULL);
8214 - if (!mc_dev_cache) {
8215 - pr_err("Could not create fsl_mc_device cache\n");
8216 - return -ENOMEM;
8217 - }
8218 -
8219 error = bus_register(&fsl_mc_bus_type);
8220 if (error < 0) {
8221 - pr_err("fsl-mc bus type registration failed: %d\n", error);
8222 + pr_err("bus type registration failed: %d\n", error);
8223 goto error_cleanup_cache;
8224 }
8225
8226 - pr_info("fsl-mc bus type registered\n");
8227 -
8228 error = platform_driver_register(&fsl_mc_bus_driver);
8229 if (error < 0) {
8230 pr_err("platform_driver_register() failed: %d\n", error);
8231 @@ -914,7 +1011,6 @@ error_cleanup_bus:
8232 bus_unregister(&fsl_mc_bus_type);
8233
8234 error_cleanup_cache:
8235 - kmem_cache_destroy(mc_dev_cache);
8236 return error;
8237 }
8238 postcore_initcall(fsl_mc_bus_driver_init);
8239 --- /dev/null
8240 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
8241 @@ -0,0 +1,104 @@
8242 +/*
8243 + * Copyright 2016-17 NXP
8244 + * Author: Nipun Gupta <nipun.gupta@nxp.com>
8245 + *
8246 + * This file is licensed under the terms of the GNU General Public
8247 + * License version 2. This program is licensed "as is" without any
8248 + * warranty of any kind, whether express or implied.
8249 + */
8250 +
8251 +#include <linux/iommu.h>
8252 +#include <linux/of.h>
8253 +#include <linux/of_iommu.h>
8254 +#include "../include/mc.h"
8255 +
8256 +/* Setup the IOMMU for the DPRC container */
8257 +static const struct iommu_ops
8258 +*fsl_mc_iommu_configure(struct fsl_mc_device *mc_dev,
8259 + struct device_node *fsl_mc_platform_node)
8260 +{
8261 + struct of_phandle_args iommu_spec;
8262 + const struct iommu_ops *ops;
8263 + u32 iommu_phandle;
8264 + struct device_node *iommu_node;
8265 + const __be32 *map = NULL;
8266 + int iommu_cells, map_len, ret;
8267 +
8268 + map = of_get_property(fsl_mc_platform_node, "iommu-map", &map_len);
8269 + if (!map)
8270 + return NULL;
8271 +
8272 + ops = mc_dev->dev.bus->iommu_ops;
8273 + if (!ops || !ops->of_xlate)
8274 + return NULL;
8275 +
8276 + iommu_phandle = be32_to_cpup(map + 1);
8277 + iommu_node = of_find_node_by_phandle(iommu_phandle);
8278 +
8279 + if (of_property_read_u32(iommu_node, "#iommu-cells", &iommu_cells)) {
8280 + pr_err("%s: missing #iommu-cells property\n", iommu_node->name);
8281 + return NULL;
8282 + }
8283 +
8284 + /* Initialize the fwspec */
8285 + ret = iommu_fwspec_init(&mc_dev->dev, &iommu_node->fwnode, ops);
8286 + if (ret)
8287 + return NULL;
8288 +
8289 + /*
8290 + * Fill in the required stream-id before calling the iommu's
8291 + * ops->xlate callback.
8292 + */
8293 + iommu_spec.np = iommu_node;
8294 + iommu_spec.args[0] = mc_dev->icid;
8295 + iommu_spec.args_count = 1;
8296 +
8297 + ret = ops->of_xlate(&mc_dev->dev, &iommu_spec);
8298 + if (ret)
8299 + return NULL;
8300 +
8301 + of_node_put(iommu_spec.np);
8302 +
8303 + return ops;
8304 +}
8305 +
8306 +/* Set up DMA configuration for fsl-mc devices */
8307 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
8308 + struct device_node *fsl_mc_platform_node, int coherent)
8309 +{
8310 + const struct iommu_ops *ops;
8311 +
8312 + ops = fsl_mc_iommu_configure(mc_dev, fsl_mc_platform_node);
8313 +
8314 + mc_dev->dev.coherent_dma_mask = DMA_BIT_MASK(48);
8315 + mc_dev->dev.dma_mask = &mc_dev->dev.coherent_dma_mask;
8316 + arch_setup_dma_ops(&mc_dev->dev, 0,
8317 + mc_dev->dev.coherent_dma_mask + 1, ops, coherent);
8318 +}
8319 +
8320 +/* Macro to get the container device of a MC device */
8321 +#define fsl_mc_cont_dev(_dev) ((to_fsl_mc_device(_dev)->flags & \
8322 + FSL_MC_IS_DPRC) ? (_dev) : ((_dev)->parent))
8323 +
8324 +/* Macro to check if a device is a container device */
8325 +#define is_cont_dev(_dev) (to_fsl_mc_device(_dev)->flags & FSL_MC_IS_DPRC)
8326 +
8327 +/* Get the IOMMU group for device on fsl-mc bus */
8328 +struct iommu_group *fsl_mc_device_group(struct device *dev)
8329 +{
8330 + struct device *cont_dev = fsl_mc_cont_dev(dev);
8331 + struct iommu_group *group;
8332 +
8333 + /* Container device is responsible for creating the iommu group */
8334 + if (is_cont_dev(dev)) {
8335 + group = iommu_group_alloc();
8336 + if (IS_ERR(group))
8337 + return NULL;
8338 + } else {
8339 + get_device(cont_dev);
8340 + group = iommu_group_get(cont_dev);
8341 + put_device(cont_dev);
8342 + }
8343 +
8344 + return group;
8345 +}
8346 --- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8347 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8348 @@ -1,7 +1,7 @@
8349 /*
8350 * Freescale Management Complex (MC) bus driver MSI support
8351 *
8352 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8353 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8354 * Author: German Rivera <German.Rivera@freescale.com>
8355 *
8356 * This file is licensed under the terms of the GNU General Public
8357 @@ -17,6 +17,7 @@
8358 #include <linux/irqdomain.h>
8359 #include <linux/msi.h>
8360 #include "../include/mc-bus.h"
8361 +#include "fsl-mc-private.h"
8362
8363 /*
8364 * Generate a unique ID identifying the interrupt (only used within the MSI
8365 --- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8366 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8367 @@ -10,13 +10,15 @@
8368 #ifndef _FSL_MC_PRIVATE_H_
8369 #define _FSL_MC_PRIVATE_H_
8370
8371 +#include "../include/mc.h"
8372 +#include "../include/mc-bus.h"
8373 +
8374 int __must_check fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8375 struct fsl_mc_io *mc_io,
8376 struct device *parent_dev,
8377 + const char *driver_override,
8378 struct fsl_mc_device **new_mc_dev);
8379
8380 -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
8381 -
8382 int __init dprc_driver_init(void);
8383
8384 void dprc_driver_exit(void);
8385 --- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8386 +++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8387 @@ -1,7 +1,7 @@
8388 /*
8389 * Freescale Management Complex (MC) bus driver MSI support
8390 *
8391 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8392 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8393 * Author: German Rivera <German.Rivera@freescale.com>
8394 *
8395 * This file is licensed under the terms of the GNU General Public
8396 @@ -17,9 +17,10 @@
8397 #include <linux/of.h>
8398 #include <linux/of_irq.h>
8399 #include "../include/mc-bus.h"
8400 +#include "fsl-mc-private.h"
8401
8402 static struct irq_chip its_msi_irq_chip = {
8403 - .name = "fsl-mc-bus-msi",
8404 + .name = "ITS-fMSI",
8405 .irq_mask = irq_chip_mask_parent,
8406 .irq_unmask = irq_chip_unmask_parent,
8407 .irq_eoi = irq_chip_eoi_parent,
8408 @@ -51,7 +52,7 @@ static int its_fsl_mc_msi_prepare(struct
8409 return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info);
8410 }
8411
8412 -static struct msi_domain_ops its_fsl_mc_msi_ops = {
8413 +static struct msi_domain_ops its_fsl_mc_msi_ops __ro_after_init = {
8414 .msi_prepare = its_fsl_mc_msi_prepare,
8415 };
8416
8417 @@ -94,8 +95,8 @@ int __init its_fsl_mc_msi_init(void)
8418 continue;
8419 }
8420
8421 - WARN_ON(mc_msi_domain->
8422 - host_data != &its_fsl_mc_msi_domain_info);
8423 + WARN_ON(mc_msi_domain->host_data !=
8424 + &its_fsl_mc_msi_domain_info);
8425
8426 pr_info("fsl-mc MSI: %s domain created\n", np->full_name);
8427 }
8428 --- a/drivers/staging/fsl-mc/bus/mc-io.c
8429 +++ b/drivers/staging/fsl-mc/bus/mc-io.c
8430 @@ -1,4 +1,5 @@
8431 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
8432 +/*
8433 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8434 *
8435 * Redistribution and use in source and binary forms, with or without
8436 * modification, are permitted provided that the following conditions are met:
8437 @@ -11,7 +12,6 @@
8438 * names of any contributors may be used to endorse or promote products
8439 * derived from this software without specific prior written permission.
8440 *
8441 - *
8442 * ALTERNATIVELY, this software may be distributed under the terms of the
8443 * GNU General Public License ("GPL") as published by the Free Software
8444 * Foundation, either version 2 of that License or (at your option) any
8445 --- /dev/null
8446 +++ b/drivers/staging/fsl-mc/bus/mc-ioctl.h
8447 @@ -0,0 +1,22 @@
8448 +/*
8449 + * Freescale Management Complex (MC) ioclt interface
8450 + *
8451 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8452 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8453 + *
8454 + * This file is licensed under the terms of the GNU General Public
8455 + * License version 2. This program is licensed "as is" without any
8456 + * warranty of any kind, whether express or implied.
8457 + */
8458 +#ifndef _FSL_MC_IOCTL_H_
8459 +#define _FSL_MC_IOCTL_H_
8460 +
8461 +#include <linux/ioctl.h>
8462 +#include "../include/mc-sys.h"
8463 +
8464 +#define RESTOOL_IOCTL_TYPE 'R'
8465 +
8466 +#define RESTOOL_SEND_MC_COMMAND \
8467 + _IOWR(RESTOOL_IOCTL_TYPE, 0xE0, struct mc_command)
8468 +
8469 +#endif /* _FSL_MC_IOCTL_H_ */
8470 --- /dev/null
8471 +++ b/drivers/staging/fsl-mc/bus/mc-restool.c
8472 @@ -0,0 +1,405 @@
8473 +/*
8474 + * Freescale Management Complex (MC) restool driver
8475 + *
8476 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8477 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8478 + *
8479 + * This file is licensed under the terms of the GNU General Public
8480 + * License version 2. This program is licensed "as is" without any
8481 + * warranty of any kind, whether express or implied.
8482 + */
8483 +
8484 +#include "../include/mc.h"
8485 +#include <linux/module.h>
8486 +#include <linux/fs.h>
8487 +#include <linux/miscdevice.h>
8488 +#include <linux/mm.h>
8489 +#include <linux/slab.h>
8490 +#include <linux/uaccess.h>
8491 +#include <linux/mutex.h>
8492 +#include <linux/platform_device.h>
8493 +#include "mc-ioctl.h"
8494 +#include "../include/mc-sys.h"
8495 +#include "../include/mc-bus.h"
8496 +#include "../include/mc-cmd.h"
8497 +#include "../include/dpmng.h"
8498 +
8499 +/**
8500 + * Maximum number of DPRCs that can be opened at the same time
8501 + */
8502 +#define MAX_DPRC_HANDLES 64
8503 +
8504 +/**
8505 + * restool_misc - information associated with the newly added miscdevice
8506 + * @misc: newly created miscdevice associated with root dprc
8507 + * @miscdevt: device id of this miscdevice
8508 + * @list: a linked list node representing this miscdevcie
8509 + * @static_mc_io: pointer to the static MC I/O object used by the restool
8510 + * @dynamic_instance_count: number of dynamically created instances
8511 + * @static_instance_in_use: static instance is in use or not
8512 + * @mutex: mutex lock to serialze the open/release operations
8513 + * @dev: root dprc associated with this miscdevice
8514 + */
8515 +struct restool_misc {
8516 + struct miscdevice misc;
8517 + dev_t miscdevt;
8518 + struct list_head list;
8519 + struct fsl_mc_io *static_mc_io;
8520 + u32 dynamic_instance_count;
8521 + bool static_instance_in_use;
8522 + struct mutex mutex; /* serialze the open/release operations */
8523 + struct device *dev;
8524 +};
8525 +
8526 +/**
8527 + * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
8528 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
8529 + * @num_translation_ranges: number of entries in addr_translation_ranges
8530 + * @translation_ranges: array of bus to system address translation ranges
8531 + */
8532 +struct fsl_mc {
8533 + struct fsl_mc_device *root_mc_bus_dev;
8534 + u8 num_translation_ranges;
8535 + struct fsl_mc_addr_translation_range *translation_ranges;
8536 +};
8537 +
8538 +/*
8539 + * initialize a global list to link all
8540 + * the miscdevice nodes (struct restool_misc)
8541 + */
8542 +static LIST_HEAD(misc_list);
8543 +static DEFINE_MUTEX(misc_list_mutex);
8544 +
8545 +static int fsl_mc_restool_dev_open(struct inode *inode, struct file *filep)
8546 +{
8547 + struct fsl_mc_device *root_mc_dev;
8548 + int error;
8549 + struct fsl_mc_io *dynamic_mc_io = NULL;
8550 + struct restool_misc *restool_misc = NULL;
8551 + struct restool_misc *restool_misc_cursor;
8552 +
8553 + mutex_lock(&misc_list_mutex);
8554 +
8555 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8556 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8557 + restool_misc = restool_misc_cursor;
8558 + break;
8559 + }
8560 + }
8561 +
8562 + mutex_unlock(&misc_list_mutex);
8563 +
8564 + if (!restool_misc)
8565 + return -EINVAL;
8566 +
8567 + if (WARN_ON(!restool_misc->dev))
8568 + return -EINVAL;
8569 +
8570 + mutex_lock(&restool_misc->mutex);
8571 +
8572 + if (!restool_misc->static_instance_in_use) {
8573 + restool_misc->static_instance_in_use = true;
8574 + filep->private_data = restool_misc->static_mc_io;
8575 + } else {
8576 + dynamic_mc_io = kzalloc(sizeof(*dynamic_mc_io), GFP_KERNEL);
8577 + if (!dynamic_mc_io) {
8578 + error = -ENOMEM;
8579 + goto err_unlock;
8580 + }
8581 +
8582 + root_mc_dev = to_fsl_mc_device(restool_misc->dev);
8583 + error = fsl_mc_portal_allocate(root_mc_dev, 0, &dynamic_mc_io);
8584 + if (error < 0) {
8585 + pr_err("Not able to allocate MC portal\n");
8586 + goto free_dynamic_mc_io;
8587 + }
8588 + ++restool_misc->dynamic_instance_count;
8589 + filep->private_data = dynamic_mc_io;
8590 + }
8591 +
8592 + mutex_unlock(&restool_misc->mutex);
8593 +
8594 + return 0;
8595 +
8596 +free_dynamic_mc_io:
8597 + kfree(dynamic_mc_io);
8598 +err_unlock:
8599 + mutex_unlock(&restool_misc->mutex);
8600 +
8601 + return error;
8602 +}
8603 +
8604 +static int fsl_mc_restool_dev_release(struct inode *inode, struct file *filep)
8605 +{
8606 + struct fsl_mc_io *local_mc_io = filep->private_data;
8607 + struct restool_misc *restool_misc = NULL;
8608 + struct restool_misc *restool_misc_cursor;
8609 +
8610 + if (WARN_ON(!filep->private_data))
8611 + return -EINVAL;
8612 +
8613 + mutex_lock(&misc_list_mutex);
8614 +
8615 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8616 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8617 + restool_misc = restool_misc_cursor;
8618 + break;
8619 + }
8620 + }
8621 +
8622 + mutex_unlock(&misc_list_mutex);
8623 +
8624 + if (!restool_misc)
8625 + return -EINVAL;
8626 +
8627 + mutex_lock(&restool_misc->mutex);
8628 +
8629 + if (WARN_ON(restool_misc->dynamic_instance_count == 0 &&
8630 + !restool_misc->static_instance_in_use)) {
8631 + mutex_unlock(&restool_misc->mutex);
8632 + return -EINVAL;
8633 + }
8634 +
8635 + /* Globally clean up opened/untracked handles */
8636 + fsl_mc_portal_reset(local_mc_io);
8637 +
8638 + /*
8639 + * must check
8640 + * whether local_mc_io is dynamic or static instance
8641 + * Otherwise it will free up the reserved portal by accident
8642 + * or even not free up the dynamic allocated portal
8643 + * if 2 or more instances running concurrently
8644 + */
8645 + if (local_mc_io == restool_misc->static_mc_io) {
8646 + restool_misc->static_instance_in_use = false;
8647 + } else {
8648 + fsl_mc_portal_free(local_mc_io);
8649 + kfree(filep->private_data);
8650 + --restool_misc->dynamic_instance_count;
8651 + }
8652 +
8653 + filep->private_data = NULL;
8654 + mutex_unlock(&restool_misc->mutex);
8655 +
8656 + return 0;
8657 +}
8658 +
8659 +static int restool_send_mc_command(unsigned long arg,
8660 + struct fsl_mc_io *local_mc_io)
8661 +{
8662 + int error;
8663 + struct mc_command mc_cmd;
8664 +
8665 + if (copy_from_user(&mc_cmd, (void __user *)arg, sizeof(mc_cmd)))
8666 + return -EFAULT;
8667 +
8668 + /*
8669 + * Send MC command to the MC:
8670 + */
8671 + error = mc_send_command(local_mc_io, &mc_cmd);
8672 + if (error < 0)
8673 + return error;
8674 +
8675 + if (copy_to_user((void __user *)arg, &mc_cmd, sizeof(mc_cmd)))
8676 + return -EFAULT;
8677 +
8678 + return 0;
8679 +}
8680 +
8681 +static long
8682 +fsl_mc_restool_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
8683 +{
8684 + int error;
8685 +
8686 + switch (cmd) {
8687 + case RESTOOL_SEND_MC_COMMAND:
8688 + error = restool_send_mc_command(arg, file->private_data);
8689 + break;
8690 + default:
8691 + pr_err("%s: unexpected ioctl call number\n", __func__);
8692 + error = -EINVAL;
8693 + }
8694 +
8695 + return error;
8696 +}
8697 +
8698 +static const struct file_operations fsl_mc_restool_dev_fops = {
8699 + .owner = THIS_MODULE,
8700 + .open = fsl_mc_restool_dev_open,
8701 + .release = fsl_mc_restool_dev_release,
8702 + .unlocked_ioctl = fsl_mc_restool_dev_ioctl,
8703 +};
8704 +
8705 +static int restool_add_device_file(struct device *dev)
8706 +{
8707 + u32 name1 = 0;
8708 + char name2[20] = {0};
8709 + int error;
8710 + struct fsl_mc_device *root_mc_dev;
8711 + struct restool_misc *restool_misc;
8712 +
8713 + if (dev->bus == &platform_bus_type && dev->driver_data) {
8714 + if (sscanf(dev_name(dev), "%x.%s", &name1, name2) != 2)
8715 + return -EINVAL;
8716 +
8717 + if (strcmp(name2, "fsl-mc") == 0)
8718 + pr_debug("platform's root dprc name is: %s\n",
8719 + dev_name(&(((struct fsl_mc *)
8720 + (dev->driver_data))->root_mc_bus_dev->dev)));
8721 + }
8722 +
8723 + if (!fsl_mc_is_root_dprc(dev))
8724 + return 0;
8725 +
8726 + restool_misc = kzalloc(sizeof(*restool_misc), GFP_KERNEL);
8727 + if (!restool_misc)
8728 + return -ENOMEM;
8729 +
8730 + restool_misc->dev = dev;
8731 + root_mc_dev = to_fsl_mc_device(dev);
8732 + error = fsl_mc_portal_allocate(root_mc_dev, 0,
8733 + &restool_misc->static_mc_io);
8734 + if (error < 0) {
8735 + pr_err("Not able to allocate MC portal\n");
8736 + goto free_restool_misc;
8737 + }
8738 +
8739 + restool_misc->misc.minor = MISC_DYNAMIC_MINOR;
8740 + restool_misc->misc.name = dev_name(dev);
8741 + restool_misc->misc.fops = &fsl_mc_restool_dev_fops;
8742 +
8743 + error = misc_register(&restool_misc->misc);
8744 + if (error < 0) {
8745 + pr_err("misc_register() failed: %d\n", error);
8746 + goto free_portal;
8747 + }
8748 +
8749 + restool_misc->miscdevt = restool_misc->misc.this_device->devt;
8750 + mutex_init(&restool_misc->mutex);
8751 + mutex_lock(&misc_list_mutex);
8752 + list_add(&restool_misc->list, &misc_list);
8753 + mutex_unlock(&misc_list_mutex);
8754 +
8755 + pr_info("/dev/%s driver registered\n", dev_name(dev));
8756 +
8757 + return 0;
8758 +
8759 +free_portal:
8760 + fsl_mc_portal_free(restool_misc->static_mc_io);
8761 +free_restool_misc:
8762 + kfree(restool_misc);
8763 +
8764 + return error;
8765 +}
8766 +
8767 +static int restool_bus_notifier(struct notifier_block *nb,
8768 + unsigned long action, void *data)
8769 +{
8770 + int error;
8771 + struct device *dev = data;
8772 +
8773 + switch (action) {
8774 + case BUS_NOTIFY_ADD_DEVICE:
8775 + error = restool_add_device_file(dev);
8776 + if (error)
8777 + return error;
8778 + break;
8779 + case BUS_NOTIFY_DEL_DEVICE:
8780 + case BUS_NOTIFY_REMOVED_DEVICE:
8781 + case BUS_NOTIFY_BIND_DRIVER:
8782 + case BUS_NOTIFY_BOUND_DRIVER:
8783 + case BUS_NOTIFY_UNBIND_DRIVER:
8784 + case BUS_NOTIFY_UNBOUND_DRIVER:
8785 + break;
8786 + default:
8787 + pr_err("%s: unrecognized device action from %s\n", __func__,
8788 + dev_name(dev));
8789 + return -EINVAL;
8790 + }
8791 +
8792 + return 0;
8793 +}
8794 +
8795 +static int add_to_restool(struct device *dev, void *data)
8796 +{
8797 + return restool_add_device_file(dev);
8798 +}
8799 +
8800 +static int __init fsl_mc_restool_driver_init(void)
8801 +{
8802 + int error;
8803 + struct notifier_block *nb;
8804 +
8805 + nb = kzalloc(sizeof(*nb), GFP_KERNEL);
8806 + if (!nb)
8807 + return -ENOMEM;
8808 +
8809 + nb->notifier_call = restool_bus_notifier;
8810 + error = bus_register_notifier(&fsl_mc_bus_type, nb);
8811 + if (error)
8812 + goto free_nb;
8813 +
8814 + /*
8815 + * This driver runs after fsl-mc bus driver runs.
8816 + * Hence, many of the root dprcs are already attached to fsl-mc bus
8817 + * In order to make sure we find all the root dprcs,
8818 + * we need to scan the fsl_mc_bus_type.
8819 + */
8820 + error = bus_for_each_dev(&fsl_mc_bus_type, NULL, NULL, add_to_restool);
8821 + if (error) {
8822 + bus_unregister_notifier(&fsl_mc_bus_type, nb);
8823 + kfree(nb);
8824 + pr_err("restool driver registration failure\n");
8825 + return error;
8826 + }
8827 +
8828 + return 0;
8829 +
8830 +free_nb:
8831 + kfree(nb);
8832 + return error;
8833 +}
8834 +
8835 +module_init(fsl_mc_restool_driver_init);
8836 +
8837 +static void __exit fsl_mc_restool_driver_exit(void)
8838 +{
8839 + struct restool_misc *restool_misc;
8840 + struct restool_misc *restool_misc_tmp;
8841 + char name1[20] = {0};
8842 + u32 name2 = 0;
8843 +
8844 + list_for_each_entry_safe(restool_misc, restool_misc_tmp,
8845 + &misc_list, list) {
8846 + if (sscanf(restool_misc->misc.name, "%4s.%u", name1, &name2)
8847 + != 2)
8848 + continue;
8849 +
8850 + pr_debug("name1=%s,name2=%u\n", name1, name2);
8851 + pr_debug("misc-device: %s\n", restool_misc->misc.name);
8852 + if (strcmp(name1, "dprc") != 0)
8853 + continue;
8854 +
8855 + if (WARN_ON(!restool_misc->static_mc_io))
8856 + return;
8857 +
8858 + if (WARN_ON(restool_misc->dynamic_instance_count != 0))
8859 + return;
8860 +
8861 + if (WARN_ON(restool_misc->static_instance_in_use))
8862 + return;
8863 +
8864 + misc_deregister(&restool_misc->misc);
8865 + pr_info("/dev/%s driver unregistered\n",
8866 + restool_misc->misc.name);
8867 + fsl_mc_portal_free(restool_misc->static_mc_io);
8868 + list_del(&restool_misc->list);
8869 + kfree(restool_misc);
8870 + }
8871 +}
8872 +
8873 +module_exit(fsl_mc_restool_driver_exit);
8874 +
8875 +MODULE_AUTHOR("Freescale Semiconductor Inc.");
8876 +MODULE_DESCRIPTION("Freescale's MC restool driver");
8877 +MODULE_LICENSE("GPL");
8878 --- a/drivers/staging/fsl-mc/bus/mc-sys.c
8879 +++ b/drivers/staging/fsl-mc/bus/mc-sys.c
8880 @@ -1,4 +1,5 @@
8881 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
8882 +/*
8883 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8884 *
8885 * I/O services to send MC commands to the MC hardware
8886 *
8887 @@ -13,7 +14,6 @@
8888 * names of any contributors may be used to endorse or promote products
8889 * derived from this software without specific prior written permission.
8890 *
8891 - *
8892 * ALTERNATIVELY, this software may be distributed under the terms of the
8893 * GNU General Public License ("GPL") as published by the Free Software
8894 * Foundation, either version 2 of that License or (at your option) any
8895 @@ -46,7 +46,7 @@
8896 /**
8897 * Timeout in milliseconds to wait for the completion of an MC command
8898 */
8899 -#define MC_CMD_COMPLETION_TIMEOUT_MS 500
8900 +#define MC_CMD_COMPLETION_TIMEOUT_MS 15000
8901
8902 /*
8903 * usleep_range() min and max values used to throttle down polling
8904 @@ -67,7 +67,7 @@ static u16 mc_cmd_hdr_read_cmdid(struct
8905 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
8906 u16 cmd_id = le16_to_cpu(hdr->cmd_id);
8907
8908 - return (cmd_id & MC_CMD_HDR_CMDID_MASK) >> MC_CMD_HDR_CMDID_SHIFT;
8909 + return cmd_id;
8910 }
8911
8912 static int mc_status_to_error(enum mc_cmd_status status)
8913 @@ -200,7 +200,7 @@ static int mc_polling_wait_preemptible(s
8914
8915 if (time_after_eq(jiffies, jiffies_until_timeout)) {
8916 dev_dbg(mc_io->dev,
8917 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8918 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8919 mc_io->portal_phys_addr,
8920 (unsigned int)mc_cmd_hdr_read_token(cmd),
8921 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8922 @@ -240,7 +240,7 @@ static int mc_polling_wait_atomic(struct
8923 timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS;
8924 if (timeout_usecs == 0) {
8925 dev_dbg(mc_io->dev,
8926 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8927 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8928 mc_io->portal_phys_addr,
8929 (unsigned int)mc_cmd_hdr_read_token(cmd),
8930 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8931 @@ -294,7 +294,7 @@ int mc_send_command(struct fsl_mc_io *mc
8932
8933 if (status != MC_CMD_STATUS_OK) {
8934 dev_dbg(mc_io->dev,
8935 - "MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n",
8936 + "MC command failed: portal: %#llx, dprc handle: %#x, command: %#x, status: %s (%#x)\n",
8937 mc_io->portal_phys_addr,
8938 (unsigned int)mc_cmd_hdr_read_token(cmd),
8939 (unsigned int)mc_cmd_hdr_read_cmdid(cmd),
8940 --- /dev/null
8941 +++ b/drivers/staging/fsl-mc/include/dpaa2-fd.h
8942 @@ -0,0 +1,706 @@
8943 +/*
8944 + * Copyright 2014-2016 Freescale Semiconductor Inc.
8945 + * Copyright 2016 NXP
8946 + *
8947 + * Redistribution and use in source and binary forms, with or without
8948 + * modification, are permitted provided that the following conditions are met:
8949 + * * Redistributions of source code must retain the above copyright
8950 + * notice, this list of conditions and the following disclaimer.
8951 + * * Redistributions in binary form must reproduce the above copyright
8952 + * notice, this list of conditions and the following disclaimer in the
8953 + * documentation and/or other materials provided with the distribution.
8954 + * * Neither the name of Freescale Semiconductor nor the
8955 + * names of its contributors may be used to endorse or promote products
8956 + * derived from this software without specific prior written permission.
8957 + *
8958 + * ALTERNATIVELY, this software may be distributed under the terms of the
8959 + * GNU General Public License ("GPL") as published by the Free Software
8960 + * Foundation, either version 2 of that License or (at your option) any
8961 + * later version.
8962 + *
8963 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
8964 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
8965 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8966 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
8967 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
8968 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
8969 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
8970 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8971 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
8972 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8973 + */
8974 +#ifndef __FSL_DPAA2_FD_H
8975 +#define __FSL_DPAA2_FD_H
8976 +
8977 +#include <linux/kernel.h>
8978 +
8979 +/**
8980 + * DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
8981 + *
8982 + * Frame Descriptors (FDs) are used to describe frame data in the DPAA2.
8983 + * Frames can be enqueued and dequeued to Frame Queues (FQs) which are consumed
8984 + * by the various DPAA accelerators (WRIOP, SEC, PME, DCE)
8985 + *
8986 + * There are three types of frames: single, scatter gather, and frame lists.
8987 + *
8988 + * The set of APIs in this file must be used to create, manipulate and
8989 + * query Frame Descriptors.
8990 + */
8991 +
8992 +/**
8993 + * struct dpaa2_fd - Struct describing FDs
8994 + * @words: for easier/faster copying the whole FD structure
8995 + * @addr: address in the FD
8996 + * @len: length in the FD
8997 + * @bpid: buffer pool ID
8998 + * @format_offset: format, offset, and short-length fields
8999 + * @frc: frame context
9000 + * @ctrl: control bits...including dd, sc, va, err, etc
9001 + * @flc: flow context address
9002 + *
9003 + * This structure represents the basic Frame Descriptor used in the system.
9004 + */
9005 +struct dpaa2_fd {
9006 + union {
9007 + u32 words[8];
9008 + struct dpaa2_fd_simple {
9009 + __le64 addr;
9010 + __le32 len;
9011 + __le16 bpid;
9012 + __le16 format_offset;
9013 + __le32 frc;
9014 + __le32 ctrl;
9015 + __le64 flc;
9016 + } simple;
9017 + };
9018 +};
9019 +
9020 +#define FD_SHORT_LEN_FLAG_MASK 0x1
9021 +#define FD_SHORT_LEN_FLAG_SHIFT 14
9022 +#define FD_SHORT_LEN_MASK 0x3FFFF
9023 +#define FD_OFFSET_MASK 0x0FFF
9024 +#define FD_FORMAT_MASK 0x3
9025 +#define FD_FORMAT_SHIFT 12
9026 +#define FD_BPID_MASK 0x3FFF
9027 +#define SG_SHORT_LEN_FLAG_MASK 0x1
9028 +#define SG_SHORT_LEN_FLAG_SHIFT 14
9029 +#define SG_SHORT_LEN_MASK 0x1FFFF
9030 +#define SG_OFFSET_MASK 0x0FFF
9031 +#define SG_FORMAT_MASK 0x3
9032 +#define SG_FORMAT_SHIFT 12
9033 +#define SG_BPID_MASK 0x3FFF
9034 +#define SG_FINAL_FLAG_MASK 0x1
9035 +#define SG_FINAL_FLAG_SHIFT 15
9036 +#define FL_SHORT_LEN_FLAG_MASK 0x1
9037 +#define FL_SHORT_LEN_FLAG_SHIFT 14
9038 +#define FL_SHORT_LEN_MASK 0x3FFFF
9039 +#define FL_OFFSET_MASK 0x0FFF
9040 +#define FL_FORMAT_MASK 0x3
9041 +#define FL_FORMAT_SHIFT 12
9042 +#define FL_BPID_MASK 0x3FFF
9043 +#define FL_FINAL_FLAG_MASK 0x1
9044 +#define FL_FINAL_FLAG_SHIFT 15
9045 +
9046 +/* Error bits in FD CTRL */
9047 +#define FD_CTRL_ERR_MASK 0x000000FF
9048 +#define FD_CTRL_UFD 0x00000004
9049 +#define FD_CTRL_SBE 0x00000008
9050 +#define FD_CTRL_FLC 0x00000010
9051 +#define FD_CTRL_FSE 0x00000020
9052 +#define FD_CTRL_FAERR 0x00000040
9053 +
9054 +/* Annotation bits in FD CTRL */
9055 +#define FD_CTRL_PTA 0x00800000
9056 +#define FD_CTRL_PTV1 0x00400000
9057 +
9058 +enum dpaa2_fd_format {
9059 + dpaa2_fd_single = 0,
9060 + dpaa2_fd_list,
9061 + dpaa2_fd_sg
9062 +};
9063 +
9064 +/**
9065 + * dpaa2_fd_get_addr() - get the addr field of frame descriptor
9066 + * @fd: the given frame descriptor
9067 + *
9068 + * Return the address in the frame descriptor.
9069 + */
9070 +static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd)
9071 +{
9072 + return (dma_addr_t)le64_to_cpu(fd->simple.addr);
9073 +}
9074 +
9075 +/**
9076 + * dpaa2_fd_set_addr() - Set the addr field of frame descriptor
9077 + * @fd: the given frame descriptor
9078 + * @addr: the address needs to be set in frame descriptor
9079 + */
9080 +static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr)
9081 +{
9082 + fd->simple.addr = cpu_to_le64(addr);
9083 +}
9084 +
9085 +/**
9086 + * dpaa2_fd_get_frc() - Get the frame context in the frame descriptor
9087 + * @fd: the given frame descriptor
9088 + *
9089 + * Return the frame context field in the frame descriptor.
9090 + */
9091 +static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd)
9092 +{
9093 + return le32_to_cpu(fd->simple.frc);
9094 +}
9095 +
9096 +/**
9097 + * dpaa2_fd_set_frc() - Set the frame context in the frame descriptor
9098 + * @fd: the given frame descriptor
9099 + * @frc: the frame context needs to be set in frame descriptor
9100 + */
9101 +static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc)
9102 +{
9103 + fd->simple.frc = cpu_to_le32(frc);
9104 +}
9105 +
9106 +/**
9107 + * dpaa2_fd_get_ctrl() - Get the control bits in the frame descriptor
9108 + * @fd: the given frame descriptor
9109 + *
9110 + * Return the control bits field in the frame descriptor.
9111 + */
9112 +static inline u32 dpaa2_fd_get_ctrl(const struct dpaa2_fd *fd)
9113 +{
9114 + return le32_to_cpu(fd->simple.ctrl);
9115 +}
9116 +
9117 +/**
9118 + * dpaa2_fd_set_ctrl() - Set the control bits in the frame descriptor
9119 + * @fd: the given frame descriptor
9120 + * @ctrl: the control bits to be set in the frame descriptor
9121 + */
9122 +static inline void dpaa2_fd_set_ctrl(struct dpaa2_fd *fd, u32 ctrl)
9123 +{
9124 + fd->simple.ctrl = cpu_to_le32(ctrl);
9125 +}
9126 +
9127 +/**
9128 + * dpaa2_fd_get_flc() - Get the flow context in the frame descriptor
9129 + * @fd: the given frame descriptor
9130 + *
9131 + * Return the flow context in the frame descriptor.
9132 + */
9133 +static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd)
9134 +{
9135 + return (dma_addr_t)le64_to_cpu(fd->simple.flc);
9136 +}
9137 +
9138 +/**
9139 + * dpaa2_fd_set_flc() - Set the flow context field of frame descriptor
9140 + * @fd: the given frame descriptor
9141 + * @flc_addr: the flow context needs to be set in frame descriptor
9142 + */
9143 +static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd, dma_addr_t flc_addr)
9144 +{
9145 + fd->simple.flc = cpu_to_le64(flc_addr);
9146 +}
9147 +
9148 +static inline bool dpaa2_fd_short_len(const struct dpaa2_fd *fd)
9149 +{
9150 + return !!((le16_to_cpu(fd->simple.format_offset) >>
9151 + FD_SHORT_LEN_FLAG_SHIFT) & FD_SHORT_LEN_FLAG_MASK);
9152 +}
9153 +
9154 +/**
9155 + * dpaa2_fd_get_len() - Get the length in the frame descriptor
9156 + * @fd: the given frame descriptor
9157 + *
9158 + * Return the length field in the frame descriptor.
9159 + */
9160 +static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd)
9161 +{
9162 + if (dpaa2_fd_short_len(fd))
9163 + return le32_to_cpu(fd->simple.len) & FD_SHORT_LEN_MASK;
9164 +
9165 + return le32_to_cpu(fd->simple.len);
9166 +}
9167 +
9168 +/**
9169 + * dpaa2_fd_set_len() - Set the length field of frame descriptor
9170 + * @fd: the given frame descriptor
9171 + * @len: the length needs to be set in frame descriptor
9172 + */
9173 +static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len)
9174 +{
9175 + fd->simple.len = cpu_to_le32(len);
9176 +}
9177 +
9178 +/**
9179 + * dpaa2_fd_get_offset() - Get the offset field in the frame descriptor
9180 + * @fd: the given frame descriptor
9181 + *
9182 + * Return the offset.
9183 + */
9184 +static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd)
9185 +{
9186 + return le16_to_cpu(fd->simple.format_offset) & FD_OFFSET_MASK;
9187 +}
9188 +
9189 +/**
9190 + * dpaa2_fd_set_offset() - Set the offset field of frame descriptor
9191 + * @fd: the given frame descriptor
9192 + * @offset: the offset needs to be set in frame descriptor
9193 + */
9194 +static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset)
9195 +{
9196 + fd->simple.format_offset &= cpu_to_le16(~FD_OFFSET_MASK);
9197 + fd->simple.format_offset |= cpu_to_le16(offset);
9198 +}
9199 +
9200 +/**
9201 + * dpaa2_fd_get_format() - Get the format field in the frame descriptor
9202 + * @fd: the given frame descriptor
9203 + *
9204 + * Return the format.
9205 + */
9206 +static inline enum dpaa2_fd_format dpaa2_fd_get_format(
9207 + const struct dpaa2_fd *fd)
9208 +{
9209 + return (enum dpaa2_fd_format)((le16_to_cpu(fd->simple.format_offset)
9210 + >> FD_FORMAT_SHIFT) & FD_FORMAT_MASK);
9211 +}
9212 +
9213 +/**
9214 + * dpaa2_fd_set_format() - Set the format field of frame descriptor
9215 + * @fd: the given frame descriptor
9216 + * @format: the format needs to be set in frame descriptor
9217 + */
9218 +static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd,
9219 + enum dpaa2_fd_format format)
9220 +{
9221 + fd->simple.format_offset &=
9222 + cpu_to_le16(~(FD_FORMAT_MASK << FD_FORMAT_SHIFT));
9223 + fd->simple.format_offset |= cpu_to_le16(format << FD_FORMAT_SHIFT);
9224 +}
9225 +
9226 +/**
9227 + * dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor
9228 + * @fd: the given frame descriptor
9229 + *
9230 + * Return the buffer pool id.
9231 + */
9232 +static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd)
9233 +{
9234 + return le16_to_cpu(fd->simple.bpid) & FD_BPID_MASK;
9235 +}
9236 +
9237 +/**
9238 + * dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor
9239 + * @fd: the given frame descriptor
9240 + * @bpid: buffer pool id to be set
9241 + */
9242 +static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid)
9243 +{
9244 + fd->simple.bpid &= cpu_to_le16(~(FD_BPID_MASK));
9245 + fd->simple.bpid |= cpu_to_le16(bpid);
9246 +}
9247 +
9248 +/**
9249 + * struct dpaa2_sg_entry - the scatter-gathering structure
9250 + * @addr: address of the sg entry
9251 + * @len: length in this sg entry
9252 + * @bpid: buffer pool id
9253 + * @format_offset: format and offset fields
9254 + */
9255 +struct dpaa2_sg_entry {
9256 + __le64 addr;
9257 + __le32 len;
9258 + __le16 bpid;
9259 + __le16 format_offset;
9260 +};
9261 +
9262 +enum dpaa2_sg_format {
9263 + dpaa2_sg_single = 0,
9264 + dpaa2_sg_frame_data,
9265 + dpaa2_sg_sgt_ext
9266 +};
9267 +
9268 +/* Accessors for SG entry fields */
9269 +
9270 +/**
9271 + * dpaa2_sg_get_addr() - Get the address from SG entry
9272 + * @sg: the given scatter-gathering object
9273 + *
9274 + * Return the address.
9275 + */
9276 +static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
9277 +{
9278 + return le64_to_cpu((dma_addr_t)sg->addr);
9279 +}
9280 +
9281 +/**
9282 + * dpaa2_sg_set_addr() - Set the address in SG entry
9283 + * @sg: the given scatter-gathering object
9284 + * @addr: the address to be set
9285 + */
9286 +static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr)
9287 +{
9288 + sg->addr = cpu_to_le64(addr);
9289 +}
9290 +
9291 +static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg)
9292 +{
9293 + return !!((le16_to_cpu(sg->format_offset) >> SG_SHORT_LEN_FLAG_SHIFT)
9294 + & SG_SHORT_LEN_FLAG_MASK);
9295 +}
9296 +
9297 +/**
9298 + * dpaa2_sg_get_len() - Get the length in SG entry
9299 + * @sg: the given scatter-gathering object
9300 + *
9301 + * Return the length.
9302 + */
9303 +static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg)
9304 +{
9305 + if (dpaa2_sg_short_len(sg))
9306 + return le32_to_cpu(sg->len) & SG_SHORT_LEN_MASK;
9307 +
9308 + return le32_to_cpu(sg->len);
9309 +}
9310 +
9311 +/**
9312 + * dpaa2_sg_set_len() - Set the length in SG entry
9313 + * @sg: the given scatter-gathering object
9314 + * @len: the length to be set
9315 + */
9316 +static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len)
9317 +{
9318 + sg->len = cpu_to_le32(len);
9319 +}
9320 +
9321 +/**
9322 + * dpaa2_sg_get_offset() - Get the offset in SG entry
9323 + * @sg: the given scatter-gathering object
9324 + *
9325 + * Return the offset.
9326 + */
9327 +static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg)
9328 +{
9329 + return le16_to_cpu(sg->format_offset) & SG_OFFSET_MASK;
9330 +}
9331 +
9332 +/**
9333 + * dpaa2_sg_set_offset() - Set the offset in SG entry
9334 + * @sg: the given scatter-gathering object
9335 + * @offset: the offset to be set
9336 + */
9337 +static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg,
9338 + u16 offset)
9339 +{
9340 + sg->format_offset &= cpu_to_le16(~SG_OFFSET_MASK);
9341 + sg->format_offset |= cpu_to_le16(offset);
9342 +}
9343 +
9344 +/**
9345 + * dpaa2_sg_get_format() - Get the SG format in SG entry
9346 + * @sg: the given scatter-gathering object
9347 + *
9348 + * Return the format.
9349 + */
9350 +static inline enum dpaa2_sg_format
9351 + dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg)
9352 +{
9353 + return (enum dpaa2_sg_format)((le16_to_cpu(sg->format_offset)
9354 + >> SG_FORMAT_SHIFT) & SG_FORMAT_MASK);
9355 +}
9356 +
9357 +/**
9358 + * dpaa2_sg_set_format() - Set the SG format in SG entry
9359 + * @sg: the given scatter-gathering object
9360 + * @format: the format to be set
9361 + */
9362 +static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg,
9363 + enum dpaa2_sg_format format)
9364 +{
9365 + sg->format_offset &= cpu_to_le16(~(SG_FORMAT_MASK << SG_FORMAT_SHIFT));
9366 + sg->format_offset |= cpu_to_le16(format << SG_FORMAT_SHIFT);
9367 +}
9368 +
9369 +/**
9370 + * dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry
9371 + * @sg: the given scatter-gathering object
9372 + *
9373 + * Return the bpid.
9374 + */
9375 +static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg)
9376 +{
9377 + return le16_to_cpu(sg->bpid) & SG_BPID_MASK;
9378 +}
9379 +
9380 +/**
9381 + * dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry
9382 + * @sg: the given scatter-gathering object
9383 + * @bpid: the bpid to be set
9384 + */
9385 +static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid)
9386 +{
9387 + sg->bpid &= cpu_to_le16(~(SG_BPID_MASK));
9388 + sg->bpid |= cpu_to_le16(bpid);
9389 +}
9390 +
9391 +/**
9392 + * dpaa2_sg_is_final() - Check final bit in SG entry
9393 + * @sg: the given scatter-gathering object
9394 + *
9395 + * Return bool.
9396 + */
9397 +static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg)
9398 +{
9399 + return !!(le16_to_cpu(sg->format_offset) >> SG_FINAL_FLAG_SHIFT);
9400 +}
9401 +
9402 +/**
9403 + * dpaa2_sg_set_final() - Set the final bit in SG entry
9404 + * @sg: the given scatter-gathering object
9405 + * @final: the final boolean to be set
9406 + */
9407 +static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
9408 +{
9409 + sg->format_offset &= cpu_to_le16(~(SG_FINAL_FLAG_MASK
9410 + << SG_FINAL_FLAG_SHIFT));
9411 + sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
9412 +}
9413 +
9414 +/**
9415 + * struct dpaa2_fl_entry - structure for frame list entry.
9416 + * @addr: address in the FLE
9417 + * @len: length in the FLE
9418 + * @bpid: buffer pool ID
9419 + * @format_offset: format, offset, and short-length fields
9420 + * @frc: frame context
9421 + * @ctrl: control bits...including pta, pvt1, pvt2, err, etc
9422 + * @flc: flow context address
9423 + */
9424 +struct dpaa2_fl_entry {
9425 + __le64 addr;
9426 + __le32 len;
9427 + __le16 bpid;
9428 + __le16 format_offset;
9429 + __le32 frc;
9430 + __le32 ctrl;
9431 + __le64 flc;
9432 +};
9433 +
9434 +enum dpaa2_fl_format {
9435 + dpaa2_fl_single = 0,
9436 + dpaa2_fl_res,
9437 + dpaa2_fl_sg
9438 +};
9439 +
9440 +/**
9441 + * dpaa2_fl_get_addr() - get the addr field of FLE
9442 + * @fle: the given frame list entry
9443 + *
9444 + * Return the address in the frame list entry.
9445 + */
9446 +static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
9447 +{
9448 + return (dma_addr_t)le64_to_cpu(fle->addr);
9449 +}
9450 +
9451 +/**
9452 + * dpaa2_fl_set_addr() - Set the addr field of FLE
9453 + * @fle: the given frame list entry
9454 + * @addr: the address needs to be set in frame list entry
9455 + */
9456 +static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
9457 + dma_addr_t addr)
9458 +{
9459 + fle->addr = cpu_to_le64(addr);
9460 +}
9461 +
9462 +/**
9463 + * dpaa2_fl_get_frc() - Get the frame context in the FLE
9464 + * @fle: the given frame list entry
9465 + *
9466 + * Return the frame context field in the frame lsit entry.
9467 + */
9468 +static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
9469 +{
9470 + return le32_to_cpu(fle->frc);
9471 +}
9472 +
9473 +/**
9474 + * dpaa2_fl_set_frc() - Set the frame context in the FLE
9475 + * @fle: the given frame list entry
9476 + * @frc: the frame context needs to be set in frame list entry
9477 + */
9478 +static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
9479 +{
9480 + fle->frc = cpu_to_le32(frc);
9481 +}
9482 +
9483 +/**
9484 + * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
9485 + * @fle: the given frame list entry
9486 + *
9487 + * Return the control bits field in the frame list entry.
9488 + */
9489 +static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
9490 +{
9491 + return le32_to_cpu(fle->ctrl);
9492 +}
9493 +
9494 +/**
9495 + * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
9496 + * @fle: the given frame list entry
9497 + * @ctrl: the control bits to be set in the frame list entry
9498 + */
9499 +static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
9500 +{
9501 + fle->ctrl = cpu_to_le32(ctrl);
9502 +}
9503 +
9504 +/**
9505 + * dpaa2_fl_get_flc() - Get the flow context in the FLE
9506 + * @fle: the given frame list entry
9507 + *
9508 + * Return the flow context in the frame list entry.
9509 + */
9510 +static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
9511 +{
9512 + return (dma_addr_t)le64_to_cpu(fle->flc);
9513 +}
9514 +
9515 +/**
9516 + * dpaa2_fl_set_flc() - Set the flow context field of FLE
9517 + * @fle: the given frame list entry
9518 + * @flc_addr: the flow context needs to be set in frame list entry
9519 + */
9520 +static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
9521 + dma_addr_t flc_addr)
9522 +{
9523 + fle->flc = cpu_to_le64(flc_addr);
9524 +}
9525 +
9526 +static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
9527 +{
9528 + return !!((le16_to_cpu(fle->format_offset) >>
9529 + FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
9530 +}
9531 +
9532 +/**
9533 + * dpaa2_fl_get_len() - Get the length in the FLE
9534 + * @fle: the given frame list entry
9535 + *
9536 + * Return the length field in the frame list entry.
9537 + */
9538 +static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
9539 +{
9540 + if (dpaa2_fl_short_len(fle))
9541 + return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
9542 +
9543 + return le32_to_cpu(fle->len);
9544 +}
9545 +
9546 +/**
9547 + * dpaa2_fl_set_len() - Set the length field of FLE
9548 + * @fle: the given frame list entry
9549 + * @len: the length needs to be set in frame list entry
9550 + */
9551 +static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
9552 +{
9553 + fle->len = cpu_to_le32(len);
9554 +}
9555 +
9556 +/**
9557 + * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
9558 + * @fle: the given frame list entry
9559 + *
9560 + * Return the offset.
9561 + */
9562 +static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
9563 +{
9564 + return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
9565 +}
9566 +
9567 +/**
9568 + * dpaa2_fl_set_offset() - Set the offset field of FLE
9569 + * @fle: the given frame list entry
9570 + * @offset: the offset needs to be set in frame list entry
9571 + */
9572 +static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
9573 +{
9574 + fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
9575 + fle->format_offset |= cpu_to_le16(offset);
9576 +}
9577 +
9578 +/**
9579 + * dpaa2_fl_get_format() - Get the format field in the FLE
9580 + * @fle: the given frame list entry
9581 + *
9582 + * Return the format.
9583 + */
9584 +static inline enum dpaa2_fl_format dpaa2_fl_get_format(
9585 + const struct dpaa2_fl_entry *fle)
9586 +{
9587 + return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
9588 + FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
9589 +}
9590 +
9591 +/**
9592 + * dpaa2_fl_set_format() - Set the format field of FLE
9593 + * @fle: the given frame list entry
9594 + * @format: the format needs to be set in frame list entry
9595 + */
9596 +static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
9597 + enum dpaa2_fl_format format)
9598 +{
9599 + fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
9600 + fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
9601 +}
9602 +
9603 +/**
9604 + * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
9605 + * @fle: the given frame list entry
9606 + *
9607 + * Return the buffer pool id.
9608 + */
9609 +static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
9610 +{
9611 + return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
9612 +}
9613 +
9614 +/**
9615 + * dpaa2_fl_set_bpid() - Set the bpid field of FLE
9616 + * @fle: the given frame list entry
9617 + * @bpid: buffer pool id to be set
9618 + */
9619 +static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
9620 +{
9621 + fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
9622 + fle->bpid |= cpu_to_le16(bpid);
9623 +}
9624 +
9625 +/**
9626 + * dpaa2_fl_is_final() - Check final bit in FLE
9627 + * @fle: the given frame list entry
9628 + *
9629 + * Return bool.
9630 + */
9631 +static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
9632 +{
9633 + return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
9634 +}
9635 +
9636 +/**
9637 + * dpaa2_fl_set_final() - Set the final bit in FLE
9638 + * @fle: the given frame list entry
9639 + * @final: the final boolean to be set
9640 + */
9641 +static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
9642 +{
9643 + fle->format_offset &= cpu_to_le16(~(FL_FINAL_FLAG_MASK <<
9644 + FL_FINAL_FLAG_SHIFT));
9645 + fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
9646 +}
9647 +
9648 +#endif /* __FSL_DPAA2_FD_H */
9649 --- /dev/null
9650 +++ b/drivers/staging/fsl-mc/include/dpaa2-global.h
9651 @@ -0,0 +1,202 @@
9652 +/*
9653 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9654 + * Copyright 2016 NXP
9655 + *
9656 + * Redistribution and use in source and binary forms, with or without
9657 + * modification, are permitted provided that the following conditions are met:
9658 + * * Redistributions of source code must retain the above copyright
9659 + * notice, this list of conditions and the following disclaimer.
9660 + * * Redistributions in binary form must reproduce the above copyright
9661 + * notice, this list of conditions and the following disclaimer in the
9662 + * documentation and/or other materials provided with the distribution.
9663 + * * Neither the name of Freescale Semiconductor nor the
9664 + * names of its contributors may be used to endorse or promote products
9665 + * derived from this software without specific prior written permission.
9666 + *
9667 + * ALTERNATIVELY, this software may be distributed under the terms of the
9668 + * GNU General Public License ("GPL") as published by the Free Software
9669 + * Foundation, either version 2 of that License or (at your option) any
9670 + * later version.
9671 + *
9672 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9673 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9674 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9675 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9676 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9677 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9678 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9679 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9680 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9681 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9682 + */
9683 +#ifndef __FSL_DPAA2_GLOBAL_H
9684 +#define __FSL_DPAA2_GLOBAL_H
9685 +
9686 +#include <linux/types.h>
9687 +#include <linux/cpumask.h>
9688 +#include "dpaa2-fd.h"
9689 +
9690 +struct dpaa2_dq {
9691 + union {
9692 + struct common {
9693 + u8 verb;
9694 + u8 reserved[63];
9695 + } common;
9696 + struct dq {
9697 + u8 verb;
9698 + u8 stat;
9699 + __le16 seqnum;
9700 + __le16 oprid;
9701 + u8 reserved;
9702 + u8 tok;
9703 + __le32 fqid;
9704 + u32 reserved2;
9705 + __le32 fq_byte_cnt;
9706 + __le32 fq_frm_cnt;
9707 + __le64 fqd_ctx;
9708 + u8 fd[32];
9709 + } dq;
9710 + struct scn {
9711 + u8 verb;
9712 + u8 stat;
9713 + u8 state;
9714 + u8 reserved;
9715 + __le32 rid_tok;
9716 + __le64 ctx;
9717 + } scn;
9718 + };
9719 +};
9720 +
9721 +/* Parsing frame dequeue results */
9722 +/* FQ empty */
9723 +#define DPAA2_DQ_STAT_FQEMPTY 0x80
9724 +/* FQ held active */
9725 +#define DPAA2_DQ_STAT_HELDACTIVE 0x40
9726 +/* FQ force eligible */
9727 +#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
9728 +/* valid frame */
9729 +#define DPAA2_DQ_STAT_VALIDFRAME 0x10
9730 +/* FQ ODP enable */
9731 +#define DPAA2_DQ_STAT_ODPVALID 0x04
9732 +/* volatile dequeue */
9733 +#define DPAA2_DQ_STAT_VOLATILE 0x02
9734 +/* volatile dequeue command is expired */
9735 +#define DPAA2_DQ_STAT_EXPIRED 0x01
9736 +
9737 +#define DQ_FQID_MASK 0x00FFFFFF
9738 +#define DQ_FRAME_COUNT_MASK 0x00FFFFFF
9739 +
9740 +/**
9741 + * dpaa2_dq_flags() - Get the stat field of dequeue response
9742 + * @dq: the dequeue result.
9743 + */
9744 +static inline u32 dpaa2_dq_flags(const struct dpaa2_dq *dq)
9745 +{
9746 + return dq->dq.stat;
9747 +}
9748 +
9749 +/**
9750 + * dpaa2_dq_is_pull() - Check whether the dq response is from a pull
9751 + * command.
9752 + * @dq: the dequeue result
9753 + *
9754 + * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
9755 + */
9756 +static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq)
9757 +{
9758 + return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE);
9759 +}
9760 +
9761 +/**
9762 + * dpaa2_dq_is_pull_complete() - Check whether the pull command is completed.
9763 + * @dq: the dequeue result
9764 + *
9765 + * Return boolean.
9766 + */
9767 +static inline bool dpaa2_dq_is_pull_complete(const struct dpaa2_dq *dq)
9768 +{
9769 + return !!(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED);
9770 +}
9771 +
9772 +/**
9773 + * dpaa2_dq_seqnum() - Get the seqnum field in dequeue response
9774 + * @dq: the dequeue result
9775 + *
9776 + * seqnum is valid only if VALIDFRAME flag is TRUE
9777 + *
9778 + * Return seqnum.
9779 + */
9780 +static inline u16 dpaa2_dq_seqnum(const struct dpaa2_dq *dq)
9781 +{
9782 + return le16_to_cpu(dq->dq.seqnum);
9783 +}
9784 +
9785 +/**
9786 + * dpaa2_dq_odpid() - Get the odpid field in dequeue response
9787 + * @dq: the dequeue result
9788 + *
9789 + * odpid is valid only if ODPVALID flag is TRUE.
9790 + *
9791 + * Return odpid.
9792 + */
9793 +static inline u16 dpaa2_dq_odpid(const struct dpaa2_dq *dq)
9794 +{
9795 + return le16_to_cpu(dq->dq.oprid);
9796 +}
9797 +
9798 +/**
9799 + * dpaa2_dq_fqid() - Get the fqid in dequeue response
9800 + * @dq: the dequeue result
9801 + *
9802 + * Return fqid.
9803 + */
9804 +static inline u32 dpaa2_dq_fqid(const struct dpaa2_dq *dq)
9805 +{
9806 + return le32_to_cpu(dq->dq.fqid) & DQ_FQID_MASK;
9807 +}
9808 +
9809 +/**
9810 + * dpaa2_dq_byte_count() - Get the byte count in dequeue response
9811 + * @dq: the dequeue result
9812 + *
9813 + * Return the byte count remaining in the FQ.
9814 + */
9815 +static inline u32 dpaa2_dq_byte_count(const struct dpaa2_dq *dq)
9816 +{
9817 + return le32_to_cpu(dq->dq.fq_byte_cnt);
9818 +}
9819 +
9820 +/**
9821 + * dpaa2_dq_frame_count() - Get the frame count in dequeue response
9822 + * @dq: the dequeue result
9823 + *
9824 + * Return the frame count remaining in the FQ.
9825 + */
9826 +static inline u32 dpaa2_dq_frame_count(const struct dpaa2_dq *dq)
9827 +{
9828 + return le32_to_cpu(dq->dq.fq_frm_cnt) & DQ_FRAME_COUNT_MASK;
9829 +}
9830 +
9831 +/**
9832 + * dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response
9833 + * @dq: the dequeue result
9834 + *
9835 + * Return the frame queue context.
9836 + */
9837 +static inline u64 dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq)
9838 +{
9839 + return le64_to_cpu(dq->dq.fqd_ctx);
9840 +}
9841 +
9842 +/**
9843 + * dpaa2_dq_fd() - Get the frame descriptor in dequeue response
9844 + * @dq: the dequeue result
9845 + *
9846 + * Return the frame descriptor.
9847 + */
9848 +static inline const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq)
9849 +{
9850 + return (const struct dpaa2_fd *)&dq->dq.fd[0];
9851 +}
9852 +
9853 +#endif /* __FSL_DPAA2_GLOBAL_H */
9854 --- /dev/null
9855 +++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
9856 @@ -0,0 +1,190 @@
9857 +/*
9858 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9859 + * Copyright 2017 NXP
9860 + *
9861 + * Redistribution and use in source and binary forms, with or without
9862 + * modification, are permitted provided that the following conditions are met:
9863 + * * Redistributions of source code must retain the above copyright
9864 + * notice, this list of conditions and the following disclaimer.
9865 + * * Redistributions in binary form must reproduce the above copyright
9866 + * notice, this list of conditions and the following disclaimer in the
9867 + * documentation and/or other materials provided with the distribution.
9868 + * * Neither the name of Freescale Semiconductor nor the
9869 + * names of its contributors may be used to endorse or promote products
9870 + * derived from this software without specific prior written permission.
9871 + *
9872 + * ALTERNATIVELY, this software may be distributed under the terms of the
9873 + * GNU General Public License ("GPL") as published by the Free Software
9874 + * Foundation, either version 2 of that License or (at your option) any
9875 + * later version.
9876 + *
9877 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9878 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9879 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9880 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9881 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9882 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9883 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9884 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9885 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9886 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9887 + */
9888 +#ifndef __FSL_DPAA2_IO_H
9889 +#define __FSL_DPAA2_IO_H
9890 +
9891 +#include <linux/types.h>
9892 +#include <linux/cpumask.h>
9893 +
9894 +#include "dpaa2-fd.h"
9895 +#include "dpaa2-global.h"
9896 +
9897 +struct dpaa2_io;
9898 +struct dpaa2_io_store;
9899 +struct device;
9900 +
9901 +/**
9902 + * DOC: DPIO Service
9903 + *
9904 + * The DPIO service provides APIs for users to interact with the datapath
9905 + * by enqueueing and dequeing frame descriptors.
9906 + *
9907 + * The following set of APIs can be used to enqueue and dequeue frames
9908 + * as well as producing notification callbacks when data is available
9909 + * for dequeue.
9910 + */
9911 +
9912 +/**
9913 + * struct dpaa2_io_desc - The DPIO descriptor
9914 + * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
9915 + * has a channel.
9916 + * @has_8prio: Set to non-zero for channel with 8 priority WQs. Ignored
9917 + * unless receives_notification is TRUE.
9918 + * @cpu: The cpu index that at least interrupt handlers will
9919 + * execute on.
9920 + * @stash_affinity: The stash affinity for this portal favour 'cpu'
9921 + * @regs_cena: The cache enabled regs.
9922 + * @regs_cinh: The cache inhibited regs
9923 + * @dpio_id: The dpio index
9924 + * @qman_version: The qman version
9925 + *
9926 + * Describes the attributes and features of the DPIO object.
9927 + */
9928 +struct dpaa2_io_desc {
9929 + int receives_notifications;
9930 + int has_8prio;
9931 + int cpu;
9932 + void *regs_cena;
9933 + void *regs_cinh;
9934 + int dpio_id;
9935 + u32 qman_version;
9936 +};
9937 +
9938 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc);
9939 +
9940 +void dpaa2_io_down(struct dpaa2_io *d);
9941 +
9942 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
9943 +
9944 +/**
9945 + * struct dpaa2_io_notification_ctx - The DPIO notification context structure
9946 + * @cb: The callback to be invoked when the notification arrives
9947 + * @is_cdan: Zero for FQDAN, non-zero for CDAN
9948 + * @id: FQID or channel ID, needed for rearm
9949 + * @desired_cpu: The cpu on which the notifications will show up. -1 means
9950 + * any CPU.
9951 + * @dpio_id: The dpio index
9952 + * @qman64: The 64-bit context value shows up in the FQDAN/CDAN.
9953 + * @node: The list node
9954 + * @dpio_private: The dpio object internal to dpio_service
9955 + *
9956 + * Used when a FQDAN/CDAN registration is made by drivers.
9957 + */
9958 +struct dpaa2_io_notification_ctx {
9959 + void (*cb)(struct dpaa2_io_notification_ctx *);
9960 + int is_cdan;
9961 + u32 id;
9962 + int desired_cpu;
9963 + int dpio_id;
9964 + u64 qman64;
9965 + struct list_head node;
9966 + void *dpio_private;
9967 +};
9968 +
9969 +int dpaa2_io_service_register(struct dpaa2_io *service,
9970 + struct dpaa2_io_notification_ctx *ctx);
9971 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
9972 + struct dpaa2_io_notification_ctx *ctx);
9973 +int dpaa2_io_service_rearm(struct dpaa2_io *service,
9974 + struct dpaa2_io_notification_ctx *ctx);
9975 +
9976 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
9977 + struct dpaa2_io_store *s);
9978 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
9979 + struct dpaa2_io_store *s);
9980 +
9981 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, u32 fqid,
9982 + const struct dpaa2_fd *fd);
9983 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
9984 + u16 qdbin, const struct dpaa2_fd *fd);
9985 +int dpaa2_io_service_release(struct dpaa2_io *d, u32 bpid,
9986 + const u64 *buffers, unsigned int num_buffers);
9987 +int dpaa2_io_service_acquire(struct dpaa2_io *d, u32 bpid,
9988 + u64 *buffers, unsigned int num_buffers);
9989 +
9990 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
9991 + struct device *dev);
9992 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
9993 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
9994 +
9995 +#ifdef CONFIG_FSL_QBMAN_DEBUG
9996 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
9997 + uint32_t *fcnt, uint32_t *bcnt);
9998 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid,
9999 + uint32_t *num);
10000 +#endif
10001 +
10002 +
10003 +/***************/
10004 +/* CSCN */
10005 +/***************/
10006 +
10007 +/**
10008 + * struct dpaa2_cscn - The CSCN message format
10009 + * @verb: identifies the type of message (should be 0x27).
10010 + * @stat: status bits related to dequeuing response (not used)
10011 + * @state: bit 0 = 0/1 if CG is no/is congested
10012 + * @reserved: reserved byte
10013 + * @cgid: congest grp ID - the first 16 bits
10014 + * @ctx: context data
10015 + *
10016 + * Congestion management can be implemented in software through
10017 + * the use of Congestion State Change Notifications (CSCN). These
10018 + * are messages written by DPAA2 hardware to memory whenever the
10019 + * instantaneous count (I_CNT field in the CG) exceeds the
10020 + * Congestion State (CS) entrance threshold, signifying congestion
10021 + * entrance, or when the instantaneous count returns below exit
10022 + * threshold, signifying congestion exit. The format of the message
10023 + * is given by the dpaa2_cscn structure. Bit 0 of the state field
10024 + * represents congestion state written by the hardware.
10025 + */
10026 +struct dpaa2_cscn {
10027 + u8 verb;
10028 + u8 stat;
10029 + u8 state;
10030 + u8 reserved;
10031 + __le32 cgid;
10032 + __le64 ctx;
10033 +};
10034 +
10035 +#define DPAA2_CSCN_SIZE 64
10036 +#define DPAA2_CSCN_ALIGN 16
10037 +
10038 +#define DPAA2_CSCN_STATE_MASK 0x1
10039 +#define DPAA2_CSCN_CONGESTED 1
10040 +
10041 +static inline bool dpaa2_cscn_state_congested(struct dpaa2_cscn *cscn)
10042 +{
10043 + return ((cscn->state & DPAA2_CSCN_STATE_MASK) == DPAA2_CSCN_CONGESTED);
10044 +}
10045 +
10046 +#endif /* __FSL_DPAA2_IO_H */
10047 --- a/drivers/staging/fsl-mc/include/dpbp-cmd.h
10048 +++ /dev/null
10049 @@ -1,185 +0,0 @@
10050 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
10051 - *
10052 - * Redistribution and use in source and binary forms, with or without
10053 - * modification, are permitted provided that the following conditions are met:
10054 - * * Redistributions of source code must retain the above copyright
10055 - * notice, this list of conditions and the following disclaimer.
10056 - * * Redistributions in binary form must reproduce the above copyright
10057 - * notice, this list of conditions and the following disclaimer in the
10058 - * documentation and/or other materials provided with the distribution.
10059 - * * Neither the name of the above-listed copyright holders nor the
10060 - * names of any contributors may be used to endorse or promote products
10061 - * derived from this software without specific prior written permission.
10062 - *
10063 - *
10064 - * ALTERNATIVELY, this software may be distributed under the terms of the
10065 - * GNU General Public License ("GPL") as published by the Free Software
10066 - * Foundation, either version 2 of that License or (at your option) any
10067 - * later version.
10068 - *
10069 - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10070 - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10071 - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10072 - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10073 - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10074 - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10075 - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10076 - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10077 - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10078 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10079 - * POSSIBILITY OF SUCH DAMAGE.
10080 - */
10081 -#ifndef _FSL_DPBP_CMD_H
10082 -#define _FSL_DPBP_CMD_H
10083 -
10084 -/* DPBP Version */
10085 -#define DPBP_VER_MAJOR 2
10086 -#define DPBP_VER_MINOR 2
10087 -
10088 -/* Command IDs */
10089 -#define DPBP_CMDID_CLOSE 0x800
10090 -#define DPBP_CMDID_OPEN 0x804
10091 -#define DPBP_CMDID_CREATE 0x904
10092 -#define DPBP_CMDID_DESTROY 0x900
10093 -
10094 -#define DPBP_CMDID_ENABLE 0x002
10095 -#define DPBP_CMDID_DISABLE 0x003
10096 -#define DPBP_CMDID_GET_ATTR 0x004
10097 -#define DPBP_CMDID_RESET 0x005
10098 -#define DPBP_CMDID_IS_ENABLED 0x006
10099 -
10100 -#define DPBP_CMDID_SET_IRQ 0x010
10101 -#define DPBP_CMDID_GET_IRQ 0x011
10102 -#define DPBP_CMDID_SET_IRQ_ENABLE 0x012
10103 -#define DPBP_CMDID_GET_IRQ_ENABLE 0x013
10104 -#define DPBP_CMDID_SET_IRQ_MASK 0x014
10105 -#define DPBP_CMDID_GET_IRQ_MASK 0x015
10106 -#define DPBP_CMDID_GET_IRQ_STATUS 0x016
10107 -#define DPBP_CMDID_CLEAR_IRQ_STATUS 0x017
10108 -
10109 -#define DPBP_CMDID_SET_NOTIFICATIONS 0x01b0
10110 -#define DPBP_CMDID_GET_NOTIFICATIONS 0x01b1
10111 -
10112 -struct dpbp_cmd_open {
10113 - __le32 dpbp_id;
10114 -};
10115 -
10116 -#define DPBP_ENABLE 0x1
10117 -
10118 -struct dpbp_rsp_is_enabled {
10119 - u8 enabled;
10120 -};
10121 -
10122 -struct dpbp_cmd_set_irq {
10123 - /* cmd word 0 */
10124 - u8 irq_index;
10125 - u8 pad[3];
10126 - __le32 irq_val;
10127 - /* cmd word 1 */
10128 - __le64 irq_addr;
10129 - /* cmd word 2 */
10130 - __le32 irq_num;
10131 -};
10132 -
10133 -struct dpbp_cmd_get_irq {
10134 - __le32 pad;
10135 - u8 irq_index;
10136 -};
10137 -
10138 -struct dpbp_rsp_get_irq {
10139 - /* response word 0 */
10140 - __le32 irq_val;
10141 - __le32 pad;
10142 - /* response word 1 */
10143 - __le64 irq_addr;
10144 - /* response word 2 */
10145 - __le32 irq_num;
10146 - __le32 type;
10147 -};
10148 -
10149 -struct dpbp_cmd_set_irq_enable {
10150 - u8 enable;
10151 - u8 pad[3];
10152 - u8 irq_index;
10153 -};
10154 -
10155 -struct dpbp_cmd_get_irq_enable {
10156 - __le32 pad;
10157 - u8 irq_index;
10158 -};
10159 -
10160 -struct dpbp_rsp_get_irq_enable {
10161 - u8 enabled;
10162 -};
10163 -
10164 -struct dpbp_cmd_set_irq_mask {
10165 - __le32 mask;
10166 - u8 irq_index;
10167 -};
10168 -
10169 -struct dpbp_cmd_get_irq_mask {
10170 - __le32 pad;
10171 - u8 irq_index;
10172 -};
10173 -
10174 -struct dpbp_rsp_get_irq_mask {
10175 - __le32 mask;
10176 -};
10177 -
10178 -struct dpbp_cmd_get_irq_status {
10179 - __le32 status;
10180 - u8 irq_index;
10181 -};
10182 -
10183 -struct dpbp_rsp_get_irq_status {
10184 - __le32 status;
10185 -};
10186 -
10187 -struct dpbp_cmd_clear_irq_status {
10188 - __le32 status;
10189 - u8 irq_index;
10190 -};
10191 -
10192 -struct dpbp_rsp_get_attributes {
10193 - /* response word 0 */
10194 - __le16 pad;
10195 - __le16 bpid;
10196 - __le32 id;
10197 - /* response word 1 */
10198 - __le16 version_major;
10199 - __le16 version_minor;
10200 -};
10201 -
10202 -struct dpbp_cmd_set_notifications {
10203 - /* cmd word 0 */
10204 - __le32 depletion_entry;
10205 - __le32 depletion_exit;
10206 - /* cmd word 1 */
10207 - __le32 surplus_entry;
10208 - __le32 surplus_exit;
10209 - /* cmd word 2 */
10210 - __le16 options;
10211 - __le16 pad[3];
10212 - /* cmd word 3 */
10213 - __le64 message_ctx;
10214 - /* cmd word 4 */
10215 - __le64 message_iova;
10216 -};
10217 -
10218 -struct dpbp_rsp_get_notifications {
10219 - /* response word 0 */
10220 - __le32 depletion_entry;
10221 - __le32 depletion_exit;
10222 - /* response word 1 */
10223 - __le32 surplus_entry;
10224 - __le32 surplus_exit;
10225 - /* response word 2 */
10226 - __le16 options;
10227 - __le16 pad[3];
10228 - /* response word 3 */
10229 - __le64 message_ctx;
10230 - /* response word 4 */
10231 - __le64 message_iova;
10232 -};
10233 -
10234 -#endif /* _FSL_DPBP_CMD_H */
10235 --- a/drivers/staging/fsl-mc/include/dpbp.h
10236 +++ b/drivers/staging/fsl-mc/include/dpbp.h
10237 @@ -1,4 +1,5 @@
10238 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10239 +/*
10240 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10241 *
10242 * Redistribution and use in source and binary forms, with or without
10243 * modification, are permitted provided that the following conditions are met:
10244 @@ -32,7 +33,8 @@
10245 #ifndef __FSL_DPBP_H
10246 #define __FSL_DPBP_H
10247
10248 -/* Data Path Buffer Pool API
10249 +/*
10250 + * Data Path Buffer Pool API
10251 * Contains initialization APIs and runtime control APIs for DPBP
10252 */
10253
10254 @@ -44,25 +46,8 @@ int dpbp_open(struct fsl_mc_io *mc_io,
10255 u16 *token);
10256
10257 int dpbp_close(struct fsl_mc_io *mc_io,
10258 - u32 cmd_flags,
10259 - u16 token);
10260 -
10261 -/**
10262 - * struct dpbp_cfg - Structure representing DPBP configuration
10263 - * @options: place holder
10264 - */
10265 -struct dpbp_cfg {
10266 - u32 options;
10267 -};
10268 -
10269 -int dpbp_create(struct fsl_mc_io *mc_io,
10270 - u32 cmd_flags,
10271 - const struct dpbp_cfg *cfg,
10272 - u16 *token);
10273 -
10274 -int dpbp_destroy(struct fsl_mc_io *mc_io,
10275 - u32 cmd_flags,
10276 - u16 token);
10277 + u32 cmd_flags,
10278 + u16 token);
10279
10280 int dpbp_enable(struct fsl_mc_io *mc_io,
10281 u32 cmd_flags,
10282 @@ -82,139 +67,24 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
10283 u16 token);
10284
10285 /**
10286 - * struct dpbp_irq_cfg - IRQ configuration
10287 - * @addr: Address that must be written to signal a message-based interrupt
10288 - * @val: Value to write into irq_addr address
10289 - * @irq_num: A user defined number associated with this IRQ
10290 - */
10291 -struct dpbp_irq_cfg {
10292 - u64 addr;
10293 - u32 val;
10294 - int irq_num;
10295 -};
10296 -
10297 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
10298 - u32 cmd_flags,
10299 - u16 token,
10300 - u8 irq_index,
10301 - struct dpbp_irq_cfg *irq_cfg);
10302 -
10303 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
10304 - u32 cmd_flags,
10305 - u16 token,
10306 - u8 irq_index,
10307 - int *type,
10308 - struct dpbp_irq_cfg *irq_cfg);
10309 -
10310 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
10311 - u32 cmd_flags,
10312 - u16 token,
10313 - u8 irq_index,
10314 - u8 en);
10315 -
10316 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
10317 - u32 cmd_flags,
10318 - u16 token,
10319 - u8 irq_index,
10320 - u8 *en);
10321 -
10322 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
10323 - u32 cmd_flags,
10324 - u16 token,
10325 - u8 irq_index,
10326 - u32 mask);
10327 -
10328 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
10329 - u32 cmd_flags,
10330 - u16 token,
10331 - u8 irq_index,
10332 - u32 *mask);
10333 -
10334 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
10335 - u32 cmd_flags,
10336 - u16 token,
10337 - u8 irq_index,
10338 - u32 *status);
10339 -
10340 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
10341 - u32 cmd_flags,
10342 - u16 token,
10343 - u8 irq_index,
10344 - u32 status);
10345 -
10346 -/**
10347 * struct dpbp_attr - Structure representing DPBP attributes
10348 * @id: DPBP object ID
10349 - * @version: DPBP version
10350 * @bpid: Hardware buffer pool ID; should be used as an argument in
10351 * acquire/release operations on buffers
10352 */
10353 struct dpbp_attr {
10354 int id;
10355 - /**
10356 - * struct version - Structure representing DPBP version
10357 - * @major: DPBP major version
10358 - * @minor: DPBP minor version
10359 - */
10360 - struct {
10361 - u16 major;
10362 - u16 minor;
10363 - } version;
10364 u16 bpid;
10365 };
10366
10367 -int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10368 - u32 cmd_flags,
10369 - u16 token,
10370 - struct dpbp_attr *attr);
10371 -
10372 -/**
10373 - * DPBP notifications options
10374 - */
10375 -
10376 -/**
10377 - * BPSCN write will attempt to allocate into a cache (coherent write)
10378 - */
10379 -#define DPBP_NOTIF_OPT_COHERENT_WRITE 0x00000001
10380 -
10381 -/**
10382 - * struct dpbp_notification_cfg - Structure representing DPBP notifications
10383 - * towards software
10384 - * @depletion_entry: below this threshold the pool is "depleted";
10385 - * set it to '0' to disable it
10386 - * @depletion_exit: greater than or equal to this threshold the pool exit its
10387 - * "depleted" state
10388 - * @surplus_entry: above this threshold the pool is in "surplus" state;
10389 - * set it to '0' to disable it
10390 - * @surplus_exit: less than or equal to this threshold the pool exit its
10391 - * "surplus" state
10392 - * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry'
10393 - * is not '0' (enable); I/O virtual address (must be in DMA-able memory),
10394 - * must be 16B aligned.
10395 - * @message_ctx: The context that will be part of the BPSCN message and will
10396 - * be written to 'message_iova'
10397 - * @options: Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
10398 - */
10399 -struct dpbp_notification_cfg {
10400 - u32 depletion_entry;
10401 - u32 depletion_exit;
10402 - u32 surplus_entry;
10403 - u32 surplus_exit;
10404 - u64 message_iova;
10405 - u64 message_ctx;
10406 - u16 options;
10407 -};
10408 -
10409 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
10410 - u32 cmd_flags,
10411 - u16 token,
10412 - struct dpbp_notification_cfg *cfg);
10413 -
10414 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
10415 - u32 cmd_flags,
10416 - u16 token,
10417 - struct dpbp_notification_cfg *cfg);
10418 -
10419 -/** @} */
10420 +int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10421 + u32 cmd_flags,
10422 + u16 token,
10423 + struct dpbp_attr *attr);
10424 +
10425 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
10426 + u32 cmd_flags,
10427 + u16 *major_ver,
10428 + u16 *minor_ver);
10429
10430 #endif /* __FSL_DPBP_H */
10431 --- /dev/null
10432 +++ b/drivers/staging/fsl-mc/include/dpcon.h
10433 @@ -0,0 +1,115 @@
10434 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
10435 + *
10436 + * Redistribution and use in source and binary forms, with or without
10437 + * modification, are permitted provided that the following conditions are met:
10438 + * * Redistributions of source code must retain the above copyright
10439 + * notice, this list of conditions and the following disclaimer.
10440 + * * Redistributions in binary form must reproduce the above copyright
10441 + * notice, this list of conditions and the following disclaimer in the
10442 + * documentation and/or other materials provided with the distribution.
10443 + * * Neither the name of the above-listed copyright holders nor the
10444 + * names of any contributors may be used to endorse or promote products
10445 + * derived from this software without specific prior written permission.
10446 + *
10447 + *
10448 + * ALTERNATIVELY, this software may be distributed under the terms of the
10449 + * GNU General Public License ("GPL") as published by the Free Software
10450 + * Foundation, either version 2 of that License or (at your option) any
10451 + * later version.
10452 + *
10453 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10454 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10455 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10456 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10457 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10458 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10459 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10460 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10461 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10462 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10463 + * POSSIBILITY OF SUCH DAMAGE.
10464 + */
10465 +#ifndef __FSL_DPCON_H
10466 +#define __FSL_DPCON_H
10467 +
10468 +/* Data Path Concentrator API
10469 + * Contains initialization APIs and runtime control APIs for DPCON
10470 + */
10471 +
10472 +struct fsl_mc_io;
10473 +
10474 +/** General DPCON macros */
10475 +
10476 +/**
10477 + * Use it to disable notifications; see dpcon_set_notification()
10478 + */
10479 +#define DPCON_INVALID_DPIO_ID (int)(-1)
10480 +
10481 +int dpcon_open(struct fsl_mc_io *mc_io,
10482 + u32 cmd_flags,
10483 + int dpcon_id,
10484 + u16 *token);
10485 +
10486 +int dpcon_close(struct fsl_mc_io *mc_io,
10487 + u32 cmd_flags,
10488 + u16 token);
10489 +
10490 +int dpcon_enable(struct fsl_mc_io *mc_io,
10491 + u32 cmd_flags,
10492 + u16 token);
10493 +
10494 +int dpcon_disable(struct fsl_mc_io *mc_io,
10495 + u32 cmd_flags,
10496 + u16 token);
10497 +
10498 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
10499 + u32 cmd_flags,
10500 + u16 token,
10501 + int *en);
10502 +
10503 +int dpcon_reset(struct fsl_mc_io *mc_io,
10504 + u32 cmd_flags,
10505 + u16 token);
10506 +
10507 +/**
10508 + * struct dpcon_attr - Structure representing DPCON attributes
10509 + * @id: DPCON object ID
10510 + * @qbman_ch_id: Channel ID to be used by dequeue operation
10511 + * @num_priorities: Number of priorities for the DPCON channel (1-8)
10512 + */
10513 +struct dpcon_attr {
10514 + int id;
10515 + u16 qbman_ch_id;
10516 + u8 num_priorities;
10517 +};
10518 +
10519 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
10520 + u32 cmd_flags,
10521 + u16 token,
10522 + struct dpcon_attr *attr);
10523 +
10524 +/**
10525 + * struct dpcon_notification_cfg - Structure representing notification params
10526 + * @dpio_id: DPIO object ID; must be configured with a notification channel;
10527 + * to disable notifications set it to 'DPCON_INVALID_DPIO_ID';
10528 + * @priority: Priority selection within the DPIO channel; valid values
10529 + * are 0-7, depending on the number of priorities in that channel
10530 + * @user_ctx: User context value provided with each CDAN message
10531 + */
10532 +struct dpcon_notification_cfg {
10533 + int dpio_id;
10534 + u8 priority;
10535 + u64 user_ctx;
10536 +};
10537 +
10538 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
10539 + u32 cmd_flags,
10540 + u16 token,
10541 + struct dpcon_notification_cfg *cfg);
10542 +
10543 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
10544 + u32 cmd_flags,
10545 + u16 *major_ver,
10546 + u16 *minor_ver);
10547 +
10548 +#endif /* __FSL_DPCON_H */
10549 --- a/drivers/staging/fsl-mc/include/dpmng.h
10550 +++ b/drivers/staging/fsl-mc/include/dpmng.h
10551 @@ -1,4 +1,5 @@
10552 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10553 +/*
10554 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10555 *
10556 * Redistribution and use in source and binary forms, with or without
10557 * modification, are permitted provided that the following conditions are met:
10558 @@ -32,7 +33,8 @@
10559 #ifndef __FSL_DPMNG_H
10560 #define __FSL_DPMNG_H
10561
10562 -/* Management Complex General API
10563 +/*
10564 + * Management Complex General API
10565 * Contains general API for the Management Complex firmware
10566 */
10567
10568 @@ -58,12 +60,8 @@ struct mc_version {
10569 u32 revision;
10570 };
10571
10572 -int mc_get_version(struct fsl_mc_io *mc_io,
10573 - u32 cmd_flags,
10574 - struct mc_version *mc_ver_info);
10575 -
10576 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
10577 - u32 cmd_flags,
10578 - int *container_id);
10579 +int mc_get_version(struct fsl_mc_io *mc_io,
10580 + u32 cmd_flags,
10581 + struct mc_version *mc_ver_info);
10582
10583 #endif /* __FSL_DPMNG_H */
10584 --- /dev/null
10585 +++ b/drivers/staging/fsl-mc/include/dpopr.h
10586 @@ -0,0 +1,110 @@
10587 +/*
10588 + * Copyright 2017 NXP
10589 + *
10590 + * Redistribution and use in source and binary forms, with or without
10591 + * modification, are permitted provided that the following conditions are met:
10592 + * * Redistributions of source code must retain the above copyright
10593 + * notice, this list of conditions and the following disclaimer.
10594 + * * Redistributions in binary form must reproduce the above copyright
10595 + * notice, this list of conditions and the following disclaimer in the
10596 + * documentation and/or other materials provided with the distribution.
10597 + * * Neither the name of the above-listed copyright holders nor the
10598 + * names of any contributors may be used to endorse or promote products
10599 + * derived from this software without specific prior written permission.
10600 + *
10601 + *
10602 + * ALTERNATIVELY, this software may be distributed under the terms of the
10603 + * GNU General Public License ("GPL") as published by the Free Software
10604 + * Foundation, either version 2 of that License or (at your option) any
10605 + * later version.
10606 + *
10607 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10608 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10609 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10610 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10611 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10612 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10613 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10614 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10615 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10616 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10617 + * POSSIBILITY OF SUCH DAMAGE.
10618 + */
10619 +#ifndef __FSL_DPOPR_H_
10620 +#define __FSL_DPOPR_H_
10621 +
10622 +/* Data Path Order Restoration API
10623 + * Contains initialization APIs and runtime APIs for the Order Restoration
10624 + */
10625 +
10626 +/** Order Restoration properties */
10627 +
10628 +/**
10629 + * Create a new Order Point Record option
10630 + */
10631 +#define OPR_OPT_CREATE 0x1
10632 +/**
10633 + * Retire an existing Order Point Record option
10634 + */
10635 +#define OPR_OPT_RETIRE 0x2
10636 +
10637 +/**
10638 + * struct opr_cfg - Structure representing OPR configuration
10639 + * @oprrws: Order point record (OPR) restoration window size (0 to 5)
10640 + * 0 - Window size is 32 frames.
10641 + * 1 - Window size is 64 frames.
10642 + * 2 - Window size is 128 frames.
10643 + * 3 - Window size is 256 frames.
10644 + * 4 - Window size is 512 frames.
10645 + * 5 - Window size is 1024 frames.
10646 + * @oa: OPR auto advance NESN window size (0 disabled, 1 enabled)
10647 + * @olws: OPR acceptable late arrival window size (0 to 3)
10648 + * 0 - Disabled. Late arrivals are always rejected.
10649 + * 1 - Window size is 32 frames.
10650 + * 2 - Window size is the same as the OPR restoration
10651 + * window size configured in the OPRRWS field.
10652 + * 3 - Window size is 8192 frames. Late arrivals are
10653 + * always accepted.
10654 + * @oeane: Order restoration list (ORL) resource exhaustion
10655 + * advance NESN enable (0 disabled, 1 enabled)
10656 + * @oloe: OPR loose ordering enable (0 disabled, 1 enabled)
10657 + */
10658 +struct opr_cfg {
10659 + u8 oprrws;
10660 + u8 oa;
10661 + u8 olws;
10662 + u8 oeane;
10663 + u8 oloe;
10664 +};
10665 +
10666 +/**
10667 + * struct opr_qry - Structure representing OPR configuration
10668 + * @enable: Enabled state
10669 + * @rip: Retirement In Progress
10670 + * @ndsn: Next dispensed sequence number
10671 + * @nesn: Next expected sequence number
10672 + * @ea_hseq: Early arrival head sequence number
10673 + * @hseq_nlis: HSEQ not last in sequence
10674 + * @ea_tseq: Early arrival tail sequence number
10675 + * @tseq_nlis: TSEQ not last in sequence
10676 + * @ea_tptr: Early arrival tail pointer
10677 + * @ea_hptr: Early arrival head pointer
10678 + * @opr_id: Order Point Record ID
10679 + * @opr_vid: Order Point Record Virtual ID
10680 + */
10681 +struct opr_qry {
10682 + char enable;
10683 + char rip;
10684 + u16 ndsn;
10685 + u16 nesn;
10686 + u16 ea_hseq;
10687 + char hseq_nlis;
10688 + u16 ea_tseq;
10689 + char tseq_nlis;
10690 + u16 ea_tptr;
10691 + u16 ea_hptr;
10692 + u16 opr_id;
10693 + u16 opr_vid;
10694 +};
10695 +
10696 +#endif /* __FSL_DPOPR_H_ */
10697 --- a/drivers/staging/fsl-mc/include/dprc.h
10698 +++ b/drivers/staging/fsl-mc/include/dprc.h
10699 @@ -1,4 +1,5 @@
10700 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10701 +/*
10702 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10703 *
10704 * Redistribution and use in source and binary forms, with or without
10705 * modification, are permitted provided that the following conditions are met:
10706 @@ -34,26 +35,13 @@
10707
10708 #include "mc-cmd.h"
10709
10710 -/* Data Path Resource Container API
10711 +/*
10712 + * Data Path Resource Container API
10713 * Contains DPRC API for managing and querying DPAA resources
10714 */
10715
10716 struct fsl_mc_io;
10717
10718 -/**
10719 - * Set this value as the icid value in dprc_cfg structure when creating a
10720 - * container, in case the ICID is not selected by the user and should be
10721 - * allocated by the DPRC from the pool of ICIDs.
10722 - */
10723 -#define DPRC_GET_ICID_FROM_POOL (u16)(~(0))
10724 -
10725 -/**
10726 - * Set this value as the portal_id value in dprc_cfg structure when creating a
10727 - * container, in case the portal ID is not specifically selected by the
10728 - * user and should be allocated by the DPRC from the pool of portal ids.
10729 - */
10730 -#define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0))
10731 -
10732 int dprc_open(struct fsl_mc_io *mc_io,
10733 u32 cmd_flags,
10734 int container_id,
10735 @@ -63,75 +51,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
10736 u32 cmd_flags,
10737 u16 token);
10738
10739 -/**
10740 - * Container general options
10741 - *
10742 - * These options may be selected at container creation by the container creator
10743 - * and can be retrieved using dprc_get_attributes()
10744 - */
10745 -
10746 -/* Spawn Policy Option allowed - Indicates that the new container is allowed
10747 - * to spawn and have its own child containers.
10748 - */
10749 -#define DPRC_CFG_OPT_SPAWN_ALLOWED 0x00000001
10750 -
10751 -/* General Container allocation policy - Indicates that the new container is
10752 - * allowed to allocate requested resources from its parent container; if not
10753 - * set, the container is only allowed to use resources in its own pools; Note
10754 - * that this is a container's global policy, but the parent container may
10755 - * override it and set specific quota per resource type.
10756 - */
10757 -#define DPRC_CFG_OPT_ALLOC_ALLOWED 0x00000002
10758 -
10759 -/* Object initialization allowed - software context associated with this
10760 - * container is allowed to invoke object initialization operations.
10761 - */
10762 -#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED 0x00000004
10763 -
10764 -/* Topology change allowed - software context associated with this
10765 - * container is allowed to invoke topology operations, such as attach/detach
10766 - * of network objects.
10767 - */
10768 -#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008
10769 -
10770 -/* AIOP - Indicates that container belongs to AIOP. */
10771 -#define DPRC_CFG_OPT_AIOP 0x00000020
10772 -
10773 -/* IRQ Config - Indicates that the container allowed to configure its IRQs. */
10774 -#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040
10775 -
10776 -/**
10777 - * struct dprc_cfg - Container configuration options
10778 - * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
10779 - * ICID value is allocated by the DPRC
10780 - * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free
10781 - * portal ID is allocated by the DPRC
10782 - * @options: Combination of 'DPRC_CFG_OPT_<X>' options
10783 - * @label: Object's label
10784 - */
10785 -struct dprc_cfg {
10786 - u16 icid;
10787 - int portal_id;
10788 - u64 options;
10789 - char label[16];
10790 -};
10791 -
10792 -int dprc_create_container(struct fsl_mc_io *mc_io,
10793 - u32 cmd_flags,
10794 - u16 token,
10795 - struct dprc_cfg *cfg,
10796 - int *child_container_id,
10797 - u64 *child_portal_offset);
10798 -
10799 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
10800 - u32 cmd_flags,
10801 - u16 token,
10802 - int child_container_id);
10803 -
10804 -int dprc_reset_container(struct fsl_mc_io *mc_io,
10805 - u32 cmd_flags,
10806 - u16 token,
10807 - int child_container_id);
10808
10809 /* IRQ */
10810
10811 @@ -139,7 +58,7 @@ int dprc_reset_container(struct fsl_mc_i
10812 #define DPRC_IRQ_INDEX 0
10813
10814 /* Number of dprc's IRQs */
10815 -#define DPRC_NUM_OF_IRQS 1
10816 +#define DPRC_NUM_OF_IRQS 1
10817
10818 /* DPRC IRQ events */
10819
10820 @@ -151,12 +70,14 @@ int dprc_reset_container(struct fsl_mc_i
10821 #define DPRC_IRQ_EVENT_RES_ADDED 0x00000004
10822 /* IRQ event - Indicates that resources removed from the container */
10823 #define DPRC_IRQ_EVENT_RES_REMOVED 0x00000008
10824 -/* IRQ event - Indicates that one of the descendant containers that opened by
10825 +/*
10826 + * IRQ event - Indicates that one of the descendant containers that opened by
10827 * this container is destroyed
10828 */
10829 #define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010
10830
10831 -/* IRQ event - Indicates that on one of the container's opened object is
10832 +/*
10833 + * IRQ event - Indicates that on one of the container's opened object is
10834 * destroyed
10835 */
10836 #define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020
10837 @@ -171,59 +92,59 @@ int dprc_reset_container(struct fsl_mc_i
10838 * @irq_num: A user defined number associated with this IRQ
10839 */
10840 struct dprc_irq_cfg {
10841 - phys_addr_t paddr;
10842 - u32 val;
10843 - int irq_num;
10844 -};
10845 -
10846 -int dprc_set_irq(struct fsl_mc_io *mc_io,
10847 - u32 cmd_flags,
10848 - u16 token,
10849 - u8 irq_index,
10850 - struct dprc_irq_cfg *irq_cfg);
10851 -
10852 -int dprc_get_irq(struct fsl_mc_io *mc_io,
10853 - u32 cmd_flags,
10854 - u16 token,
10855 - u8 irq_index,
10856 - int *type,
10857 - struct dprc_irq_cfg *irq_cfg);
10858 -
10859 -int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10860 - u32 cmd_flags,
10861 - u16 token,
10862 - u8 irq_index,
10863 - u8 en);
10864 -
10865 -int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10866 - u32 cmd_flags,
10867 - u16 token,
10868 - u8 irq_index,
10869 - u8 *en);
10870 -
10871 -int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10872 - u32 cmd_flags,
10873 - u16 token,
10874 - u8 irq_index,
10875 - u32 mask);
10876 -
10877 -int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10878 - u32 cmd_flags,
10879 - u16 token,
10880 - u8 irq_index,
10881 - u32 *mask);
10882 -
10883 -int dprc_get_irq_status(struct fsl_mc_io *mc_io,
10884 - u32 cmd_flags,
10885 - u16 token,
10886 - u8 irq_index,
10887 - u32 *status);
10888 -
10889 -int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
10890 - u32 cmd_flags,
10891 - u16 token,
10892 - u8 irq_index,
10893 - u32 status);
10894 + phys_addr_t paddr;
10895 + u32 val;
10896 + int irq_num;
10897 +};
10898 +
10899 +int dprc_set_irq(struct fsl_mc_io *mc_io,
10900 + u32 cmd_flags,
10901 + u16 token,
10902 + u8 irq_index,
10903 + struct dprc_irq_cfg *irq_cfg);
10904 +
10905 +int dprc_get_irq(struct fsl_mc_io *mc_io,
10906 + u32 cmd_flags,
10907 + u16 token,
10908 + u8 irq_index,
10909 + int *type,
10910 + struct dprc_irq_cfg *irq_cfg);
10911 +
10912 +int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10913 + u32 cmd_flags,
10914 + u16 token,
10915 + u8 irq_index,
10916 + u8 en);
10917 +
10918 +int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10919 + u32 cmd_flags,
10920 + u16 token,
10921 + u8 irq_index,
10922 + u8 *en);
10923 +
10924 +int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10925 + u32 cmd_flags,
10926 + u16 token,
10927 + u8 irq_index,
10928 + u32 mask);
10929 +
10930 +int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10931 + u32 cmd_flags,
10932 + u16 token,
10933 + u8 irq_index,
10934 + u32 *mask);
10935 +
10936 +int dprc_get_irq_status(struct fsl_mc_io *mc_io,
10937 + u32 cmd_flags,
10938 + u16 token,
10939 + u8 irq_index,
10940 + u32 *status);
10941 +
10942 +int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
10943 + u32 cmd_flags,
10944 + u16 token,
10945 + u8 irq_index,
10946 + u32 status);
10947
10948 /**
10949 * struct dprc_attributes - Container attributes
10950 @@ -231,114 +152,23 @@ int dprc_clear_irq_status(struct fsl_mc_
10951 * @icid: Container's ICID
10952 * @portal_id: Container's portal ID
10953 * @options: Container's options as set at container's creation
10954 - * @version: DPRC version
10955 */
10956 struct dprc_attributes {
10957 int container_id;
10958 u16 icid;
10959 int portal_id;
10960 u64 options;
10961 - /**
10962 - * struct version - DPRC version
10963 - * @major: DPRC major version
10964 - * @minor: DPRC minor version
10965 - */
10966 - struct {
10967 - u16 major;
10968 - u16 minor;
10969 - } version;
10970 };
10971
10972 -int dprc_get_attributes(struct fsl_mc_io *mc_io,
10973 - u32 cmd_flags,
10974 - u16 token,
10975 - struct dprc_attributes *attributes);
10976 -
10977 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
10978 - u32 cmd_flags,
10979 - u16 token,
10980 - int child_container_id,
10981 - char *type,
10982 - u16 quota);
10983 -
10984 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
10985 - u32 cmd_flags,
10986 - u16 token,
10987 - int child_container_id,
10988 - char *type,
10989 - u16 *quota);
10990 -
10991 -/* Resource request options */
10992 -
10993 -/* Explicit resource ID request - The requested objects/resources
10994 - * are explicit and sequential (in case of resources).
10995 - * The base ID is given at res_req at base_align field
10996 - */
10997 -#define DPRC_RES_REQ_OPT_EXPLICIT 0x00000001
10998 -
10999 -/* Aligned resources request - Relevant only for resources
11000 - * request (and not objects). Indicates that resources base ID should be
11001 - * sequential and aligned to the value given at dprc_res_req base_align field
11002 - */
11003 -#define DPRC_RES_REQ_OPT_ALIGNED 0x00000002
11004 -
11005 -/* Plugged Flag - Relevant only for object assignment request.
11006 - * Indicates that after all objects assigned. An interrupt will be invoked at
11007 - * the relevant GPP. The assigned object will be marked as plugged.
11008 - * plugged objects can't be assigned from their container
11009 - */
11010 -#define DPRC_RES_REQ_OPT_PLUGGED 0x00000004
11011 -
11012 -/**
11013 - * struct dprc_res_req - Resource request descriptor, to be used in assignment
11014 - * or un-assignment of resources and objects.
11015 - * @type: Resource/object type: Represent as a NULL terminated string.
11016 - * This string may received by using dprc_get_pool() to get resource
11017 - * type and dprc_get_obj() to get object type;
11018 - * Note: it is not possible to assign/un-assign DPRC objects
11019 - * @num: Number of resources
11020 - * @options: Request options: combination of DPRC_RES_REQ_OPT_ options
11021 - * @id_base_align: In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT
11022 - * is set at option), this field represents the required base ID
11023 - * for resource allocation; In case of aligned assignment
11024 - * (DPRC_RES_REQ_OPT_ALIGNED is set at option), this field
11025 - * indicates the required alignment for the resource ID(s) -
11026 - * use 0 if there is no alignment or explicit ID requirements
11027 - */
11028 -struct dprc_res_req {
11029 - char type[16];
11030 - u32 num;
11031 - u32 options;
11032 - int id_base_align;
11033 -};
11034 -
11035 -int dprc_assign(struct fsl_mc_io *mc_io,
11036 - u32 cmd_flags,
11037 - u16 token,
11038 - int container_id,
11039 - struct dprc_res_req *res_req);
11040 -
11041 -int dprc_unassign(struct fsl_mc_io *mc_io,
11042 - u32 cmd_flags,
11043 - u16 token,
11044 - int child_container_id,
11045 - struct dprc_res_req *res_req);
11046 -
11047 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
11048 - u32 cmd_flags,
11049 - u16 token,
11050 - int *pool_count);
11051 -
11052 -int dprc_get_pool(struct fsl_mc_io *mc_io,
11053 - u32 cmd_flags,
11054 - u16 token,
11055 - int pool_index,
11056 - char *type);
11057 +int dprc_get_attributes(struct fsl_mc_io *mc_io,
11058 + u32 cmd_flags,
11059 + u16 token,
11060 + struct dprc_attributes *attributes);
11061
11062 int dprc_get_obj_count(struct fsl_mc_io *mc_io,
11063 - u32 cmd_flags,
11064 - u16 token,
11065 - int *obj_count);
11066 + u32 cmd_flags,
11067 + u16 token,
11068 + int *obj_count);
11069
11070 /* Objects Attributes Flags */
11071
11072 @@ -353,7 +183,7 @@ int dprc_get_obj_count(struct fsl_mc_io
11073 * masters;
11074 * user is responsible for proper memory handling through IOMMU configuration.
11075 */
11076 -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
11077 +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
11078
11079 /**
11080 * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
11081 @@ -381,41 +211,41 @@ struct dprc_obj_desc {
11082 u16 flags;
11083 };
11084
11085 -int dprc_get_obj(struct fsl_mc_io *mc_io,
11086 - u32 cmd_flags,
11087 - u16 token,
11088 - int obj_index,
11089 - struct dprc_obj_desc *obj_desc);
11090 -
11091 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
11092 - u32 cmd_flags,
11093 - u16 token,
11094 - char *obj_type,
11095 - int obj_id,
11096 - struct dprc_obj_desc *obj_desc);
11097 -
11098 -int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
11099 - u32 cmd_flags,
11100 - u16 token,
11101 - char *obj_type,
11102 - int obj_id,
11103 - u8 irq_index,
11104 - struct dprc_irq_cfg *irq_cfg);
11105 -
11106 -int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
11107 - u32 cmd_flags,
11108 - u16 token,
11109 - char *obj_type,
11110 - int obj_id,
11111 - u8 irq_index,
11112 - int *type,
11113 - struct dprc_irq_cfg *irq_cfg);
11114 -
11115 -int dprc_get_res_count(struct fsl_mc_io *mc_io,
11116 - u32 cmd_flags,
11117 - u16 token,
11118 - char *type,
11119 - int *res_count);
11120 +int dprc_get_obj(struct fsl_mc_io *mc_io,
11121 + u32 cmd_flags,
11122 + u16 token,
11123 + int obj_index,
11124 + struct dprc_obj_desc *obj_desc);
11125 +
11126 +int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
11127 + u32 cmd_flags,
11128 + u16 token,
11129 + char *obj_type,
11130 + int obj_id,
11131 + struct dprc_obj_desc *obj_desc);
11132 +
11133 +int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
11134 + u32 cmd_flags,
11135 + u16 token,
11136 + char *obj_type,
11137 + int obj_id,
11138 + u8 irq_index,
11139 + struct dprc_irq_cfg *irq_cfg);
11140 +
11141 +int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
11142 + u32 cmd_flags,
11143 + u16 token,
11144 + char *obj_type,
11145 + int obj_id,
11146 + u8 irq_index,
11147 + int *type,
11148 + struct dprc_irq_cfg *irq_cfg);
11149 +
11150 +int dprc_get_res_count(struct fsl_mc_io *mc_io,
11151 + u32 cmd_flags,
11152 + u16 token,
11153 + char *type,
11154 + int *res_count);
11155
11156 /**
11157 * enum dprc_iter_status - Iteration status
11158 @@ -429,27 +259,6 @@ enum dprc_iter_status {
11159 DPRC_ITER_STATUS_LAST = 2
11160 };
11161
11162 -/**
11163 - * struct dprc_res_ids_range_desc - Resource ID range descriptor
11164 - * @base_id: Base resource ID of this range
11165 - * @last_id: Last resource ID of this range
11166 - * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
11167 - * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
11168 - * additional iterations are needed, until the returned marker is
11169 - * DPRC_ITER_STATUS_LAST
11170 - */
11171 -struct dprc_res_ids_range_desc {
11172 - int base_id;
11173 - int last_id;
11174 - enum dprc_iter_status iter_status;
11175 -};
11176 -
11177 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
11178 - u32 cmd_flags,
11179 - u16 token,
11180 - char *type,
11181 - struct dprc_res_ids_range_desc *range_desc);
11182 -
11183 /* Region flags */
11184 /* Cacheable - Indicates that region should be mapped as cacheable */
11185 #define DPRC_REGION_CACHEABLE 0x00000001
11186 @@ -481,64 +290,27 @@ struct dprc_region_desc {
11187 enum dprc_region_type type;
11188 };
11189
11190 -int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11191 - u32 cmd_flags,
11192 - u16 token,
11193 - char *obj_type,
11194 - int obj_id,
11195 - u8 region_index,
11196 - struct dprc_region_desc *region_desc);
11197 -
11198 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
11199 - u32 cmd_flags,
11200 - u16 token,
11201 - char *obj_type,
11202 - int obj_id,
11203 - char *label);
11204 +int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11205 + u32 cmd_flags,
11206 + u16 token,
11207 + char *obj_type,
11208 + int obj_id,
11209 + u8 region_index,
11210 + struct dprc_region_desc *region_desc);
11211
11212 -/**
11213 - * struct dprc_endpoint - Endpoint description for link connect/disconnect
11214 - * operations
11215 - * @type: Endpoint object type: NULL terminated string
11216 - * @id: Endpoint object ID
11217 - * @if_id: Interface ID; should be set for endpoints with multiple
11218 - * interfaces ("dpsw", "dpdmux"); for others, always set to 0
11219 - */
11220 -struct dprc_endpoint {
11221 - char type[16];
11222 - int id;
11223 - int if_id;
11224 -};
11225 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
11226 + u32 cmd_flags,
11227 + u16 *major_ver,
11228 + u16 *minor_ver);
11229
11230 -/**
11231 - * struct dprc_connection_cfg - Connection configuration.
11232 - * Used for virtual connections only
11233 - * @committed_rate: Committed rate (Mbits/s)
11234 - * @max_rate: Maximum rate (Mbits/s)
11235 - */
11236 -struct dprc_connection_cfg {
11237 - u32 committed_rate;
11238 - u32 max_rate;
11239 -};
11240 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
11241 + u32 cmd_flags,
11242 + int *container_id);
11243
11244 -int dprc_connect(struct fsl_mc_io *mc_io,
11245 - u32 cmd_flags,
11246 - u16 token,
11247 - const struct dprc_endpoint *endpoint1,
11248 - const struct dprc_endpoint *endpoint2,
11249 - const struct dprc_connection_cfg *cfg);
11250 -
11251 -int dprc_disconnect(struct fsl_mc_io *mc_io,
11252 - u32 cmd_flags,
11253 - u16 token,
11254 - const struct dprc_endpoint *endpoint);
11255 -
11256 -int dprc_get_connection(struct fsl_mc_io *mc_io,
11257 - u32 cmd_flags,
11258 - u16 token,
11259 - const struct dprc_endpoint *endpoint1,
11260 - struct dprc_endpoint *endpoint2,
11261 - int *state);
11262 +int dprc_reset_container(struct fsl_mc_io *mc_io,
11263 + u32 cmd_flags,
11264 + u16 token,
11265 + int child_container_id);
11266
11267 #endif /* _FSL_DPRC_H */
11268
11269 --- a/drivers/staging/fsl-mc/include/mc-bus.h
11270 +++ b/drivers/staging/fsl-mc/include/mc-bus.h
11271 @@ -1,7 +1,7 @@
11272 /*
11273 * Freescale Management Complex (MC) bus declarations
11274 *
11275 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11276 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11277 * Author: German Rivera <German.Rivera@freescale.com>
11278 *
11279 * This file is licensed under the terms of the GNU General Public
11280 @@ -42,8 +42,8 @@ struct msi_domain_info;
11281 */
11282 struct fsl_mc_resource_pool {
11283 enum fsl_mc_pool_type type;
11284 - int16_t max_count;
11285 - int16_t free_count;
11286 + int max_count;
11287 + int free_count;
11288 struct mutex mutex; /* serializes access to free_list */
11289 struct list_head free_list;
11290 struct fsl_mc_bus *mc_bus;
11291 @@ -73,6 +73,7 @@ struct fsl_mc_bus {
11292 int dprc_scan_container(struct fsl_mc_device *mc_bus_dev);
11293
11294 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
11295 + const char *driver_override,
11296 unsigned int *total_irq_count);
11297
11298 int __init dprc_driver_init(void);
11299 --- a/drivers/staging/fsl-mc/include/mc-cmd.h
11300 +++ b/drivers/staging/fsl-mc/include/mc-cmd.h
11301 @@ -1,4 +1,5 @@
11302 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
11303 +/*
11304 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11305 *
11306 * Redistribution and use in source and binary forms, with or without
11307 * modification, are permitted provided that the following conditions are met:
11308 @@ -48,6 +49,15 @@ struct mc_command {
11309 u64 params[MC_CMD_NUM_OF_PARAMS];
11310 };
11311
11312 +struct mc_rsp_create {
11313 + __le32 object_id;
11314 +};
11315 +
11316 +struct mc_rsp_api_ver {
11317 + __le16 major_ver;
11318 + __le16 minor_ver;
11319 +};
11320 +
11321 enum mc_cmd_status {
11322 MC_CMD_STATUS_OK = 0x0, /* Completed successfully */
11323 MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */
11324 @@ -72,11 +82,6 @@ enum mc_cmd_status {
11325 /* Command completion flag */
11326 #define MC_CMD_FLAG_INTR_DIS 0x01
11327
11328 -#define MC_CMD_HDR_CMDID_MASK 0xFFF0
11329 -#define MC_CMD_HDR_CMDID_SHIFT 4
11330 -#define MC_CMD_HDR_TOKEN_MASK 0xFFC0
11331 -#define MC_CMD_HDR_TOKEN_SHIFT 6
11332 -
11333 static inline u64 mc_encode_cmd_header(u16 cmd_id,
11334 u32 cmd_flags,
11335 u16 token)
11336 @@ -84,10 +89,8 @@ static inline u64 mc_encode_cmd_header(u
11337 u64 header = 0;
11338 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header;
11339
11340 - hdr->cmd_id = cpu_to_le16((cmd_id << MC_CMD_HDR_CMDID_SHIFT) &
11341 - MC_CMD_HDR_CMDID_MASK);
11342 - hdr->token = cpu_to_le16((token << MC_CMD_HDR_TOKEN_SHIFT) &
11343 - MC_CMD_HDR_TOKEN_MASK);
11344 + hdr->cmd_id = cpu_to_le16(cmd_id);
11345 + hdr->token = cpu_to_le16(token);
11346 hdr->status = MC_CMD_STATUS_READY;
11347 if (cmd_flags & MC_CMD_FLAG_PRI)
11348 hdr->flags_hw = MC_CMD_FLAG_PRI;
11349 @@ -102,7 +105,26 @@ static inline u16 mc_cmd_hdr_read_token(
11350 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
11351 u16 token = le16_to_cpu(hdr->token);
11352
11353 - return (token & MC_CMD_HDR_TOKEN_MASK) >> MC_CMD_HDR_TOKEN_SHIFT;
11354 + return token;
11355 +}
11356 +
11357 +static inline u32 mc_cmd_read_object_id(struct mc_command *cmd)
11358 +{
11359 + struct mc_rsp_create *rsp_params;
11360 +
11361 + rsp_params = (struct mc_rsp_create *)cmd->params;
11362 + return le32_to_cpu(rsp_params->object_id);
11363 +}
11364 +
11365 +static inline void mc_cmd_read_api_version(struct mc_command *cmd,
11366 + u16 *major_ver,
11367 + u16 *minor_ver)
11368 +{
11369 + struct mc_rsp_api_ver *rsp_params;
11370 +
11371 + rsp_params = (struct mc_rsp_api_ver *)cmd->params;
11372 + *major_ver = le16_to_cpu(rsp_params->major_ver);
11373 + *minor_ver = le16_to_cpu(rsp_params->minor_ver);
11374 }
11375
11376 #endif /* __FSL_MC_CMD_H */
11377 --- a/drivers/staging/fsl-mc/include/mc-sys.h
11378 +++ b/drivers/staging/fsl-mc/include/mc-sys.h
11379 @@ -1,4 +1,5 @@
11380 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
11381 +/*
11382 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11383 *
11384 * Interface of the I/O services to send MC commands to the MC hardware
11385 *
11386 --- a/drivers/staging/fsl-mc/include/mc.h
11387 +++ b/drivers/staging/fsl-mc/include/mc.h
11388 @@ -1,7 +1,7 @@
11389 /*
11390 * Freescale Management Complex (MC) bus public interface
11391 *
11392 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11393 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11394 * Author: German Rivera <German.Rivera@freescale.com>
11395 *
11396 * This file is licensed under the terms of the GNU General Public
11397 @@ -81,7 +81,7 @@ enum fsl_mc_pool_type {
11398 */
11399 struct fsl_mc_resource {
11400 enum fsl_mc_pool_type type;
11401 - int32_t id;
11402 + s32 id;
11403 void *data;
11404 struct fsl_mc_resource_pool *parent_pool;
11405 struct list_head node;
11406 @@ -122,6 +122,7 @@ struct fsl_mc_device_irq {
11407 * @regions: pointer to array of MMIO region entries
11408 * @irqs: pointer to array of pointers to interrupts allocated to this device
11409 * @resource: generic resource associated with this MC object device, if any.
11410 + * @driver_override: Driver name to force a match
11411 *
11412 * Generic device object for MC object devices that are "attached" to a
11413 * MC bus.
11414 @@ -154,6 +155,7 @@ struct fsl_mc_device {
11415 struct resource *regions;
11416 struct fsl_mc_device_irq **irqs;
11417 struct fsl_mc_resource *resource;
11418 + const char *driver_override;
11419 };
11420
11421 #define to_fsl_mc_device(_dev) \
11422 @@ -175,6 +177,8 @@ struct fsl_mc_device {
11423 #define fsl_mc_driver_register(drv) \
11424 __fsl_mc_driver_register(drv, THIS_MODULE)
11425
11426 +void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
11427 +
11428 int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver,
11429 struct module *owner);
11430
11431 @@ -198,4 +202,13 @@ int __must_check fsl_mc_allocate_irqs(st
11432
11433 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
11434
11435 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
11436 + struct device_node *fsl_mc_platform_node, int coherent);
11437 +
11438 +#ifdef CONFIG_FSL_MC_BUS
11439 +struct iommu_group *fsl_mc_device_group(struct device *dev);
11440 +#else
11441 +#define fsl_mc_device_group(__dev) NULL
11442 +#endif
11443 +
11444 #endif /* _FSL_MC_H_ */
Staging tree of Zoltan Herpai