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kernel: bump 4.9 to 4.9.63
[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-4.9 / 704-fsl-mc-layerscape-support.patch
1 From afb7254de9f03c3efaf4e306dcf5f88e1873fc6b Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:06:25 +0800
4 Subject: [PATCH] fsl-mc: layerscape support
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 This is a integrated patch for layerscape mc-bus support.
10
11 Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
12 Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
13 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
14 Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
15 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
16 Signed-off-by: Shiva Kerdel <shiva@exdev.nl>
17 Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
18 Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
19 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
20 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
21 ---
22 drivers/staging/fsl-mc/bus/Kconfig | 41 +-
23 drivers/staging/fsl-mc/bus/Makefile | 10 +-
24 drivers/staging/fsl-mc/bus/dpbp-cmd.h | 80 ++
25 drivers/staging/fsl-mc/bus/dpbp.c | 450 +--------
26 drivers/staging/fsl-mc/bus/dpcon-cmd.h | 85 ++
27 drivers/staging/fsl-mc/bus/dpcon.c | 317 ++++++
28 drivers/staging/fsl-mc/bus/dpio/Makefile | 11 +
29 .../{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} | 73 +-
30 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c | 296 ++++++
31 drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt | 135 +++
32 drivers/staging/fsl-mc/bus/dpio/dpio-service.c | 693 +++++++++++++
33 drivers/staging/fsl-mc/bus/dpio/dpio.c | 224 +++++
34 drivers/staging/fsl-mc/bus/dpio/dpio.h | 109 ++
35 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c | 1049 ++++++++++++++++++++
36 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h | 662 ++++++++++++
37 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c | 853 ++++++++++++++++
38 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h | 136 +++
39 drivers/staging/fsl-mc/bus/dpio/qbman_private.h | 171 ++++
40 drivers/staging/fsl-mc/bus/dpmcp-cmd.h | 112 +--
41 drivers/staging/fsl-mc/bus/dpmcp.c | 374 +------
42 drivers/staging/fsl-mc/bus/dpmcp.h | 127 +--
43 drivers/staging/fsl-mc/bus/dpmng-cmd.h | 14 +-
44 drivers/staging/fsl-mc/bus/dpmng.c | 37 +-
45 drivers/staging/fsl-mc/bus/dprc-cmd.h | 82 +-
46 drivers/staging/fsl-mc/bus/dprc-driver.c | 38 +-
47 drivers/staging/fsl-mc/bus/dprc.c | 629 +-----------
48 drivers/staging/fsl-mc/bus/fsl-mc-allocator.c | 78 +-
49 drivers/staging/fsl-mc/bus/fsl-mc-bus.c | 318 +++---
50 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c | 104 ++
51 drivers/staging/fsl-mc/bus/fsl-mc-msi.c | 3 +-
52 drivers/staging/fsl-mc/bus/fsl-mc-private.h | 6 +-
53 .../staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c | 11 +-
54 drivers/staging/fsl-mc/bus/mc-io.c | 4 +-
55 drivers/staging/fsl-mc/bus/mc-ioctl.h | 22 +
56 drivers/staging/fsl-mc/bus/mc-restool.c | 405 ++++++++
57 drivers/staging/fsl-mc/bus/mc-sys.c | 14 +-
58 drivers/staging/fsl-mc/include/dpaa2-fd.h | 706 +++++++++++++
59 drivers/staging/fsl-mc/include/dpaa2-global.h | 202 ++++
60 drivers/staging/fsl-mc/include/dpaa2-io.h | 190 ++++
61 drivers/staging/fsl-mc/include/dpbp-cmd.h | 185 ----
62 drivers/staging/fsl-mc/include/dpbp.h | 158 +--
63 drivers/staging/fsl-mc/include/dpcon.h | 115 +++
64 drivers/staging/fsl-mc/include/dpmng.h | 16 +-
65 drivers/staging/fsl-mc/include/dpopr.h | 110 ++
66 drivers/staging/fsl-mc/include/dprc.h | 470 +++------
67 drivers/staging/fsl-mc/include/mc-bus.h | 7 +-
68 drivers/staging/fsl-mc/include/mc-cmd.h | 44 +-
69 drivers/staging/fsl-mc/include/mc-sys.h | 3 +-
70 drivers/staging/fsl-mc/include/mc.h | 17 +-
71 49 files changed, 7384 insertions(+), 2612 deletions(-)
72 create mode 100644 drivers/staging/fsl-mc/bus/dpbp-cmd.h
73 create mode 100644 drivers/staging/fsl-mc/bus/dpcon-cmd.h
74 create mode 100644 drivers/staging/fsl-mc/bus/dpcon.c
75 create mode 100644 drivers/staging/fsl-mc/bus/dpio/Makefile
76 rename drivers/staging/fsl-mc/{include/dpcon-cmd.h => bus/dpio/dpio-cmd.h} (64%)
77 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
78 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt
79 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio-service.c
80 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.c
81 create mode 100644 drivers/staging/fsl-mc/bus/dpio/dpio.h
82 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
83 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
84 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
85 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
86 create mode 100644 drivers/staging/fsl-mc/bus/dpio/qbman_private.h
87 create mode 100644 drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
88 create mode 100644 drivers/staging/fsl-mc/bus/mc-ioctl.h
89 create mode 100644 drivers/staging/fsl-mc/bus/mc-restool.c
90 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-fd.h
91 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-global.h
92 create mode 100644 drivers/staging/fsl-mc/include/dpaa2-io.h
93 delete mode 100644 drivers/staging/fsl-mc/include/dpbp-cmd.h
94 create mode 100644 drivers/staging/fsl-mc/include/dpcon.h
95 create mode 100644 drivers/staging/fsl-mc/include/dpopr.h
96
97 --- a/drivers/staging/fsl-mc/bus/Kconfig
98 +++ b/drivers/staging/fsl-mc/bus/Kconfig
99 @@ -1,25 +1,40 @@
100 #
101 -# Freescale Management Complex (MC) bus drivers
102 +# DPAA2 fsl-mc bus
103 #
104 -# Copyright (C) 2014 Freescale Semiconductor, Inc.
105 +# Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
106 #
107 # This file is released under the GPLv2
108 #
109
110 config FSL_MC_BUS
111 - bool "Freescale Management Complex (MC) bus driver"
112 - depends on OF && ARM64
113 + bool "QorIQ DPAA2 fsl-mc bus driver"
114 + depends on OF && ARCH_LAYERSCAPE
115 select GENERIC_MSI_IRQ_DOMAIN
116 help
117 - Driver to enable the bus infrastructure for the Freescale
118 - QorIQ Management Complex (fsl-mc). The fsl-mc is a hardware
119 - module of the QorIQ LS2 SoCs, that does resource management
120 - for hardware building-blocks in the SoC that can be used
121 - to dynamically create networking hardware objects such as
122 - network interfaces (NICs), crypto accelerator instances,
123 - or L2 switches.
124 + Driver to enable the bus infrastructure for the QorIQ DPAA2
125 + architecture. The fsl-mc bus driver handles discovery of
126 + DPAA2 objects (which are represented as Linux devices) and
127 + binding objects to drivers.
128
129 - Only enable this option when building the kernel for
130 - Freescale QorQIQ LS2xxxx SoCs.
131 +config FSL_MC_DPIO
132 + tristate "QorIQ DPAA2 DPIO driver"
133 + depends on FSL_MC_BUS
134 + help
135 + Driver for the DPAA2 DPIO object. A DPIO provides queue and
136 + buffer management facilities for software to interact with
137 + other DPAA2 objects. This driver does not expose the DPIO
138 + objects individually, but groups them under a service layer
139 + API.
140
141 +config FSL_QBMAN_DEBUG
142 + tristate "Freescale QBMAN Debug APIs"
143 + depends on FSL_MC_DPIO
144 + help
145 + QBMan debug assistant APIs.
146
147 +config FSL_MC_RESTOOL
148 + tristate "Freescale Management Complex (MC) restool driver"
149 + depends on FSL_MC_BUS
150 + help
151 + Driver that provides kernel support for the Freescale Management
152 + Complex resource manager user-space tool.
153 --- a/drivers/staging/fsl-mc/bus/Makefile
154 +++ b/drivers/staging/fsl-mc/bus/Makefile
155 @@ -17,4 +17,12 @@ mc-bus-driver-objs := fsl-mc-bus.o \
156 fsl-mc-msi.o \
157 irq-gic-v3-its-fsl-mc-msi.o \
158 dpmcp.o \
159 - dpbp.o
160 + dpbp.o \
161 + dpcon.o \
162 + fsl-mc-iommu.o
163 +
164 +# MC DPIO driver
165 +obj-$(CONFIG_FSL_MC_DPIO) += dpio/
166 +
167 +# MC restool kernel support
168 +obj-$(CONFIG_FSL_MC_RESTOOL) += mc-restool.o
169 --- /dev/null
170 +++ b/drivers/staging/fsl-mc/bus/dpbp-cmd.h
171 @@ -0,0 +1,80 @@
172 +/*
173 + * Copyright 2013-2016 Freescale Semiconductor Inc.
174 + *
175 + * Redistribution and use in source and binary forms, with or without
176 + * modification, are permitted provided that the following conditions are met:
177 + * * Redistributions of source code must retain the above copyright
178 + * notice, this list of conditions and the following disclaimer.
179 + * * Redistributions in binary form must reproduce the above copyright
180 + * notice, this list of conditions and the following disclaimer in the
181 + * documentation and/or other materials provided with the distribution.
182 + * * Neither the name of the above-listed copyright holders nor the
183 + * names of any contributors may be used to endorse or promote products
184 + * derived from this software without specific prior written permission.
185 + *
186 + * ALTERNATIVELY, this software may be distributed under the terms of the
187 + * GNU General Public License ("GPL") as published by the Free Software
188 + * Foundation, either version 2 of that License or (at your option) any
189 + * later version.
190 + *
191 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
192 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
193 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
194 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
195 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
196 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
197 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
198 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
199 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
200 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
201 + * POSSIBILITY OF SUCH DAMAGE.
202 + */
203 +#ifndef _FSL_DPBP_CMD_H
204 +#define _FSL_DPBP_CMD_H
205 +
206 +/* DPBP Version */
207 +#define DPBP_VER_MAJOR 3
208 +#define DPBP_VER_MINOR 2
209 +
210 +/* Command versioning */
211 +#define DPBP_CMD_BASE_VERSION 1
212 +#define DPBP_CMD_ID_OFFSET 4
213 +
214 +#define DPBP_CMD(id) ((id << DPBP_CMD_ID_OFFSET) | DPBP_CMD_BASE_VERSION)
215 +
216 +/* Command IDs */
217 +#define DPBP_CMDID_CLOSE DPBP_CMD(0x800)
218 +#define DPBP_CMDID_OPEN DPBP_CMD(0x804)
219 +#define DPBP_CMDID_GET_API_VERSION DPBP_CMD(0xa04)
220 +
221 +#define DPBP_CMDID_ENABLE DPBP_CMD(0x002)
222 +#define DPBP_CMDID_DISABLE DPBP_CMD(0x003)
223 +#define DPBP_CMDID_GET_ATTR DPBP_CMD(0x004)
224 +#define DPBP_CMDID_RESET DPBP_CMD(0x005)
225 +#define DPBP_CMDID_IS_ENABLED DPBP_CMD(0x006)
226 +
227 +struct dpbp_cmd_open {
228 + __le32 dpbp_id;
229 +};
230 +
231 +struct dpbp_cmd_destroy {
232 + __le32 object_id;
233 +};
234 +
235 +#define DPBP_ENABLE 0x1
236 +
237 +struct dpbp_rsp_is_enabled {
238 + u8 enabled;
239 +};
240 +
241 +struct dpbp_rsp_get_attributes {
242 + /* response word 0 */
243 + __le16 pad;
244 + __le16 bpid;
245 + __le32 id;
246 + /* response word 1 */
247 + __le16 version_major;
248 + __le16 version_minor;
249 +};
250 +
251 +#endif /* _FSL_DPBP_CMD_H */
252 --- a/drivers/staging/fsl-mc/bus/dpbp.c
253 +++ b/drivers/staging/fsl-mc/bus/dpbp.c
254 @@ -1,4 +1,5 @@
255 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
256 +/*
257 + * Copyright 2013-2016 Freescale Semiconductor Inc.
258 *
259 * Redistribution and use in source and binary forms, with or without
260 * modification, are permitted provided that the following conditions are met:
261 @@ -11,7 +12,6 @@
262 * names of any contributors may be used to endorse or promote products
263 * derived from this software without specific prior written permission.
264 *
265 - *
266 * ALTERNATIVELY, this software may be distributed under the terms of the
267 * GNU General Public License ("GPL") as published by the Free Software
268 * Foundation, either version 2 of that License or (at your option) any
269 @@ -32,7 +32,8 @@
270 #include "../include/mc-sys.h"
271 #include "../include/mc-cmd.h"
272 #include "../include/dpbp.h"
273 -#include "../include/dpbp-cmd.h"
274 +
275 +#include "dpbp-cmd.h"
276
277 /**
278 * dpbp_open() - Open a control session for the specified object.
279 @@ -105,74 +106,6 @@ int dpbp_close(struct fsl_mc_io *mc_io,
280 EXPORT_SYMBOL(dpbp_close);
281
282 /**
283 - * dpbp_create() - Create the DPBP object.
284 - * @mc_io: Pointer to MC portal's I/O object
285 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
286 - * @cfg: Configuration structure
287 - * @token: Returned token; use in subsequent API calls
288 - *
289 - * Create the DPBP object, allocate required resources and
290 - * perform required initialization.
291 - *
292 - * The object can be created either by declaring it in the
293 - * DPL file, or by calling this function.
294 - * This function returns a unique authentication token,
295 - * associated with the specific object ID and the specific MC
296 - * portal; this token must be used in all subsequent calls to
297 - * this specific object. For objects that are created using the
298 - * DPL file, call dpbp_open function to get an authentication
299 - * token first.
300 - *
301 - * Return: '0' on Success; Error code otherwise.
302 - */
303 -int dpbp_create(struct fsl_mc_io *mc_io,
304 - u32 cmd_flags,
305 - const struct dpbp_cfg *cfg,
306 - u16 *token)
307 -{
308 - struct mc_command cmd = { 0 };
309 - int err;
310 -
311 - (void)(cfg); /* unused */
312 -
313 - /* prepare command */
314 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE,
315 - cmd_flags, 0);
316 -
317 - /* send command to mc*/
318 - err = mc_send_command(mc_io, &cmd);
319 - if (err)
320 - return err;
321 -
322 - /* retrieve response parameters */
323 - *token = mc_cmd_hdr_read_token(&cmd);
324 -
325 - return 0;
326 -}
327 -
328 -/**
329 - * dpbp_destroy() - Destroy the DPBP object and release all its resources.
330 - * @mc_io: Pointer to MC portal's I/O object
331 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
332 - * @token: Token of DPBP object
333 - *
334 - * Return: '0' on Success; error code otherwise.
335 - */
336 -int dpbp_destroy(struct fsl_mc_io *mc_io,
337 - u32 cmd_flags,
338 - u16 token)
339 -{
340 - struct mc_command cmd = { 0 };
341 -
342 - /* prepare command */
343 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY,
344 - cmd_flags, token);
345 -
346 - /* send command to mc*/
347 - return mc_send_command(mc_io, &cmd);
348 -}
349 -
350 -/**
351 * dpbp_enable() - Enable the DPBP.
352 * @mc_io: Pointer to MC portal's I/O object
353 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
354 @@ -250,6 +183,7 @@ int dpbp_is_enabled(struct fsl_mc_io *mc
355
356 return 0;
357 }
358 +EXPORT_SYMBOL(dpbp_is_enabled);
359
360 /**
361 * dpbp_reset() - Reset the DPBP, returns the object to initial state.
362 @@ -272,310 +206,7 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
363 /* send command to mc*/
364 return mc_send_command(mc_io, &cmd);
365 }
366 -
367 -/**
368 - * dpbp_set_irq() - Set IRQ information for the DPBP to trigger an interrupt.
369 - * @mc_io: Pointer to MC portal's I/O object
370 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
371 - * @token: Token of DPBP object
372 - * @irq_index: Identifies the interrupt index to configure
373 - * @irq_cfg: IRQ configuration
374 - *
375 - * Return: '0' on Success; Error code otherwise.
376 - */
377 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
378 - u32 cmd_flags,
379 - u16 token,
380 - u8 irq_index,
381 - struct dpbp_irq_cfg *irq_cfg)
382 -{
383 - struct mc_command cmd = { 0 };
384 - struct dpbp_cmd_set_irq *cmd_params;
385 -
386 - /* prepare command */
387 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ,
388 - cmd_flags, token);
389 - cmd_params = (struct dpbp_cmd_set_irq *)cmd.params;
390 - cmd_params->irq_index = irq_index;
391 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
392 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->addr);
393 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
394 -
395 - /* send command to mc*/
396 - return mc_send_command(mc_io, &cmd);
397 -}
398 -
399 -/**
400 - * dpbp_get_irq() - Get IRQ information from the DPBP.
401 - * @mc_io: Pointer to MC portal's I/O object
402 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
403 - * @token: Token of DPBP object
404 - * @irq_index: The interrupt index to configure
405 - * @type: Interrupt type: 0 represents message interrupt
406 - * type (both irq_addr and irq_val are valid)
407 - * @irq_cfg: IRQ attributes
408 - *
409 - * Return: '0' on Success; Error code otherwise.
410 - */
411 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
412 - u32 cmd_flags,
413 - u16 token,
414 - u8 irq_index,
415 - int *type,
416 - struct dpbp_irq_cfg *irq_cfg)
417 -{
418 - struct mc_command cmd = { 0 };
419 - struct dpbp_cmd_get_irq *cmd_params;
420 - struct dpbp_rsp_get_irq *rsp_params;
421 - int err;
422 -
423 - /* prepare command */
424 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ,
425 - cmd_flags, token);
426 - cmd_params = (struct dpbp_cmd_get_irq *)cmd.params;
427 - cmd_params->irq_index = irq_index;
428 -
429 - /* send command to mc*/
430 - err = mc_send_command(mc_io, &cmd);
431 - if (err)
432 - return err;
433 -
434 - /* retrieve response parameters */
435 - rsp_params = (struct dpbp_rsp_get_irq *)cmd.params;
436 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
437 - irq_cfg->addr = le64_to_cpu(rsp_params->irq_addr);
438 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
439 - *type = le32_to_cpu(rsp_params->type);
440 -
441 - return 0;
442 -}
443 -
444 -/**
445 - * dpbp_set_irq_enable() - Set overall interrupt state.
446 - * @mc_io: Pointer to MC portal's I/O object
447 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
448 - * @token: Token of DPBP object
449 - * @irq_index: The interrupt index to configure
450 - * @en: Interrupt state - enable = 1, disable = 0
451 - *
452 - * Allows GPP software to control when interrupts are generated.
453 - * Each interrupt can have up to 32 causes. The enable/disable control's the
454 - * overall interrupt state. if the interrupt is disabled no causes will cause
455 - * an interrupt.
456 - *
457 - * Return: '0' on Success; Error code otherwise.
458 - */
459 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
460 - u32 cmd_flags,
461 - u16 token,
462 - u8 irq_index,
463 - u8 en)
464 -{
465 - struct mc_command cmd = { 0 };
466 - struct dpbp_cmd_set_irq_enable *cmd_params;
467 -
468 - /* prepare command */
469 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_ENABLE,
470 - cmd_flags, token);
471 - cmd_params = (struct dpbp_cmd_set_irq_enable *)cmd.params;
472 - cmd_params->enable = en & DPBP_ENABLE;
473 - cmd_params->irq_index = irq_index;
474 -
475 - /* send command to mc*/
476 - return mc_send_command(mc_io, &cmd);
477 -}
478 -
479 -/**
480 - * dpbp_get_irq_enable() - Get overall interrupt state
481 - * @mc_io: Pointer to MC portal's I/O object
482 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
483 - * @token: Token of DPBP object
484 - * @irq_index: The interrupt index to configure
485 - * @en: Returned interrupt state - enable = 1, disable = 0
486 - *
487 - * Return: '0' on Success; Error code otherwise.
488 - */
489 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
490 - u32 cmd_flags,
491 - u16 token,
492 - u8 irq_index,
493 - u8 *en)
494 -{
495 - struct mc_command cmd = { 0 };
496 - struct dpbp_cmd_get_irq_enable *cmd_params;
497 - struct dpbp_rsp_get_irq_enable *rsp_params;
498 - int err;
499 -
500 - /* prepare command */
501 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_ENABLE,
502 - cmd_flags, token);
503 - cmd_params = (struct dpbp_cmd_get_irq_enable *)cmd.params;
504 - cmd_params->irq_index = irq_index;
505 -
506 - /* send command to mc*/
507 - err = mc_send_command(mc_io, &cmd);
508 - if (err)
509 - return err;
510 -
511 - /* retrieve response parameters */
512 - rsp_params = (struct dpbp_rsp_get_irq_enable *)cmd.params;
513 - *en = rsp_params->enabled & DPBP_ENABLE;
514 - return 0;
515 -}
516 -
517 -/**
518 - * dpbp_set_irq_mask() - Set interrupt mask.
519 - * @mc_io: Pointer to MC portal's I/O object
520 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
521 - * @token: Token of DPBP object
522 - * @irq_index: The interrupt index to configure
523 - * @mask: Event mask to trigger interrupt;
524 - * each bit:
525 - * 0 = ignore event
526 - * 1 = consider event for asserting IRQ
527 - *
528 - * Every interrupt can have up to 32 causes and the interrupt model supports
529 - * masking/unmasking each cause independently
530 - *
531 - * Return: '0' on Success; Error code otherwise.
532 - */
533 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
534 - u32 cmd_flags,
535 - u16 token,
536 - u8 irq_index,
537 - u32 mask)
538 -{
539 - struct mc_command cmd = { 0 };
540 - struct dpbp_cmd_set_irq_mask *cmd_params;
541 -
542 - /* prepare command */
543 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_IRQ_MASK,
544 - cmd_flags, token);
545 - cmd_params = (struct dpbp_cmd_set_irq_mask *)cmd.params;
546 - cmd_params->mask = cpu_to_le32(mask);
547 - cmd_params->irq_index = irq_index;
548 -
549 - /* send command to mc*/
550 - return mc_send_command(mc_io, &cmd);
551 -}
552 -
553 -/**
554 - * dpbp_get_irq_mask() - Get interrupt mask.
555 - * @mc_io: Pointer to MC portal's I/O object
556 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
557 - * @token: Token of DPBP object
558 - * @irq_index: The interrupt index to configure
559 - * @mask: Returned event mask to trigger interrupt
560 - *
561 - * Every interrupt can have up to 32 causes and the interrupt model supports
562 - * masking/unmasking each cause independently
563 - *
564 - * Return: '0' on Success; Error code otherwise.
565 - */
566 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
567 - u32 cmd_flags,
568 - u16 token,
569 - u8 irq_index,
570 - u32 *mask)
571 -{
572 - struct mc_command cmd = { 0 };
573 - struct dpbp_cmd_get_irq_mask *cmd_params;
574 - struct dpbp_rsp_get_irq_mask *rsp_params;
575 - int err;
576 -
577 - /* prepare command */
578 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_MASK,
579 - cmd_flags, token);
580 - cmd_params = (struct dpbp_cmd_get_irq_mask *)cmd.params;
581 - cmd_params->irq_index = irq_index;
582 -
583 - /* send command to mc*/
584 - err = mc_send_command(mc_io, &cmd);
585 - if (err)
586 - return err;
587 -
588 - /* retrieve response parameters */
589 - rsp_params = (struct dpbp_rsp_get_irq_mask *)cmd.params;
590 - *mask = le32_to_cpu(rsp_params->mask);
591 -
592 - return 0;
593 -}
594 -
595 -/**
596 - * dpbp_get_irq_status() - Get the current status of any pending interrupts.
597 - *
598 - * @mc_io: Pointer to MC portal's I/O object
599 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
600 - * @token: Token of DPBP object
601 - * @irq_index: The interrupt index to configure
602 - * @status: Returned interrupts status - one bit per cause:
603 - * 0 = no interrupt pending
604 - * 1 = interrupt pending
605 - *
606 - * Return: '0' on Success; Error code otherwise.
607 - */
608 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
609 - u32 cmd_flags,
610 - u16 token,
611 - u8 irq_index,
612 - u32 *status)
613 -{
614 - struct mc_command cmd = { 0 };
615 - struct dpbp_cmd_get_irq_status *cmd_params;
616 - struct dpbp_rsp_get_irq_status *rsp_params;
617 - int err;
618 -
619 - /* prepare command */
620 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_IRQ_STATUS,
621 - cmd_flags, token);
622 - cmd_params = (struct dpbp_cmd_get_irq_status *)cmd.params;
623 - cmd_params->status = cpu_to_le32(*status);
624 - cmd_params->irq_index = irq_index;
625 -
626 - /* send command to mc*/
627 - err = mc_send_command(mc_io, &cmd);
628 - if (err)
629 - return err;
630 -
631 - /* retrieve response parameters */
632 - rsp_params = (struct dpbp_rsp_get_irq_status *)cmd.params;
633 - *status = le32_to_cpu(rsp_params->status);
634 -
635 - return 0;
636 -}
637 -
638 -/**
639 - * dpbp_clear_irq_status() - Clear a pending interrupt's status
640 - *
641 - * @mc_io: Pointer to MC portal's I/O object
642 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
643 - * @token: Token of DPBP object
644 - * @irq_index: The interrupt index to configure
645 - * @status: Bits to clear (W1C) - one bit per cause:
646 - * 0 = don't change
647 - * 1 = clear status bit
648 - *
649 - * Return: '0' on Success; Error code otherwise.
650 - */
651 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
652 - u32 cmd_flags,
653 - u16 token,
654 - u8 irq_index,
655 - u32 status)
656 -{
657 - struct mc_command cmd = { 0 };
658 - struct dpbp_cmd_clear_irq_status *cmd_params;
659 -
660 - /* prepare command */
661 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_CLEAR_IRQ_STATUS,
662 - cmd_flags, token);
663 - cmd_params = (struct dpbp_cmd_clear_irq_status *)cmd.params;
664 - cmd_params->status = cpu_to_le32(status);
665 - cmd_params->irq_index = irq_index;
666 -
667 - /* send command to mc*/
668 - return mc_send_command(mc_io, &cmd);
669 -}
670 +EXPORT_SYMBOL(dpbp_reset);
671
672 /**
673 * dpbp_get_attributes - Retrieve DPBP attributes.
674 @@ -609,83 +240,40 @@ int dpbp_get_attributes(struct fsl_mc_io
675 rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params;
676 attr->bpid = le16_to_cpu(rsp_params->bpid);
677 attr->id = le32_to_cpu(rsp_params->id);
678 - attr->version.major = le16_to_cpu(rsp_params->version_major);
679 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
680
681 return 0;
682 }
683 EXPORT_SYMBOL(dpbp_get_attributes);
684
685 /**
686 - * dpbp_set_notifications() - Set notifications towards software
687 - * @mc_io: Pointer to MC portal's I/O object
688 + * dpbp_get_api_version - Get Data Path Buffer Pool API version
689 + * @mc_io: Pointer to Mc portal's I/O object
690 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
691 - * @token: Token of DPBP object
692 - * @cfg: notifications configuration
693 + * @major_ver: Major version of Buffer Pool API
694 + * @minor_ver: Minor version of Buffer Pool API
695 *
696 * Return: '0' on Success; Error code otherwise.
697 */
698 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
699 - u32 cmd_flags,
700 - u16 token,
701 - struct dpbp_notification_cfg *cfg)
702 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
703 + u32 cmd_flags,
704 + u16 *major_ver,
705 + u16 *minor_ver)
706 {
707 struct mc_command cmd = { 0 };
708 - struct dpbp_cmd_set_notifications *cmd_params;
709 -
710 - /* prepare command */
711 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_SET_NOTIFICATIONS,
712 - cmd_flags, token);
713 - cmd_params = (struct dpbp_cmd_set_notifications *)cmd.params;
714 - cmd_params->depletion_entry = cpu_to_le32(cfg->depletion_entry);
715 - cmd_params->depletion_exit = cpu_to_le32(cfg->depletion_exit);
716 - cmd_params->surplus_entry = cpu_to_le32(cfg->surplus_entry);
717 - cmd_params->surplus_exit = cpu_to_le32(cfg->surplus_exit);
718 - cmd_params->options = cpu_to_le16(cfg->options);
719 - cmd_params->message_ctx = cpu_to_le64(cfg->message_ctx);
720 - cmd_params->message_iova = cpu_to_le64(cfg->message_iova);
721 -
722 - /* send command to mc*/
723 - return mc_send_command(mc_io, &cmd);
724 -}
725 -
726 -/**
727 - * dpbp_get_notifications() - Get the notifications configuration
728 - * @mc_io: Pointer to MC portal's I/O object
729 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
730 - * @token: Token of DPBP object
731 - * @cfg: notifications configuration
732 - *
733 - * Return: '0' on Success; Error code otherwise.
734 - */
735 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
736 - u32 cmd_flags,
737 - u16 token,
738 - struct dpbp_notification_cfg *cfg)
739 -{
740 - struct mc_command cmd = { 0 };
741 - struct dpbp_rsp_get_notifications *rsp_params;
742 int err;
743
744 /* prepare command */
745 - cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_NOTIFICATIONS,
746 - cmd_flags,
747 - token);
748 + cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_API_VERSION,
749 + cmd_flags, 0);
750
751 - /* send command to mc*/
752 + /* send command to mc */
753 err = mc_send_command(mc_io, &cmd);
754 if (err)
755 return err;
756
757 /* retrieve response parameters */
758 - rsp_params = (struct dpbp_rsp_get_notifications *)cmd.params;
759 - cfg->depletion_entry = le32_to_cpu(rsp_params->depletion_entry);
760 - cfg->depletion_exit = le32_to_cpu(rsp_params->depletion_exit);
761 - cfg->surplus_entry = le32_to_cpu(rsp_params->surplus_entry);
762 - cfg->surplus_exit = le32_to_cpu(rsp_params->surplus_exit);
763 - cfg->options = le16_to_cpu(rsp_params->options);
764 - cfg->message_ctx = le64_to_cpu(rsp_params->message_ctx);
765 - cfg->message_iova = le64_to_cpu(rsp_params->message_iova);
766 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
767
768 return 0;
769 }
770 +EXPORT_SYMBOL(dpbp_get_api_version);
771 --- /dev/null
772 +++ b/drivers/staging/fsl-mc/bus/dpcon-cmd.h
773 @@ -0,0 +1,85 @@
774 +/*
775 + * Copyright 2013-2016 Freescale Semiconductor Inc.
776 + *
777 + * Redistribution and use in source and binary forms, with or without
778 + * modification, are permitted provided that the following conditions are met:
779 + * * Redistributions of source code must retain the above copyright
780 + * notice, this list of conditions and the following disclaimer.
781 + * * Redistributions in binary form must reproduce the above copyright
782 + * notice, this list of conditions and the following disclaimer in the
783 + * documentation and/or other materials provided with the distribution.
784 + * * Neither the name of the above-listed copyright holders nor the
785 + * names of any contributors may be used to endorse or promote products
786 + * derived from this software without specific prior written permission.
787 + *
788 + * ALTERNATIVELY, this software may be distributed under the terms of the
789 + * GNU General Public License ("GPL") as published by the Free Software
790 + * Foundation, either version 2 of that License or (at your option) any
791 + * later version.
792 + *
793 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
794 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
795 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
796 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
797 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
798 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
799 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
800 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
801 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
802 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
803 + * POSSIBILITY OF SUCH DAMAGE.
804 + */
805 +#ifndef _FSL_DPCON_CMD_H
806 +#define _FSL_DPCON_CMD_H
807 +
808 +/* DPCON Version */
809 +#define DPCON_VER_MAJOR 3
810 +#define DPCON_VER_MINOR 2
811 +
812 +/* Command versioning */
813 +#define DPCON_CMD_BASE_VERSION 1
814 +#define DPCON_CMD_ID_OFFSET 4
815 +
816 +#define DPCON_CMD(id) (((id) << DPCON_CMD_ID_OFFSET) | DPCON_CMD_BASE_VERSION)
817 +
818 +/* Command IDs */
819 +#define DPCON_CMDID_CLOSE DPCON_CMD(0x800)
820 +#define DPCON_CMDID_OPEN DPCON_CMD(0x808)
821 +#define DPCON_CMDID_GET_API_VERSION DPCON_CMD(0xa08)
822 +
823 +#define DPCON_CMDID_ENABLE DPCON_CMD(0x002)
824 +#define DPCON_CMDID_DISABLE DPCON_CMD(0x003)
825 +#define DPCON_CMDID_GET_ATTR DPCON_CMD(0x004)
826 +#define DPCON_CMDID_RESET DPCON_CMD(0x005)
827 +#define DPCON_CMDID_IS_ENABLED DPCON_CMD(0x006)
828 +
829 +#define DPCON_CMDID_SET_NOTIFICATION DPCON_CMD(0x100)
830 +
831 +struct dpcon_cmd_open {
832 + __le32 dpcon_id;
833 +};
834 +
835 +#define DPCON_ENABLE 1
836 +
837 +struct dpcon_rsp_is_enabled {
838 + u8 enabled;
839 +};
840 +
841 +struct dpcon_rsp_get_attr {
842 + /* response word 0 */
843 + __le32 id;
844 + __le16 qbman_ch_id;
845 + u8 num_priorities;
846 + u8 pad;
847 +};
848 +
849 +struct dpcon_cmd_set_notification {
850 + /* cmd word 0 */
851 + __le32 dpio_id;
852 + u8 priority;
853 + u8 pad[3];
854 + /* cmd word 1 */
855 + __le64 user_ctx;
856 +};
857 +
858 +#endif /* _FSL_DPCON_CMD_H */
859 --- /dev/null
860 +++ b/drivers/staging/fsl-mc/bus/dpcon.c
861 @@ -0,0 +1,317 @@
862 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
863 + *
864 + * Redistribution and use in source and binary forms, with or without
865 + * modification, are permitted provided that the following conditions are met:
866 + * * Redistributions of source code must retain the above copyright
867 + * notice, this list of conditions and the following disclaimer.
868 + * * Redistributions in binary form must reproduce the above copyright
869 + * notice, this list of conditions and the following disclaimer in the
870 + * documentation and/or other materials provided with the distribution.
871 + * * Neither the name of the above-listed copyright holders nor the
872 + * names of any contributors may be used to endorse or promote products
873 + * derived from this software without specific prior written permission.
874 + *
875 + *
876 + * ALTERNATIVELY, this software may be distributed under the terms of the
877 + * GNU General Public License ("GPL") as published by the Free Software
878 + * Foundation, either version 2 of that License or (at your option) any
879 + * later version.
880 + *
881 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
882 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
883 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
884 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
885 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
886 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
887 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
888 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
889 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
890 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
891 + * POSSIBILITY OF SUCH DAMAGE.
892 + */
893 +#include "../include/mc-sys.h"
894 +#include "../include/mc-cmd.h"
895 +#include "../include/dpcon.h"
896 +
897 +#include "dpcon-cmd.h"
898 +
899 +/**
900 + * dpcon_open() - Open a control session for the specified object
901 + * @mc_io: Pointer to MC portal's I/O object
902 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
903 + * @dpcon_id: DPCON unique ID
904 + * @token: Returned token; use in subsequent API calls
905 + *
906 + * This function can be used to open a control session for an
907 + * already created object; an object may have been declared in
908 + * the DPL or by calling the dpcon_create() function.
909 + * This function returns a unique authentication token,
910 + * associated with the specific object ID and the specific MC
911 + * portal; this token must be used in all subsequent commands for
912 + * this specific object.
913 + *
914 + * Return: '0' on Success; Error code otherwise.
915 + */
916 +int dpcon_open(struct fsl_mc_io *mc_io,
917 + u32 cmd_flags,
918 + int dpcon_id,
919 + u16 *token)
920 +{
921 + struct mc_command cmd = { 0 };
922 + struct dpcon_cmd_open *dpcon_cmd;
923 + int err;
924 +
925 + /* prepare command */
926 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_OPEN,
927 + cmd_flags,
928 + 0);
929 + dpcon_cmd = (struct dpcon_cmd_open *)cmd.params;
930 + dpcon_cmd->dpcon_id = cpu_to_le32(dpcon_id);
931 +
932 + /* send command to mc*/
933 + err = mc_send_command(mc_io, &cmd);
934 + if (err)
935 + return err;
936 +
937 + /* retrieve response parameters */
938 + *token = mc_cmd_hdr_read_token(&cmd);
939 +
940 + return 0;
941 +}
942 +EXPORT_SYMBOL(dpcon_open);
943 +
944 +/**
945 + * dpcon_close() - Close the control session of the object
946 + * @mc_io: Pointer to MC portal's I/O object
947 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
948 + * @token: Token of DPCON object
949 + *
950 + * After this function is called, no further operations are
951 + * allowed on the object without opening a new control session.
952 + *
953 + * Return: '0' on Success; Error code otherwise.
954 + */
955 +int dpcon_close(struct fsl_mc_io *mc_io,
956 + u32 cmd_flags,
957 + u16 token)
958 +{
959 + struct mc_command cmd = { 0 };
960 +
961 + /* prepare command */
962 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_CLOSE,
963 + cmd_flags,
964 + token);
965 +
966 + /* send command to mc*/
967 + return mc_send_command(mc_io, &cmd);
968 +}
969 +EXPORT_SYMBOL(dpcon_close);
970 +
971 +/**
972 + * dpcon_enable() - Enable the DPCON
973 + * @mc_io: Pointer to MC portal's I/O object
974 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
975 + * @token: Token of DPCON object
976 + *
977 + * Return: '0' on Success; Error code otherwise
978 + */
979 +int dpcon_enable(struct fsl_mc_io *mc_io,
980 + u32 cmd_flags,
981 + u16 token)
982 +{
983 + struct mc_command cmd = { 0 };
984 +
985 + /* prepare command */
986 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_ENABLE,
987 + cmd_flags,
988 + token);
989 +
990 + /* send command to mc*/
991 + return mc_send_command(mc_io, &cmd);
992 +}
993 +EXPORT_SYMBOL(dpcon_enable);
994 +
995 +/**
996 + * dpcon_disable() - Disable the DPCON
997 + * @mc_io: Pointer to MC portal's I/O object
998 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
999 + * @token: Token of DPCON object
1000 + *
1001 + * Return: '0' on Success; Error code otherwise
1002 + */
1003 +int dpcon_disable(struct fsl_mc_io *mc_io,
1004 + u32 cmd_flags,
1005 + u16 token)
1006 +{
1007 + struct mc_command cmd = { 0 };
1008 +
1009 + /* prepare command */
1010 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_DISABLE,
1011 + cmd_flags,
1012 + token);
1013 +
1014 + /* send command to mc*/
1015 + return mc_send_command(mc_io, &cmd);
1016 +}
1017 +EXPORT_SYMBOL(dpcon_disable);
1018 +
1019 +/**
1020 + * dpcon_is_enabled() - Check if the DPCON is enabled.
1021 + * @mc_io: Pointer to MC portal's I/O object
1022 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1023 + * @token: Token of DPCON object
1024 + * @en: Returns '1' if object is enabled; '0' otherwise
1025 + *
1026 + * Return: '0' on Success; Error code otherwise.
1027 + */
1028 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
1029 + u32 cmd_flags,
1030 + u16 token,
1031 + int *en)
1032 +{
1033 + struct mc_command cmd = { 0 };
1034 + struct dpcon_rsp_is_enabled *dpcon_rsp;
1035 + int err;
1036 +
1037 + /* prepare command */
1038 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_IS_ENABLED,
1039 + cmd_flags,
1040 + token);
1041 +
1042 + /* send command to mc*/
1043 + err = mc_send_command(mc_io, &cmd);
1044 + if (err)
1045 + return err;
1046 +
1047 + /* retrieve response parameters */
1048 + dpcon_rsp = (struct dpcon_rsp_is_enabled *)cmd.params;
1049 + *en = dpcon_rsp->enabled & DPCON_ENABLE;
1050 +
1051 + return 0;
1052 +}
1053 +EXPORT_SYMBOL(dpcon_is_enabled);
1054 +
1055 +/**
1056 + * dpcon_reset() - Reset the DPCON, returns the object to initial state.
1057 + * @mc_io: Pointer to MC portal's I/O object
1058 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1059 + * @token: Token of DPCON object
1060 + *
1061 + * Return: '0' on Success; Error code otherwise.
1062 + */
1063 +int dpcon_reset(struct fsl_mc_io *mc_io,
1064 + u32 cmd_flags,
1065 + u16 token)
1066 +{
1067 + struct mc_command cmd = { 0 };
1068 +
1069 + /* prepare command */
1070 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_RESET,
1071 + cmd_flags, token);
1072 +
1073 + /* send command to mc*/
1074 + return mc_send_command(mc_io, &cmd);
1075 +}
1076 +EXPORT_SYMBOL(dpcon_reset);
1077 +
1078 +/**
1079 + * dpcon_get_attributes() - Retrieve DPCON attributes.
1080 + * @mc_io: Pointer to MC portal's I/O object
1081 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1082 + * @token: Token of DPCON object
1083 + * @attr: Object's attributes
1084 + *
1085 + * Return: '0' on Success; Error code otherwise.
1086 + */
1087 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
1088 + u32 cmd_flags,
1089 + u16 token,
1090 + struct dpcon_attr *attr)
1091 +{
1092 + struct mc_command cmd = { 0 };
1093 + struct dpcon_rsp_get_attr *dpcon_rsp;
1094 + int err;
1095 +
1096 + /* prepare command */
1097 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_ATTR,
1098 + cmd_flags,
1099 + token);
1100 +
1101 + /* send command to mc*/
1102 + err = mc_send_command(mc_io, &cmd);
1103 + if (err)
1104 + return err;
1105 +
1106 + /* retrieve response parameters */
1107 + dpcon_rsp = (struct dpcon_rsp_get_attr *)cmd.params;
1108 + attr->id = le32_to_cpu(dpcon_rsp->id);
1109 + attr->qbman_ch_id = le16_to_cpu(dpcon_rsp->qbman_ch_id);
1110 + attr->num_priorities = dpcon_rsp->num_priorities;
1111 +
1112 + return 0;
1113 +}
1114 +EXPORT_SYMBOL(dpcon_get_attributes);
1115 +
1116 +/**
1117 + * dpcon_set_notification() - Set DPCON notification destination
1118 + * @mc_io: Pointer to MC portal's I/O object
1119 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1120 + * @token: Token of DPCON object
1121 + * @cfg: Notification parameters
1122 + *
1123 + * Return: '0' on Success; Error code otherwise
1124 + */
1125 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
1126 + u32 cmd_flags,
1127 + u16 token,
1128 + struct dpcon_notification_cfg *cfg)
1129 +{
1130 + struct mc_command cmd = { 0 };
1131 + struct dpcon_cmd_set_notification *dpcon_cmd;
1132 +
1133 + /* prepare command */
1134 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_SET_NOTIFICATION,
1135 + cmd_flags,
1136 + token);
1137 + dpcon_cmd = (struct dpcon_cmd_set_notification *)cmd.params;
1138 + dpcon_cmd->dpio_id = cpu_to_le32(cfg->dpio_id);
1139 + dpcon_cmd->priority = cfg->priority;
1140 + dpcon_cmd->user_ctx = cpu_to_le64(cfg->user_ctx);
1141 +
1142 + /* send command to mc*/
1143 + return mc_send_command(mc_io, &cmd);
1144 +}
1145 +EXPORT_SYMBOL(dpcon_set_notification);
1146 +
1147 +/**
1148 + * dpcon_get_api_version - Get Data Path Concentrator API version
1149 + * @mc_io: Pointer to MC portal's DPCON object
1150 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
1151 + * @major_ver: Major version of DPCON API
1152 + * @minor_ver: Minor version of DPCON API
1153 + *
1154 + * Return: '0' on Success; Error code otherwise
1155 + */
1156 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
1157 + u32 cmd_flags,
1158 + u16 *major_ver,
1159 + u16 *minor_ver)
1160 +{
1161 + struct mc_command cmd = { 0 };
1162 + int err;
1163 +
1164 + /* prepare command */
1165 + cmd.header = mc_encode_cmd_header(DPCON_CMDID_GET_API_VERSION,
1166 + cmd_flags, 0);
1167 +
1168 + /* send command to mc */
1169 + err = mc_send_command(mc_io, &cmd);
1170 + if (err)
1171 + return err;
1172 +
1173 + /* retrieve response parameters */
1174 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
1175 +
1176 + return 0;
1177 +}
1178 +EXPORT_SYMBOL(dpcon_get_api_version);
1179 --- /dev/null
1180 +++ b/drivers/staging/fsl-mc/bus/dpio/Makefile
1181 @@ -0,0 +1,11 @@
1182 +#
1183 +# QorIQ DPAA2 DPIO driver
1184 +#
1185 +
1186 +subdir-ccflags-y := -Werror
1187 +
1188 +obj-$(CONFIG_FSL_MC_DPIO) += fsl-mc-dpio.o
1189 +
1190 +fsl-mc-dpio-objs := dpio.o qbman-portal.o dpio-service.o dpio-driver.o
1191 +
1192 +obj-$(CONFIG_FSL_QBMAN_DEBUG) += qbman_debug.o
1193 --- a/drivers/staging/fsl-mc/include/dpcon-cmd.h
1194 +++ /dev/null
1195 @@ -1,62 +0,0 @@
1196 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
1197 - *
1198 - * Redistribution and use in source and binary forms, with or without
1199 - * modification, are permitted provided that the following conditions are met:
1200 - * * Redistributions of source code must retain the above copyright
1201 - * notice, this list of conditions and the following disclaimer.
1202 - * * Redistributions in binary form must reproduce the above copyright
1203 - * notice, this list of conditions and the following disclaimer in the
1204 - * documentation and/or other materials provided with the distribution.
1205 - * * Neither the name of the above-listed copyright holders nor the
1206 - * names of any contributors may be used to endorse or promote products
1207 - * derived from this software without specific prior written permission.
1208 - *
1209 - *
1210 - * ALTERNATIVELY, this software may be distributed under the terms of the
1211 - * GNU General Public License ("GPL") as published by the Free Software
1212 - * Foundation, either version 2 of that License or (at your option) any
1213 - * later version.
1214 - *
1215 - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1216 - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1217 - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1218 - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1219 - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1220 - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1221 - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1222 - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1223 - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1224 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1225 - * POSSIBILITY OF SUCH DAMAGE.
1226 - */
1227 -#ifndef _FSL_DPCON_CMD_H
1228 -#define _FSL_DPCON_CMD_H
1229 -
1230 -/* DPCON Version */
1231 -#define DPCON_VER_MAJOR 2
1232 -#define DPCON_VER_MINOR 1
1233 -
1234 -/* Command IDs */
1235 -#define DPCON_CMDID_CLOSE 0x800
1236 -#define DPCON_CMDID_OPEN 0x808
1237 -#define DPCON_CMDID_CREATE 0x908
1238 -#define DPCON_CMDID_DESTROY 0x900
1239 -
1240 -#define DPCON_CMDID_ENABLE 0x002
1241 -#define DPCON_CMDID_DISABLE 0x003
1242 -#define DPCON_CMDID_GET_ATTR 0x004
1243 -#define DPCON_CMDID_RESET 0x005
1244 -#define DPCON_CMDID_IS_ENABLED 0x006
1245 -
1246 -#define DPCON_CMDID_SET_IRQ 0x010
1247 -#define DPCON_CMDID_GET_IRQ 0x011
1248 -#define DPCON_CMDID_SET_IRQ_ENABLE 0x012
1249 -#define DPCON_CMDID_GET_IRQ_ENABLE 0x013
1250 -#define DPCON_CMDID_SET_IRQ_MASK 0x014
1251 -#define DPCON_CMDID_GET_IRQ_MASK 0x015
1252 -#define DPCON_CMDID_GET_IRQ_STATUS 0x016
1253 -#define DPCON_CMDID_CLEAR_IRQ_STATUS 0x017
1254 -
1255 -#define DPCON_CMDID_SET_NOTIFICATION 0x100
1256 -
1257 -#endif /* _FSL_DPCON_CMD_H */
1258 --- /dev/null
1259 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-cmd.h
1260 @@ -0,0 +1,75 @@
1261 +/*
1262 + * Copyright 2013-2016 Freescale Semiconductor Inc.
1263 + * Copyright 2016 NXP
1264 + *
1265 + * Redistribution and use in source and binary forms, with or without
1266 + * modification, are permitted provided that the following conditions are met:
1267 + * * Redistributions of source code must retain the above copyright
1268 + * notice, this list of conditions and the following disclaimer.
1269 + * * Redistributions in binary form must reproduce the above copyright
1270 + * notice, this list of conditions and the following disclaimer in the
1271 + * documentation and/or other materials provided with the distribution.
1272 + * * Neither the name of the above-listed copyright holders nor the
1273 + * names of any contributors may be used to endorse or promote products
1274 + * derived from this software without specific prior written permission.
1275 + *
1276 + * ALTERNATIVELY, this software may be distributed under the terms of the
1277 + * GNU General Public License ("GPL") as published by the Free Software
1278 + * Foundation, either version 2 of that License or (at your option) any
1279 + * later version.
1280 + *
1281 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
1282 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
1283 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
1284 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
1285 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
1286 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
1287 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
1288 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
1289 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
1290 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
1291 + * POSSIBILITY OF SUCH DAMAGE.
1292 + */
1293 +#ifndef _FSL_DPIO_CMD_H
1294 +#define _FSL_DPIO_CMD_H
1295 +
1296 +/* DPIO Version */
1297 +#define DPIO_VER_MAJOR 4
1298 +#define DPIO_VER_MINOR 2
1299 +
1300 +/* Command Versioning */
1301 +
1302 +#define DPIO_CMD_ID_OFFSET 4
1303 +#define DPIO_CMD_BASE_VERSION 1
1304 +
1305 +#define DPIO_CMD(id) (((id) << DPIO_CMD_ID_OFFSET) | DPIO_CMD_BASE_VERSION)
1306 +
1307 +/* Command IDs */
1308 +#define DPIO_CMDID_CLOSE DPIO_CMD(0x800)
1309 +#define DPIO_CMDID_OPEN DPIO_CMD(0x803)
1310 +#define DPIO_CMDID_GET_API_VERSION DPIO_CMD(0xa03)
1311 +#define DPIO_CMDID_ENABLE DPIO_CMD(0x002)
1312 +#define DPIO_CMDID_DISABLE DPIO_CMD(0x003)
1313 +#define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004)
1314 +
1315 +struct dpio_cmd_open {
1316 + __le32 dpio_id;
1317 +};
1318 +
1319 +#define DPIO_CHANNEL_MODE_MASK 0x3
1320 +
1321 +struct dpio_rsp_get_attr {
1322 + /* cmd word 0 */
1323 + __le32 id;
1324 + __le16 qbman_portal_id;
1325 + u8 num_priorities;
1326 + u8 channel_mode;
1327 + /* cmd word 1 */
1328 + __le64 qbman_portal_ce_addr;
1329 + /* cmd word 2 */
1330 + __le64 qbman_portal_ci_addr;
1331 + /* cmd word 3 */
1332 + __le32 qbman_version;
1333 +};
1334 +
1335 +#endif /* _FSL_DPIO_CMD_H */
1336 --- /dev/null
1337 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.c
1338 @@ -0,0 +1,296 @@
1339 +/*
1340 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1341 + * Copyright 2016 NXP
1342 + *
1343 + * Redistribution and use in source and binary forms, with or without
1344 + * modification, are permitted provided that the following conditions are met:
1345 + * * Redistributions of source code must retain the above copyright
1346 + * notice, this list of conditions and the following disclaimer.
1347 + * * Redistributions in binary form must reproduce the above copyright
1348 + * notice, this list of conditions and the following disclaimer in the
1349 + * documentation and/or other materials provided with the distribution.
1350 + * * Neither the name of Freescale Semiconductor nor the
1351 + * names of its contributors may be used to endorse or promote products
1352 + * derived from this software without specific prior written permission.
1353 + *
1354 + * ALTERNATIVELY, this software may be distributed under the terms of the
1355 + * GNU General Public License ("GPL") as published by the Free Software
1356 + * Foundation, either version 2 of that License or (at your option) any
1357 + * later version.
1358 + *
1359 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1360 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1361 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1362 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1363 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1364 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1365 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1366 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1367 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1368 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1369 + */
1370 +
1371 +#include <linux/types.h>
1372 +#include <linux/init.h>
1373 +#include <linux/module.h>
1374 +#include <linux/platform_device.h>
1375 +#include <linux/interrupt.h>
1376 +#include <linux/msi.h>
1377 +#include <linux/dma-mapping.h>
1378 +#include <linux/delay.h>
1379 +
1380 +#include "../../include/mc.h"
1381 +#include "../../include/dpaa2-io.h"
1382 +
1383 +#include "qbman-portal.h"
1384 +#include "dpio.h"
1385 +#include "dpio-cmd.h"
1386 +
1387 +MODULE_LICENSE("Dual BSD/GPL");
1388 +MODULE_AUTHOR("Freescale Semiconductor, Inc");
1389 +MODULE_DESCRIPTION("DPIO Driver");
1390 +
1391 +struct dpio_priv {
1392 + struct dpaa2_io *io;
1393 +};
1394 +
1395 +static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
1396 +{
1397 + struct device *dev = (struct device *)arg;
1398 + struct dpio_priv *priv = dev_get_drvdata(dev);
1399 +
1400 + return dpaa2_io_irq(priv->io);
1401 +}
1402 +
1403 +static void unregister_dpio_irq_handlers(struct fsl_mc_device *dpio_dev)
1404 +{
1405 + struct fsl_mc_device_irq *irq;
1406 +
1407 + irq = dpio_dev->irqs[0];
1408 +
1409 + /* clear the affinity hint */
1410 + irq_set_affinity_hint(irq->msi_desc->irq, NULL);
1411 +}
1412 +
1413 +static int register_dpio_irq_handlers(struct fsl_mc_device *dpio_dev, int cpu)
1414 +{
1415 + struct dpio_priv *priv;
1416 + int error;
1417 + struct fsl_mc_device_irq *irq;
1418 + cpumask_t mask;
1419 +
1420 + priv = dev_get_drvdata(&dpio_dev->dev);
1421 +
1422 + irq = dpio_dev->irqs[0];
1423 + error = devm_request_irq(&dpio_dev->dev,
1424 + irq->msi_desc->irq,
1425 + dpio_irq_handler,
1426 + 0,
1427 + dev_name(&dpio_dev->dev),
1428 + &dpio_dev->dev);
1429 + if (error < 0) {
1430 + dev_err(&dpio_dev->dev,
1431 + "devm_request_irq() failed: %d\n",
1432 + error);
1433 + return error;
1434 + }
1435 +
1436 + /* set the affinity hint */
1437 + cpumask_clear(&mask);
1438 + cpumask_set_cpu(cpu, &mask);
1439 + if (irq_set_affinity_hint(irq->msi_desc->irq, &mask))
1440 + dev_err(&dpio_dev->dev,
1441 + "irq_set_affinity failed irq %d cpu %d\n",
1442 + irq->msi_desc->irq, cpu);
1443 +
1444 + return 0;
1445 +}
1446 +
1447 +static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
1448 +{
1449 + struct dpio_attr dpio_attrs;
1450 + struct dpaa2_io_desc desc;
1451 + struct dpio_priv *priv;
1452 + int err = -ENOMEM;
1453 + struct device *dev = &dpio_dev->dev;
1454 + static int next_cpu = -1;
1455 +
1456 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1457 + if (!priv)
1458 + goto err_priv_alloc;
1459 +
1460 + dev_set_drvdata(dev, priv);
1461 +
1462 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1463 + if (err) {
1464 + dev_dbg(dev, "MC portal allocation failed\n");
1465 + err = -EPROBE_DEFER;
1466 + goto err_mcportal;
1467 + }
1468 +
1469 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1470 + &dpio_dev->mc_handle);
1471 + if (err) {
1472 + dev_err(dev, "dpio_open() failed\n");
1473 + goto err_open;
1474 + }
1475 +
1476 + err = dpio_get_attributes(dpio_dev->mc_io, 0, dpio_dev->mc_handle,
1477 + &dpio_attrs);
1478 + if (err) {
1479 + dev_err(dev, "dpio_get_attributes() failed %d\n", err);
1480 + goto err_get_attr;
1481 + }
1482 + desc.qman_version = dpio_attrs.qbman_version;
1483 +
1484 + err = dpio_enable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1485 + if (err) {
1486 + dev_err(dev, "dpio_enable() failed %d\n", err);
1487 + goto err_get_attr;
1488 + }
1489 +
1490 + /* initialize DPIO descriptor */
1491 + desc.receives_notifications = dpio_attrs.num_priorities ? 1 : 0;
1492 + desc.has_8prio = dpio_attrs.num_priorities == 8 ? 1 : 0;
1493 + desc.dpio_id = dpio_dev->obj_desc.id;
1494 +
1495 + /* get the cpu to use for the affinity hint */
1496 + if (next_cpu == -1)
1497 + next_cpu = cpumask_first(cpu_online_mask);
1498 + else
1499 + next_cpu = cpumask_next(next_cpu, cpu_online_mask);
1500 +
1501 + if (!cpu_possible(next_cpu)) {
1502 + dev_err(dev, "probe failed. Number of DPIOs exceeds NR_CPUS.\n");
1503 + err = -ERANGE;
1504 + goto err_allocate_irqs;
1505 + }
1506 + desc.cpu = next_cpu;
1507 +
1508 + /*
1509 + * Set the CENA regs to be the cache enabled area of the portal to
1510 + * achieve the best performance.
1511 + */
1512 + desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start,
1513 + resource_size(&dpio_dev->regions[0]));
1514 + desc.regs_cinh = ioremap(dpio_dev->regions[1].start,
1515 + resource_size(&dpio_dev->regions[1]));
1516 +
1517 + err = fsl_mc_allocate_irqs(dpio_dev);
1518 + if (err) {
1519 + dev_err(dev, "fsl_mc_allocate_irqs failed. err=%d\n", err);
1520 + goto err_allocate_irqs;
1521 + }
1522 +
1523 + err = register_dpio_irq_handlers(dpio_dev, desc.cpu);
1524 + if (err)
1525 + goto err_register_dpio_irq;
1526 +
1527 + priv->io = dpaa2_io_create(&desc);
1528 + if (!priv->io) {
1529 + dev_err(dev, "dpaa2_io_create failed\n");
1530 + goto err_dpaa2_io_create;
1531 + }
1532 +
1533 + dev_info(dev, "probed\n");
1534 + dev_dbg(dev, " receives_notifications = %d\n",
1535 + desc.receives_notifications);
1536 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1537 + fsl_mc_portal_free(dpio_dev->mc_io);
1538 +
1539 + return 0;
1540 +
1541 +err_dpaa2_io_create:
1542 + unregister_dpio_irq_handlers(dpio_dev);
1543 +err_register_dpio_irq:
1544 + fsl_mc_free_irqs(dpio_dev);
1545 +err_allocate_irqs:
1546 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1547 +err_get_attr:
1548 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1549 +err_open:
1550 + fsl_mc_portal_free(dpio_dev->mc_io);
1551 +err_mcportal:
1552 + dev_set_drvdata(dev, NULL);
1553 +err_priv_alloc:
1554 + return err;
1555 +}
1556 +
1557 +/* Tear down interrupts for a given DPIO object */
1558 +static void dpio_teardown_irqs(struct fsl_mc_device *dpio_dev)
1559 +{
1560 + unregister_dpio_irq_handlers(dpio_dev);
1561 + fsl_mc_free_irqs(dpio_dev);
1562 +}
1563 +
1564 +static int dpaa2_dpio_remove(struct fsl_mc_device *dpio_dev)
1565 +{
1566 + struct device *dev;
1567 + struct dpio_priv *priv;
1568 + int err;
1569 +
1570 + dev = &dpio_dev->dev;
1571 + priv = dev_get_drvdata(dev);
1572 +
1573 + dpaa2_io_down(priv->io);
1574 +
1575 + dpio_teardown_irqs(dpio_dev);
1576 +
1577 + err = fsl_mc_portal_allocate(dpio_dev, 0, &dpio_dev->mc_io);
1578 + if (err) {
1579 + dev_err(dev, "MC portal allocation failed\n");
1580 + goto err_mcportal;
1581 + }
1582 +
1583 + err = dpio_open(dpio_dev->mc_io, 0, dpio_dev->obj_desc.id,
1584 + &dpio_dev->mc_handle);
1585 + if (err) {
1586 + dev_err(dev, "dpio_open() failed\n");
1587 + goto err_open;
1588 + }
1589 +
1590 + dpio_disable(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1591 +
1592 + dpio_close(dpio_dev->mc_io, 0, dpio_dev->mc_handle);
1593 +
1594 + fsl_mc_portal_free(dpio_dev->mc_io);
1595 +
1596 + dev_set_drvdata(dev, NULL);
1597 +
1598 + return 0;
1599 +
1600 +err_open:
1601 + fsl_mc_portal_free(dpio_dev->mc_io);
1602 +err_mcportal:
1603 + return err;
1604 +}
1605 +
1606 +static const struct fsl_mc_device_id dpaa2_dpio_match_id_table[] = {
1607 + {
1608 + .vendor = FSL_MC_VENDOR_FREESCALE,
1609 + .obj_type = "dpio",
1610 + },
1611 + { .vendor = 0x0 }
1612 +};
1613 +
1614 +static struct fsl_mc_driver dpaa2_dpio_driver = {
1615 + .driver = {
1616 + .name = KBUILD_MODNAME,
1617 + .owner = THIS_MODULE,
1618 + },
1619 + .probe = dpaa2_dpio_probe,
1620 + .remove = dpaa2_dpio_remove,
1621 + .match_id_table = dpaa2_dpio_match_id_table
1622 +};
1623 +
1624 +static int dpio_driver_init(void)
1625 +{
1626 + return fsl_mc_driver_register(&dpaa2_dpio_driver);
1627 +}
1628 +
1629 +static void dpio_driver_exit(void)
1630 +{
1631 + fsl_mc_driver_unregister(&dpaa2_dpio_driver);
1632 +}
1633 +module_init(dpio_driver_init);
1634 +module_exit(dpio_driver_exit);
1635 --- /dev/null
1636 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-driver.txt
1637 @@ -0,0 +1,135 @@
1638 +Copyright 2016 NXP
1639 +
1640 +Introduction
1641 +------------
1642 +
1643 +A DPAA2 DPIO (Data Path I/O) is a hardware object that provides
1644 +interfaces to enqueue and dequeue frames to/from network interfaces
1645 +and other accelerators. A DPIO also provides hardware buffer
1646 +pool management for network interfaces.
1647 +
1648 +This document provides an overview the Linux DPIO driver, its
1649 +subcomponents, and its APIs.
1650 +
1651 +See Documentation/dpaa2/overview.txt for a general overview of DPAA2
1652 +and the general DPAA2 driver architecture in Linux.
1653 +
1654 +Driver Overview
1655 +---------------
1656 +
1657 +The DPIO driver is bound to DPIO objects discovered on the fsl-mc bus and
1658 +provides services that:
1659 + A) allow other drivers, such as the Ethernet driver, to enqueue and dequeue
1660 + frames for their respective objects
1661 + B) allow drivers to register callbacks for data availability notifications
1662 + when data becomes available on a queue or channel
1663 + C) allow drivers to manage hardware buffer pools
1664 +
1665 +The Linux DPIO driver consists of 3 primary components--
1666 + DPIO object driver-- fsl-mc driver that manages the DPIO object
1667 + DPIO service-- provides APIs to other Linux drivers for services
1668 + QBman portal interface-- sends portal commands, gets responses
1669 +
1670 + fsl-mc other
1671 + bus drivers
1672 + | |
1673 + +---+----+ +------+-----+
1674 + |DPIO obj| |DPIO service|
1675 + | driver |---| (DPIO) |
1676 + +--------+ +------+-----+
1677 + |
1678 + +------+-----+
1679 + | QBman |
1680 + | portal i/f |
1681 + +------------+
1682 + |
1683 + hardware
1684 +
1685 +The diagram below shows how the DPIO driver components fit with the other
1686 +DPAA2 Linux driver components:
1687 + +------------+
1688 + | OS Network |
1689 + | Stack |
1690 + +------------+ +------------+
1691 + | Allocator |. . . . . . . | Ethernet |
1692 + |(DPMCP,DPBP)| | (DPNI) |
1693 + +-.----------+ +---+---+----+
1694 + . . ^ |
1695 + . . <data avail, | |<enqueue,
1696 + . . tx confirm> | | dequeue>
1697 + +-------------+ . | |
1698 + | DPRC driver | . +--------+ +------------+
1699 + | (DPRC) | . . |DPIO obj| |DPIO service|
1700 + +----------+--+ | driver |-| (DPIO) |
1701 + | +--------+ +------+-----+
1702 + |<dev add/remove> +------|-----+
1703 + | | QBman |
1704 + +----+--------------+ | portal i/f |
1705 + | MC-bus driver | +------------+
1706 + | | |
1707 + | /soc/fsl-mc | |
1708 + +-------------------+ |
1709 + |
1710 + =========================================|=========|========================
1711 + +-+--DPIO---|-----------+
1712 + | | |
1713 + | QBman Portal |
1714 + +-----------------------+
1715 +
1716 + ============================================================================
1717 +
1718 +
1719 +DPIO Object Driver (dpio-driver.c)
1720 +----------------------------------
1721 +
1722 + The dpio-driver component registers with the fsl-mc bus to handle objects of
1723 + type "dpio". The implementation of probe() handles basic initialization
1724 + of the DPIO including mapping of the DPIO regions (the QBman SW portal)
1725 + and initializing interrupts and registering irq handlers. The dpio-driver
1726 + registers the probed DPIO with dpio-service.
1727 +
1728 +DPIO service (dpio-service.c, dpaa2-io.h)
1729 +------------------------------------------
1730 +
1731 + The dpio service component provides queuing, notification, and buffers
1732 + management services to DPAA2 drivers, such as the Ethernet driver. A system
1733 + will typically allocate 1 DPIO object per CPU to allow queuing operations
1734 + to happen simultaneously across all CPUs.
1735 +
1736 + Notification handling
1737 + dpaa2_io_service_register()
1738 + dpaa2_io_service_deregister()
1739 + dpaa2_io_service_rearm()
1740 +
1741 + Queuing
1742 + dpaa2_io_service_pull_fq()
1743 + dpaa2_io_service_pull_channel()
1744 + dpaa2_io_service_enqueue_fq()
1745 + dpaa2_io_service_enqueue_qd()
1746 + dpaa2_io_store_create()
1747 + dpaa2_io_store_destroy()
1748 + dpaa2_io_store_next()
1749 +
1750 + Buffer pool management
1751 + dpaa2_io_service_release()
1752 + dpaa2_io_service_acquire()
1753 +
1754 +QBman portal interface (qbman-portal.c)
1755 +---------------------------------------
1756 +
1757 + The qbman-portal component provides APIs to do the low level hardware
1758 + bit twiddling for operations such as:
1759 + -initializing Qman software portals
1760 + -building and sending portal commands
1761 + -portal interrupt configuration and processing
1762 +
1763 + The qbman-portal APIs are not public to other drivers, and are
1764 + only used by dpio-service.
1765 +
1766 +Other (dpaa2-fd.h, dpaa2-global.h)
1767 +----------------------------------
1768 +
1769 + Frame descriptor and scatter-gather definitions and the APIs used to
1770 + manipulate them are defined in dpaa2-fd.h.
1771 +
1772 + Dequeue result struct and parsing APIs are defined in dpaa2-global.h.
1773 --- /dev/null
1774 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio-service.c
1775 @@ -0,0 +1,693 @@
1776 +/*
1777 + * Copyright 2014-2016 Freescale Semiconductor Inc.
1778 + * Copyright 2016 NXP
1779 + *
1780 + * Redistribution and use in source and binary forms, with or without
1781 + * modification, are permitted provided that the following conditions are met:
1782 + * * Redistributions of source code must retain the above copyright
1783 + * notice, this list of conditions and the following disclaimer.
1784 + * * Redistributions in binary form must reproduce the above copyright
1785 + * notice, this list of conditions and the following disclaimer in the
1786 + * documentation and/or other materials provided with the distribution.
1787 + * * Neither the name of Freescale Semiconductor nor the
1788 + * names of its contributors may be used to endorse or promote products
1789 + * derived from this software without specific prior written permission.
1790 + *
1791 + * ALTERNATIVELY, this software may be distributed under the terms of the
1792 + * GNU General Public License ("GPL") as published by the Free Software
1793 + * Foundation, either version 2 of that License or (at your option) any
1794 + * later version.
1795 + *
1796 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
1797 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
1798 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
1799 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
1800 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
1801 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
1802 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
1803 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1804 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1805 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1806 + */
1807 +#include <linux/types.h>
1808 +#include "../../include/mc.h"
1809 +#include "../../include/dpaa2-io.h"
1810 +#include <linux/init.h>
1811 +#include <linux/module.h>
1812 +#include <linux/platform_device.h>
1813 +#include <linux/interrupt.h>
1814 +#include <linux/dma-mapping.h>
1815 +#include <linux/slab.h>
1816 +
1817 +#include "dpio.h"
1818 +#include "qbman-portal.h"
1819 +#include "qbman_debug.h"
1820 +
1821 +struct dpaa2_io {
1822 + atomic_t refs;
1823 + struct dpaa2_io_desc dpio_desc;
1824 + struct qbman_swp_desc swp_desc;
1825 + struct qbman_swp *swp;
1826 + struct list_head node;
1827 + /* protect against multiple management commands */
1828 + spinlock_t lock_mgmt_cmd;
1829 + /* protect notifications list */
1830 + spinlock_t lock_notifications;
1831 + struct list_head notifications;
1832 +};
1833 +
1834 +struct dpaa2_io_store {
1835 + unsigned int max;
1836 + dma_addr_t paddr;
1837 + struct dpaa2_dq *vaddr;
1838 + void *alloced_addr; /* unaligned value from kmalloc() */
1839 + unsigned int idx; /* position of the next-to-be-returned entry */
1840 + struct qbman_swp *swp; /* portal used to issue VDQCR */
1841 + struct device *dev; /* device used for DMA mapping */
1842 +};
1843 +
1844 +/* keep a per cpu array of DPIOs for fast access */
1845 +static struct dpaa2_io *dpio_by_cpu[NR_CPUS];
1846 +static struct list_head dpio_list = LIST_HEAD_INIT(dpio_list);
1847 +static DEFINE_SPINLOCK(dpio_list_lock);
1848 +
1849 +static inline struct dpaa2_io *service_select_by_cpu(struct dpaa2_io *d,
1850 + int cpu)
1851 +{
1852 + if (d)
1853 + return d;
1854 +
1855 + if (unlikely(cpu >= (int)num_possible_cpus()))
1856 + return NULL;
1857 +
1858 + /*
1859 + * If cpu == -1, choose the current cpu, with no guarantees about
1860 + * potentially being migrated away.
1861 + */
1862 + if (cpu < 0)
1863 + cpu = smp_processor_id();
1864 +
1865 + /* If a specific cpu was requested, pick it up immediately */
1866 + return dpio_by_cpu[cpu];
1867 +}
1868 +
1869 +static inline struct dpaa2_io *service_select(struct dpaa2_io *d)
1870 +{
1871 + if (d)
1872 + return d;
1873 +
1874 + d = service_select_by_cpu(d, -1);
1875 + if (d)
1876 + return d;
1877 +
1878 + spin_lock(&dpio_list_lock);
1879 + d = list_entry(dpio_list.next, struct dpaa2_io, node);
1880 + list_del(&d->node);
1881 + list_add_tail(&d->node, &dpio_list);
1882 + spin_unlock(&dpio_list_lock);
1883 +
1884 + return d;
1885 +}
1886 +
1887 +/**
1888 + * dpaa2_io_create() - create a dpaa2_io object.
1889 + * @desc: the dpaa2_io descriptor
1890 + *
1891 + * Activates a "struct dpaa2_io" corresponding to the given config of an actual
1892 + * DPIO object.
1893 + *
1894 + * Return a valid dpaa2_io object for success, or NULL for failure.
1895 + */
1896 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc)
1897 +{
1898 + struct dpaa2_io *obj = kmalloc(sizeof(*obj), GFP_KERNEL);
1899 +
1900 + if (!obj)
1901 + return NULL;
1902 +
1903 + /* check if CPU is out of range (-1 means any cpu) */
1904 + if (desc->cpu >= (int)num_possible_cpus()) {
1905 + kfree(obj);
1906 + return NULL;
1907 + }
1908 +
1909 + atomic_set(&obj->refs, 1);
1910 + obj->dpio_desc = *desc;
1911 + obj->swp_desc.cena_bar = obj->dpio_desc.regs_cena;
1912 + obj->swp_desc.cinh_bar = obj->dpio_desc.regs_cinh;
1913 + obj->swp_desc.qman_version = obj->dpio_desc.qman_version;
1914 + obj->swp = qbman_swp_init(&obj->swp_desc);
1915 +
1916 + if (!obj->swp) {
1917 + kfree(obj);
1918 + return NULL;
1919 + }
1920 +
1921 + INIT_LIST_HEAD(&obj->node);
1922 + spin_lock_init(&obj->lock_mgmt_cmd);
1923 + spin_lock_init(&obj->lock_notifications);
1924 + INIT_LIST_HEAD(&obj->notifications);
1925 +
1926 + /* For now only enable DQRR interrupts */
1927 + qbman_swp_interrupt_set_trigger(obj->swp,
1928 + QBMAN_SWP_INTERRUPT_DQRI);
1929 + qbman_swp_interrupt_clear_status(obj->swp, 0xffffffff);
1930 + if (obj->dpio_desc.receives_notifications)
1931 + qbman_swp_push_set(obj->swp, 0, 1);
1932 +
1933 + spin_lock(&dpio_list_lock);
1934 + list_add_tail(&obj->node, &dpio_list);
1935 + if (desc->cpu >= 0 && !dpio_by_cpu[desc->cpu])
1936 + dpio_by_cpu[desc->cpu] = obj;
1937 + spin_unlock(&dpio_list_lock);
1938 +
1939 + return obj;
1940 +}
1941 +EXPORT_SYMBOL(dpaa2_io_create);
1942 +
1943 +/**
1944 + * dpaa2_io_down() - release the dpaa2_io object.
1945 + * @d: the dpaa2_io object to be released.
1946 + *
1947 + * The "struct dpaa2_io" type can represent an individual DPIO object (as
1948 + * described by "struct dpaa2_io_desc") or an instance of a "DPIO service",
1949 + * which can be used to group/encapsulate multiple DPIO objects. In all cases,
1950 + * each handle obtained should be released using this function.
1951 + */
1952 +void dpaa2_io_down(struct dpaa2_io *d)
1953 +{
1954 + if (!atomic_dec_and_test(&d->refs))
1955 + return;
1956 + kfree(d);
1957 +}
1958 +EXPORT_SYMBOL(dpaa2_io_down);
1959 +
1960 +#define DPAA_POLL_MAX 32
1961 +
1962 +/**
1963 + * dpaa2_io_irq() - ISR for DPIO interrupts
1964 + *
1965 + * @obj: the given DPIO object.
1966 + *
1967 + * Return IRQ_HANDLED for success or IRQ_NONE if there
1968 + * were no pending interrupts.
1969 + */
1970 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj)
1971 +{
1972 + const struct dpaa2_dq *dq;
1973 + int max = 0;
1974 + struct qbman_swp *swp;
1975 + u32 status;
1976 +
1977 + swp = obj->swp;
1978 + status = qbman_swp_interrupt_read_status(swp);
1979 + if (!status)
1980 + return IRQ_NONE;
1981 +
1982 + dq = qbman_swp_dqrr_next(swp);
1983 + while (dq) {
1984 + if (qbman_result_is_SCN(dq)) {
1985 + struct dpaa2_io_notification_ctx *ctx;
1986 + u64 q64;
1987 +
1988 + q64 = qbman_result_SCN_ctx(dq);
1989 + ctx = (void *)q64;
1990 + ctx->cb(ctx);
1991 + } else {
1992 + pr_crit("fsl-mc-dpio: Unrecognised/ignored DQRR entry\n");
1993 + }
1994 + qbman_swp_dqrr_consume(swp, dq);
1995 + ++max;
1996 + if (max > DPAA_POLL_MAX)
1997 + goto done;
1998 + dq = qbman_swp_dqrr_next(swp);
1999 + }
2000 +done:
2001 + qbman_swp_interrupt_clear_status(swp, status);
2002 + qbman_swp_interrupt_set_inhibit(swp, 0);
2003 + return IRQ_HANDLED;
2004 +}
2005 +EXPORT_SYMBOL(dpaa2_io_irq);
2006 +
2007 +/**
2008 + * dpaa2_io_service_register() - Prepare for servicing of FQDAN or CDAN
2009 + * notifications on the given DPIO service.
2010 + * @d: the given DPIO service.
2011 + * @ctx: the notification context.
2012 + *
2013 + * The caller should make the MC command to attach a DPAA2 object to
2014 + * a DPIO after this function completes successfully. In that way:
2015 + * (a) The DPIO service is "ready" to handle a notification arrival
2016 + * (which might happen before the "attach" command to MC has
2017 + * returned control of execution back to the caller)
2018 + * (b) The DPIO service can provide back to the caller the 'dpio_id' and
2019 + * 'qman64' parameters that it should pass along in the MC command
2020 + * in order for the object to be configured to produce the right
2021 + * notification fields to the DPIO service.
2022 + *
2023 + * Return 0 for success, or -ENODEV for failure.
2024 + */
2025 +int dpaa2_io_service_register(struct dpaa2_io *d,
2026 + struct dpaa2_io_notification_ctx *ctx)
2027 +{
2028 + unsigned long irqflags;
2029 +
2030 + d = service_select_by_cpu(d, ctx->desired_cpu);
2031 + if (!d)
2032 + return -ENODEV;
2033 +
2034 + ctx->dpio_id = d->dpio_desc.dpio_id;
2035 + ctx->qman64 = (u64)ctx;
2036 + ctx->dpio_private = d;
2037 + spin_lock_irqsave(&d->lock_notifications, irqflags);
2038 + list_add(&ctx->node, &d->notifications);
2039 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
2040 +
2041 + /* Enable the generation of CDAN notifications */
2042 + if (ctx->is_cdan)
2043 + qbman_swp_CDAN_set_context_enable(d->swp,
2044 + (u16)ctx->id,
2045 + ctx->qman64);
2046 + return 0;
2047 +}
2048 +EXPORT_SYMBOL(dpaa2_io_service_register);
2049 +
2050 +/**
2051 + * dpaa2_io_service_deregister - The opposite of 'register'.
2052 + * @service: the given DPIO service.
2053 + * @ctx: the notification context.
2054 + *
2055 + * This function should be called only after sending the MC command to
2056 + * to detach the notification-producing device from the DPIO.
2057 + */
2058 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
2059 + struct dpaa2_io_notification_ctx *ctx)
2060 +{
2061 + struct dpaa2_io *d = ctx->dpio_private;
2062 + unsigned long irqflags;
2063 +
2064 + if (ctx->is_cdan)
2065 + qbman_swp_CDAN_disable(d->swp, (u16)ctx->id);
2066 +
2067 + spin_lock_irqsave(&d->lock_notifications, irqflags);
2068 + list_del(&ctx->node);
2069 + spin_unlock_irqrestore(&d->lock_notifications, irqflags);
2070 +}
2071 +EXPORT_SYMBOL(dpaa2_io_service_deregister);
2072 +
2073 +/**
2074 + * dpaa2_io_service_rearm() - Rearm the notification for the given DPIO service.
2075 + * @d: the given DPIO service.
2076 + * @ctx: the notification context.
2077 + *
2078 + * Once a FQDAN/CDAN has been produced, the corresponding FQ/channel is
2079 + * considered "disarmed". Ie. the user can issue pull dequeue operations on that
2080 + * traffic source for as long as it likes. Eventually it may wish to "rearm"
2081 + * that source to allow it to produce another FQDAN/CDAN, that's what this
2082 + * function achieves.
2083 + *
2084 + * Return 0 for success.
2085 + */
2086 +int dpaa2_io_service_rearm(struct dpaa2_io *d,
2087 + struct dpaa2_io_notification_ctx *ctx)
2088 +{
2089 + unsigned long irqflags;
2090 + int err;
2091 +
2092 + d = service_select_by_cpu(d, ctx->desired_cpu);
2093 + if (!unlikely(d))
2094 + return -ENODEV;
2095 +
2096 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2097 + if (ctx->is_cdan)
2098 + err = qbman_swp_CDAN_enable(d->swp, (u16)ctx->id);
2099 + else
2100 + err = qbman_swp_fq_schedule(d->swp, ctx->id);
2101 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2102 +
2103 + return err;
2104 +}
2105 +EXPORT_SYMBOL(dpaa2_io_service_rearm);
2106 +
2107 +/**
2108 + * dpaa2_io_service_pull_fq() - pull dequeue functions from a fq.
2109 + * @d: the given DPIO service.
2110 + * @fqid: the given frame queue id.
2111 + * @s: the dpaa2_io_store object for the result.
2112 + *
2113 + * Return 0 for success, or error code for failure.
2114 + */
2115 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
2116 + struct dpaa2_io_store *s)
2117 +{
2118 + struct qbman_pull_desc pd;
2119 + int err;
2120 +
2121 + qbman_pull_desc_clear(&pd);
2122 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
2123 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
2124 + qbman_pull_desc_set_fq(&pd, fqid);
2125 +
2126 + d = service_select(d);
2127 + if (!d)
2128 + return -ENODEV;
2129 + s->swp = d->swp;
2130 + err = qbman_swp_pull(d->swp, &pd);
2131 + if (err)
2132 + s->swp = NULL;
2133 +
2134 + return err;
2135 +}
2136 +EXPORT_SYMBOL(dpaa2_io_service_pull_fq);
2137 +
2138 +/**
2139 + * dpaa2_io_service_pull_channel() - pull dequeue functions from a channel.
2140 + * @d: the given DPIO service.
2141 + * @channelid: the given channel id.
2142 + * @s: the dpaa2_io_store object for the result.
2143 + *
2144 + * Return 0 for success, or error code for failure.
2145 + */
2146 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
2147 + struct dpaa2_io_store *s)
2148 +{
2149 + struct qbman_pull_desc pd;
2150 + int err;
2151 +
2152 + qbman_pull_desc_clear(&pd);
2153 + qbman_pull_desc_set_storage(&pd, s->vaddr, s->paddr, 1);
2154 + qbman_pull_desc_set_numframes(&pd, (u8)s->max);
2155 + qbman_pull_desc_set_channel(&pd, channelid, qbman_pull_type_prio);
2156 +
2157 + d = service_select(d);
2158 + if (!d)
2159 + return -ENODEV;
2160 +
2161 + s->swp = d->swp;
2162 + err = qbman_swp_pull(d->swp, &pd);
2163 + if (err)
2164 + s->swp = NULL;
2165 +
2166 + return err;
2167 +}
2168 +EXPORT_SYMBOL(dpaa2_io_service_pull_channel);
2169 +
2170 +/**
2171 + * dpaa2_io_service_enqueue_fq() - Enqueue a frame to a frame queue.
2172 + * @d: the given DPIO service.
2173 + * @fqid: the given frame queue id.
2174 + * @fd: the frame descriptor which is enqueued.
2175 + *
2176 + * Return 0 for successful enqueue, -EBUSY if the enqueue ring is not ready,
2177 + * or -ENODEV if there is no dpio service.
2178 + */
2179 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d,
2180 + u32 fqid,
2181 + const struct dpaa2_fd *fd)
2182 +{
2183 + struct qbman_eq_desc ed;
2184 +
2185 + d = service_select(d);
2186 + if (!d)
2187 + return -ENODEV;
2188 +
2189 + qbman_eq_desc_clear(&ed);
2190 + qbman_eq_desc_set_no_orp(&ed, 0);
2191 + qbman_eq_desc_set_fq(&ed, fqid);
2192 +
2193 + return qbman_swp_enqueue(d->swp, &ed, fd);
2194 +}
2195 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_fq);
2196 +
2197 +/**
2198 + * dpaa2_io_service_enqueue_qd() - Enqueue a frame to a QD.
2199 + * @d: the given DPIO service.
2200 + * @qdid: the given queuing destination id.
2201 + * @prio: the given queuing priority.
2202 + * @qdbin: the given queuing destination bin.
2203 + * @fd: the frame descriptor which is enqueued.
2204 + *
2205 + * Return 0 for successful enqueue, or -EBUSY if the enqueue ring is not ready,
2206 + * or -ENODEV if there is no dpio service.
2207 + */
2208 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d,
2209 + u32 qdid, u8 prio, u16 qdbin,
2210 + const struct dpaa2_fd *fd)
2211 +{
2212 + struct qbman_eq_desc ed;
2213 +
2214 + d = service_select(d);
2215 + if (!d)
2216 + return -ENODEV;
2217 +
2218 + qbman_eq_desc_clear(&ed);
2219 + qbman_eq_desc_set_no_orp(&ed, 0);
2220 + qbman_eq_desc_set_qd(&ed, qdid, qdbin, prio);
2221 +
2222 + return qbman_swp_enqueue(d->swp, &ed, fd);
2223 +}
2224 +EXPORT_SYMBOL(dpaa2_io_service_enqueue_qd);
2225 +
2226 +/**
2227 + * dpaa2_io_service_release() - Release buffers to a buffer pool.
2228 + * @d: the given DPIO object.
2229 + * @bpid: the buffer pool id.
2230 + * @buffers: the buffers to be released.
2231 + * @num_buffers: the number of the buffers to be released.
2232 + *
2233 + * Return 0 for success, and negative error code for failure.
2234 + */
2235 +int dpaa2_io_service_release(struct dpaa2_io *d,
2236 + u32 bpid,
2237 + const u64 *buffers,
2238 + unsigned int num_buffers)
2239 +{
2240 + struct qbman_release_desc rd;
2241 +
2242 + d = service_select(d);
2243 + if (!d)
2244 + return -ENODEV;
2245 +
2246 + qbman_release_desc_clear(&rd);
2247 + qbman_release_desc_set_bpid(&rd, bpid);
2248 +
2249 + return qbman_swp_release(d->swp, &rd, buffers, num_buffers);
2250 +}
2251 +EXPORT_SYMBOL(dpaa2_io_service_release);
2252 +
2253 +/**
2254 + * dpaa2_io_service_acquire() - Acquire buffers from a buffer pool.
2255 + * @d: the given DPIO object.
2256 + * @bpid: the buffer pool id.
2257 + * @buffers: the buffer addresses for acquired buffers.
2258 + * @num_buffers: the expected number of the buffers to acquire.
2259 + *
2260 + * Return a negative error code if the command failed, otherwise it returns
2261 + * the number of buffers acquired, which may be less than the number requested.
2262 + * Eg. if the buffer pool is empty, this will return zero.
2263 + */
2264 +int dpaa2_io_service_acquire(struct dpaa2_io *d,
2265 + u32 bpid,
2266 + u64 *buffers,
2267 + unsigned int num_buffers)
2268 +{
2269 + unsigned long irqflags;
2270 + int err;
2271 +
2272 + d = service_select(d);
2273 + if (!d)
2274 + return -ENODEV;
2275 +
2276 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2277 + err = qbman_swp_acquire(d->swp, bpid, buffers, num_buffers);
2278 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2279 +
2280 + return err;
2281 +}
2282 +EXPORT_SYMBOL(dpaa2_io_service_acquire);
2283 +
2284 +/*
2285 + * 'Stores' are reusable memory blocks for holding dequeue results, and to
2286 + * assist with parsing those results.
2287 + */
2288 +
2289 +/**
2290 + * dpaa2_io_store_create() - Create the dma memory storage for dequeue result.
2291 + * @max_frames: the maximum number of dequeued result for frames, must be <= 16.
2292 + * @dev: the device to allow mapping/unmapping the DMAable region.
2293 + *
2294 + * The size of the storage is "max_frames*sizeof(struct dpaa2_dq)".
2295 + * The 'dpaa2_io_store' returned is a DPIO service managed object.
2296 + *
2297 + * Return pointer to dpaa2_io_store struct for successfuly created storage
2298 + * memory, or NULL on error.
2299 + */
2300 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
2301 + struct device *dev)
2302 +{
2303 + struct dpaa2_io_store *ret;
2304 + size_t size;
2305 +
2306 + if (!max_frames || (max_frames > 16))
2307 + return NULL;
2308 +
2309 + ret = kmalloc(sizeof(*ret), GFP_KERNEL);
2310 + if (!ret)
2311 + return NULL;
2312 +
2313 + ret->max = max_frames;
2314 + size = max_frames * sizeof(struct dpaa2_dq) + 64;
2315 + ret->alloced_addr = kzalloc(size, GFP_KERNEL);
2316 + if (!ret->alloced_addr) {
2317 + kfree(ret);
2318 + return NULL;
2319 + }
2320 +
2321 + ret->vaddr = PTR_ALIGN(ret->alloced_addr, 64);
2322 + ret->paddr = dma_map_single(dev, ret->vaddr,
2323 + sizeof(struct dpaa2_dq) * max_frames,
2324 + DMA_FROM_DEVICE);
2325 + if (dma_mapping_error(dev, ret->paddr)) {
2326 + kfree(ret->alloced_addr);
2327 + kfree(ret);
2328 + return NULL;
2329 + }
2330 +
2331 + ret->idx = 0;
2332 + ret->dev = dev;
2333 +
2334 + return ret;
2335 +}
2336 +EXPORT_SYMBOL(dpaa2_io_store_create);
2337 +
2338 +/**
2339 + * dpaa2_io_store_destroy() - Frees the dma memory storage for dequeue
2340 + * result.
2341 + * @s: the storage memory to be destroyed.
2342 + */
2343 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s)
2344 +{
2345 + dma_unmap_single(s->dev, s->paddr, sizeof(struct dpaa2_dq) * s->max,
2346 + DMA_FROM_DEVICE);
2347 + kfree(s->alloced_addr);
2348 + kfree(s);
2349 +}
2350 +EXPORT_SYMBOL(dpaa2_io_store_destroy);
2351 +
2352 +/**
2353 + * dpaa2_io_store_next() - Determine when the next dequeue result is available.
2354 + * @s: the dpaa2_io_store object.
2355 + * @is_last: indicate whether this is the last frame in the pull command.
2356 + *
2357 + * When an object driver performs dequeues to a dpaa2_io_store, this function
2358 + * can be used to determine when the next frame result is available. Once
2359 + * this function returns non-NULL, a subsequent call to it will try to find
2360 + * the next dequeue result.
2361 + *
2362 + * Note that if a pull-dequeue has a NULL result because the target FQ/channel
2363 + * was empty, then this function will also return NULL (rather than expecting
2364 + * the caller to always check for this. As such, "is_last" can be used to
2365 + * differentiate between "end-of-empty-dequeue" and "still-waiting".
2366 + *
2367 + * Return dequeue result for a valid dequeue result, or NULL for empty dequeue.
2368 + */
2369 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last)
2370 +{
2371 + int match;
2372 + struct dpaa2_dq *ret = &s->vaddr[s->idx];
2373 +
2374 + match = qbman_result_has_new_result(s->swp, ret);
2375 + if (!match) {
2376 + *is_last = 0;
2377 + return NULL;
2378 + }
2379 +
2380 + s->idx++;
2381 +
2382 + if (dpaa2_dq_is_pull_complete(ret)) {
2383 + *is_last = 1;
2384 + s->idx = 0;
2385 + /*
2386 + * If we get an empty dequeue result to terminate a zero-results
2387 + * vdqcr, return NULL to the caller rather than expecting him to
2388 + * check non-NULL results every time.
2389 + */
2390 + if (!(dpaa2_dq_flags(ret) & DPAA2_DQ_STAT_VALIDFRAME))
2391 + ret = NULL;
2392 + } else {
2393 + *is_last = 0;
2394 + }
2395 +
2396 + return ret;
2397 +}
2398 +EXPORT_SYMBOL(dpaa2_io_store_next);
2399 +
2400 +#ifdef CONFIG_FSL_QBMAN_DEBUG
2401 +/**
2402 + * dpaa2_io_query_fq_count() - Get the frame and byte count for a given fq.
2403 + * @d: the given DPIO object.
2404 + * @fqid: the id of frame queue to be queried.
2405 + * @fcnt: the queried frame count.
2406 + * @bcnt: the queried byte count.
2407 + *
2408 + * Knowing the FQ count at run-time can be useful in debugging situations.
2409 + * The instantaneous frame- and byte-count are hereby returned.
2410 + *
2411 + * Return 0 for a successful query, and negative error code if query fails.
2412 + */
2413 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
2414 + u32 *fcnt, u32 *bcnt)
2415 +{
2416 + struct qbman_attr state;
2417 + struct qbman_swp *swp;
2418 + unsigned long irqflags;
2419 + int ret;
2420 +
2421 + d = service_select(d);
2422 + if (!d)
2423 + return -ENODEV;
2424 +
2425 + swp = d->swp;
2426 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2427 + ret = qbman_fq_query_state(swp, fqid, &state);
2428 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2429 + if (ret)
2430 + return ret;
2431 + *fcnt = qbman_fq_state_frame_count(&state);
2432 + *bcnt = qbman_fq_state_byte_count(&state);
2433 +
2434 + return 0;
2435 +}
2436 +EXPORT_SYMBOL(dpaa2_io_query_fq_count);
2437 +
2438 +/**
2439 + * dpaa2_io_query_bp_count() - Query the number of buffers currenty in a
2440 + * buffer pool.
2441 + * @d: the given DPIO object.
2442 + * @bpid: the index of buffer pool to be queried.
2443 + * @num: the queried number of buffers in the buffer pool.
2444 + *
2445 + * Return 0 for a sucessful query, and negative error code if query fails.
2446 + */
2447 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid, u32 *num)
2448 +{
2449 + struct qbman_attr state;
2450 + struct qbman_swp *swp;
2451 + unsigned long irqflags;
2452 + int ret;
2453 +
2454 + d = service_select(d);
2455 + if (!d)
2456 + return -ENODEV;
2457 +
2458 + swp = d->swp;
2459 + spin_lock_irqsave(&d->lock_mgmt_cmd, irqflags);
2460 + ret = qbman_bp_query(swp, bpid, &state);
2461 + spin_unlock_irqrestore(&d->lock_mgmt_cmd, irqflags);
2462 + if (ret)
2463 + return ret;
2464 + *num = qbman_bp_info_num_free_bufs(&state);
2465 + return 0;
2466 +}
2467 +EXPORT_SYMBOL(dpaa2_io_query_bp_count);
2468 +#endif
2469 --- /dev/null
2470 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.c
2471 @@ -0,0 +1,224 @@
2472 +/*
2473 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2474 + * Copyright 2016 NXP
2475 + *
2476 + * Redistribution and use in source and binary forms, with or without
2477 + * modification, are permitted provided that the following conditions are met:
2478 + * * Redistributions of source code must retain the above copyright
2479 + * notice, this list of conditions and the following disclaimer.
2480 + * * Redistributions in binary form must reproduce the above copyright
2481 + * notice, this list of conditions and the following disclaimer in the
2482 + * documentation and/or other materials provided with the distribution.
2483 + * * Neither the name of the above-listed copyright holders nor the
2484 + * names of any contributors may be used to endorse or promote products
2485 + * derived from this software without specific prior written permission.
2486 + *
2487 + * ALTERNATIVELY, this software may be distributed under the terms of the
2488 + * GNU General Public License ("GPL") as published by the Free Software
2489 + * Foundation, either version 2 of that License or (at your option) any
2490 + * later version.
2491 + *
2492 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2493 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2494 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2495 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2496 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2497 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2498 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2499 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2500 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2501 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2502 + * POSSIBILITY OF SUCH DAMAGE.
2503 + */
2504 +#include "../../include/mc-sys.h"
2505 +#include "../../include/mc-cmd.h"
2506 +
2507 +#include "dpio.h"
2508 +#include "dpio-cmd.h"
2509 +
2510 +/*
2511 + * Data Path I/O Portal API
2512 + * Contains initialization APIs and runtime control APIs for DPIO
2513 + */
2514 +
2515 +/**
2516 + * dpio_open() - Open a control session for the specified object
2517 + * @mc_io: Pointer to MC portal's I/O object
2518 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2519 + * @dpio_id: DPIO unique ID
2520 + * @token: Returned token; use in subsequent API calls
2521 + *
2522 + * This function can be used to open a control session for an
2523 + * already created object; an object may have been declared in
2524 + * the DPL or by calling the dpio_create() function.
2525 + * This function returns a unique authentication token,
2526 + * associated with the specific object ID and the specific MC
2527 + * portal; this token must be used in all subsequent commands for
2528 + * this specific object.
2529 + *
2530 + * Return: '0' on Success; Error code otherwise.
2531 + */
2532 +int dpio_open(struct fsl_mc_io *mc_io,
2533 + u32 cmd_flags,
2534 + int dpio_id,
2535 + u16 *token)
2536 +{
2537 + struct mc_command cmd = { 0 };
2538 + struct dpio_cmd_open *dpio_cmd;
2539 + int err;
2540 +
2541 + /* prepare command */
2542 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN,
2543 + cmd_flags,
2544 + 0);
2545 + dpio_cmd = (struct dpio_cmd_open *)cmd.params;
2546 + dpio_cmd->dpio_id = cpu_to_le32(dpio_id);
2547 +
2548 + err = mc_send_command(mc_io, &cmd);
2549 + if (err)
2550 + return err;
2551 +
2552 + /* retrieve response parameters */
2553 + *token = mc_cmd_hdr_read_token(&cmd);
2554 +
2555 + return 0;
2556 +}
2557 +
2558 +/**
2559 + * dpio_close() - Close the control session of the object
2560 + * @mc_io: Pointer to MC portal's I/O object
2561 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2562 + * @token: Token of DPIO object
2563 + *
2564 + * Return: '0' on Success; Error code otherwise.
2565 + */
2566 +int dpio_close(struct fsl_mc_io *mc_io,
2567 + u32 cmd_flags,
2568 + u16 token)
2569 +{
2570 + struct mc_command cmd = { 0 };
2571 +
2572 + /* prepare command */
2573 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_CLOSE,
2574 + cmd_flags,
2575 + token);
2576 +
2577 + return mc_send_command(mc_io, &cmd);
2578 +}
2579 +
2580 +/**
2581 + * dpio_enable() - Enable the DPIO, allow I/O portal operations.
2582 + * @mc_io: Pointer to MC portal's I/O object
2583 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2584 + * @token: Token of DPIO object
2585 + *
2586 + * Return: '0' on Success; Error code otherwise
2587 + */
2588 +int dpio_enable(struct fsl_mc_io *mc_io,
2589 + u32 cmd_flags,
2590 + u16 token)
2591 +{
2592 + struct mc_command cmd = { 0 };
2593 +
2594 + /* prepare command */
2595 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_ENABLE,
2596 + cmd_flags,
2597 + token);
2598 +
2599 + return mc_send_command(mc_io, &cmd);
2600 +}
2601 +
2602 +/**
2603 + * dpio_disable() - Disable the DPIO, stop any I/O portal operation.
2604 + * @mc_io: Pointer to MC portal's I/O object
2605 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2606 + * @token: Token of DPIO object
2607 + *
2608 + * Return: '0' on Success; Error code otherwise
2609 + */
2610 +int dpio_disable(struct fsl_mc_io *mc_io,
2611 + u32 cmd_flags,
2612 + u16 token)
2613 +{
2614 + struct mc_command cmd = { 0 };
2615 +
2616 + /* prepare command */
2617 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_DISABLE,
2618 + cmd_flags,
2619 + token);
2620 +
2621 + return mc_send_command(mc_io, &cmd);
2622 +}
2623 +
2624 +/**
2625 + * dpio_get_attributes() - Retrieve DPIO attributes
2626 + * @mc_io: Pointer to MC portal's I/O object
2627 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2628 + * @token: Token of DPIO object
2629 + * @attr: Returned object's attributes
2630 + *
2631 + * Return: '0' on Success; Error code otherwise
2632 + */
2633 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2634 + u32 cmd_flags,
2635 + u16 token,
2636 + struct dpio_attr *attr)
2637 +{
2638 + struct mc_command cmd = { 0 };
2639 + struct dpio_rsp_get_attr *dpio_rsp;
2640 + int err;
2641 +
2642 + /* prepare command */
2643 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_ATTR,
2644 + cmd_flags,
2645 + token);
2646 +
2647 + err = mc_send_command(mc_io, &cmd);
2648 + if (err)
2649 + return err;
2650 +
2651 + /* retrieve response parameters */
2652 + dpio_rsp = (struct dpio_rsp_get_attr *)cmd.params;
2653 + attr->id = le32_to_cpu(dpio_rsp->id);
2654 + attr->qbman_portal_id = le16_to_cpu(dpio_rsp->qbman_portal_id);
2655 + attr->num_priorities = dpio_rsp->num_priorities;
2656 + attr->channel_mode = dpio_rsp->channel_mode & DPIO_CHANNEL_MODE_MASK;
2657 + attr->qbman_portal_ce_offset =
2658 + le64_to_cpu(dpio_rsp->qbman_portal_ce_addr);
2659 + attr->qbman_portal_ci_offset =
2660 + le64_to_cpu(dpio_rsp->qbman_portal_ci_addr);
2661 + attr->qbman_version = le32_to_cpu(dpio_rsp->qbman_version);
2662 +
2663 + return 0;
2664 +}
2665 +
2666 +/**
2667 + * dpio_get_api_version - Get Data Path I/O API version
2668 + * @mc_io: Pointer to MC portal's DPIO object
2669 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
2670 + * @major_ver: Major version of DPIO API
2671 + * @minor_ver: Minor version of DPIO API
2672 + *
2673 + * Return: '0' on Success; Error code otherwise
2674 + */
2675 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2676 + u32 cmd_flags,
2677 + u16 *major_ver,
2678 + u16 *minor_ver)
2679 +{
2680 + struct mc_command cmd = { 0 };
2681 + int err;
2682 +
2683 + /* prepare command */
2684 + cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION,
2685 + cmd_flags, 0);
2686 +
2687 + err = mc_send_command(mc_io, &cmd);
2688 + if (err)
2689 + return err;
2690 +
2691 + /* retrieve response parameters */
2692 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
2693 +
2694 + return 0;
2695 +}
2696 --- /dev/null
2697 +++ b/drivers/staging/fsl-mc/bus/dpio/dpio.h
2698 @@ -0,0 +1,109 @@
2699 +/*
2700 + * Copyright 2013-2016 Freescale Semiconductor Inc.
2701 + * Copyright 2016 NXP
2702 + *
2703 + * Redistribution and use in source and binary forms, with or without
2704 + * modification, are permitted provided that the following conditions are met:
2705 + * * Redistributions of source code must retain the above copyright
2706 + * notice, this list of conditions and the following disclaimer.
2707 + * * Redistributions in binary form must reproduce the above copyright
2708 + * notice, this list of conditions and the following disclaimer in the
2709 + * documentation and/or other materials provided with the distribution.
2710 + * * Neither the name of the above-listed copyright holders nor the
2711 + * names of any contributors may be used to endorse or promote products
2712 + * derived from this software without specific prior written permission.
2713 + *
2714 + * ALTERNATIVELY, this software may be distributed under the terms of the
2715 + * GNU General Public License ("GPL") as published by the Free Software
2716 + * Foundation, either version 2 of that License or (at your option) any
2717 + * later version.
2718 + *
2719 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
2720 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2721 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2722 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
2723 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2724 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2725 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2726 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2727 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
2728 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
2729 + * POSSIBILITY OF SUCH DAMAGE.
2730 + */
2731 +#ifndef __FSL_DPIO_H
2732 +#define __FSL_DPIO_H
2733 +
2734 +struct fsl_mc_io;
2735 +
2736 +int dpio_open(struct fsl_mc_io *mc_io,
2737 + u32 cmd_flags,
2738 + int dpio_id,
2739 + u16 *token);
2740 +
2741 +int dpio_close(struct fsl_mc_io *mc_io,
2742 + u32 cmd_flags,
2743 + u16 token);
2744 +
2745 +/**
2746 + * enum dpio_channel_mode - DPIO notification channel mode
2747 + * @DPIO_NO_CHANNEL: No support for notification channel
2748 + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a
2749 + * dedicated channel in the DPIO; user should point the queue's
2750 + * destination in the relevant interface to this DPIO
2751 + */
2752 +enum dpio_channel_mode {
2753 + DPIO_NO_CHANNEL = 0,
2754 + DPIO_LOCAL_CHANNEL = 1,
2755 +};
2756 +
2757 +/**
2758 + * struct dpio_cfg - Structure representing DPIO configuration
2759 + * @channel_mode: Notification channel mode
2760 + * @num_priorities: Number of priorities for the notification channel (1-8);
2761 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2762 + */
2763 +struct dpio_cfg {
2764 + enum dpio_channel_mode channel_mode;
2765 + u8 num_priorities;
2766 +};
2767 +
2768 +int dpio_enable(struct fsl_mc_io *mc_io,
2769 + u32 cmd_flags,
2770 + u16 token);
2771 +
2772 +int dpio_disable(struct fsl_mc_io *mc_io,
2773 + u32 cmd_flags,
2774 + u16 token);
2775 +
2776 +/**
2777 + * struct dpio_attr - Structure representing DPIO attributes
2778 + * @id: DPIO object ID
2779 + * @qbman_portal_ce_offset: offset of the software portal cache-enabled area
2780 + * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area
2781 + * @qbman_portal_id: Software portal ID
2782 + * @channel_mode: Notification channel mode
2783 + * @num_priorities: Number of priorities for the notification channel (1-8);
2784 + * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL'
2785 + * @qbman_version: QBMAN version
2786 + */
2787 +struct dpio_attr {
2788 + int id;
2789 + u64 qbman_portal_ce_offset;
2790 + u64 qbman_portal_ci_offset;
2791 + u16 qbman_portal_id;
2792 + enum dpio_channel_mode channel_mode;
2793 + u8 num_priorities;
2794 + u32 qbman_version;
2795 +};
2796 +
2797 +int dpio_get_attributes(struct fsl_mc_io *mc_io,
2798 + u32 cmd_flags,
2799 + u16 token,
2800 + struct dpio_attr *attr);
2801 +
2802 +int dpio_get_api_version(struct fsl_mc_io *mc_io,
2803 + u32 cmd_flags,
2804 + u16 *major_ver,
2805 + u16 *minor_ver);
2806 +
2807 +#endif /* __FSL_DPIO_H */
2808 --- /dev/null
2809 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.c
2810 @@ -0,0 +1,1049 @@
2811 +/*
2812 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
2813 + * Copyright 2016 NXP
2814 + *
2815 + * Redistribution and use in source and binary forms, with or without
2816 + * modification, are permitted provided that the following conditions are met:
2817 + * * Redistributions of source code must retain the above copyright
2818 + * notice, this list of conditions and the following disclaimer.
2819 + * * Redistributions in binary form must reproduce the above copyright
2820 + * notice, this list of conditions and the following disclaimer in the
2821 + * documentation and/or other materials provided with the distribution.
2822 + * * Neither the name of Freescale Semiconductor nor the
2823 + * names of its contributors may be used to endorse or promote products
2824 + * derived from this software without specific prior written permission.
2825 + *
2826 + * ALTERNATIVELY, this software may be distributed under the terms of the
2827 + * GNU General Public License ("GPL") as published by the Free Software
2828 + * Foundation, either version 2 of that License or (at your option) any
2829 + * later version.
2830 + *
2831 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
2832 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2833 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
2834 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
2835 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
2836 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
2837 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
2838 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2839 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
2840 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2841 + */
2842 +
2843 +#include <asm/cacheflush.h>
2844 +#include <linux/io.h>
2845 +#include <linux/slab.h>
2846 +#include "../../include/dpaa2-global.h"
2847 +
2848 +#include "qbman-portal.h"
2849 +
2850 +struct qb_attr_code code_generic_verb = QB_CODE(0, 0, 7);
2851 +struct qb_attr_code code_generic_rslt = QB_CODE(0, 8, 8);
2852 +
2853 +#define QMAN_REV_4000 0x04000000
2854 +#define QMAN_REV_4100 0x04010000
2855 +#define QMAN_REV_4101 0x04010001
2856 +#define QMAN_REV_MASK 0xffff0000
2857 +
2858 +/* All QBMan command and result structures use this "valid bit" encoding */
2859 +#define QB_VALID_BIT ((u32)0x80)
2860 +
2861 +/* QBMan portal management command codes */
2862 +#define QBMAN_MC_ACQUIRE 0x30
2863 +#define QBMAN_WQCHAN_CONFIGURE 0x46
2864 +
2865 +/* CINH register offsets */
2866 +#define QBMAN_CINH_SWP_EQAR 0x8c0
2867 +#define QBMAN_CINH_SWP_DQPI 0xa00
2868 +#define QBMAN_CINH_SWP_DCAP 0xac0
2869 +#define QBMAN_CINH_SWP_SDQCR 0xb00
2870 +#define QBMAN_CINH_SWP_RAR 0xcc0
2871 +#define QBMAN_CINH_SWP_ISR 0xe00
2872 +#define QBMAN_CINH_SWP_IER 0xe40
2873 +#define QBMAN_CINH_SWP_ISDR 0xe80
2874 +#define QBMAN_CINH_SWP_IIR 0xec0
2875 +
2876 +/* CENA register offsets */
2877 +#define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((u32)(n) << 6))
2878 +#define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((u32)(n) << 6))
2879 +#define QBMAN_CENA_SWP_RCR(n) (0x400 + ((u32)(n) << 6))
2880 +#define QBMAN_CENA_SWP_CR 0x600
2881 +#define QBMAN_CENA_SWP_RR(vb) (0x700 + ((u32)(vb) >> 1))
2882 +#define QBMAN_CENA_SWP_VDQCR 0x780
2883 +
2884 +/* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
2885 +#define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)(p) & 0x1ff) >> 6)
2886 +
2887 +/* Define token used to determine if response written to memory is valid */
2888 +#define QMAN_DQ_TOKEN_VALID 1
2889 +
2890 +/* SDQCR attribute codes */
2891 +#define QB_SDQCR_FC_SHIFT 29
2892 +#define QB_SDQCR_FC_MASK 0x1
2893 +#define QB_SDQCR_DCT_SHIFT 24
2894 +#define QB_SDQCR_DCT_MASK 0x3
2895 +#define QB_SDQCR_TOK_SHIFT 16
2896 +#define QB_SDQCR_TOK_MASK 0xff
2897 +#define QB_SDQCR_SRC_SHIFT 0
2898 +#define QB_SDQCR_SRC_MASK 0xffff
2899 +
2900 +/* opaque token for static dequeues */
2901 +#define QMAN_SDQCR_TOKEN 0xbb
2902 +
2903 +enum qbman_sdqcr_dct {
2904 + qbman_sdqcr_dct_null = 0,
2905 + qbman_sdqcr_dct_prio_ics,
2906 + qbman_sdqcr_dct_active_ics,
2907 + qbman_sdqcr_dct_active
2908 +};
2909 +
2910 +enum qbman_sdqcr_fc {
2911 + qbman_sdqcr_fc_one = 0,
2912 + qbman_sdqcr_fc_up_to_3 = 1
2913 +};
2914 +
2915 +#define dccvac(p) { asm volatile("dc cvac, %0;" : : "r" (p) : "memory"); }
2916 +#define dcivac(p) { asm volatile("dc ivac, %0" : : "r"(p) : "memory"); }
2917 +static inline void qbman_inval_prefetch(struct qbman_swp *p, uint32_t offset)
2918 +{
2919 + dcivac(p->addr_cena + offset);
2920 + prefetch(p->addr_cena + offset);
2921 +}
2922 +
2923 +/* Portal Access */
2924 +
2925 +static inline u32 qbman_read_register(struct qbman_swp *p, u32 offset)
2926 +{
2927 + return readl_relaxed(p->addr_cinh + offset);
2928 +}
2929 +
2930 +static inline void qbman_write_register(struct qbman_swp *p, u32 offset,
2931 + u32 value)
2932 +{
2933 + writel_relaxed(value, p->addr_cinh + offset);
2934 +}
2935 +
2936 +static inline void *qbman_get_cmd(struct qbman_swp *p, u32 offset)
2937 +{
2938 + return p->addr_cena + offset;
2939 +}
2940 +
2941 +#define QBMAN_CINH_SWP_CFG 0xd00
2942 +
2943 +#define SWP_CFG_DQRR_MF_SHIFT 20
2944 +#define SWP_CFG_EST_SHIFT 16
2945 +#define SWP_CFG_WN_SHIFT 14
2946 +#define SWP_CFG_RPM_SHIFT 12
2947 +#define SWP_CFG_DCM_SHIFT 10
2948 +#define SWP_CFG_EPM_SHIFT 8
2949 +#define SWP_CFG_SD_SHIFT 5
2950 +#define SWP_CFG_SP_SHIFT 4
2951 +#define SWP_CFG_SE_SHIFT 3
2952 +#define SWP_CFG_DP_SHIFT 2
2953 +#define SWP_CFG_DE_SHIFT 1
2954 +#define SWP_CFG_EP_SHIFT 0
2955 +
2956 +static inline u32 qbman_set_swp_cfg(u8 max_fill, u8 wn, u8 est, u8 rpm, u8 dcm,
2957 + u8 epm, int sd, int sp, int se,
2958 + int dp, int de, int ep)
2959 +{
2960 + return cpu_to_le32 (max_fill << SWP_CFG_DQRR_MF_SHIFT |
2961 + est << SWP_CFG_EST_SHIFT |
2962 + wn << SWP_CFG_WN_SHIFT |
2963 + rpm << SWP_CFG_RPM_SHIFT |
2964 + dcm << SWP_CFG_DCM_SHIFT |
2965 + epm << SWP_CFG_EPM_SHIFT |
2966 + sd << SWP_CFG_SD_SHIFT |
2967 + sp << SWP_CFG_SP_SHIFT |
2968 + se << SWP_CFG_SE_SHIFT |
2969 + dp << SWP_CFG_DP_SHIFT |
2970 + de << SWP_CFG_DE_SHIFT |
2971 + ep << SWP_CFG_EP_SHIFT);
2972 +}
2973 +
2974 +/**
2975 + * qbman_swp_init() - Create a functional object representing the given
2976 + * QBMan portal descriptor.
2977 + * @d: the given qbman swp descriptor
2978 + *
2979 + * Return qbman_swp portal for success, NULL if the object cannot
2980 + * be created.
2981 + */
2982 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
2983 +{
2984 + struct qbman_swp *p = kmalloc(sizeof(*p), GFP_KERNEL);
2985 + u32 reg;
2986 +
2987 + if (!p)
2988 + return NULL;
2989 + p->desc = d;
2990 + p->mc.valid_bit = QB_VALID_BIT;
2991 + p->sdq = 0;
2992 + p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
2993 + p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
2994 + p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
2995 +
2996 + atomic_set(&p->vdq.available, 1);
2997 + p->vdq.valid_bit = QB_VALID_BIT;
2998 + p->dqrr.next_idx = 0;
2999 + p->dqrr.valid_bit = QB_VALID_BIT;
3000 +
3001 + if ((p->desc->qman_version & QMAN_REV_MASK) < QMAN_REV_4100) {
3002 + p->dqrr.dqrr_size = 4;
3003 + p->dqrr.reset_bug = 1;
3004 + } else {
3005 + p->dqrr.dqrr_size = 8;
3006 + p->dqrr.reset_bug = 0;
3007 + }
3008 +
3009 + p->addr_cena = d->cena_bar;
3010 + p->addr_cinh = d->cinh_bar;
3011 +
3012 + reg = qbman_set_swp_cfg(p->dqrr.dqrr_size,
3013 + 0, /* Writes cacheable */
3014 + 0, /* EQCR_CI stashing threshold */
3015 + 3, /* RPM: Valid bit mode, RCR in array mode */
3016 + 2, /* DCM: Discrete consumption ack mode */
3017 + 3, /* EPM: Valid bit mode, EQCR in array mode */
3018 + 0, /* mem stashing drop enable == FALSE */
3019 + 1, /* mem stashing priority == TRUE */
3020 + 0, /* mem stashing enable == FALSE */
3021 + 1, /* dequeue stashing priority == TRUE */
3022 + 0, /* dequeue stashing enable == FALSE */
3023 + 0); /* EQCR_CI stashing priority == FALSE */
3024 +
3025 + qbman_write_register(p, QBMAN_CINH_SWP_CFG, reg);
3026 + reg = qbman_read_register(p, QBMAN_CINH_SWP_CFG);
3027 + if (!reg) {
3028 + pr_err("qbman: the portal is not enabled!\n");
3029 + return NULL;
3030 + }
3031 +
3032 + /*
3033 + * SDQCR needs to be initialized to 0 when no channels are
3034 + * being dequeued from or else the QMan HW will indicate an
3035 + * error. The values that were calculated above will be
3036 + * applied when dequeues from a specific channel are enabled.
3037 + */
3038 + qbman_write_register(p, QBMAN_CINH_SWP_SDQCR, 0);
3039 + return p;
3040 +}
3041 +
3042 +/**
3043 + * qbman_swp_finish() - Create and destroy a functional object representing
3044 + * the given QBMan portal descriptor.
3045 + * @p: the qbman_swp object to be destroyed
3046 + */
3047 +void qbman_swp_finish(struct qbman_swp *p)
3048 +{
3049 + kfree(p);
3050 +}
3051 +
3052 +/**
3053 + * qbman_swp_interrupt_read_status()
3054 + * @p: the given software portal
3055 + *
3056 + * Return the value in the SWP_ISR register.
3057 + */
3058 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p)
3059 +{
3060 + return qbman_read_register(p, QBMAN_CINH_SWP_ISR);
3061 +}
3062 +
3063 +/**
3064 + * qbman_swp_interrupt_clear_status()
3065 + * @p: the given software portal
3066 + * @mask: The mask to clear in SWP_ISR register
3067 + */
3068 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask)
3069 +{
3070 + qbman_write_register(p, QBMAN_CINH_SWP_ISR, mask);
3071 +}
3072 +
3073 +/**
3074 + * qbman_swp_interrupt_get_trigger() - read interrupt enable register
3075 + * @p: the given software portal
3076 + *
3077 + * Return the value in the SWP_IER register.
3078 + */
3079 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
3080 +{
3081 + return qbman_read_register(p, QBMAN_CINH_SWP_IER);
3082 +}
3083 +
3084 +/**
3085 + * qbman_swp_interrupt_set_trigger() - enable interrupts for a swp
3086 + * @p: the given software portal
3087 + * @mask: The mask of bits to enable in SWP_IER
3088 + */
3089 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask)
3090 +{
3091 + qbman_write_register(p, QBMAN_CINH_SWP_IER, mask);
3092 +}
3093 +
3094 +/**
3095 + * qbman_swp_interrupt_get_inhibit() - read interrupt mask register
3096 + * @p: the given software portal object
3097 + *
3098 + * Return the value in the SWP_IIR register.
3099 + */
3100 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
3101 +{
3102 + return qbman_read_register(p, QBMAN_CINH_SWP_IIR);
3103 +}
3104 +
3105 +/**
3106 + * qbman_swp_interrupt_set_inhibit() - write interrupt mask register
3107 + * @p: the given software portal object
3108 + * @mask: The mask to set in SWP_IIR register
3109 + */
3110 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
3111 +{
3112 + qbman_write_register(p, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
3113 +}
3114 +
3115 +/*
3116 + * Different management commands all use this common base layer of code to issue
3117 + * commands and poll for results.
3118 + */
3119 +
3120 +/*
3121 + * Returns a pointer to where the caller should fill in their management command
3122 + * (caller should ignore the verb byte)
3123 + */
3124 +void *qbman_swp_mc_start(struct qbman_swp *p)
3125 +{
3126 + return qbman_get_cmd(p, QBMAN_CENA_SWP_CR);
3127 +}
3128 +
3129 +/*
3130 + * Commits merges in the caller-supplied command verb (which should not include
3131 + * the valid-bit) and submits the command to hardware
3132 + */
3133 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb)
3134 +{
3135 + u8 *v = cmd;
3136 +
3137 + dma_wmb();
3138 + *v = cmd_verb | p->mc.valid_bit;
3139 + dccvac(cmd);
3140 +}
3141 +
3142 +/*
3143 + * Checks for a completed response (returns non-NULL if only if the response
3144 + * is complete).
3145 + */
3146 +void *qbman_swp_mc_result(struct qbman_swp *p)
3147 +{
3148 + u32 *ret, verb;
3149 +
3150 + qbman_inval_prefetch(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3151 + ret = qbman_get_cmd(p, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
3152 +
3153 + /* Remove the valid-bit - command completed if the rest is non-zero */
3154 + verb = ret[0] & ~QB_VALID_BIT;
3155 + if (!verb)
3156 + return NULL;
3157 + p->mc.valid_bit ^= QB_VALID_BIT;
3158 + return ret;
3159 +}
3160 +
3161 +#define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0
3162 +enum qb_enqueue_commands {
3163 + enqueue_empty = 0,
3164 + enqueue_response_always = 1,
3165 + enqueue_rejects_to_fq = 2
3166 +};
3167 +
3168 +#define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
3169 +#define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
3170 +#define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
3171 +
3172 +/**
3173 + * qbman_eq_desc_clear() - Clear the contents of a descriptor to
3174 + * default/starting state.
3175 + */
3176 +void qbman_eq_desc_clear(struct qbman_eq_desc *d)
3177 +{
3178 + memset(d, 0, sizeof(*d));
3179 +}
3180 +
3181 +/**
3182 + * qbman_eq_desc_set_no_orp() - Set enqueue descriptor without orp
3183 + * @d: the enqueue descriptor.
3184 + * @response_success: 1 = enqueue with response always; 0 = enqueue with
3185 + * rejections returned on a FQ.
3186 + */
3187 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
3188 +{
3189 + d->verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
3190 + if (respond_success)
3191 + d->verb |= enqueue_response_always;
3192 + else
3193 + d->verb |= enqueue_rejects_to_fq;
3194 +}
3195 +
3196 +/*
3197 + * Exactly one of the following descriptor "targets" should be set. (Calling any
3198 + * one of these will replace the effect of any prior call to one of these.)
3199 + * -enqueue to a frame queue
3200 + * -enqueue to a queuing destination
3201 + */
3202 +
3203 +/**
3204 + * qbman_eq_desc_set_fq() - set the FQ for the enqueue command
3205 + * @d: the enqueue descriptor
3206 + * @fqid: the id of the frame queue to be enqueued
3207 + */
3208 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid)
3209 +{
3210 + d->verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
3211 + d->tgtid = cpu_to_le32(fqid);
3212 +}
3213 +
3214 +/**
3215 + * qbman_eq_desc_set_qd() - Set Queuing Destination for the enqueue command
3216 + * @d: the enqueue descriptor
3217 + * @qdid: the id of the queuing destination to be enqueued
3218 + * @qd_bin: the queuing destination bin
3219 + * @qd_prio: the queuing destination priority
3220 + */
3221 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
3222 + u32 qd_bin, u32 qd_prio)
3223 +{
3224 + d->verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
3225 + d->tgtid = cpu_to_le32(qdid);
3226 + d->qdbin = cpu_to_le16(qd_bin);
3227 + d->qpri = qd_prio;
3228 +}
3229 +
3230 +#define EQAR_IDX(eqar) ((eqar) & 0x7)
3231 +#define EQAR_VB(eqar) ((eqar) & 0x80)
3232 +#define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
3233 +
3234 +/**
3235 + * qbman_swp_enqueue() - Issue an enqueue command
3236 + * @s: the software portal used for enqueue
3237 + * @d: the enqueue descriptor
3238 + * @fd: the frame descriptor to be enqueued
3239 + *
3240 + * Please note that 'fd' should only be NULL if the "action" of the
3241 + * descriptor is "orp_hole" or "orp_nesn".
3242 + *
3243 + * Return 0 for successful enqueue, -EBUSY if the EQCR is not ready.
3244 + */
3245 +int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
3246 + const struct dpaa2_fd *fd)
3247 +{
3248 + struct qbman_eq_desc *p;
3249 + u32 eqar = qbman_read_register(s, QBMAN_CINH_SWP_EQAR);
3250 +
3251 + if (!EQAR_SUCCESS(eqar))
3252 + return -EBUSY;
3253 +
3254 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
3255 + memcpy(&p->dca, &d->dca, 31);
3256 + memcpy(&p->fd, fd, sizeof(*fd));
3257 +
3258 + /* Set the verb byte, have to substitute in the valid-bit */
3259 + dma_wmb();
3260 + p->verb = d->verb | EQAR_VB(eqar);
3261 + dccvac(p);
3262 +
3263 + return 0;
3264 +}
3265 +
3266 +/* Static (push) dequeue */
3267 +
3268 +/**
3269 + * qbman_swp_push_get() - Get the push dequeue setup
3270 + * @p: the software portal object
3271 + * @channel_idx: the channel index to query
3272 + * @enabled: returned boolean to show whether the push dequeue is enabled
3273 + * for the given channel
3274 + */
3275 +void qbman_swp_push_get(struct qbman_swp *s, u8 channel_idx, int *enabled)
3276 +{
3277 + u16 src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3278 +
3279 + WARN_ON(channel_idx > 15);
3280 + *enabled = src | (1 << channel_idx);
3281 +}
3282 +
3283 +/**
3284 + * qbman_swp_push_set() - Enable or disable push dequeue
3285 + * @p: the software portal object
3286 + * @channel_idx: the channel index (0 to 15)
3287 + * @enable: enable or disable push dequeue
3288 + */
3289 +void qbman_swp_push_set(struct qbman_swp *s, u8 channel_idx, int enable)
3290 +{
3291 + u16 dqsrc;
3292 +
3293 + WARN_ON(channel_idx > 15);
3294 + if (enable)
3295 + s->sdq |= 1 << channel_idx;
3296 + else
3297 + s->sdq &= ~(1 << channel_idx);
3298 +
3299 + /* Read make the complete src map. If no channels are enabled
3300 + * the SDQCR must be 0 or else QMan will assert errors
3301 + */
3302 + dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
3303 + if (dqsrc != 0)
3304 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, s->sdq);
3305 + else
3306 + qbman_write_register(s, QBMAN_CINH_SWP_SDQCR, 0);
3307 +}
3308 +
3309 +#define QB_VDQCR_VERB_DCT_SHIFT 0
3310 +#define QB_VDQCR_VERB_DT_SHIFT 2
3311 +#define QB_VDQCR_VERB_RLS_SHIFT 4
3312 +#define QB_VDQCR_VERB_WAE_SHIFT 5
3313 +
3314 +enum qb_pull_dt_e {
3315 + qb_pull_dt_channel,
3316 + qb_pull_dt_workqueue,
3317 + qb_pull_dt_framequeue
3318 +};
3319 +
3320 +/**
3321 + * qbman_pull_desc_clear() - Clear the contents of a descriptor to
3322 + * default/starting state
3323 + * @d: the pull dequeue descriptor to be cleared
3324 + */
3325 +void qbman_pull_desc_clear(struct qbman_pull_desc *d)
3326 +{
3327 + memset(d, 0, sizeof(*d));
3328 +}
3329 +
3330 +/**
3331 + * qbman_pull_desc_set_storage()- Set the pull dequeue storage
3332 + * @d: the pull dequeue descriptor to be set
3333 + * @storage: the pointer of the memory to store the dequeue result
3334 + * @storage_phys: the physical address of the storage memory
3335 + * @stash: to indicate whether write allocate is enabled
3336 + *
3337 + * If not called, or if called with 'storage' as NULL, the result pull dequeues
3338 + * will produce results to DQRR. If 'storage' is non-NULL, then results are
3339 + * produced to the given memory location (using the DMA address which
3340 + * the caller provides in 'storage_phys'), and 'stash' controls whether or not
3341 + * those writes to main-memory express a cache-warming attribute.
3342 + */
3343 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
3344 + struct dpaa2_dq *storage,
3345 + dma_addr_t storage_phys,
3346 + int stash)
3347 +{
3348 + /* save the virtual address */
3349 + d->rsp_addr_virt = (u64)storage;
3350 +
3351 + if (!storage) {
3352 + d->verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
3353 + return;
3354 + }
3355 + d->verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
3356 + if (stash)
3357 + d->verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
3358 + else
3359 + d->verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
3360 +
3361 + d->rsp_addr = cpu_to_le64(storage_phys);
3362 +}
3363 +
3364 +/**
3365 + * qbman_pull_desc_set_numframes() - Set the number of frames to be dequeued
3366 + * @d: the pull dequeue descriptor to be set
3367 + * @numframes: number of frames to be set, must be between 1 and 16, inclusive
3368 + */
3369 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes)
3370 +{
3371 + d->numf = numframes - 1;
3372 +}
3373 +
3374 +void qbman_pull_desc_set_token(struct qbman_pull_desc *d, u8 token)
3375 +{
3376 + d->tok = token;
3377 +}
3378 +
3379 +/*
3380 + * Exactly one of the following descriptor "actions" should be set. (Calling any
3381 + * one of these will replace the effect of any prior call to one of these.)
3382 + * - pull dequeue from the given frame queue (FQ)
3383 + * - pull dequeue from any FQ in the given work queue (WQ)
3384 + * - pull dequeue from any FQ in any WQ in the given channel
3385 + */
3386 +
3387 +/**
3388 + * qbman_pull_desc_set_fq() - Set fqid from which the dequeue command dequeues
3389 + * @fqid: the frame queue index of the given FQ
3390 + */
3391 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid)
3392 +{
3393 + d->verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
3394 + d->verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
3395 + d->dq_src = cpu_to_le32(fqid);
3396 +}
3397 +
3398 +/**
3399 + * qbman_pull_desc_set_wq() - Set wqid from which the dequeue command dequeues
3400 + * @wqid: composed of channel id and wqid within the channel
3401 + * @dct: the dequeue command type
3402 + */
3403 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
3404 + enum qbman_pull_type_e dct)
3405 +{
3406 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3407 + d->verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
3408 + d->dq_src = cpu_to_le32(wqid);
3409 +}
3410 +
3411 +/**
3412 + * qbman_pull_desc_set_channel() - Set channelid from which the dequeue command
3413 + * dequeues
3414 + * @chid: the channel id to be dequeued
3415 + * @dct: the dequeue command type
3416 + */
3417 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
3418 + enum qbman_pull_type_e dct)
3419 +{
3420 + d->verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
3421 + d->verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
3422 + d->dq_src = cpu_to_le32(chid);
3423 +}
3424 +
3425 +/**
3426 + * qbman_swp_pull() - Issue the pull dequeue command
3427 + * @s: the software portal object
3428 + * @d: the software portal descriptor which has been configured with
3429 + * the set of qbman_pull_desc_set_*() calls
3430 + *
3431 + * Return 0 for success, and -EBUSY if the software portal is not ready
3432 + * to do pull dequeue.
3433 + */
3434 +int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
3435 +{
3436 + struct qbman_pull_desc *p;
3437 +
3438 + if (!atomic_dec_and_test(&s->vdq.available)) {
3439 + atomic_inc(&s->vdq.available);
3440 + return -EBUSY;
3441 + }
3442 + s->vdq.storage = (void *)d->rsp_addr_virt;
3443 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_VDQCR);
3444 + p->numf = d->numf;
3445 + p->tok = QMAN_DQ_TOKEN_VALID;
3446 + p->dq_src = d->dq_src;
3447 + p->rsp_addr = d->rsp_addr;
3448 + p->rsp_addr_virt = d->rsp_addr_virt;
3449 + dma_wmb();
3450 +
3451 + /* Set the verb byte, have to substitute in the valid-bit */
3452 + p->verb = d->verb | s->vdq.valid_bit;
3453 + s->vdq.valid_bit ^= QB_VALID_BIT;
3454 + dccvac(p);
3455 +
3456 + return 0;
3457 +}
3458 +
3459 +#define QMAN_DQRR_PI_MASK 0xf
3460 +
3461 +/**
3462 + * qbman_swp_dqrr_next() - Get an valid DQRR entry
3463 + * @s: the software portal object
3464 + *
3465 + * Return NULL if there are no unconsumed DQRR entries. Return a DQRR entry
3466 + * only once, so repeated calls can return a sequence of DQRR entries, without
3467 + * requiring they be consumed immediately or in any particular order.
3468 + */
3469 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s)
3470 +{
3471 + u32 verb;
3472 + u32 response_verb;
3473 + u32 flags;
3474 + struct dpaa2_dq *p;
3475 +
3476 + /* Before using valid-bit to detect if something is there, we have to
3477 + * handle the case of the DQRR reset bug...
3478 + */
3479 + if (unlikely(s->dqrr.reset_bug)) {
3480 + /*
3481 + * We pick up new entries by cache-inhibited producer index,
3482 + * which means that a non-coherent mapping would require us to
3483 + * invalidate and read *only* once that PI has indicated that
3484 + * there's an entry here. The first trip around the DQRR ring
3485 + * will be much less efficient than all subsequent trips around
3486 + * it...
3487 + */
3488 + u8 pi = qbman_read_register(s, QBMAN_CINH_SWP_DQPI) &
3489 + QMAN_DQRR_PI_MASK;
3490 +
3491 + /* there are new entries if pi != next_idx */
3492 + if (pi == s->dqrr.next_idx)
3493 + return NULL;
3494 +
3495 + /*
3496 + * if next_idx is/was the last ring index, and 'pi' is
3497 + * different, we can disable the workaround as all the ring
3498 + * entries have now been DMA'd to so valid-bit checking is
3499 + * repaired. Note: this logic needs to be based on next_idx
3500 + * (which increments one at a time), rather than on pi (which
3501 + * can burst and wrap-around between our snapshots of it).
3502 + */
3503 + if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1)) {
3504 + pr_debug("next_idx=%d, pi=%d, clear reset bug\n",
3505 + s->dqrr.next_idx, pi);
3506 + s->dqrr.reset_bug = 0;
3507 + }
3508 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3509 + }
3510 +
3511 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3512 + verb = p->dq.verb;
3513 +
3514 + /*
3515 + * If the valid-bit isn't of the expected polarity, nothing there. Note,
3516 + * in the DQRR reset bug workaround, we shouldn't need to skip these
3517 + * check, because we've already determined that a new entry is available
3518 + * and we've invalidated the cacheline before reading it, so the
3519 + * valid-bit behaviour is repaired and should tell us what we already
3520 + * knew from reading PI.
3521 + */
3522 + if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit) {
3523 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3524 + return NULL;
3525 + }
3526 + /*
3527 + * There's something there. Move "next_idx" attention to the next ring
3528 + * entry (and prefetch it) before returning what we found.
3529 + */
3530 + s->dqrr.next_idx++;
3531 + s->dqrr.next_idx &= s->dqrr.dqrr_size - 1; /* Wrap around */
3532 + if (!s->dqrr.next_idx)
3533 + s->dqrr.valid_bit ^= QB_VALID_BIT;
3534 +
3535 + /*
3536 + * If this is the final response to a volatile dequeue command
3537 + * indicate that the vdq is available
3538 + */
3539 + flags = p->dq.stat;
3540 + response_verb = verb & QBMAN_RESULT_MASK;
3541 + if ((response_verb == QBMAN_RESULT_DQ) &&
3542 + (flags & DPAA2_DQ_STAT_VOLATILE) &&
3543 + (flags & DPAA2_DQ_STAT_EXPIRED))
3544 + atomic_inc(&s->vdq.available);
3545 +
3546 + qbman_inval_prefetch(s, QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
3547 +
3548 + return p;
3549 +}
3550 +
3551 +/**
3552 + * qbman_swp_dqrr_consume() - Consume DQRR entries previously returned from
3553 + * qbman_swp_dqrr_next().
3554 + * @s: the software portal object
3555 + * @dq: the DQRR entry to be consumed
3556 + */
3557 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq)
3558 +{
3559 + qbman_write_register(s, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
3560 +}
3561 +
3562 +/**
3563 + * qbman_result_has_new_result() - Check and get the dequeue response from the
3564 + * dq storage memory set in pull dequeue command
3565 + * @s: the software portal object
3566 + * @dq: the dequeue result read from the memory
3567 + *
3568 + * Return 1 for getting a valid dequeue result, or 0 for not getting a valid
3569 + * dequeue result.
3570 + *
3571 + * Only used for user-provided storage of dequeue results, not DQRR. For
3572 + * efficiency purposes, the driver will perform any required endianness
3573 + * conversion to ensure that the user's dequeue result storage is in host-endian
3574 + * format. As such, once the user has called qbman_result_has_new_result() and
3575 + * been returned a valid dequeue result, they should not call it again on
3576 + * the same memory location (except of course if another dequeue command has
3577 + * been executed to produce a new result to that location).
3578 + */
3579 +int qbman_result_has_new_result(struct qbman_swp *s, const struct dpaa2_dq *dq)
3580 +{
3581 + if (dq->dq.tok != QMAN_DQ_TOKEN_VALID)
3582 + return 0;
3583 +
3584 + /*
3585 + * Set token to be 0 so we will detect change back to 1
3586 + * next time the looping is traversed. Const is cast away here
3587 + * as we want users to treat the dequeue responses as read only.
3588 + */
3589 + ((struct dpaa2_dq *)dq)->dq.tok = 0;
3590 +
3591 + /*
3592 + * Determine whether VDQCR is available based on whether the
3593 + * current result is sitting in the first storage location of
3594 + * the busy command.
3595 + */
3596 + if (s->vdq.storage == dq) {
3597 + s->vdq.storage = NULL;
3598 + atomic_inc(&s->vdq.available);
3599 + }
3600 +
3601 + return 1;
3602 +}
3603 +
3604 +/**
3605 + * qbman_release_desc_clear() - Clear the contents of a descriptor to
3606 + * default/starting state.
3607 + */
3608 +void qbman_release_desc_clear(struct qbman_release_desc *d)
3609 +{
3610 + memset(d, 0, sizeof(*d));
3611 + d->verb = 1 << 5; /* Release Command Valid */
3612 +}
3613 +
3614 +/**
3615 + * qbman_release_desc_set_bpid() - Set the ID of the buffer pool to release to
3616 + */
3617 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid)
3618 +{
3619 + d->bpid = cpu_to_le16(bpid);
3620 +}
3621 +
3622 +/**
3623 + * qbman_release_desc_set_rcdi() - Determines whether or not the portal's RCDI
3624 + * interrupt source should be asserted after the release command is completed.
3625 + */
3626 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
3627 +{
3628 + if (enable)
3629 + d->verb |= 1 << 6;
3630 + else
3631 + d->verb &= ~(1 << 6);
3632 +}
3633 +
3634 +#define RAR_IDX(rar) ((rar) & 0x7)
3635 +#define RAR_VB(rar) ((rar) & 0x80)
3636 +#define RAR_SUCCESS(rar) ((rar) & 0x100)
3637 +
3638 +/**
3639 + * qbman_swp_release() - Issue a buffer release command
3640 + * @s: the software portal object
3641 + * @d: the release descriptor
3642 + * @buffers: a pointer pointing to the buffer address to be released
3643 + * @num_buffers: number of buffers to be released, must be less than 8
3644 + *
3645 + * Return 0 for success, -EBUSY if the release command ring is not ready.
3646 + */
3647 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
3648 + const u64 *buffers, unsigned int num_buffers)
3649 +{
3650 + int i;
3651 + struct qbman_release_desc *p;
3652 + u32 rar;
3653 +
3654 + if (!num_buffers || (num_buffers > 7))
3655 + return -EINVAL;
3656 +
3657 + rar = qbman_read_register(s, QBMAN_CINH_SWP_RAR);
3658 + if (!RAR_SUCCESS(rar))
3659 + return -EBUSY;
3660 +
3661 + /* Start the release command */
3662 + p = qbman_get_cmd(s, QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
3663 + /* Copy the caller's buffer pointers to the command */
3664 + for (i = 0; i < num_buffers; i++)
3665 + p->buf[i] = cpu_to_le64(buffers[i]);
3666 + p->bpid = d->bpid;
3667 +
3668 + /*
3669 + * Set the verb byte, have to substitute in the valid-bit and the number
3670 + * of buffers.
3671 + */
3672 + dma_wmb();
3673 + p->verb = d->verb | RAR_VB(rar) | num_buffers;
3674 + dccvac(p);
3675 +
3676 + return 0;
3677 +}
3678 +
3679 +struct qbman_acquire_desc {
3680 + u8 verb;
3681 + u8 reserved;
3682 + u16 bpid;
3683 + u8 num;
3684 + u8 reserved2[59];
3685 +};
3686 +
3687 +struct qbman_acquire_rslt {
3688 + u8 verb;
3689 + u8 rslt;
3690 + u16 reserved;
3691 + u8 num;
3692 + u8 reserved2[3];
3693 + u64 buf[7];
3694 +};
3695 +
3696 +/**
3697 + * qbman_swp_acquire() - Issue a buffer acquire command
3698 + * @s: the software portal object
3699 + * @bpid: the buffer pool index
3700 + * @buffers: a pointer pointing to the acquired buffer addresses
3701 + * @num_buffers: number of buffers to be acquired, must be less than 8
3702 + *
3703 + * Return 0 for success, or negative error code if the acquire command
3704 + * fails.
3705 + */
3706 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
3707 + unsigned int num_buffers)
3708 +{
3709 + struct qbman_acquire_desc *p;
3710 + struct qbman_acquire_rslt *r;
3711 + int i;
3712 +
3713 + if (!num_buffers || (num_buffers > 7))
3714 + return -EINVAL;
3715 +
3716 + /* Start the management command */
3717 + p = qbman_swp_mc_start(s);
3718 +
3719 + if (!p)
3720 + return -EBUSY;
3721 +
3722 + /* Encode the caller-provided attributes */
3723 + p->bpid = cpu_to_le16(bpid);
3724 + p->num = num_buffers;
3725 +
3726 + /* Complete the management command */
3727 + r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
3728 + if (unlikely(!r)) {
3729 + pr_err("qbman: acquire from BPID %d failed, no response\n",
3730 + bpid);
3731 + return -EIO;
3732 + }
3733 +
3734 + /* Decode the outcome */
3735 + WARN_ON((r->verb & 0x7f) != QBMAN_MC_ACQUIRE);
3736 +
3737 + /* Determine success or failure */
3738 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3739 + pr_err("qbman: acquire from BPID 0x%x failed, code=0x%02x\n",
3740 + bpid, r->rslt);
3741 + return -EIO;
3742 + }
3743 +
3744 + WARN_ON(r->num > num_buffers);
3745 +
3746 + /* Copy the acquired buffers to the caller's array */
3747 + for (i = 0; i < r->num; i++)
3748 + buffers[i] = le64_to_cpu(r->buf[i]);
3749 +
3750 + return (int)r->num;
3751 +}
3752 +
3753 +struct qbman_alt_fq_state_desc {
3754 + u8 verb;
3755 + u8 reserved[3];
3756 + u32 fqid;
3757 + u8 reserved2[56];
3758 +};
3759 +
3760 +struct qbman_alt_fq_state_rslt {
3761 + u8 verb;
3762 + u8 rslt;
3763 + u8 reserved[62];
3764 +};
3765 +
3766 +#define ALT_FQ_FQID_MASK 0x00FFFFFF
3767 +
3768 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
3769 + u8 alt_fq_verb)
3770 +{
3771 + struct qbman_alt_fq_state_desc *p;
3772 + struct qbman_alt_fq_state_rslt *r;
3773 +
3774 + /* Start the management command */
3775 + p = qbman_swp_mc_start(s);
3776 + if (!p)
3777 + return -EBUSY;
3778 +
3779 + p->fqid = cpu_to_le32(fqid) & ALT_FQ_FQID_MASK;
3780 +
3781 + /* Complete the management command */
3782 + r = qbman_swp_mc_complete(s, p, alt_fq_verb);
3783 + if (unlikely(!r)) {
3784 + pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
3785 + alt_fq_verb);
3786 + return -EIO;
3787 + }
3788 +
3789 + /* Decode the outcome */
3790 + WARN_ON((r->verb & QBMAN_RESULT_MASK) != alt_fq_verb);
3791 +
3792 + /* Determine success or failure */
3793 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3794 + pr_err("qbman: ALT FQID %d failed: verb = 0x%08x code = 0x%02x\n",
3795 + fqid, r->verb, r->rslt);
3796 + return -EIO;
3797 + }
3798 +
3799 + return 0;
3800 +}
3801 +
3802 +struct qbman_cdan_ctrl_desc {
3803 + u8 verb;
3804 + u8 reserved;
3805 + u16 ch;
3806 + u8 we;
3807 + u8 ctrl;
3808 + u16 reserved2;
3809 + u64 cdan_ctx;
3810 + u8 reserved3[48];
3811 +
3812 +};
3813 +
3814 +struct qbman_cdan_ctrl_rslt {
3815 + u8 verb;
3816 + u8 rslt;
3817 + u16 ch;
3818 + u8 reserved[60];
3819 +};
3820 +
3821 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
3822 + u8 we_mask, u8 cdan_en,
3823 + u64 ctx)
3824 +{
3825 + struct qbman_cdan_ctrl_desc *p = NULL;
3826 + struct qbman_cdan_ctrl_rslt *r = NULL;
3827 +
3828 + /* Start the management command */
3829 + p = qbman_swp_mc_start(s);
3830 + if (!p)
3831 + return -EBUSY;
3832 +
3833 + /* Encode the caller-provided attributes */
3834 + p->ch = cpu_to_le16(channelid);
3835 + p->we = we_mask;
3836 + if (cdan_en)
3837 + p->ctrl = 1;
3838 + else
3839 + p->ctrl = 0;
3840 + p->cdan_ctx = cpu_to_le64(ctx);
3841 +
3842 + /* Complete the management command */
3843 + r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
3844 + if (unlikely(!r)) {
3845 + pr_err("qbman: wqchan config failed, no response\n");
3846 + return -EIO;
3847 + }
3848 +
3849 + WARN_ON((r->verb & 0x7f) != QBMAN_WQCHAN_CONFIGURE);
3850 +
3851 + /* Determine success or failure */
3852 + if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
3853 + pr_err("qbman: CDAN cQID %d failed: code = 0x%02x\n",
3854 + channelid, r->rslt);
3855 + return -EIO;
3856 + }
3857 +
3858 + return 0;
3859 +}
3860 --- /dev/null
3861 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman-portal.h
3862 @@ -0,0 +1,662 @@
3863 +/*
3864 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
3865 + * Copyright 2016 NXP
3866 + *
3867 + * Redistribution and use in source and binary forms, with or without
3868 + * modification, are permitted provided that the following conditions are met:
3869 + * * Redistributions of source code must retain the above copyright
3870 + * notice, this list of conditions and the following disclaimer.
3871 + * * Redistributions in binary form must reproduce the above copyright
3872 + * notice, this list of conditions and the following disclaimer in the
3873 + * documentation and/or other materials provided with the distribution.
3874 + * * Neither the name of Freescale Semiconductor nor the
3875 + * names of its contributors may be used to endorse or promote products
3876 + * derived from this software without specific prior written permission.
3877 + *
3878 + * ALTERNATIVELY, this software may be distributed under the terms of the
3879 + * GNU General Public License ("GPL") as published by the Free Software
3880 + * Foundation, either version 2 of that License or (at your option) any
3881 + * later version.
3882 + *
3883 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
3884 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
3885 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
3886 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
3887 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
3888 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
3889 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
3890 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3891 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
3892 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3893 + */
3894 +#ifndef __FSL_QBMAN_PORTAL_H
3895 +#define __FSL_QBMAN_PORTAL_H
3896 +
3897 +#include "qbman_private.h"
3898 +#include "../../include/dpaa2-fd.h"
3899 +
3900 +struct dpaa2_dq;
3901 +struct qbman_swp;
3902 +
3903 +/* qbman software portal descriptor structure */
3904 +struct qbman_swp_desc {
3905 + void *cena_bar; /* Cache-enabled portal base address */
3906 + void *cinh_bar; /* Cache-inhibited portal base address */
3907 + u32 qman_version;
3908 +};
3909 +
3910 +#define QBMAN_SWP_INTERRUPT_EQRI 0x01
3911 +#define QBMAN_SWP_INTERRUPT_EQDI 0x02
3912 +#define QBMAN_SWP_INTERRUPT_DQRI 0x04
3913 +#define QBMAN_SWP_INTERRUPT_RCRI 0x08
3914 +#define QBMAN_SWP_INTERRUPT_RCDI 0x10
3915 +#define QBMAN_SWP_INTERRUPT_VDCI 0x20
3916 +
3917 +/* the structure for pull dequeue descriptor */
3918 +struct qbman_pull_desc {
3919 + u8 verb;
3920 + u8 numf;
3921 + u8 tok;
3922 + u8 reserved;
3923 + u32 dq_src;
3924 + u64 rsp_addr;
3925 + u64 rsp_addr_virt;
3926 + u8 padding[40];
3927 +};
3928 +
3929 +enum qbman_pull_type_e {
3930 + /* dequeue with priority precedence, respect intra-class scheduling */
3931 + qbman_pull_type_prio = 1,
3932 + /* dequeue with active FQ precedence, respect ICS */
3933 + qbman_pull_type_active,
3934 + /* dequeue with active FQ precedence, no ICS */
3935 + qbman_pull_type_active_noics
3936 +};
3937 +
3938 +/* Definitions for parsing dequeue entries */
3939 +#define QBMAN_RESULT_MASK 0x7f
3940 +#define QBMAN_RESULT_DQ 0x60
3941 +#define QBMAN_RESULT_FQRN 0x21
3942 +#define QBMAN_RESULT_FQRNI 0x22
3943 +#define QBMAN_RESULT_FQPN 0x24
3944 +#define QBMAN_RESULT_FQDAN 0x25
3945 +#define QBMAN_RESULT_CDAN 0x26
3946 +#define QBMAN_RESULT_CSCN_MEM 0x27
3947 +#define QBMAN_RESULT_CGCU 0x28
3948 +#define QBMAN_RESULT_BPSCN 0x29
3949 +#define QBMAN_RESULT_CSCN_WQ 0x2a
3950 +
3951 +/* QBMan FQ management command codes */
3952 +#define QBMAN_FQ_SCHEDULE 0x48
3953 +#define QBMAN_FQ_FORCE 0x49
3954 +#define QBMAN_FQ_XON 0x4d
3955 +#define QBMAN_FQ_XOFF 0x4e
3956 +
3957 +/* structure of enqueue descriptor */
3958 +struct qbman_eq_desc {
3959 + u8 verb;
3960 + u8 dca;
3961 + u16 seqnum;
3962 + u16 orpid;
3963 + u16 reserved1;
3964 + u32 tgtid;
3965 + u32 tag;
3966 + u16 qdbin;
3967 + u8 qpri;
3968 + u8 reserved[3];
3969 + u8 wae;
3970 + u8 rspid;
3971 + u64 rsp_addr;
3972 + u8 fd[32];
3973 +};
3974 +
3975 +/* buffer release descriptor */
3976 +struct qbman_release_desc {
3977 + u8 verb;
3978 + u8 reserved;
3979 + u16 bpid;
3980 + u32 reserved2;
3981 + u64 buf[7];
3982 +};
3983 +
3984 +/* Management command result codes */
3985 +#define QBMAN_MC_RSLT_OK 0xf0
3986 +
3987 +#define CODE_CDAN_WE_EN 0x1
3988 +#define CODE_CDAN_WE_CTX 0x4
3989 +
3990 +/* portal data structure */
3991 +struct qbman_swp {
3992 + const struct qbman_swp_desc *desc;
3993 + void __iomem *addr_cena;
3994 + void __iomem *addr_cinh;
3995 +
3996 + /* Management commands */
3997 + struct {
3998 + u32 valid_bit; /* 0x00 or 0x80 */
3999 + } mc;
4000 +
4001 + /* Push dequeues */
4002 + u32 sdq;
4003 +
4004 + /* Volatile dequeues */
4005 + struct {
4006 + atomic_t available; /* indicates if a command can be sent */
4007 + u32 valid_bit; /* 0x00 or 0x80 */
4008 + struct dpaa2_dq *storage; /* NULL if DQRR */
4009 + } vdq;
4010 +
4011 + /* DQRR */
4012 + struct {
4013 + u32 next_idx;
4014 + u32 valid_bit;
4015 + u8 dqrr_size;
4016 + int reset_bug; /* indicates dqrr reset workaround is needed */
4017 + } dqrr;
4018 +};
4019 +
4020 +struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d);
4021 +void qbman_swp_finish(struct qbman_swp *p);
4022 +u32 qbman_swp_interrupt_read_status(struct qbman_swp *p);
4023 +void qbman_swp_interrupt_clear_status(struct qbman_swp *p, u32 mask);
4024 +u32 qbman_swp_interrupt_get_trigger(struct qbman_swp *p);
4025 +void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, u32 mask);
4026 +int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p);
4027 +void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit);
4028 +
4029 +void qbman_swp_push_get(struct qbman_swp *p, u8 channel_idx, int *enabled);
4030 +void qbman_swp_push_set(struct qbman_swp *p, u8 channel_idx, int enable);
4031 +
4032 +void qbman_pull_desc_clear(struct qbman_pull_desc *d);
4033 +void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
4034 + struct dpaa2_dq *storage,
4035 + dma_addr_t storage_phys,
4036 + int stash);
4037 +void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, u8 numframes);
4038 +void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, u32 fqid);
4039 +void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, u32 wqid,
4040 + enum qbman_pull_type_e dct);
4041 +void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, u32 chid,
4042 + enum qbman_pull_type_e dct);
4043 +
4044 +int qbman_swp_pull(struct qbman_swp *p, struct qbman_pull_desc *d);
4045 +
4046 +const struct dpaa2_dq *qbman_swp_dqrr_next(struct qbman_swp *s);
4047 +void qbman_swp_dqrr_consume(struct qbman_swp *s, const struct dpaa2_dq *dq);
4048 +
4049 +int qbman_result_has_new_result(struct qbman_swp *p, const struct dpaa2_dq *dq);
4050 +
4051 +void qbman_eq_desc_clear(struct qbman_eq_desc *d);
4052 +void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success);
4053 +void qbman_eq_desc_set_token(struct qbman_eq_desc *d, u8 token);
4054 +void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, u32 fqid);
4055 +void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, u32 qdid,
4056 + u32 qd_bin, u32 qd_prio);
4057 +
4058 +int qbman_swp_enqueue(struct qbman_swp *p, const struct qbman_eq_desc *d,
4059 + const struct dpaa2_fd *fd);
4060 +
4061 +void qbman_release_desc_clear(struct qbman_release_desc *d);
4062 +void qbman_release_desc_set_bpid(struct qbman_release_desc *d, u16 bpid);
4063 +void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable);
4064 +
4065 +int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
4066 + const u64 *buffers, unsigned int num_buffers);
4067 +int qbman_swp_acquire(struct qbman_swp *s, u16 bpid, u64 *buffers,
4068 + unsigned int num_buffers);
4069 +int qbman_swp_alt_fq_state(struct qbman_swp *s, u32 fqid,
4070 + u8 alt_fq_verb);
4071 +int qbman_swp_CDAN_set(struct qbman_swp *s, u16 channelid,
4072 + u8 we_mask, u8 cdan_en,
4073 + u64 ctx);
4074 +
4075 +void *qbman_swp_mc_start(struct qbman_swp *p);
4076 +void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, u8 cmd_verb);
4077 +void *qbman_swp_mc_result(struct qbman_swp *p);
4078 +
4079 +/**
4080 + * qbman_result_is_DQ() - check if the dequeue result is a dequeue response
4081 + * @dq: the dequeue result to be checked
4082 + *
4083 + * DQRR entries may contain non-dequeue results, ie. notifications
4084 + */
4085 +static inline int qbman_result_is_DQ(const struct dpaa2_dq *dq)
4086 +{
4087 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_DQ);
4088 +}
4089 +
4090 +/**
4091 + * qbman_result_is_SCN() - Check the dequeue result is notification or not
4092 + * @dq: the dequeue result to be checked
4093 + *
4094 + */
4095 +static inline int qbman_result_is_SCN(const struct dpaa2_dq *dq)
4096 +{
4097 + return !qbman_result_is_DQ(dq);
4098 +}
4099 +
4100 +/* FQ Data Availability */
4101 +static inline int qbman_result_is_FQDAN(const struct dpaa2_dq *dq)
4102 +{
4103 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQDAN);
4104 +}
4105 +
4106 +/* Channel Data Availability */
4107 +static inline int qbman_result_is_CDAN(const struct dpaa2_dq *dq)
4108 +{
4109 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CDAN);
4110 +}
4111 +
4112 +/* Congestion State Change */
4113 +static inline int qbman_result_is_CSCN(const struct dpaa2_dq *dq)
4114 +{
4115 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CSCN_WQ);
4116 +}
4117 +
4118 +/* Buffer Pool State Change */
4119 +static inline int qbman_result_is_BPSCN(const struct dpaa2_dq *dq)
4120 +{
4121 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_BPSCN);
4122 +}
4123 +
4124 +/* Congestion Group Count Update */
4125 +static inline int qbman_result_is_CGCU(const struct dpaa2_dq *dq)
4126 +{
4127 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_CGCU);
4128 +}
4129 +
4130 +/* Retirement */
4131 +static inline int qbman_result_is_FQRN(const struct dpaa2_dq *dq)
4132 +{
4133 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRN);
4134 +}
4135 +
4136 +/* Retirement Immediate */
4137 +static inline int qbman_result_is_FQRNI(const struct dpaa2_dq *dq)
4138 +{
4139 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQRNI);
4140 +}
4141 +
4142 + /* Park */
4143 +static inline int qbman_result_is_FQPN(const struct dpaa2_dq *dq)
4144 +{
4145 + return ((dq->dq.verb & QBMAN_RESULT_MASK) == QBMAN_RESULT_FQPN);
4146 +}
4147 +
4148 +/**
4149 + * qbman_result_SCN_state() - Get the state field in State-change notification
4150 + */
4151 +static inline u8 qbman_result_SCN_state(const struct dpaa2_dq *scn)
4152 +{
4153 + return scn->scn.state;
4154 +}
4155 +
4156 +#define SCN_RID_MASK 0x00FFFFFF
4157 +
4158 +/**
4159 + * qbman_result_SCN_rid() - Get the resource id in State-change notification
4160 + */
4161 +static inline u32 qbman_result_SCN_rid(const struct dpaa2_dq *scn)
4162 +{
4163 + return le32_to_cpu(scn->scn.rid_tok) & SCN_RID_MASK;
4164 +}
4165 +
4166 +/**
4167 + * qbman_result_SCN_ctx() - Get the context data in State-change notification
4168 + */
4169 +static inline u64 qbman_result_SCN_ctx(const struct dpaa2_dq *scn)
4170 +{
4171 + return le64_to_cpu(scn->scn.ctx);
4172 +}
4173 +
4174 +/**
4175 + * qbman_swp_fq_schedule() - Move the fq to the scheduled state
4176 + * @s: the software portal object
4177 + * @fqid: the index of frame queue to be scheduled
4178 + *
4179 + * There are a couple of different ways that a FQ can end up parked state,
4180 + * This schedules it.
4181 + *
4182 + * Return 0 for success, or negative error code for failure.
4183 + */
4184 +static inline int qbman_swp_fq_schedule(struct qbman_swp *s, u32 fqid)
4185 +{
4186 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
4187 +}
4188 +
4189 +/**
4190 + * qbman_swp_fq_force() - Force the FQ to fully scheduled state
4191 + * @s: the software portal object
4192 + * @fqid: the index of frame queue to be forced
4193 + *
4194 + * Force eligible will force a tentatively-scheduled FQ to be fully-scheduled
4195 + * and thus be available for selection by any channel-dequeuing behaviour (push
4196 + * or pull). If the FQ is subsequently "dequeued" from the channel and is still
4197 + * empty at the time this happens, the resulting dq_entry will have no FD.
4198 + * (qbman_result_DQ_fd() will return NULL.)
4199 + *
4200 + * Return 0 for success, or negative error code for failure.
4201 + */
4202 +static inline int qbman_swp_fq_force(struct qbman_swp *s, u32 fqid)
4203 +{
4204 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
4205 +}
4206 +
4207 +/**
4208 + * qbman_swp_fq_xon() - sets FQ flow-control to XON
4209 + * @s: the software portal object
4210 + * @fqid: the index of frame queue
4211 + *
4212 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4213 + *
4214 + * Return 0 for success, or negative error code for failure.
4215 + */
4216 +static inline int qbman_swp_fq_xon(struct qbman_swp *s, u32 fqid)
4217 +{
4218 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
4219 +}
4220 +
4221 +/**
4222 + * qbman_swp_fq_xoff() - sets FQ flow-control to XOFF
4223 + * @s: the software portal object
4224 + * @fqid: the index of frame queue
4225 + *
4226 + * This setting doesn't affect enqueues to the FQ, just dequeues.
4227 + * XOFF FQs will remain in the tenatively-scheduled state, even when
4228 + * non-empty, meaning they won't be selected for scheduled dequeuing.
4229 + * If a FQ is changed to XOFF after it had already become truly-scheduled
4230 + * to a channel, and a pull dequeue of that channel occurs that selects
4231 + * that FQ for dequeuing, then the resulting dq_entry will have no FD.
4232 + * (qbman_result_DQ_fd() will return NULL.)
4233 + *
4234 + * Return 0 for success, or negative error code for failure.
4235 + */
4236 +static inline int qbman_swp_fq_xoff(struct qbman_swp *s, u32 fqid)
4237 +{
4238 + return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
4239 +}
4240 +
4241 +/* If the user has been allocated a channel object that is going to generate
4242 + * CDANs to another channel, then the qbman_swp_CDAN* functions will be
4243 + * necessary.
4244 + *
4245 + * CDAN-enabled channels only generate a single CDAN notification, after which
4246 + * they need to be reenabled before they'll generate another. The idea is
4247 + * that pull dequeuing will occur in reaction to the CDAN, followed by a
4248 + * reenable step. Each function generates a distinct command to hardware, so a
4249 + * combination function is provided if the user wishes to modify the "context"
4250 + * (which shows up in each CDAN message) each time they reenable, as a single
4251 + * command to hardware.
4252 + */
4253 +
4254 +/**
4255 + * qbman_swp_CDAN_set_context() - Set CDAN context
4256 + * @s: the software portal object
4257 + * @channelid: the channel index
4258 + * @ctx: the context to be set in CDAN
4259 + *
4260 + * Return 0 for success, or negative error code for failure.
4261 + */
4262 +static inline int qbman_swp_CDAN_set_context(struct qbman_swp *s, u16 channelid,
4263 + u64 ctx)
4264 +{
4265 + return qbman_swp_CDAN_set(s, channelid,
4266 + CODE_CDAN_WE_CTX,
4267 + 0, ctx);
4268 +}
4269 +
4270 +/**
4271 + * qbman_swp_CDAN_enable() - Enable CDAN for the channel
4272 + * @s: the software portal object
4273 + * @channelid: the index of the channel to generate CDAN
4274 + *
4275 + * Return 0 for success, or negative error code for failure.
4276 + */
4277 +static inline int qbman_swp_CDAN_enable(struct qbman_swp *s, u16 channelid)
4278 +{
4279 + return qbman_swp_CDAN_set(s, channelid,
4280 + CODE_CDAN_WE_EN,
4281 + 1, 0);
4282 +}
4283 +
4284 +/**
4285 + * qbman_swp_CDAN_disable() - disable CDAN for the channel
4286 + * @s: the software portal object
4287 + * @channelid: the index of the channel to generate CDAN
4288 + *
4289 + * Return 0 for success, or negative error code for failure.
4290 + */
4291 +static inline int qbman_swp_CDAN_disable(struct qbman_swp *s, u16 channelid)
4292 +{
4293 + return qbman_swp_CDAN_set(s, channelid,
4294 + CODE_CDAN_WE_EN,
4295 + 0, 0);
4296 +}
4297 +
4298 +/**
4299 + * qbman_swp_CDAN_set_context_enable() - Set CDAN contest and enable CDAN
4300 + * @s: the software portal object
4301 + * @channelid: the index of the channel to generate CDAN
4302 + * @ctx:i the context set in CDAN
4303 + *
4304 + * Return 0 for success, or negative error code for failure.
4305 + */
4306 +static inline int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s,
4307 + u16 channelid,
4308 + u64 ctx)
4309 +{
4310 + return qbman_swp_CDAN_set(s, channelid,
4311 + CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
4312 + 1, ctx);
4313 +}
4314 +
4315 +/* Wraps up submit + poll-for-result */
4316 +static inline void *qbman_swp_mc_complete(struct qbman_swp *swp, void *cmd,
4317 + u8 cmd_verb)
4318 +{
4319 + int loopvar = 1000;
4320 +
4321 + qbman_swp_mc_submit(swp, cmd, cmd_verb);
4322 +
4323 + do {
4324 + cmd = qbman_swp_mc_result(swp);
4325 + } while (!cmd && loopvar--);
4326 +
4327 + WARN_ON(!loopvar);
4328 +
4329 + return cmd;
4330 +}
4331 +
4332 +/* ------------ */
4333 +/* qb_attr_code */
4334 +/* ------------ */
4335 +
4336 +/* This struct locates a sub-field within a QBMan portal (CENA) cacheline which
4337 + * is either serving as a configuration command or a query result. The
4338 + * representation is inherently little-endian, as the indexing of the words is
4339 + * itself little-endian in nature and layerscape is little endian for anything
4340 + * that crosses a word boundary too (64-bit fields are the obvious examples).
4341 + */
4342 +struct qb_attr_code {
4343 + unsigned int word; /* which u32[] array member encodes the field */
4344 + unsigned int lsoffset; /* encoding offset from ls-bit */
4345 + unsigned int width; /* encoding width. (bool must be 1.) */
4346 +};
4347 +
4348 +/* Some pre-defined codes */
4349 +extern struct qb_attr_code code_generic_verb;
4350 +extern struct qb_attr_code code_generic_rslt;
4351 +
4352 +/* Macros to define codes */
4353 +#define QB_CODE(a, b, c) { a, b, c}
4354 +#define QB_CODE_NULL \
4355 + QB_CODE((unsigned int)-1, (unsigned int)-1, (unsigned int)-1)
4356 +
4357 +/* Rotate a code "ms", meaning that it moves from less-significant bytes to
4358 + * more-significant, from less-significant words to more-significant, etc. The
4359 + * "ls" version does the inverse, from more-significant towards
4360 + * less-significant.
4361 + */
4362 +static inline void qb_attr_code_rotate_ms(struct qb_attr_code *code,
4363 + unsigned int bits)
4364 +{
4365 + code->lsoffset += bits;
4366 + while (code->lsoffset > 31) {
4367 + code->word++;
4368 + code->lsoffset -= 32;
4369 + }
4370 +}
4371 +
4372 +static inline void qb_attr_code_rotate_ls(struct qb_attr_code *code,
4373 + unsigned int bits)
4374 +{
4375 + /* Don't be fooled, this trick should work because the types are
4376 + * unsigned. So the case that interests the while loop (the rotate has
4377 + * gone too far and the word count needs to compensate for it), is
4378 + * manifested when lsoffset is negative. But that equates to a really
4379 + * large unsigned value, starting with lots of "F"s. As such, we can
4380 + * continue adding 32 back to it until it wraps back round above zero,
4381 + * to a value of 31 or less...
4382 + */
4383 + code->lsoffset -= bits;
4384 + while (code->lsoffset > 31) {
4385 + code->word--;
4386 + code->lsoffset += 32;
4387 + }
4388 +}
4389 +
4390 +/* Implement a loop of code rotations until 'expr' evaluates to FALSE (0). */
4391 +#define qb_attr_code_for_ms(code, bits, expr) \
4392 + for (; expr; qb_attr_code_rotate_ms(code, bits))
4393 +#define qb_attr_code_for_ls(code, bits, expr) \
4394 + for (; expr; qb_attr_code_rotate_ls(code, bits))
4395 +
4396 +static inline void word_copy(void *d, const void *s, unsigned int cnt)
4397 +{
4398 + u32 *dd = d;
4399 + const u32 *ss = s;
4400 +
4401 + while (cnt--)
4402 + *(dd++) = *(ss++);
4403 +}
4404 +
4405 +/*
4406 + * Currently, the CENA support code expects each 32-bit word to be written in
4407 + * host order, and these are converted to hardware (little-endian) order on
4408 + * command submission. However, 64-bit quantities are must be written (and read)
4409 + * as two 32-bit words with the least-significant word first, irrespective of
4410 + * host endianness.
4411 + */
4412 +static inline void u64_to_le32_copy(void *d, const u64 *s,
4413 + unsigned int cnt)
4414 +{
4415 + u32 *dd = d;
4416 + const u32 *ss = (const u32 *)s;
4417 +
4418 + while (cnt--) {
4419 + /*
4420 + * TBD: the toolchain was choking on the use of 64-bit types up
4421 + * until recently so this works entirely with 32-bit variables.
4422 + * When 64-bit types become usable again, investigate better
4423 + * ways of doing this.
4424 + */
4425 +#if defined(__BIG_ENDIAN)
4426 + *(dd++) = ss[1];
4427 + *(dd++) = ss[0];
4428 + ss += 2;
4429 +#else
4430 + *(dd++) = *(ss++);
4431 + *(dd++) = *(ss++);
4432 +#endif
4433 + }
4434 +}
4435 +
4436 +static inline void u64_from_le32_copy(u64 *d, const void *s,
4437 + unsigned int cnt)
4438 +{
4439 + const u32 *ss = s;
4440 + u32 *dd = (u32 *)d;
4441 +
4442 + while (cnt--) {
4443 +#if defined(__BIG_ENDIAN)
4444 + dd[1] = *(ss++);
4445 + dd[0] = *(ss++);
4446 + dd += 2;
4447 +#else
4448 + *(dd++) = *(ss++);
4449 + *(dd++) = *(ss++);
4450 +#endif
4451 + }
4452 +}
4453 +
4454 +/* decode a field from a cacheline */
4455 +static inline u32 qb_attr_code_decode(const struct qb_attr_code *code,
4456 + const u32 *cacheline)
4457 +{
4458 + return d32_u32(code->lsoffset, code->width, cacheline[code->word]);
4459 +}
4460 +
4461 +static inline u64 qb_attr_code_decode_64(const struct qb_attr_code *code,
4462 + const u64 *cacheline)
4463 +{
4464 + u64 res;
4465 +
4466 + u64_from_le32_copy(&res, &cacheline[code->word / 2], 1);
4467 + return res;
4468 +}
4469 +
4470 +/* encode a field to a cacheline */
4471 +static inline void qb_attr_code_encode(const struct qb_attr_code *code,
4472 + u32 *cacheline, u32 val)
4473 +{
4474 + cacheline[code->word] =
4475 + r32_u32(code->lsoffset, code->width, cacheline[code->word])
4476 + | e32_u32(code->lsoffset, code->width, val);
4477 +}
4478 +
4479 +static inline void qb_attr_code_encode_64(const struct qb_attr_code *code,
4480 + u64 *cacheline, u64 val)
4481 +{
4482 + u64_to_le32_copy(&cacheline[code->word / 2], &val, 1);
4483 +}
4484 +
4485 +/* Small-width signed values (two's-complement) will decode into medium-width
4486 + * positives. (Eg. for an 8-bit signed field, which stores values from -128 to
4487 + * +127, a setting of -7 would appear to decode to the 32-bit unsigned value
4488 + * 249. Likewise -120 would decode as 136.) This function allows the caller to
4489 + * "re-sign" such fields to 32-bit signed. (Eg. -7, which was 249 with an 8-bit
4490 + * encoding, will become 0xfffffff9 if you cast the return value to u32).
4491 + */
4492 +static inline int32_t qb_attr_code_makesigned(const struct qb_attr_code *code,
4493 + u32 val)
4494 +{
4495 + WARN_ON(val >= (1 << code->width));
4496 + /* If the high bit was set, it was encoding a negative */
4497 + if (val >= (1 << (code->width - 1)))
4498 + return (int32_t)0 - (int32_t)(((u32)1 << code->width) -
4499 + val);
4500 + /* Otherwise, it was encoding a positive */
4501 + return (int32_t)val;
4502 +}
4503 +
4504 +/* ---------------------- */
4505 +/* Descriptors/cachelines */
4506 +/* ---------------------- */
4507 +
4508 +/* To avoid needless dynamic allocation, the driver API often gives the caller
4509 + * a "descriptor" type that the caller can instantiate however they like.
4510 + * Ultimately though, it is just a cacheline of binary storage (or something
4511 + * smaller when it is known that the descriptor doesn't need all 64 bytes) for
4512 + * holding pre-formatted pieces of hardware commands. The performance-critical
4513 + * code can then copy these descriptors directly into hardware command
4514 + * registers more efficiently than trying to construct/format commands
4515 + * on-the-fly. The API user sees the descriptor as an array of 32-bit words in
4516 + * order for the compiler to know its size, but the internal details are not
4517 + * exposed. The following macro is used within the driver for converting *any*
4518 + * descriptor pointer to a usable array pointer. The use of a macro (instead of
4519 + * an inline) is necessary to work with different descriptor types and to work
4520 + * correctly with const and non-const inputs (and similarly-qualified outputs).
4521 + */
4522 +#define qb_cl(d) (&(d)->dont_manipulate_directly[0])
4523 +
4524 +#endif /* __FSL_QBMAN_PORTAL_H */
4525 --- /dev/null
4526 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.c
4527 @@ -0,0 +1,853 @@
4528 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
4529 + *
4530 + * Redistribution and use in source and binary forms, with or without
4531 + * modification, are permitted provided that the following conditions are met:
4532 + * * Redistributions of source code must retain the above copyright
4533 + * notice, this list of conditions and the following disclaimer.
4534 + * * Redistributions in binary form must reproduce the above copyright
4535 + * notice, this list of conditions and the following disclaimer in the
4536 + * documentation and/or other materials provided with the distribution.
4537 + * * Neither the name of Freescale Semiconductor nor the
4538 + * names of its contributors may be used to endorse or promote products
4539 + * derived from this software without specific prior written permission.
4540 + *
4541 + *
4542 + * ALTERNATIVELY, this software may be distributed under the terms of the
4543 + * GNU General Public License ("GPL") as published by the Free Software
4544 + * Foundation, either version 2 of that License or (at your option) any
4545 + * later version.
4546 + *
4547 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
4548 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
4549 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
4550 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
4551 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
4552 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
4553 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
4554 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4555 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
4556 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4557 + */
4558 +
4559 +#include <linux/errno.h>
4560 +
4561 +#include "../../include/dpaa2-global.h"
4562 +#include "qbman-portal.h"
4563 +#include "qbman_debug.h"
4564 +
4565 +/* QBMan portal management command code */
4566 +#define QBMAN_BP_QUERY 0x32
4567 +#define QBMAN_FQ_QUERY 0x44
4568 +#define QBMAN_FQ_QUERY_NP 0x45
4569 +#define QBMAN_CGR_QUERY 0x51
4570 +#define QBMAN_WRED_QUERY 0x54
4571 +#define QBMAN_CGR_STAT_QUERY 0x55
4572 +#define QBMAN_CGR_STAT_QUERY_CLR 0x56
4573 +
4574 +enum qbman_attr_usage_e {
4575 + qbman_attr_usage_fq,
4576 + qbman_attr_usage_bpool,
4577 + qbman_attr_usage_cgr,
4578 +};
4579 +
4580 +struct int_qbman_attr {
4581 + u32 words[32];
4582 + enum qbman_attr_usage_e usage;
4583 +};
4584 +
4585 +#define attr_type_set(a, e) \
4586 +{ \
4587 + struct qbman_attr *__attr = a; \
4588 + enum qbman_attr_usage_e __usage = e; \
4589 + ((struct int_qbman_attr *)__attr)->usage = __usage; \
4590 +}
4591 +
4592 +#define ATTR32(d) (&(d)->dont_manipulate_directly[0])
4593 +#define ATTR32_1(d) (&(d)->dont_manipulate_directly[16])
4594 +
4595 +static struct qb_attr_code code_bp_bpid = QB_CODE(0, 16, 16);
4596 +static struct qb_attr_code code_bp_bdi = QB_CODE(1, 16, 1);
4597 +static struct qb_attr_code code_bp_va = QB_CODE(1, 17, 1);
4598 +static struct qb_attr_code code_bp_wae = QB_CODE(1, 18, 1);
4599 +static struct qb_attr_code code_bp_swdet = QB_CODE(4, 0, 16);
4600 +static struct qb_attr_code code_bp_swdxt = QB_CODE(4, 16, 16);
4601 +static struct qb_attr_code code_bp_hwdet = QB_CODE(5, 0, 16);
4602 +static struct qb_attr_code code_bp_hwdxt = QB_CODE(5, 16, 16);
4603 +static struct qb_attr_code code_bp_swset = QB_CODE(6, 0, 16);
4604 +static struct qb_attr_code code_bp_swsxt = QB_CODE(6, 16, 16);
4605 +static struct qb_attr_code code_bp_vbpid = QB_CODE(7, 0, 14);
4606 +static struct qb_attr_code code_bp_icid = QB_CODE(7, 16, 15);
4607 +static struct qb_attr_code code_bp_pl = QB_CODE(7, 31, 1);
4608 +static struct qb_attr_code code_bp_bpscn_addr_lo = QB_CODE(8, 0, 32);
4609 +static struct qb_attr_code code_bp_bpscn_addr_hi = QB_CODE(9, 0, 32);
4610 +static struct qb_attr_code code_bp_bpscn_ctx_lo = QB_CODE(10, 0, 32);
4611 +static struct qb_attr_code code_bp_bpscn_ctx_hi = QB_CODE(11, 0, 32);
4612 +static struct qb_attr_code code_bp_hw_targ = QB_CODE(12, 0, 16);
4613 +static struct qb_attr_code code_bp_state = QB_CODE(1, 24, 3);
4614 +static struct qb_attr_code code_bp_fill = QB_CODE(2, 0, 32);
4615 +static struct qb_attr_code code_bp_hdptr = QB_CODE(3, 0, 32);
4616 +static struct qb_attr_code code_bp_sdcnt = QB_CODE(13, 0, 8);
4617 +static struct qb_attr_code code_bp_hdcnt = QB_CODE(13, 1, 8);
4618 +static struct qb_attr_code code_bp_sscnt = QB_CODE(13, 2, 8);
4619 +
4620 +void qbman_bp_attr_clear(struct qbman_attr *a)
4621 +{
4622 + memset(a, 0, sizeof(*a));
4623 + attr_type_set(a, qbman_attr_usage_bpool);
4624 +}
4625 +
4626 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
4627 + struct qbman_attr *a)
4628 +{
4629 + u32 *p;
4630 + u32 verb, rslt;
4631 + u32 *attr = ATTR32(a);
4632 +
4633 + qbman_bp_attr_clear(a);
4634 +
4635 + /* Start the management command */
4636 + p = qbman_swp_mc_start(s);
4637 + if (!p)
4638 + return -EBUSY;
4639 +
4640 + /* Encode the caller-provided attributes */
4641 + qb_attr_code_encode(&code_bp_bpid, p, bpid);
4642 +
4643 + /* Complete the management command */
4644 + p = qbman_swp_mc_complete(s, p, QBMAN_BP_QUERY);
4645 +
4646 + /* Decode the outcome */
4647 + verb = qb_attr_code_decode(&code_generic_verb, p);
4648 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4649 + WARN_ON(verb != QBMAN_BP_QUERY);
4650 +
4651 + /* Determine success or failure */
4652 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4653 + pr_err("Query of BPID 0x%x failed, code=0x%02x\n", bpid, rslt);
4654 + return -EIO;
4655 + }
4656 +
4657 + /* For the query, word[0] of the result contains only the
4658 + * verb/rslt fields, so skip word[0].
4659 + */
4660 + word_copy(&attr[1], &p[1], 15);
4661 + return 0;
4662 +}
4663 +
4664 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae)
4665 +{
4666 + u32 *p = ATTR32(a);
4667 +
4668 + *bdi = !!qb_attr_code_decode(&code_bp_bdi, p);
4669 + *va = !!qb_attr_code_decode(&code_bp_va, p);
4670 + *wae = !!qb_attr_code_decode(&code_bp_wae, p);
4671 +}
4672 +
4673 +static u32 qbman_bp_thresh_to_value(u32 val)
4674 +{
4675 + return (val & 0xff) << ((val & 0xf00) >> 8);
4676 +}
4677 +
4678 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet)
4679 +{
4680 + u32 *p = ATTR32(a);
4681 +
4682 + *swdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdet,
4683 + p));
4684 +}
4685 +
4686 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt)
4687 +{
4688 + u32 *p = ATTR32(a);
4689 +
4690 + *swdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swdxt,
4691 + p));
4692 +}
4693 +
4694 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet)
4695 +{
4696 + u32 *p = ATTR32(a);
4697 +
4698 + *hwdet = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdet,
4699 + p));
4700 +}
4701 +
4702 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt)
4703 +{
4704 + u32 *p = ATTR32(a);
4705 +
4706 + *hwdxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_hwdxt,
4707 + p));
4708 +}
4709 +
4710 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset)
4711 +{
4712 + u32 *p = ATTR32(a);
4713 +
4714 + *swset = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swset,
4715 + p));
4716 +}
4717 +
4718 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt)
4719 +{
4720 + u32 *p = ATTR32(a);
4721 +
4722 + *swsxt = qbman_bp_thresh_to_value(qb_attr_code_decode(&code_bp_swsxt,
4723 + p));
4724 +}
4725 +
4726 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid)
4727 +{
4728 + u32 *p = ATTR32(a);
4729 +
4730 + *vbpid = qb_attr_code_decode(&code_bp_vbpid, p);
4731 +}
4732 +
4733 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl)
4734 +{
4735 + u32 *p = ATTR32(a);
4736 +
4737 + *icid = qb_attr_code_decode(&code_bp_icid, p);
4738 + *pl = !!qb_attr_code_decode(&code_bp_pl, p);
4739 +}
4740 +
4741 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr)
4742 +{
4743 + u32 *p = ATTR32(a);
4744 +
4745 + *bpscn_addr = ((u64)qb_attr_code_decode(&code_bp_bpscn_addr_hi,
4746 + p) << 32) |
4747 + (u64)qb_attr_code_decode(&code_bp_bpscn_addr_lo,
4748 + p);
4749 +}
4750 +
4751 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx)
4752 +{
4753 + u32 *p = ATTR32(a);
4754 +
4755 + *bpscn_ctx = ((u64)qb_attr_code_decode(&code_bp_bpscn_ctx_hi, p)
4756 + << 32) |
4757 + (u64)qb_attr_code_decode(&code_bp_bpscn_ctx_lo,
4758 + p);
4759 +}
4760 +
4761 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ)
4762 +{
4763 + u32 *p = ATTR32(a);
4764 +
4765 + *hw_targ = qb_attr_code_decode(&code_bp_hw_targ, p);
4766 +}
4767 +
4768 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a)
4769 +{
4770 + u32 *p = ATTR32(a);
4771 +
4772 + return !(int)(qb_attr_code_decode(&code_bp_state, p) & 0x1);
4773 +}
4774 +
4775 +int qbman_bp_info_is_depleted(struct qbman_attr *a)
4776 +{
4777 + u32 *p = ATTR32(a);
4778 +
4779 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x2);
4780 +}
4781 +
4782 +int qbman_bp_info_is_surplus(struct qbman_attr *a)
4783 +{
4784 + u32 *p = ATTR32(a);
4785 +
4786 + return (int)(qb_attr_code_decode(&code_bp_state, p) & 0x4);
4787 +}
4788 +
4789 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a)
4790 +{
4791 + u32 *p = ATTR32(a);
4792 +
4793 + return qb_attr_code_decode(&code_bp_fill, p);
4794 +}
4795 +
4796 +u32 qbman_bp_info_hdptr(struct qbman_attr *a)
4797 +{
4798 + u32 *p = ATTR32(a);
4799 +
4800 + return qb_attr_code_decode(&code_bp_hdptr, p);
4801 +}
4802 +
4803 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a)
4804 +{
4805 + u32 *p = ATTR32(a);
4806 +
4807 + return qb_attr_code_decode(&code_bp_sdcnt, p);
4808 +}
4809 +
4810 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a)
4811 +{
4812 + u32 *p = ATTR32(a);
4813 +
4814 + return qb_attr_code_decode(&code_bp_hdcnt, p);
4815 +}
4816 +
4817 +u32 qbman_bp_info_sscnt(struct qbman_attr *a)
4818 +{
4819 + u32 *p = ATTR32(a);
4820 +
4821 + return qb_attr_code_decode(&code_bp_sscnt, p);
4822 +}
4823 +
4824 +static struct qb_attr_code code_fq_fqid = QB_CODE(1, 0, 24);
4825 +static struct qb_attr_code code_fq_cgrid = QB_CODE(2, 16, 16);
4826 +static struct qb_attr_code code_fq_destwq = QB_CODE(3, 0, 15);
4827 +static struct qb_attr_code code_fq_fqctrl = QB_CODE(3, 24, 8);
4828 +static struct qb_attr_code code_fq_icscred = QB_CODE(4, 0, 15);
4829 +static struct qb_attr_code code_fq_tdthresh = QB_CODE(4, 16, 13);
4830 +static struct qb_attr_code code_fq_oa_len = QB_CODE(5, 0, 12);
4831 +static struct qb_attr_code code_fq_oa_ics = QB_CODE(5, 14, 1);
4832 +static struct qb_attr_code code_fq_oa_cgr = QB_CODE(5, 15, 1);
4833 +static struct qb_attr_code code_fq_mctl_bdi = QB_CODE(5, 24, 1);
4834 +static struct qb_attr_code code_fq_mctl_ff = QB_CODE(5, 25, 1);
4835 +static struct qb_attr_code code_fq_mctl_va = QB_CODE(5, 26, 1);
4836 +static struct qb_attr_code code_fq_mctl_ps = QB_CODE(5, 27, 1);
4837 +static struct qb_attr_code code_fq_ctx_lower32 = QB_CODE(6, 0, 32);
4838 +static struct qb_attr_code code_fq_ctx_upper32 = QB_CODE(7, 0, 32);
4839 +static struct qb_attr_code code_fq_icid = QB_CODE(8, 0, 15);
4840 +static struct qb_attr_code code_fq_pl = QB_CODE(8, 15, 1);
4841 +static struct qb_attr_code code_fq_vfqid = QB_CODE(9, 0, 24);
4842 +static struct qb_attr_code code_fq_erfqid = QB_CODE(10, 0, 24);
4843 +
4844 +void qbman_fq_attr_clear(struct qbman_attr *a)
4845 +{
4846 + memset(a, 0, sizeof(*a));
4847 + attr_type_set(a, qbman_attr_usage_fq);
4848 +}
4849 +
4850 +/* FQ query function for programmable fields */
4851 +int qbman_fq_query(struct qbman_swp *s, u32 fqid, struct qbman_attr *desc)
4852 +{
4853 + u32 *p;
4854 + u32 verb, rslt;
4855 + u32 *d = ATTR32(desc);
4856 +
4857 + qbman_fq_attr_clear(desc);
4858 +
4859 + p = qbman_swp_mc_start(s);
4860 + if (!p)
4861 + return -EBUSY;
4862 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
4863 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY);
4864 +
4865 + /* Decode the outcome */
4866 + verb = qb_attr_code_decode(&code_generic_verb, p);
4867 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
4868 + WARN_ON(verb != QBMAN_FQ_QUERY);
4869 +
4870 + /* Determine success or failure */
4871 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
4872 + pr_err("Query of FQID 0x%x failed, code=0x%02x\n",
4873 + fqid, rslt);
4874 + return -EIO;
4875 + }
4876 + /*
4877 + * For the configure, word[0] of the command contains only the WE-mask.
4878 + * For the query, word[0] of the result contains only the verb/rslt
4879 + * fields. Skip word[0] in the latter case.
4880 + */
4881 + word_copy(&d[1], &p[1], 15);
4882 + return 0;
4883 +}
4884 +
4885 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl)
4886 +{
4887 + u32 *p = ATTR32(d);
4888 +
4889 + *fqctrl = qb_attr_code_decode(&code_fq_fqctrl, p);
4890 +}
4891 +
4892 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid)
4893 +{
4894 + u32 *p = ATTR32(d);
4895 +
4896 + *cgrid = qb_attr_code_decode(&code_fq_cgrid, p);
4897 +}
4898 +
4899 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq)
4900 +{
4901 + u32 *p = ATTR32(d);
4902 +
4903 + *destwq = qb_attr_code_decode(&code_fq_destwq, p);
4904 +}
4905 +
4906 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred)
4907 +{
4908 + u32 *p = ATTR32(d);
4909 +
4910 + *icscred = qb_attr_code_decode(&code_fq_icscred, p);
4911 +}
4912 +
4913 +static struct qb_attr_code code_tdthresh_exp = QB_CODE(0, 0, 5);
4914 +static struct qb_attr_code code_tdthresh_mant = QB_CODE(0, 5, 8);
4915 +static u32 qbman_thresh_to_value(u32 val)
4916 +{
4917 + u32 m, e;
4918 +
4919 + m = qb_attr_code_decode(&code_tdthresh_mant, &val);
4920 + e = qb_attr_code_decode(&code_tdthresh_exp, &val);
4921 + return m << e;
4922 +}
4923 +
4924 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh)
4925 +{
4926 + u32 *p = ATTR32(d);
4927 +
4928 + *tdthresh = qbman_thresh_to_value(qb_attr_code_decode(&code_fq_tdthresh,
4929 + p));
4930 +}
4931 +
4932 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
4933 + int *oa_ics, int *oa_cgr, int32_t *oa_len)
4934 +{
4935 + u32 *p = ATTR32(d);
4936 +
4937 + *oa_ics = !!qb_attr_code_decode(&code_fq_oa_ics, p);
4938 + *oa_cgr = !!qb_attr_code_decode(&code_fq_oa_cgr, p);
4939 + *oa_len = qb_attr_code_makesigned(&code_fq_oa_len,
4940 + qb_attr_code_decode(&code_fq_oa_len, p));
4941 +}
4942 +
4943 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
4944 + int *bdi, int *ff, int *va, int *ps)
4945 +{
4946 + u32 *p = ATTR32(d);
4947 +
4948 + *bdi = !!qb_attr_code_decode(&code_fq_mctl_bdi, p);
4949 + *ff = !!qb_attr_code_decode(&code_fq_mctl_ff, p);
4950 + *va = !!qb_attr_code_decode(&code_fq_mctl_va, p);
4951 + *ps = !!qb_attr_code_decode(&code_fq_mctl_ps, p);
4952 +}
4953 +
4954 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo)
4955 +{
4956 + u32 *p = ATTR32(d);
4957 +
4958 + *hi = qb_attr_code_decode(&code_fq_ctx_upper32, p);
4959 + *lo = qb_attr_code_decode(&code_fq_ctx_lower32, p);
4960 +}
4961 +
4962 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl)
4963 +{
4964 + u32 *p = ATTR32(d);
4965 +
4966 + *icid = qb_attr_code_decode(&code_fq_icid, p);
4967 + *pl = !!qb_attr_code_decode(&code_fq_pl, p);
4968 +}
4969 +
4970 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid)
4971 +{
4972 + u32 *p = ATTR32(d);
4973 +
4974 + *vfqid = qb_attr_code_decode(&code_fq_vfqid, p);
4975 +}
4976 +
4977 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid)
4978 +{
4979 + u32 *p = ATTR32(d);
4980 +
4981 + *erfqid = qb_attr_code_decode(&code_fq_erfqid, p);
4982 +}
4983 +
4984 +/* Query FQ Non-Programmalbe Fields */
4985 +static struct qb_attr_code code_fq_np_state = QB_CODE(0, 16, 3);
4986 +static struct qb_attr_code code_fq_np_fe = QB_CODE(0, 19, 1);
4987 +static struct qb_attr_code code_fq_np_x = QB_CODE(0, 20, 1);
4988 +static struct qb_attr_code code_fq_np_r = QB_CODE(0, 21, 1);
4989 +static struct qb_attr_code code_fq_np_oe = QB_CODE(0, 22, 1);
4990 +static struct qb_attr_code code_fq_np_frm_cnt = QB_CODE(6, 0, 24);
4991 +static struct qb_attr_code code_fq_np_byte_cnt = QB_CODE(7, 0, 32);
4992 +
4993 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
4994 + struct qbman_attr *state)
4995 +{
4996 + u32 *p;
4997 + u32 verb, rslt;
4998 + u32 *d = ATTR32(state);
4999 +
5000 + qbman_fq_attr_clear(state);
5001 +
5002 + p = qbman_swp_mc_start(s);
5003 + if (!p)
5004 + return -EBUSY;
5005 + qb_attr_code_encode(&code_fq_fqid, p, fqid);
5006 + p = qbman_swp_mc_complete(s, p, QBMAN_FQ_QUERY_NP);
5007 +
5008 + /* Decode the outcome */
5009 + verb = qb_attr_code_decode(&code_generic_verb, p);
5010 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5011 + WARN_ON(verb != QBMAN_FQ_QUERY_NP);
5012 +
5013 + /* Determine success or failure */
5014 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5015 + pr_err("Query NP fields of FQID 0x%x failed, code=0x%02x\n",
5016 + fqid, rslt);
5017 + return -EIO;
5018 + }
5019 + word_copy(&d[0], &p[0], 16);
5020 + return 0;
5021 +}
5022 +
5023 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state)
5024 +{
5025 + const u32 *p = ATTR32(state);
5026 +
5027 + return qb_attr_code_decode(&code_fq_np_state, p);
5028 +}
5029 +
5030 +int qbman_fq_state_force_eligible(const struct qbman_attr *state)
5031 +{
5032 + const u32 *p = ATTR32(state);
5033 +
5034 + return !!qb_attr_code_decode(&code_fq_np_fe, p);
5035 +}
5036 +
5037 +int qbman_fq_state_xoff(const struct qbman_attr *state)
5038 +{
5039 + const u32 *p = ATTR32(state);
5040 +
5041 + return !!qb_attr_code_decode(&code_fq_np_x, p);
5042 +}
5043 +
5044 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state)
5045 +{
5046 + const u32 *p = ATTR32(state);
5047 +
5048 + return !!qb_attr_code_decode(&code_fq_np_r, p);
5049 +}
5050 +
5051 +int qbman_fq_state_overflow_error(const struct qbman_attr *state)
5052 +{
5053 + const u32 *p = ATTR32(state);
5054 +
5055 + return !!qb_attr_code_decode(&code_fq_np_oe, p);
5056 +}
5057 +
5058 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state)
5059 +{
5060 + const u32 *p = ATTR32(state);
5061 +
5062 + return qb_attr_code_decode(&code_fq_np_frm_cnt, p);
5063 +}
5064 +
5065 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state)
5066 +{
5067 + const u32 *p = ATTR32(state);
5068 +
5069 + return qb_attr_code_decode(&code_fq_np_byte_cnt, p);
5070 +}
5071 +
5072 +/* Query CGR */
5073 +static struct qb_attr_code code_cgr_cgid = QB_CODE(0, 16, 16);
5074 +static struct qb_attr_code code_cgr_cscn_wq_en_enter = QB_CODE(2, 0, 1);
5075 +static struct qb_attr_code code_cgr_cscn_wq_en_exit = QB_CODE(2, 1, 1);
5076 +static struct qb_attr_code code_cgr_cscn_wq_icd = QB_CODE(2, 2, 1);
5077 +static struct qb_attr_code code_cgr_mode = QB_CODE(3, 16, 2);
5078 +static struct qb_attr_code code_cgr_rej_cnt_mode = QB_CODE(3, 18, 1);
5079 +static struct qb_attr_code code_cgr_cscn_bdi = QB_CODE(3, 19, 1);
5080 +static struct qb_attr_code code_cgr_cscn_wr_en_enter = QB_CODE(3, 24, 1);
5081 +static struct qb_attr_code code_cgr_cscn_wr_en_exit = QB_CODE(3, 25, 1);
5082 +static struct qb_attr_code code_cgr_cg_wr_ae = QB_CODE(3, 26, 1);
5083 +static struct qb_attr_code code_cgr_cscn_dcp_en = QB_CODE(3, 27, 1);
5084 +static struct qb_attr_code code_cgr_cg_wr_va = QB_CODE(3, 28, 1);
5085 +static struct qb_attr_code code_cgr_i_cnt_wr_en = QB_CODE(4, 0, 1);
5086 +static struct qb_attr_code code_cgr_i_cnt_wr_bnd = QB_CODE(4, 1, 5);
5087 +static struct qb_attr_code code_cgr_td_en = QB_CODE(4, 8, 1);
5088 +static struct qb_attr_code code_cgr_cs_thres = QB_CODE(4, 16, 13);
5089 +static struct qb_attr_code code_cgr_cs_thres_x = QB_CODE(5, 0, 13);
5090 +static struct qb_attr_code code_cgr_td_thres = QB_CODE(5, 16, 13);
5091 +static struct qb_attr_code code_cgr_cscn_tdcp = QB_CODE(6, 0, 16);
5092 +static struct qb_attr_code code_cgr_cscn_wqid = QB_CODE(6, 16, 16);
5093 +static struct qb_attr_code code_cgr_cscn_vcgid = QB_CODE(7, 0, 16);
5094 +static struct qb_attr_code code_cgr_cg_icid = QB_CODE(7, 16, 15);
5095 +static struct qb_attr_code code_cgr_cg_pl = QB_CODE(7, 31, 1);
5096 +static struct qb_attr_code code_cgr_cg_wr_addr_lo = QB_CODE(8, 0, 32);
5097 +static struct qb_attr_code code_cgr_cg_wr_addr_hi = QB_CODE(9, 0, 32);
5098 +static struct qb_attr_code code_cgr_cscn_ctx_lo = QB_CODE(10, 0, 32);
5099 +static struct qb_attr_code code_cgr_cscn_ctx_hi = QB_CODE(11, 0, 32);
5100 +
5101 +void qbman_cgr_attr_clear(struct qbman_attr *a)
5102 +{
5103 + memset(a, 0, sizeof(*a));
5104 + attr_type_set(a, qbman_attr_usage_cgr);
5105 +}
5106 +
5107 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid, struct qbman_attr *attr)
5108 +{
5109 + u32 *p;
5110 + u32 verb, rslt;
5111 + u32 *d[2];
5112 + int i;
5113 + u32 query_verb;
5114 +
5115 + d[0] = ATTR32(attr);
5116 + d[1] = ATTR32_1(attr);
5117 +
5118 + qbman_cgr_attr_clear(attr);
5119 +
5120 + for (i = 0; i < 2; i++) {
5121 + p = qbman_swp_mc_start(s);
5122 + if (!p)
5123 + return -EBUSY;
5124 + query_verb = i ? QBMAN_WRED_QUERY : QBMAN_CGR_QUERY;
5125 +
5126 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
5127 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
5128 +
5129 + /* Decode the outcome */
5130 + verb = qb_attr_code_decode(&code_generic_verb, p);
5131 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5132 + WARN_ON(verb != query_verb);
5133 +
5134 + /* Determine success or failure */
5135 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5136 + pr_err("Query CGID 0x%x failed,", cgid);
5137 + pr_err(" verb=0x%02x, code=0x%02x\n", verb, rslt);
5138 + return -EIO;
5139 + }
5140 + /* For the configure, word[0] of the command contains only the
5141 + * verb/cgid. For the query, word[0] of the result contains
5142 + * only the verb/rslt fields. Skip word[0] in the latter case.
5143 + */
5144 + word_copy(&d[i][1], &p[1], 15);
5145 + }
5146 + return 0;
5147 +}
5148 +
5149 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5150 + int *cscn_wq_en_exit, int *cscn_wq_icd)
5151 + {
5152 + u32 *p = ATTR32(d);
5153 + *cscn_wq_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_enter,
5154 + p);
5155 + *cscn_wq_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wq_en_exit, p);
5156 + *cscn_wq_icd = !!qb_attr_code_decode(&code_cgr_cscn_wq_icd, p);
5157 +}
5158 +
5159 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5160 + int *rej_cnt_mode, int *cscn_bdi)
5161 +{
5162 + u32 *p = ATTR32(d);
5163 + *mode = qb_attr_code_decode(&code_cgr_mode, p);
5164 + *rej_cnt_mode = !!qb_attr_code_decode(&code_cgr_rej_cnt_mode, p);
5165 + *cscn_bdi = !!qb_attr_code_decode(&code_cgr_cscn_bdi, p);
5166 +}
5167 +
5168 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5169 + int *cscn_wr_en_exit, int *cg_wr_ae,
5170 + int *cscn_dcp_en, int *cg_wr_va)
5171 +{
5172 + u32 *p = ATTR32(d);
5173 + *cscn_wr_en_enter = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_enter,
5174 + p);
5175 + *cscn_wr_en_exit = !!qb_attr_code_decode(&code_cgr_cscn_wr_en_exit, p);
5176 + *cg_wr_ae = !!qb_attr_code_decode(&code_cgr_cg_wr_ae, p);
5177 + *cscn_dcp_en = !!qb_attr_code_decode(&code_cgr_cscn_dcp_en, p);
5178 + *cg_wr_va = !!qb_attr_code_decode(&code_cgr_cg_wr_va, p);
5179 +}
5180 +
5181 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5182 + u32 *i_cnt_wr_bnd)
5183 +{
5184 + u32 *p = ATTR32(d);
5185 + *i_cnt_wr_en = !!qb_attr_code_decode(&code_cgr_i_cnt_wr_en, p);
5186 + *i_cnt_wr_bnd = qb_attr_code_decode(&code_cgr_i_cnt_wr_bnd, p);
5187 +}
5188 +
5189 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en)
5190 +{
5191 + u32 *p = ATTR32(d);
5192 + *td_en = !!qb_attr_code_decode(&code_cgr_td_en, p);
5193 +}
5194 +
5195 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres)
5196 +{
5197 + u32 *p = ATTR32(d);
5198 + *cs_thres = qbman_thresh_to_value(qb_attr_code_decode(
5199 + &code_cgr_cs_thres, p));
5200 +}
5201 +
5202 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5203 + u32 *cs_thres_x)
5204 +{
5205 + u32 *p = ATTR32(d);
5206 + *cs_thres_x = qbman_thresh_to_value(qb_attr_code_decode(
5207 + &code_cgr_cs_thres_x, p));
5208 +}
5209 +
5210 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres)
5211 +{
5212 + u32 *p = ATTR32(d);
5213 + *td_thres = qbman_thresh_to_value(qb_attr_code_decode(
5214 + &code_cgr_td_thres, p));
5215 +}
5216 +
5217 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp)
5218 +{
5219 + u32 *p = ATTR32(d);
5220 + *cscn_tdcp = qb_attr_code_decode(&code_cgr_cscn_tdcp, p);
5221 +}
5222 +
5223 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid)
5224 +{
5225 + u32 *p = ATTR32(d);
5226 + *cscn_wqid = qb_attr_code_decode(&code_cgr_cscn_wqid, p);
5227 +}
5228 +
5229 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5230 + u32 *cscn_vcgid)
5231 +{
5232 + u32 *p = ATTR32(d);
5233 + *cscn_vcgid = qb_attr_code_decode(&code_cgr_cscn_vcgid, p);
5234 +}
5235 +
5236 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5237 + int *pl)
5238 +{
5239 + u32 *p = ATTR32(d);
5240 + *icid = qb_attr_code_decode(&code_cgr_cg_icid, p);
5241 + *pl = !!qb_attr_code_decode(&code_cgr_cg_pl, p);
5242 +}
5243 +
5244 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5245 + u64 *cg_wr_addr)
5246 +{
5247 + u32 *p = ATTR32(d);
5248 + *cg_wr_addr = ((u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_hi,
5249 + p) << 32) |
5250 + (u64)qb_attr_code_decode(&code_cgr_cg_wr_addr_lo,
5251 + p);
5252 +}
5253 +
5254 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx)
5255 +{
5256 + u32 *p = ATTR32(d);
5257 + *cscn_ctx = ((u64)qb_attr_code_decode(&code_cgr_cscn_ctx_hi, p)
5258 + << 32) |
5259 + (u64)qb_attr_code_decode(&code_cgr_cscn_ctx_lo, p);
5260 +}
5261 +
5262 +#define WRED_EDP_WORD(n) (18 + (n) / 4)
5263 +#define WRED_EDP_OFFSET(n) (8 * ((n) % 4))
5264 +#define WRED_PARM_DP_WORD(n) ((n) + 20)
5265 +#define WRED_WE_EDP(n) (16 + (n) * 2)
5266 +#define WRED_WE_PARM_DP(n) (17 + (n) * 2)
5267 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5268 + int *edp)
5269 +{
5270 + u32 *p = ATTR32(d);
5271 + struct qb_attr_code code_wred_edp = QB_CODE(WRED_EDP_WORD(idx),
5272 + WRED_EDP_OFFSET(idx), 8);
5273 + *edp = (int)qb_attr_code_decode(&code_wred_edp, p);
5274 +}
5275 +
5276 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5277 + u64 *maxth, u8 *maxp)
5278 +{
5279 + u8 ma, mn, step_i, step_s, pn;
5280 +
5281 + ma = (u8)(dp >> 24);
5282 + mn = (u8)(dp >> 19) & 0x1f;
5283 + step_i = (u8)(dp >> 11);
5284 + step_s = (u8)(dp >> 6) & 0x1f;
5285 + pn = (u8)dp & 0x3f;
5286 +
5287 + *maxp = ((pn << 2) * 100) / 256;
5288 +
5289 + if (mn == 0)
5290 + *maxth = ma;
5291 + else
5292 + *maxth = ((ma + 256) * (1 << (mn - 1)));
5293 +
5294 + if (step_s == 0)
5295 + *minth = *maxth - step_i;
5296 + else
5297 + *minth = *maxth - (256 + step_i) * (1 << (step_s - 1));
5298 +}
5299 +
5300 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5301 + u32 *dp)
5302 +{
5303 + u32 *p = ATTR32(d);
5304 + struct qb_attr_code code_wred_parm_dp = QB_CODE(WRED_PARM_DP_WORD(idx),
5305 + 0, 8);
5306 + *dp = qb_attr_code_decode(&code_wred_parm_dp, p);
5307 +}
5308 +
5309 +/* Query CGR/CCGR/CQ statistics */
5310 +static struct qb_attr_code code_cgr_stat_ct = QB_CODE(4, 0, 32);
5311 +static struct qb_attr_code code_cgr_stat_frame_cnt_lo = QB_CODE(4, 0, 32);
5312 +static struct qb_attr_code code_cgr_stat_frame_cnt_hi = QB_CODE(5, 0, 8);
5313 +static struct qb_attr_code code_cgr_stat_byte_cnt_lo = QB_CODE(6, 0, 32);
5314 +static struct qb_attr_code code_cgr_stat_byte_cnt_hi = QB_CODE(7, 0, 16);
5315 +static int qbman_cgr_statistics_query(struct qbman_swp *s, u32 cgid,
5316 + int clear, u32 command_type,
5317 + u64 *frame_cnt, u64 *byte_cnt)
5318 +{
5319 + u32 *p;
5320 + u32 verb, rslt;
5321 + u32 query_verb;
5322 + u32 hi, lo;
5323 +
5324 + p = qbman_swp_mc_start(s);
5325 + if (!p)
5326 + return -EBUSY;
5327 +
5328 + qb_attr_code_encode(&code_cgr_cgid, p, cgid);
5329 + if (command_type < 2)
5330 + qb_attr_code_encode(&code_cgr_stat_ct, p, command_type);
5331 + query_verb = clear ?
5332 + QBMAN_CGR_STAT_QUERY_CLR : QBMAN_CGR_STAT_QUERY;
5333 + p = qbman_swp_mc_complete(s, p, p[0] | query_verb);
5334 +
5335 + /* Decode the outcome */
5336 + verb = qb_attr_code_decode(&code_generic_verb, p);
5337 + rslt = qb_attr_code_decode(&code_generic_rslt, p);
5338 + WARN_ON(verb != query_verb);
5339 +
5340 + /* Determine success or failure */
5341 + if (unlikely(rslt != QBMAN_MC_RSLT_OK)) {
5342 + pr_err("Query statistics of CGID 0x%x failed,", cgid);
5343 + pr_err(" verb=0x%02x code=0x%02x\n", verb, rslt);
5344 + return -EIO;
5345 + }
5346 +
5347 + if (*frame_cnt) {
5348 + hi = qb_attr_code_decode(&code_cgr_stat_frame_cnt_hi, p);
5349 + lo = qb_attr_code_decode(&code_cgr_stat_frame_cnt_lo, p);
5350 + *frame_cnt = ((u64)hi << 32) | (u64)lo;
5351 + }
5352 + if (*byte_cnt) {
5353 + hi = qb_attr_code_decode(&code_cgr_stat_byte_cnt_hi, p);
5354 + lo = qb_attr_code_decode(&code_cgr_stat_byte_cnt_lo, p);
5355 + *byte_cnt = ((u64)hi << 32) | (u64)lo;
5356 + }
5357 +
5358 + return 0;
5359 +}
5360 +
5361 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5362 + u64 *frame_cnt, u64 *byte_cnt)
5363 +{
5364 + return qbman_cgr_statistics_query(s, cgid, clear, 0xff,
5365 + frame_cnt, byte_cnt);
5366 +}
5367 +
5368 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5369 + u64 *frame_cnt, u64 *byte_cnt)
5370 +{
5371 + return qbman_cgr_statistics_query(s, cgid, clear, 1,
5372 + frame_cnt, byte_cnt);
5373 +}
5374 +
5375 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5376 + u64 *frame_cnt, u64 *byte_cnt)
5377 +{
5378 + return qbman_cgr_statistics_query(s, cgid, clear, 0,
5379 + frame_cnt, byte_cnt);
5380 +}
5381 --- /dev/null
5382 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_debug.h
5383 @@ -0,0 +1,136 @@
5384 +/* Copyright (C) 2015 Freescale Semiconductor, Inc.
5385 + *
5386 + * Redistribution and use in source and binary forms, with or without
5387 + * modification, are permitted provided that the following conditions are met:
5388 + * * Redistributions of source code must retain the above copyright
5389 + * notice, this list of conditions and the following disclaimer.
5390 + * * Redistributions in binary form must reproduce the above copyright
5391 + * notice, this list of conditions and the following disclaimer in the
5392 + * documentation and/or other materials provided with the distribution.
5393 + * * Neither the name of Freescale Semiconductor nor the
5394 + * names of its contributors may be used to endorse or promote products
5395 + * derived from this software without specific prior written permission.
5396 + *
5397 + *
5398 + * ALTERNATIVELY, this software may be distributed under the terms of the
5399 + * GNU General Public License ("GPL") as published by the Free Software
5400 + * Foundation, either version 2 of that License or (at your option) any
5401 + * later version.
5402 + *
5403 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5404 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5405 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5406 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5407 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5408 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5409 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5410 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5411 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5412 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5413 + */
5414 +
5415 +struct qbman_attr {
5416 + u32 dont_manipulate_directly[40];
5417 +};
5418 +
5419 +/* Buffer pool query commands */
5420 +int qbman_bp_query(struct qbman_swp *s, u32 bpid,
5421 + struct qbman_attr *a);
5422 +void qbman_bp_attr_get_bdi(struct qbman_attr *a, int *bdi, int *va, int *wae);
5423 +void qbman_bp_attr_get_swdet(struct qbman_attr *a, u32 *swdet);
5424 +void qbman_bp_attr_get_swdxt(struct qbman_attr *a, u32 *swdxt);
5425 +void qbman_bp_attr_get_hwdet(struct qbman_attr *a, u32 *hwdet);
5426 +void qbman_bp_attr_get_hwdxt(struct qbman_attr *a, u32 *hwdxt);
5427 +void qbman_bp_attr_get_swset(struct qbman_attr *a, u32 *swset);
5428 +void qbman_bp_attr_get_swsxt(struct qbman_attr *a, u32 *swsxt);
5429 +void qbman_bp_attr_get_vbpid(struct qbman_attr *a, u32 *vbpid);
5430 +void qbman_bp_attr_get_icid(struct qbman_attr *a, u32 *icid, int *pl);
5431 +void qbman_bp_attr_get_bpscn_addr(struct qbman_attr *a, u64 *bpscn_addr);
5432 +void qbman_bp_attr_get_bpscn_ctx(struct qbman_attr *a, u64 *bpscn_ctx);
5433 +void qbman_bp_attr_get_hw_targ(struct qbman_attr *a, u32 *hw_targ);
5434 +int qbman_bp_info_has_free_bufs(struct qbman_attr *a);
5435 +int qbman_bp_info_is_depleted(struct qbman_attr *a);
5436 +int qbman_bp_info_is_surplus(struct qbman_attr *a);
5437 +u32 qbman_bp_info_num_free_bufs(struct qbman_attr *a);
5438 +u32 qbman_bp_info_hdptr(struct qbman_attr *a);
5439 +u32 qbman_bp_info_sdcnt(struct qbman_attr *a);
5440 +u32 qbman_bp_info_hdcnt(struct qbman_attr *a);
5441 +u32 qbman_bp_info_sscnt(struct qbman_attr *a);
5442 +
5443 +/* FQ query function for programmable fields */
5444 +int qbman_fq_query(struct qbman_swp *s, u32 fqid,
5445 + struct qbman_attr *desc);
5446 +void qbman_fq_attr_get_fqctrl(struct qbman_attr *d, u32 *fqctrl);
5447 +void qbman_fq_attr_get_cgrid(struct qbman_attr *d, u32 *cgrid);
5448 +void qbman_fq_attr_get_destwq(struct qbman_attr *d, u32 *destwq);
5449 +void qbman_fq_attr_get_icscred(struct qbman_attr *d, u32 *icscred);
5450 +void qbman_fq_attr_get_tdthresh(struct qbman_attr *d, u32 *tdthresh);
5451 +void qbman_fq_attr_get_oa(struct qbman_attr *d,
5452 + int *oa_ics, int *oa_cgr, int32_t *oa_len);
5453 +void qbman_fq_attr_get_mctl(struct qbman_attr *d,
5454 + int *bdi, int *ff, int *va, int *ps);
5455 +void qbman_fq_attr_get_ctx(struct qbman_attr *d, u32 *hi, u32 *lo);
5456 +void qbman_fq_attr_get_icid(struct qbman_attr *d, u32 *icid, int *pl);
5457 +void qbman_fq_attr_get_vfqid(struct qbman_attr *d, u32 *vfqid);
5458 +void qbman_fq_attr_get_erfqid(struct qbman_attr *d, u32 *erfqid);
5459 +
5460 +/* FQ query command for non-programmable fields*/
5461 +enum qbman_fq_schedstate_e {
5462 + qbman_fq_schedstate_oos = 0,
5463 + qbman_fq_schedstate_retired,
5464 + qbman_fq_schedstate_tentatively_scheduled,
5465 + qbman_fq_schedstate_truly_scheduled,
5466 + qbman_fq_schedstate_parked,
5467 + qbman_fq_schedstate_held_active,
5468 +};
5469 +
5470 +int qbman_fq_query_state(struct qbman_swp *s, u32 fqid,
5471 + struct qbman_attr *state);
5472 +u32 qbman_fq_state_schedstate(const struct qbman_attr *state);
5473 +int qbman_fq_state_force_eligible(const struct qbman_attr *state);
5474 +int qbman_fq_state_xoff(const struct qbman_attr *state);
5475 +int qbman_fq_state_retirement_pending(const struct qbman_attr *state);
5476 +int qbman_fq_state_overflow_error(const struct qbman_attr *state);
5477 +u32 qbman_fq_state_frame_count(const struct qbman_attr *state);
5478 +u32 qbman_fq_state_byte_count(const struct qbman_attr *state);
5479 +
5480 +/* CGR query */
5481 +int qbman_cgr_query(struct qbman_swp *s, u32 cgid,
5482 + struct qbman_attr *attr);
5483 +void qbman_cgr_attr_get_ctl1(struct qbman_attr *d, int *cscn_wq_en_enter,
5484 + int *cscn_wq_en_exit, int *cscn_wq_icd);
5485 +void qbman_cgr_attr_get_mode(struct qbman_attr *d, u32 *mode,
5486 + int *rej_cnt_mode, int *cscn_bdi);
5487 +void qbman_cgr_attr_get_ctl2(struct qbman_attr *d, int *cscn_wr_en_enter,
5488 + int *cscn_wr_en_exit, int *cg_wr_ae,
5489 + int *cscn_dcp_en, int *cg_wr_va);
5490 +void qbman_cgr_attr_get_iwc(struct qbman_attr *d, int *i_cnt_wr_en,
5491 + u32 *i_cnt_wr_bnd);
5492 +void qbman_cgr_attr_get_tdc(struct qbman_attr *d, int *td_en);
5493 +void qbman_cgr_attr_get_cs_thres(struct qbman_attr *d, u32 *cs_thres);
5494 +void qbman_cgr_attr_get_cs_thres_x(struct qbman_attr *d,
5495 + u32 *cs_thres_x);
5496 +void qbman_cgr_attr_get_td_thres(struct qbman_attr *d, u32 *td_thres);
5497 +void qbman_cgr_attr_get_cscn_tdcp(struct qbman_attr *d, u32 *cscn_tdcp);
5498 +void qbman_cgr_attr_get_cscn_wqid(struct qbman_attr *d, u32 *cscn_wqid);
5499 +void qbman_cgr_attr_get_cscn_vcgid(struct qbman_attr *d,
5500 + u32 *cscn_vcgid);
5501 +void qbman_cgr_attr_get_cg_icid(struct qbman_attr *d, u32 *icid,
5502 + int *pl);
5503 +void qbman_cgr_attr_get_cg_wr_addr(struct qbman_attr *d,
5504 + u64 *cg_wr_addr);
5505 +void qbman_cgr_attr_get_cscn_ctx(struct qbman_attr *d, u64 *cscn_ctx);
5506 +void qbman_cgr_attr_wred_get_edp(struct qbman_attr *d, u32 idx,
5507 + int *edp);
5508 +void qbman_cgr_attr_wred_dp_decompose(u32 dp, u64 *minth,
5509 + u64 *maxth, u8 *maxp);
5510 +void qbman_cgr_attr_wred_get_parm_dp(struct qbman_attr *d, u32 idx,
5511 + u32 *dp);
5512 +
5513 +/* CGR/CCGR/CQ statistics query */
5514 +int qbman_cgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5515 + u64 *frame_cnt, u64 *byte_cnt);
5516 +int qbman_ccgr_reject_statistics(struct qbman_swp *s, u32 cgid, int clear,
5517 + u64 *frame_cnt, u64 *byte_cnt);
5518 +int qbman_cq_dequeue_statistics(struct qbman_swp *s, u32 cgid, int clear,
5519 + u64 *frame_cnt, u64 *byte_cnt);
5520 --- /dev/null
5521 +++ b/drivers/staging/fsl-mc/bus/dpio/qbman_private.h
5522 @@ -0,0 +1,171 @@
5523 +/* Copyright (C) 2014 Freescale Semiconductor, Inc.
5524 + *
5525 + * Redistribution and use in source and binary forms, with or without
5526 + * modification, are permitted provided that the following conditions are met:
5527 + * * Redistributions of source code must retain the above copyright
5528 + * notice, this list of conditions and the following disclaimer.
5529 + * * Redistributions in binary form must reproduce the above copyright
5530 + * notice, this list of conditions and the following disclaimer in the
5531 + * documentation and/or other materials provided with the distribution.
5532 + * * Neither the name of Freescale Semiconductor nor the
5533 + * names of its contributors may be used to endorse or promote products
5534 + * derived from this software without specific prior written permission.
5535 + *
5536 + *
5537 + * ALTERNATIVELY, this software may be distributed under the terms of the
5538 + * GNU General Public License ("GPL") as published by the Free Software
5539 + * Foundation, either version 2 of that License or (at your option) any
5540 + * later version.
5541 + *
5542 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
5543 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
5544 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
5545 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
5546 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
5547 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
5548 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
5549 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5550 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
5551 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5552 + */
5553 +
5554 +/* Perform extra checking */
5555 +#define QBMAN_CHECKING
5556 +
5557 +/* To maximise the amount of logic that is common between the Linux driver and
5558 + * other targets (such as the embedded MC firmware), we pivot here between the
5559 + * inclusion of two platform-specific headers.
5560 + *
5561 + * The first, qbman_sys_decl.h, includes any and all required system headers as
5562 + * well as providing any definitions for the purposes of compatibility. The
5563 + * second, qbman_sys.h, is where platform-specific routines go.
5564 + *
5565 + * The point of the split is that the platform-independent code (including this
5566 + * header) may depend on platform-specific declarations, yet other
5567 + * platform-specific routines may depend on platform-independent definitions.
5568 + */
5569 +
5570 +#define QMAN_REV_4000 0x04000000
5571 +#define QMAN_REV_4100 0x04010000
5572 +#define QMAN_REV_4101 0x04010001
5573 +
5574 +/* When things go wrong, it is a convenient trick to insert a few FOO()
5575 + * statements in the code to trace progress. TODO: remove this once we are
5576 + * hacking the code less actively.
5577 + */
5578 +#define FOO() fsl_os_print("FOO: %s:%d\n", __FILE__, __LINE__)
5579 +
5580 +/* Any time there is a register interface which we poll on, this provides a
5581 + * "break after x iterations" scheme for it. It's handy for debugging, eg.
5582 + * where you don't want millions of lines of log output from a polling loop
5583 + * that won't, because such things tend to drown out the earlier log output
5584 + * that might explain what caused the problem. (NB: put ";" after each macro!)
5585 + * TODO: we should probably remove this once we're done sanitising the
5586 + * simulator...
5587 + */
5588 +#define DBG_POLL_START(loopvar) (loopvar = 1000)
5589 +#define DBG_POLL_CHECK(loopvar) \
5590 + do {if (!((loopvar)--)) WARN_ON(1); } while (0)
5591 +
5592 +/* For CCSR or portal-CINH registers that contain fields at arbitrary offsets
5593 + * and widths, these macro-generated encode/decode/isolate/remove inlines can
5594 + * be used.
5595 + *
5596 + * Eg. to "d"ecode a 14-bit field out of a register (into a "u16" type),
5597 + * where the field is located 3 bits "up" from the least-significant bit of the
5598 + * register (ie. the field location within the 32-bit register corresponds to a
5599 + * mask of 0x0001fff8), you would do;
5600 + * u16 field = d32_u16(3, 14, reg_value);
5601 + *
5602 + * Or to "e"ncode a 1-bit boolean value (input type is "int", zero is FALSE,
5603 + * non-zero is TRUE, so must convert all non-zero inputs to 1, hence the "!!"
5604 + * operator) into a register at bit location 0x00080000 (19 bits "in" from the
5605 + * LS bit), do;
5606 + * reg_value |= e32_int(19, 1, !!field);
5607 + *
5608 + * If you wish to read-modify-write a register, such that you leave the 14-bit
5609 + * field as-is but have all other fields set to zero, then "i"solate the 14-bit
5610 + * value using;
5611 + * reg_value = i32_u16(3, 14, reg_value);
5612 + *
5613 + * Alternatively, you could "r"emove the 1-bit boolean field (setting it to
5614 + * zero) but leaving all other fields as-is;
5615 + * reg_val = r32_int(19, 1, reg_value);
5616 + *
5617 + */
5618 +#define MAKE_MASK32(width) (width == 32 ? 0xffffffff : \
5619 + (u32)((1 << width) - 1))
5620 +#define DECLARE_CODEC32(t) \
5621 +static inline u32 e32_##t(u32 lsoffset, u32 width, t val) \
5622 +{ \
5623 + WARN_ON(width > (sizeof(t) * 8)); \
5624 + return ((u32)val & MAKE_MASK32(width)) << lsoffset; \
5625 +} \
5626 +static inline t d32_##t(u32 lsoffset, u32 width, u32 val) \
5627 +{ \
5628 + WARN_ON(width > (sizeof(t) * 8)); \
5629 + return (t)((val >> lsoffset) & MAKE_MASK32(width)); \
5630 +} \
5631 +static inline u32 i32_##t(u32 lsoffset, u32 width, \
5632 + u32 val) \
5633 +{ \
5634 + WARN_ON(width > (sizeof(t) * 8)); \
5635 + return e32_##t(lsoffset, width, d32_##t(lsoffset, width, val)); \
5636 +} \
5637 +static inline u32 r32_##t(u32 lsoffset, u32 width, \
5638 + u32 val) \
5639 +{ \
5640 + WARN_ON(width > (sizeof(t) * 8)); \
5641 + return ~(MAKE_MASK32(width) << lsoffset) & val; \
5642 +}
5643 +DECLARE_CODEC32(u32)
5644 +DECLARE_CODEC32(u16)
5645 +DECLARE_CODEC32(u8)
5646 +DECLARE_CODEC32(int)
5647 +
5648 + /*********************/
5649 + /* Debugging assists */
5650 + /*********************/
5651 +
5652 +static inline void __hexdump(unsigned long start, unsigned long end,
5653 + unsigned long p, size_t sz,
5654 + const unsigned char *c)
5655 +{
5656 + while (start < end) {
5657 + unsigned int pos = 0;
5658 + char buf[64];
5659 + int nl = 0;
5660 +
5661 + pos += sprintf(buf + pos, "%08lx: ", start);
5662 + do {
5663 + if ((start < p) || (start >= (p + sz)))
5664 + pos += sprintf(buf + pos, "..");
5665 + else
5666 + pos += sprintf(buf + pos, "%02x", *(c++));
5667 + if (!(++start & 15)) {
5668 + buf[pos++] = '\n';
5669 + nl = 1;
5670 + } else {
5671 + nl = 0;
5672 + if (!(start & 1))
5673 + buf[pos++] = ' ';
5674 + if (!(start & 3))
5675 + buf[pos++] = ' ';
5676 + }
5677 + } while (start & 15);
5678 + if (!nl)
5679 + buf[pos++] = '\n';
5680 + buf[pos] = '\0';
5681 + pr_info("%s", buf);
5682 + }
5683 +}
5684 +
5685 +static inline void hexdump(const void *ptr, size_t sz)
5686 +{
5687 + unsigned long p = (unsigned long)ptr;
5688 + unsigned long start = p & ~15ul;
5689 + unsigned long end = (p + sz + 15) & ~15ul;
5690 + const unsigned char *c = ptr;
5691 +
5692 + __hexdump(start, end, p, sz, c);
5693 +}
5694 --- a/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5695 +++ b/drivers/staging/fsl-mc/bus/dpmcp-cmd.h
5696 @@ -1,4 +1,5 @@
5697 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5698 +/*
5699 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5700 *
5701 * Redistribution and use in source and binary forms, with or without
5702 * modification, are permitted provided that the following conditions are met:
5703 @@ -11,7 +12,6 @@
5704 * names of any contributors may be used to endorse or promote products
5705 * derived from this software without specific prior written permission.
5706 *
5707 - *
5708 * ALTERNATIVELY, this software may be distributed under the terms of the
5709 * GNU General Public License ("GPL") as published by the Free Software
5710 * Foundation, either version 2 of that License or (at your option) any
5711 @@ -33,108 +33,24 @@
5712 #define _FSL_DPMCP_CMD_H
5713
5714 /* Minimal supported DPMCP Version */
5715 -#define DPMCP_MIN_VER_MAJOR 3
5716 -#define DPMCP_MIN_VER_MINOR 0
5717 -
5718 -/* Command IDs */
5719 -#define DPMCP_CMDID_CLOSE 0x800
5720 -#define DPMCP_CMDID_OPEN 0x80b
5721 -#define DPMCP_CMDID_CREATE 0x90b
5722 -#define DPMCP_CMDID_DESTROY 0x900
5723 -
5724 -#define DPMCP_CMDID_GET_ATTR 0x004
5725 -#define DPMCP_CMDID_RESET 0x005
5726 -
5727 -#define DPMCP_CMDID_SET_IRQ 0x010
5728 -#define DPMCP_CMDID_GET_IRQ 0x011
5729 -#define DPMCP_CMDID_SET_IRQ_ENABLE 0x012
5730 -#define DPMCP_CMDID_GET_IRQ_ENABLE 0x013
5731 -#define DPMCP_CMDID_SET_IRQ_MASK 0x014
5732 -#define DPMCP_CMDID_GET_IRQ_MASK 0x015
5733 -#define DPMCP_CMDID_GET_IRQ_STATUS 0x016
5734 -
5735 -struct dpmcp_cmd_open {
5736 - __le32 dpmcp_id;
5737 -};
5738 -
5739 -struct dpmcp_cmd_create {
5740 - __le32 portal_id;
5741 -};
5742 -
5743 -struct dpmcp_cmd_set_irq {
5744 - /* cmd word 0 */
5745 - u8 irq_index;
5746 - u8 pad[3];
5747 - __le32 irq_val;
5748 - /* cmd word 1 */
5749 - __le64 irq_addr;
5750 - /* cmd word 2 */
5751 - __le32 irq_num;
5752 -};
5753 -
5754 -struct dpmcp_cmd_get_irq {
5755 - __le32 pad;
5756 - u8 irq_index;
5757 -};
5758 -
5759 -struct dpmcp_rsp_get_irq {
5760 - /* cmd word 0 */
5761 - __le32 irq_val;
5762 - __le32 pad;
5763 - /* cmd word 1 */
5764 - __le64 irq_paddr;
5765 - /* cmd word 2 */
5766 - __le32 irq_num;
5767 - __le32 type;
5768 -};
5769 +#define DPMCP_MIN_VER_MAJOR 3
5770 +#define DPMCP_MIN_VER_MINOR 0
5771
5772 -#define DPMCP_ENABLE 0x1
5773 +/* Command versioning */
5774 +#define DPMCP_CMD_BASE_VERSION 1
5775 +#define DPMCP_CMD_ID_OFFSET 4
5776
5777 -struct dpmcp_cmd_set_irq_enable {
5778 - u8 enable;
5779 - u8 pad[3];
5780 - u8 irq_index;
5781 -};
5782 +#define DPMCP_CMD(id) ((id << DPMCP_CMD_ID_OFFSET) | DPMCP_CMD_BASE_VERSION)
5783
5784 -struct dpmcp_cmd_get_irq_enable {
5785 - __le32 pad;
5786 - u8 irq_index;
5787 -};
5788 -
5789 -struct dpmcp_rsp_get_irq_enable {
5790 - u8 enabled;
5791 -};
5792 -
5793 -struct dpmcp_cmd_set_irq_mask {
5794 - __le32 mask;
5795 - u8 irq_index;
5796 -};
5797 -
5798 -struct dpmcp_cmd_get_irq_mask {
5799 - __le32 pad;
5800 - u8 irq_index;
5801 -};
5802 -
5803 -struct dpmcp_rsp_get_irq_mask {
5804 - __le32 mask;
5805 -};
5806 +/* Command IDs */
5807 +#define DPMCP_CMDID_CLOSE DPMCP_CMD(0x800)
5808 +#define DPMCP_CMDID_OPEN DPMCP_CMD(0x80b)
5809 +#define DPMCP_CMDID_GET_API_VERSION DPMCP_CMD(0xa0b)
5810
5811 -struct dpmcp_cmd_get_irq_status {
5812 - __le32 status;
5813 - u8 irq_index;
5814 -};
5815 +#define DPMCP_CMDID_RESET DPMCP_CMD(0x005)
5816
5817 -struct dpmcp_rsp_get_irq_status {
5818 - __le32 status;
5819 -};
5820 -
5821 -struct dpmcp_rsp_get_attributes {
5822 - /* response word 0 */
5823 - __le32 pad;
5824 - __le32 id;
5825 - /* response word 1 */
5826 - __le16 version_major;
5827 - __le16 version_minor;
5828 +struct dpmcp_cmd_open {
5829 + __le32 dpmcp_id;
5830 };
5831
5832 #endif /* _FSL_DPMCP_CMD_H */
5833 --- a/drivers/staging/fsl-mc/bus/dpmcp.c
5834 +++ b/drivers/staging/fsl-mc/bus/dpmcp.c
5835 @@ -1,4 +1,5 @@
5836 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
5837 +/*
5838 + * Copyright 2013-2016 Freescale Semiconductor Inc.
5839 *
5840 * Redistribution and use in source and binary forms, with or without
5841 * modification, are permitted provided that the following conditions are met:
5842 @@ -11,7 +12,6 @@
5843 * names of any contributors may be used to endorse or promote products
5844 * derived from this software without specific prior written permission.
5845 *
5846 - *
5847 * ALTERNATIVELY, this software may be distributed under the terms of the
5848 * GNU General Public License ("GPL") as published by the Free Software
5849 * Foundation, either version 2 of that License or (at your option) any
5850 @@ -104,76 +104,6 @@ int dpmcp_close(struct fsl_mc_io *mc_io,
5851 }
5852
5853 /**
5854 - * dpmcp_create() - Create the DPMCP object.
5855 - * @mc_io: Pointer to MC portal's I/O object
5856 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5857 - * @cfg: Configuration structure
5858 - * @token: Returned token; use in subsequent API calls
5859 - *
5860 - * Create the DPMCP object, allocate required resources and
5861 - * perform required initialization.
5862 - *
5863 - * The object can be created either by declaring it in the
5864 - * DPL file, or by calling this function.
5865 - * This function returns a unique authentication token,
5866 - * associated with the specific object ID and the specific MC
5867 - * portal; this token must be used in all subsequent calls to
5868 - * this specific object. For objects that are created using the
5869 - * DPL file, call dpmcp_open function to get an authentication
5870 - * token first.
5871 - *
5872 - * Return: '0' on Success; Error code otherwise.
5873 - */
5874 -int dpmcp_create(struct fsl_mc_io *mc_io,
5875 - u32 cmd_flags,
5876 - const struct dpmcp_cfg *cfg,
5877 - u16 *token)
5878 -{
5879 - struct mc_command cmd = { 0 };
5880 - struct dpmcp_cmd_create *cmd_params;
5881 -
5882 - int err;
5883 -
5884 - /* prepare command */
5885 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_CREATE,
5886 - cmd_flags, 0);
5887 - cmd_params = (struct dpmcp_cmd_create *)cmd.params;
5888 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
5889 -
5890 - /* send command to mc*/
5891 - err = mc_send_command(mc_io, &cmd);
5892 - if (err)
5893 - return err;
5894 -
5895 - /* retrieve response parameters */
5896 - *token = mc_cmd_hdr_read_token(&cmd);
5897 -
5898 - return 0;
5899 -}
5900 -
5901 -/**
5902 - * dpmcp_destroy() - Destroy the DPMCP object and release all its resources.
5903 - * @mc_io: Pointer to MC portal's I/O object
5904 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5905 - * @token: Token of DPMCP object
5906 - *
5907 - * Return: '0' on Success; error code otherwise.
5908 - */
5909 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
5910 - u32 cmd_flags,
5911 - u16 token)
5912 -{
5913 - struct mc_command cmd = { 0 };
5914 -
5915 - /* prepare command */
5916 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_DESTROY,
5917 - cmd_flags, token);
5918 -
5919 - /* send command to mc*/
5920 - return mc_send_command(mc_io, &cmd);
5921 -}
5922 -
5923 -/**
5924 * dpmcp_reset() - Reset the DPMCP, returns the object to initial state.
5925 * @mc_io: Pointer to MC portal's I/O object
5926 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5927 @@ -196,309 +126,33 @@ int dpmcp_reset(struct fsl_mc_io *mc_io,
5928 }
5929
5930 /**
5931 - * dpmcp_set_irq() - Set IRQ information for the DPMCP to trigger an interrupt.
5932 - * @mc_io: Pointer to MC portal's I/O object
5933 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5934 - * @token: Token of DPMCP object
5935 - * @irq_index: Identifies the interrupt index to configure
5936 - * @irq_cfg: IRQ configuration
5937 - *
5938 - * Return: '0' on Success; Error code otherwise.
5939 - */
5940 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
5941 - u32 cmd_flags,
5942 - u16 token,
5943 - u8 irq_index,
5944 - struct dpmcp_irq_cfg *irq_cfg)
5945 -{
5946 - struct mc_command cmd = { 0 };
5947 - struct dpmcp_cmd_set_irq *cmd_params;
5948 -
5949 - /* prepare command */
5950 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ,
5951 - cmd_flags, token);
5952 - cmd_params = (struct dpmcp_cmd_set_irq *)cmd.params;
5953 - cmd_params->irq_index = irq_index;
5954 - cmd_params->irq_val = cpu_to_le32(irq_cfg->val);
5955 - cmd_params->irq_addr = cpu_to_le64(irq_cfg->paddr);
5956 - cmd_params->irq_num = cpu_to_le32(irq_cfg->irq_num);
5957 -
5958 - /* send command to mc*/
5959 - return mc_send_command(mc_io, &cmd);
5960 -}
5961 -
5962 -/**
5963 - * dpmcp_get_irq() - Get IRQ information from the DPMCP.
5964 - * @mc_io: Pointer to MC portal's I/O object
5965 + * dpmcp_get_api_version - Get Data Path Management Command Portal API version
5966 + * @mc_io: Pointer to Mc portal's I/O object
5967 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
5968 - * @token: Token of DPMCP object
5969 - * @irq_index: The interrupt index to configure
5970 - * @type: Interrupt type: 0 represents message interrupt
5971 - * type (both irq_addr and irq_val are valid)
5972 - * @irq_cfg: IRQ attributes
5973 + * @major_ver: Major version of Data Path Management Command Portal API
5974 + * @minor_ver: Minor version of Data Path Management Command Portal API
5975 *
5976 * Return: '0' on Success; Error code otherwise.
5977 */
5978 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
5979 - u32 cmd_flags,
5980 - u16 token,
5981 - u8 irq_index,
5982 - int *type,
5983 - struct dpmcp_irq_cfg *irq_cfg)
5984 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
5985 + u32 cmd_flags,
5986 + u16 *major_ver,
5987 + u16 *minor_ver)
5988 {
5989 struct mc_command cmd = { 0 };
5990 - struct dpmcp_cmd_get_irq *cmd_params;
5991 - struct dpmcp_rsp_get_irq *rsp_params;
5992 int err;
5993
5994 /* prepare command */
5995 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ,
5996 - cmd_flags, token);
5997 - cmd_params = (struct dpmcp_cmd_get_irq *)cmd.params;
5998 - cmd_params->irq_index = irq_index;
5999 -
6000 - /* send command to mc*/
6001 - err = mc_send_command(mc_io, &cmd);
6002 - if (err)
6003 - return err;
6004 -
6005 - /* retrieve response parameters */
6006 - rsp_params = (struct dpmcp_rsp_get_irq *)cmd.params;
6007 - irq_cfg->val = le32_to_cpu(rsp_params->irq_val);
6008 - irq_cfg->paddr = le64_to_cpu(rsp_params->irq_paddr);
6009 - irq_cfg->irq_num = le32_to_cpu(rsp_params->irq_num);
6010 - *type = le32_to_cpu(rsp_params->type);
6011 - return 0;
6012 -}
6013 -
6014 -/**
6015 - * dpmcp_set_irq_enable() - Set overall interrupt state.
6016 - * @mc_io: Pointer to MC portal's I/O object
6017 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6018 - * @token: Token of DPMCP object
6019 - * @irq_index: The interrupt index to configure
6020 - * @en: Interrupt state - enable = 1, disable = 0
6021 - *
6022 - * Allows GPP software to control when interrupts are generated.
6023 - * Each interrupt can have up to 32 causes. The enable/disable control's the
6024 - * overall interrupt state. if the interrupt is disabled no causes will cause
6025 - * an interrupt.
6026 - *
6027 - * Return: '0' on Success; Error code otherwise.
6028 - */
6029 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
6030 - u32 cmd_flags,
6031 - u16 token,
6032 - u8 irq_index,
6033 - u8 en)
6034 -{
6035 - struct mc_command cmd = { 0 };
6036 - struct dpmcp_cmd_set_irq_enable *cmd_params;
6037 -
6038 - /* prepare command */
6039 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_ENABLE,
6040 - cmd_flags, token);
6041 - cmd_params = (struct dpmcp_cmd_set_irq_enable *)cmd.params;
6042 - cmd_params->enable = en & DPMCP_ENABLE;
6043 - cmd_params->irq_index = irq_index;
6044 -
6045 - /* send command to mc*/
6046 - return mc_send_command(mc_io, &cmd);
6047 -}
6048 -
6049 -/**
6050 - * dpmcp_get_irq_enable() - Get overall interrupt state
6051 - * @mc_io: Pointer to MC portal's I/O object
6052 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6053 - * @token: Token of DPMCP object
6054 - * @irq_index: The interrupt index to configure
6055 - * @en: Returned interrupt state - enable = 1, disable = 0
6056 - *
6057 - * Return: '0' on Success; Error code otherwise.
6058 - */
6059 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
6060 - u32 cmd_flags,
6061 - u16 token,
6062 - u8 irq_index,
6063 - u8 *en)
6064 -{
6065 - struct mc_command cmd = { 0 };
6066 - struct dpmcp_cmd_get_irq_enable *cmd_params;
6067 - struct dpmcp_rsp_get_irq_enable *rsp_params;
6068 - int err;
6069 -
6070 - /* prepare command */
6071 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_ENABLE,
6072 - cmd_flags, token);
6073 - cmd_params = (struct dpmcp_cmd_get_irq_enable *)cmd.params;
6074 - cmd_params->irq_index = irq_index;
6075 -
6076 - /* send command to mc*/
6077 - err = mc_send_command(mc_io, &cmd);
6078 - if (err)
6079 - return err;
6080 -
6081 - /* retrieve response parameters */
6082 - rsp_params = (struct dpmcp_rsp_get_irq_enable *)cmd.params;
6083 - *en = rsp_params->enabled & DPMCP_ENABLE;
6084 - return 0;
6085 -}
6086 -
6087 -/**
6088 - * dpmcp_set_irq_mask() - Set interrupt mask.
6089 - * @mc_io: Pointer to MC portal's I/O object
6090 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6091 - * @token: Token of DPMCP object
6092 - * @irq_index: The interrupt index to configure
6093 - * @mask: Event mask to trigger interrupt;
6094 - * each bit:
6095 - * 0 = ignore event
6096 - * 1 = consider event for asserting IRQ
6097 - *
6098 - * Every interrupt can have up to 32 causes and the interrupt model supports
6099 - * masking/unmasking each cause independently
6100 - *
6101 - * Return: '0' on Success; Error code otherwise.
6102 - */
6103 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
6104 - u32 cmd_flags,
6105 - u16 token,
6106 - u8 irq_index,
6107 - u32 mask)
6108 -{
6109 - struct mc_command cmd = { 0 };
6110 - struct dpmcp_cmd_set_irq_mask *cmd_params;
6111 -
6112 - /* prepare command */
6113 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_SET_IRQ_MASK,
6114 - cmd_flags, token);
6115 - cmd_params = (struct dpmcp_cmd_set_irq_mask *)cmd.params;
6116 - cmd_params->mask = cpu_to_le32(mask);
6117 - cmd_params->irq_index = irq_index;
6118 -
6119 - /* send command to mc*/
6120 - return mc_send_command(mc_io, &cmd);
6121 -}
6122 -
6123 -/**
6124 - * dpmcp_get_irq_mask() - Get interrupt mask.
6125 - * @mc_io: Pointer to MC portal's I/O object
6126 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6127 - * @token: Token of DPMCP object
6128 - * @irq_index: The interrupt index to configure
6129 - * @mask: Returned event mask to trigger interrupt
6130 - *
6131 - * Every interrupt can have up to 32 causes and the interrupt model supports
6132 - * masking/unmasking each cause independently
6133 - *
6134 - * Return: '0' on Success; Error code otherwise.
6135 - */
6136 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
6137 - u32 cmd_flags,
6138 - u16 token,
6139 - u8 irq_index,
6140 - u32 *mask)
6141 -{
6142 - struct mc_command cmd = { 0 };
6143 - struct dpmcp_cmd_get_irq_mask *cmd_params;
6144 - struct dpmcp_rsp_get_irq_mask *rsp_params;
6145 -
6146 - int err;
6147 -
6148 - /* prepare command */
6149 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_MASK,
6150 - cmd_flags, token);
6151 - cmd_params = (struct dpmcp_cmd_get_irq_mask *)cmd.params;
6152 - cmd_params->irq_index = irq_index;
6153 -
6154 - /* send command to mc*/
6155 - err = mc_send_command(mc_io, &cmd);
6156 - if (err)
6157 - return err;
6158 -
6159 - /* retrieve response parameters */
6160 - rsp_params = (struct dpmcp_rsp_get_irq_mask *)cmd.params;
6161 - *mask = le32_to_cpu(rsp_params->mask);
6162 -
6163 - return 0;
6164 -}
6165 -
6166 -/**
6167 - * dpmcp_get_irq_status() - Get the current status of any pending interrupts.
6168 - *
6169 - * @mc_io: Pointer to MC portal's I/O object
6170 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6171 - * @token: Token of DPMCP object
6172 - * @irq_index: The interrupt index to configure
6173 - * @status: Returned interrupts status - one bit per cause:
6174 - * 0 = no interrupt pending
6175 - * 1 = interrupt pending
6176 - *
6177 - * Return: '0' on Success; Error code otherwise.
6178 - */
6179 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6180 - u32 cmd_flags,
6181 - u16 token,
6182 - u8 irq_index,
6183 - u32 *status)
6184 -{
6185 - struct mc_command cmd = { 0 };
6186 - struct dpmcp_cmd_get_irq_status *cmd_params;
6187 - struct dpmcp_rsp_get_irq_status *rsp_params;
6188 - int err;
6189 -
6190 - /* prepare command */
6191 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_IRQ_STATUS,
6192 - cmd_flags, token);
6193 - cmd_params = (struct dpmcp_cmd_get_irq_status *)cmd.params;
6194 - cmd_params->status = cpu_to_le32(*status);
6195 - cmd_params->irq_index = irq_index;
6196 -
6197 - /* send command to mc*/
6198 - err = mc_send_command(mc_io, &cmd);
6199 - if (err)
6200 - return err;
6201 -
6202 - /* retrieve response parameters */
6203 - rsp_params = (struct dpmcp_rsp_get_irq_status *)cmd.params;
6204 - *status = le32_to_cpu(rsp_params->status);
6205 -
6206 - return 0;
6207 -}
6208 -
6209 -/**
6210 - * dpmcp_get_attributes - Retrieve DPMCP attributes.
6211 - *
6212 - * @mc_io: Pointer to MC portal's I/O object
6213 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6214 - * @token: Token of DPMCP object
6215 - * @attr: Returned object's attributes
6216 - *
6217 - * Return: '0' on Success; Error code otherwise.
6218 - */
6219 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6220 - u32 cmd_flags,
6221 - u16 token,
6222 - struct dpmcp_attr *attr)
6223 -{
6224 - struct mc_command cmd = { 0 };
6225 - struct dpmcp_rsp_get_attributes *rsp_params;
6226 - int err;
6227 -
6228 - /* prepare command */
6229 - cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_ATTR,
6230 - cmd_flags, token);
6231 + cmd.header = mc_encode_cmd_header(DPMCP_CMDID_GET_API_VERSION,
6232 + cmd_flags, 0);
6233
6234 - /* send command to mc*/
6235 + /* send command to mc */
6236 err = mc_send_command(mc_io, &cmd);
6237 if (err)
6238 return err;
6239
6240 /* retrieve response parameters */
6241 - rsp_params = (struct dpmcp_rsp_get_attributes *)cmd.params;
6242 - attr->id = le32_to_cpu(rsp_params->id);
6243 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6244 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6245 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
6246
6247 return 0;
6248 }
6249 --- a/drivers/staging/fsl-mc/bus/dpmcp.h
6250 +++ b/drivers/staging/fsl-mc/bus/dpmcp.h
6251 @@ -1,4 +1,5 @@
6252 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
6253 +/*
6254 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6255 *
6256 * Redistribution and use in source and binary forms, with or without
6257 * modification, are permitted provided that the following conditions are met:
6258 @@ -11,7 +12,6 @@
6259 * names of any contributors may be used to endorse or promote products
6260 * derived from this software without specific prior written permission.
6261 *
6262 - *
6263 * ALTERNATIVELY, this software may be distributed under the terms of the
6264 * GNU General Public License ("GPL") as published by the Free Software
6265 * Foundation, either version 2 of that License or (at your option) any
6266 @@ -32,128 +32,29 @@
6267 #ifndef __FSL_DPMCP_H
6268 #define __FSL_DPMCP_H
6269
6270 -/* Data Path Management Command Portal API
6271 +/*
6272 + * Data Path Management Command Portal API
6273 * Contains initialization APIs and runtime control APIs for DPMCP
6274 */
6275
6276 struct fsl_mc_io;
6277
6278 int dpmcp_open(struct fsl_mc_io *mc_io,
6279 - uint32_t cmd_flags,
6280 + u32 cmd_flags,
6281 int dpmcp_id,
6282 - uint16_t *token);
6283 -
6284 -/* Get portal ID from pool */
6285 -#define DPMCP_GET_PORTAL_ID_FROM_POOL (-1)
6286 + u16 *token);
6287
6288 int dpmcp_close(struct fsl_mc_io *mc_io,
6289 - uint32_t cmd_flags,
6290 - uint16_t token);
6291 + u32 cmd_flags,
6292 + u16 token);
6293
6294 -/**
6295 - * struct dpmcp_cfg - Structure representing DPMCP configuration
6296 - * @portal_id: Portal ID; 'DPMCP_GET_PORTAL_ID_FROM_POOL' to get the portal ID
6297 - * from pool
6298 - */
6299 -struct dpmcp_cfg {
6300 - int portal_id;
6301 -};
6302 -
6303 -int dpmcp_create(struct fsl_mc_io *mc_io,
6304 - uint32_t cmd_flags,
6305 - const struct dpmcp_cfg *cfg,
6306 - uint16_t *token);
6307 -
6308 -int dpmcp_destroy(struct fsl_mc_io *mc_io,
6309 - uint32_t cmd_flags,
6310 - uint16_t token);
6311 +int dpmcp_get_api_version(struct fsl_mc_io *mc_io,
6312 + u32 cmd_flags,
6313 + u16 *major_ver,
6314 + u16 *minor_ver);
6315
6316 int dpmcp_reset(struct fsl_mc_io *mc_io,
6317 - uint32_t cmd_flags,
6318 - uint16_t token);
6319 -
6320 -/* IRQ */
6321 -/* IRQ Index */
6322 -#define DPMCP_IRQ_INDEX 0
6323 -/* irq event - Indicates that the link state changed */
6324 -#define DPMCP_IRQ_EVENT_CMD_DONE 0x00000001
6325 -
6326 -/**
6327 - * struct dpmcp_irq_cfg - IRQ configuration
6328 - * @paddr: Address that must be written to signal a message-based interrupt
6329 - * @val: Value to write into irq_addr address
6330 - * @irq_num: A user defined number associated with this IRQ
6331 - */
6332 -struct dpmcp_irq_cfg {
6333 - uint64_t paddr;
6334 - uint32_t val;
6335 - int irq_num;
6336 -};
6337 -
6338 -int dpmcp_set_irq(struct fsl_mc_io *mc_io,
6339 - uint32_t cmd_flags,
6340 - uint16_t token,
6341 - uint8_t irq_index,
6342 - struct dpmcp_irq_cfg *irq_cfg);
6343 -
6344 -int dpmcp_get_irq(struct fsl_mc_io *mc_io,
6345 - uint32_t cmd_flags,
6346 - uint16_t token,
6347 - uint8_t irq_index,
6348 - int *type,
6349 - struct dpmcp_irq_cfg *irq_cfg);
6350 -
6351 -int dpmcp_set_irq_enable(struct fsl_mc_io *mc_io,
6352 - uint32_t cmd_flags,
6353 - uint16_t token,
6354 - uint8_t irq_index,
6355 - uint8_t en);
6356 -
6357 -int dpmcp_get_irq_enable(struct fsl_mc_io *mc_io,
6358 - uint32_t cmd_flags,
6359 - uint16_t token,
6360 - uint8_t irq_index,
6361 - uint8_t *en);
6362 -
6363 -int dpmcp_set_irq_mask(struct fsl_mc_io *mc_io,
6364 - uint32_t cmd_flags,
6365 - uint16_t token,
6366 - uint8_t irq_index,
6367 - uint32_t mask);
6368 -
6369 -int dpmcp_get_irq_mask(struct fsl_mc_io *mc_io,
6370 - uint32_t cmd_flags,
6371 - uint16_t token,
6372 - uint8_t irq_index,
6373 - uint32_t *mask);
6374 -
6375 -int dpmcp_get_irq_status(struct fsl_mc_io *mc_io,
6376 - uint32_t cmd_flags,
6377 - uint16_t token,
6378 - uint8_t irq_index,
6379 - uint32_t *status);
6380 -
6381 -/**
6382 - * struct dpmcp_attr - Structure representing DPMCP attributes
6383 - * @id: DPMCP object ID
6384 - * @version: DPMCP version
6385 - */
6386 -struct dpmcp_attr {
6387 - int id;
6388 - /**
6389 - * struct version - Structure representing DPMCP version
6390 - * @major: DPMCP major version
6391 - * @minor: DPMCP minor version
6392 - */
6393 - struct {
6394 - uint16_t major;
6395 - uint16_t minor;
6396 - } version;
6397 -};
6398 -
6399 -int dpmcp_get_attributes(struct fsl_mc_io *mc_io,
6400 - uint32_t cmd_flags,
6401 - uint16_t token,
6402 - struct dpmcp_attr *attr);
6403 + u32 cmd_flags,
6404 + u16 token);
6405
6406 #endif /* __FSL_DPMCP_H */
6407 --- a/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6408 +++ b/drivers/staging/fsl-mc/bus/dpmng-cmd.h
6409 @@ -12,7 +12,6 @@
6410 * names of any contributors may be used to endorse or promote products
6411 * derived from this software without specific prior written permission.
6412 *
6413 - *
6414 * ALTERNATIVELY, this software may be distributed under the terms of the
6415 * GNU General Public License ("GPL") as published by the Free Software
6416 * Foundation, either version 2 of that License or (at your option) any
6417 @@ -41,13 +40,14 @@
6418 #ifndef __FSL_DPMNG_CMD_H
6419 #define __FSL_DPMNG_CMD_H
6420
6421 -/* Command IDs */
6422 -#define DPMNG_CMDID_GET_CONT_ID 0x830
6423 -#define DPMNG_CMDID_GET_VERSION 0x831
6424 +/* Command versioning */
6425 +#define DPMNG_CMD_BASE_VERSION 1
6426 +#define DPMNG_CMD_ID_OFFSET 4
6427
6428 -struct dpmng_rsp_get_container_id {
6429 - __le32 container_id;
6430 -};
6431 +#define DPMNG_CMD(id) ((id << DPMNG_CMD_ID_OFFSET) | DPMNG_CMD_BASE_VERSION)
6432 +
6433 +/* Command IDs */
6434 +#define DPMNG_CMDID_GET_VERSION DPMNG_CMD(0x831)
6435
6436 struct dpmng_rsp_get_version {
6437 __le32 revision;
6438 --- a/drivers/staging/fsl-mc/bus/dpmng.c
6439 +++ b/drivers/staging/fsl-mc/bus/dpmng.c
6440 @@ -1,4 +1,5 @@
6441 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6442 +/*
6443 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6444 *
6445 * Redistribution and use in source and binary forms, with or without
6446 * modification, are permitted provided that the following conditions are met:
6447 @@ -11,7 +12,6 @@
6448 * names of any contributors may be used to endorse or promote products
6449 * derived from this software without specific prior written permission.
6450 *
6451 - *
6452 * ALTERNATIVELY, this software may be distributed under the terms of the
6453 * GNU General Public License ("GPL") as published by the Free Software
6454 * Foundation, either version 2 of that License or (at your option) any
6455 @@ -72,36 +72,3 @@ int mc_get_version(struct fsl_mc_io *mc_
6456 }
6457 EXPORT_SYMBOL(mc_get_version);
6458
6459 -/**
6460 - * dpmng_get_container_id() - Get container ID associated with a given portal.
6461 - * @mc_io: Pointer to MC portal's I/O object
6462 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6463 - * @container_id: Requested container ID
6464 - *
6465 - * Return: '0' on Success; Error code otherwise.
6466 - */
6467 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
6468 - u32 cmd_flags,
6469 - int *container_id)
6470 -{
6471 - struct mc_command cmd = { 0 };
6472 - struct dpmng_rsp_get_container_id *rsp_params;
6473 - int err;
6474 -
6475 - /* prepare command */
6476 - cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_CONT_ID,
6477 - cmd_flags,
6478 - 0);
6479 -
6480 - /* send command to mc*/
6481 - err = mc_send_command(mc_io, &cmd);
6482 - if (err)
6483 - return err;
6484 -
6485 - /* retrieve response parameters */
6486 - rsp_params = (struct dpmng_rsp_get_container_id *)cmd.params;
6487 - *container_id = le32_to_cpu(rsp_params->container_id);
6488 -
6489 - return 0;
6490 -}
6491 -
6492 --- a/drivers/staging/fsl-mc/bus/dprc-cmd.h
6493 +++ b/drivers/staging/fsl-mc/bus/dprc-cmd.h
6494 @@ -12,7 +12,6 @@
6495 * names of any contributors may be used to endorse or promote products
6496 * derived from this software without specific prior written permission.
6497 *
6498 - *
6499 * ALTERNATIVELY, this software may be distributed under the terms of the
6500 * GNU General Public License ("GPL") as published by the Free Software
6501 * Foundation, either version 2 of that License or (at your option) any
6502 @@ -42,48 +41,39 @@
6503 #define _FSL_DPRC_CMD_H
6504
6505 /* Minimal supported DPRC Version */
6506 -#define DPRC_MIN_VER_MAJOR 5
6507 +#define DPRC_MIN_VER_MAJOR 6
6508 #define DPRC_MIN_VER_MINOR 0
6509
6510 -/* Command IDs */
6511 -#define DPRC_CMDID_CLOSE 0x800
6512 -#define DPRC_CMDID_OPEN 0x805
6513 -#define DPRC_CMDID_CREATE 0x905
6514 -
6515 -#define DPRC_CMDID_GET_ATTR 0x004
6516 -#define DPRC_CMDID_RESET_CONT 0x005
6517 -
6518 -#define DPRC_CMDID_SET_IRQ 0x010
6519 -#define DPRC_CMDID_GET_IRQ 0x011
6520 -#define DPRC_CMDID_SET_IRQ_ENABLE 0x012
6521 -#define DPRC_CMDID_GET_IRQ_ENABLE 0x013
6522 -#define DPRC_CMDID_SET_IRQ_MASK 0x014
6523 -#define DPRC_CMDID_GET_IRQ_MASK 0x015
6524 -#define DPRC_CMDID_GET_IRQ_STATUS 0x016
6525 -#define DPRC_CMDID_CLEAR_IRQ_STATUS 0x017
6526 -
6527 -#define DPRC_CMDID_CREATE_CONT 0x151
6528 -#define DPRC_CMDID_DESTROY_CONT 0x152
6529 -#define DPRC_CMDID_SET_RES_QUOTA 0x155
6530 -#define DPRC_CMDID_GET_RES_QUOTA 0x156
6531 -#define DPRC_CMDID_ASSIGN 0x157
6532 -#define DPRC_CMDID_UNASSIGN 0x158
6533 -#define DPRC_CMDID_GET_OBJ_COUNT 0x159
6534 -#define DPRC_CMDID_GET_OBJ 0x15A
6535 -#define DPRC_CMDID_GET_RES_COUNT 0x15B
6536 -#define DPRC_CMDID_GET_RES_IDS 0x15C
6537 -#define DPRC_CMDID_GET_OBJ_REG 0x15E
6538 -#define DPRC_CMDID_SET_OBJ_IRQ 0x15F
6539 -#define DPRC_CMDID_GET_OBJ_IRQ 0x160
6540 -#define DPRC_CMDID_SET_OBJ_LABEL 0x161
6541 -#define DPRC_CMDID_GET_OBJ_DESC 0x162
6542 -
6543 -#define DPRC_CMDID_CONNECT 0x167
6544 -#define DPRC_CMDID_DISCONNECT 0x168
6545 -#define DPRC_CMDID_GET_POOL 0x169
6546 -#define DPRC_CMDID_GET_POOL_COUNT 0x16A
6547 +/* Command versioning */
6548 +#define DPRC_CMD_BASE_VERSION 1
6549 +#define DPRC_CMD_ID_OFFSET 4
6550
6551 -#define DPRC_CMDID_GET_CONNECTION 0x16C
6552 +#define DPRC_CMD(id) ((id << DPRC_CMD_ID_OFFSET) | DPRC_CMD_BASE_VERSION)
6553 +
6554 +/* Command IDs */
6555 +#define DPRC_CMDID_CLOSE DPRC_CMD(0x800)
6556 +#define DPRC_CMDID_OPEN DPRC_CMD(0x805)
6557 +#define DPRC_CMDID_GET_API_VERSION DPRC_CMD(0xa05)
6558 +
6559 +#define DPRC_CMDID_GET_ATTR DPRC_CMD(0x004)
6560 +#define DPRC_CMDID_RESET_CONT DPRC_CMD(0x005)
6561 +
6562 +#define DPRC_CMDID_SET_IRQ DPRC_CMD(0x010)
6563 +#define DPRC_CMDID_GET_IRQ DPRC_CMD(0x011)
6564 +#define DPRC_CMDID_SET_IRQ_ENABLE DPRC_CMD(0x012)
6565 +#define DPRC_CMDID_GET_IRQ_ENABLE DPRC_CMD(0x013)
6566 +#define DPRC_CMDID_SET_IRQ_MASK DPRC_CMD(0x014)
6567 +#define DPRC_CMDID_GET_IRQ_MASK DPRC_CMD(0x015)
6568 +#define DPRC_CMDID_GET_IRQ_STATUS DPRC_CMD(0x016)
6569 +#define DPRC_CMDID_CLEAR_IRQ_STATUS DPRC_CMD(0x017)
6570 +
6571 +#define DPRC_CMDID_GET_CONT_ID DPRC_CMD(0x830)
6572 +#define DPRC_CMDID_GET_OBJ_COUNT DPRC_CMD(0x159)
6573 +#define DPRC_CMDID_GET_OBJ DPRC_CMD(0x15A)
6574 +#define DPRC_CMDID_GET_RES_COUNT DPRC_CMD(0x15B)
6575 +#define DPRC_CMDID_GET_OBJ_REG DPRC_CMD(0x15E)
6576 +#define DPRC_CMDID_SET_OBJ_IRQ DPRC_CMD(0x15F)
6577 +#define DPRC_CMDID_GET_OBJ_IRQ DPRC_CMD(0x160)
6578
6579 struct dprc_cmd_open {
6580 __le32 container_id;
6581 @@ -199,9 +189,6 @@ struct dprc_rsp_get_attributes {
6582 /* response word 1 */
6583 __le32 options;
6584 __le32 portal_id;
6585 - /* response word 2 */
6586 - __le16 version_major;
6587 - __le16 version_minor;
6588 };
6589
6590 struct dprc_cmd_set_res_quota {
6591 @@ -367,11 +354,16 @@ struct dprc_cmd_get_obj_region {
6592
6593 struct dprc_rsp_get_obj_region {
6594 /* response word 0 */
6595 - __le64 pad;
6596 + __le64 pad0;
6597 /* response word 1 */
6598 - __le64 base_addr;
6599 + __le32 base_addr;
6600 + __le32 pad1;
6601 /* response word 2 */
6602 __le32 size;
6603 + u8 type;
6604 + u8 pad2[3];
6605 + /* response word 3 */
6606 + __le32 flags;
6607 };
6608
6609 struct dprc_cmd_set_obj_label {
6610 --- a/drivers/staging/fsl-mc/bus/dprc-driver.c
6611 +++ b/drivers/staging/fsl-mc/bus/dprc-driver.c
6612 @@ -1,7 +1,7 @@
6613 /*
6614 * Freescale data path resource container (DPRC) driver
6615 *
6616 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
6617 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
6618 * Author: German Rivera <German.Rivera@freescale.com>
6619 *
6620 * This file is licensed under the terms of the GNU General Public
6621 @@ -160,6 +160,8 @@ static void check_plugged_state_change(s
6622 * dprc_add_new_devices - Adds devices to the logical bus for a DPRC
6623 *
6624 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6625 + * @driver_override: driver override to apply to new objects found in the
6626 + * DPRC, or NULL, if none.
6627 * @obj_desc_array: array of device descriptors for child devices currently
6628 * present in the physical DPRC.
6629 * @num_child_objects_in_mc: number of entries in obj_desc_array
6630 @@ -169,6 +171,7 @@ static void check_plugged_state_change(s
6631 * in the physical DPRC.
6632 */
6633 static void dprc_add_new_devices(struct fsl_mc_device *mc_bus_dev,
6634 + const char *driver_override,
6635 struct dprc_obj_desc *obj_desc_array,
6636 int num_child_objects_in_mc)
6637 {
6638 @@ -188,11 +191,12 @@ static void dprc_add_new_devices(struct
6639 child_dev = fsl_mc_device_lookup(obj_desc, mc_bus_dev);
6640 if (child_dev) {
6641 check_plugged_state_change(child_dev, obj_desc);
6642 + put_device(&child_dev->dev);
6643 continue;
6644 }
6645
6646 error = fsl_mc_device_add(obj_desc, NULL, &mc_bus_dev->dev,
6647 - &child_dev);
6648 + driver_override, &child_dev);
6649 if (error < 0)
6650 continue;
6651 }
6652 @@ -202,6 +206,8 @@ static void dprc_add_new_devices(struct
6653 * dprc_scan_objects - Discover objects in a DPRC
6654 *
6655 * @mc_bus_dev: pointer to the fsl-mc device that represents a DPRC object
6656 + * @driver_override: driver override to apply to new objects found in the
6657 + * DPRC, or NULL, if none.
6658 * @total_irq_count: total number of IRQs needed by objects in the DPRC.
6659 *
6660 * Detects objects added and removed from a DPRC and synchronizes the
6661 @@ -217,6 +223,7 @@ static void dprc_add_new_devices(struct
6662 * of the device drivers for the non-allocatable devices.
6663 */
6664 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
6665 + const char *driver_override,
6666 unsigned int *total_irq_count)
6667 {
6668 int num_child_objects;
6669 @@ -297,7 +304,7 @@ int dprc_scan_objects(struct fsl_mc_devi
6670 dprc_remove_devices(mc_bus_dev, child_obj_desc_array,
6671 num_child_objects);
6672
6673 - dprc_add_new_devices(mc_bus_dev, child_obj_desc_array,
6674 + dprc_add_new_devices(mc_bus_dev, driver_override, child_obj_desc_array,
6675 num_child_objects);
6676
6677 if (child_obj_desc_array)
6678 @@ -328,7 +335,7 @@ int dprc_scan_container(struct fsl_mc_de
6679 * Discover objects in the DPRC:
6680 */
6681 mutex_lock(&mc_bus->scan_mutex);
6682 - error = dprc_scan_objects(mc_bus_dev, &irq_count);
6683 + error = dprc_scan_objects(mc_bus_dev, NULL, &irq_count);
6684 mutex_unlock(&mc_bus->scan_mutex);
6685 if (error < 0)
6686 goto error;
6687 @@ -415,7 +422,7 @@ static irqreturn_t dprc_irq0_handler_thr
6688 DPRC_IRQ_EVENT_OBJ_CREATED)) {
6689 unsigned int irq_count;
6690
6691 - error = dprc_scan_objects(mc_dev, &irq_count);
6692 + error = dprc_scan_objects(mc_dev, NULL, &irq_count);
6693 if (error < 0) {
6694 /*
6695 * If the error is -ENXIO, we ignore it, as it indicates
6696 @@ -505,7 +512,7 @@ static int register_dprc_irq_handler(str
6697 dprc_irq0_handler,
6698 dprc_irq0_handler_thread,
6699 IRQF_NO_SUSPEND | IRQF_ONESHOT,
6700 - "FSL MC DPRC irq0",
6701 + dev_name(&mc_dev->dev),
6702 &mc_dev->dev);
6703 if (error < 0) {
6704 dev_err(&mc_dev->dev,
6705 @@ -597,6 +604,7 @@ static int dprc_probe(struct fsl_mc_devi
6706 struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev);
6707 bool mc_io_created = false;
6708 bool msi_domain_set = false;
6709 + u16 major_ver, minor_ver;
6710
6711 if (WARN_ON(strcmp(mc_dev->obj_desc.type, "dprc") != 0))
6712 return -EINVAL;
6713 @@ -669,13 +677,21 @@ static int dprc_probe(struct fsl_mc_devi
6714 goto error_cleanup_open;
6715 }
6716
6717 - if (mc_bus->dprc_attr.version.major < DPRC_MIN_VER_MAJOR ||
6718 - (mc_bus->dprc_attr.version.major == DPRC_MIN_VER_MAJOR &&
6719 - mc_bus->dprc_attr.version.minor < DPRC_MIN_VER_MINOR)) {
6720 + error = dprc_get_api_version(mc_dev->mc_io, 0,
6721 + &major_ver,
6722 + &minor_ver);
6723 + if (error < 0) {
6724 + dev_err(&mc_dev->dev, "dprc_get_api_version() failed: %d\n",
6725 + error);
6726 + goto error_cleanup_open;
6727 + }
6728 +
6729 + if (major_ver < DPRC_MIN_VER_MAJOR ||
6730 + (major_ver == DPRC_MIN_VER_MAJOR &&
6731 + minor_ver < DPRC_MIN_VER_MINOR)) {
6732 dev_err(&mc_dev->dev,
6733 "ERROR: DPRC version %d.%d not supported\n",
6734 - mc_bus->dprc_attr.version.major,
6735 - mc_bus->dprc_attr.version.minor);
6736 + major_ver, minor_ver);
6737 error = -ENOTSUPP;
6738 goto error_cleanup_open;
6739 }
6740 --- a/drivers/staging/fsl-mc/bus/dprc.c
6741 +++ b/drivers/staging/fsl-mc/bus/dprc.c
6742 @@ -1,4 +1,5 @@
6743 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
6744 +/*
6745 + * Copyright 2013-2016 Freescale Semiconductor Inc.
6746 *
6747 * Redistribution and use in source and binary forms, with or without
6748 * modification, are permitted provided that the following conditions are met:
6749 @@ -11,7 +12,6 @@
6750 * names of any contributors may be used to endorse or promote products
6751 * derived from this software without specific prior written permission.
6752 *
6753 - *
6754 * ALTERNATIVELY, this software may be distributed under the terms of the
6755 * GNU General Public License ("GPL") as published by the Free Software
6756 * Foundation, either version 2 of that License or (at your option) any
6757 @@ -100,93 +100,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
6758 EXPORT_SYMBOL(dprc_close);
6759
6760 /**
6761 - * dprc_create_container() - Create child container
6762 - * @mc_io: Pointer to MC portal's I/O object
6763 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6764 - * @token: Token of DPRC object
6765 - * @cfg: Child container configuration
6766 - * @child_container_id: Returned child container ID
6767 - * @child_portal_offset: Returned child portal offset from MC portal base
6768 - *
6769 - * Return: '0' on Success; Error code otherwise.
6770 - */
6771 -int dprc_create_container(struct fsl_mc_io *mc_io,
6772 - u32 cmd_flags,
6773 - u16 token,
6774 - struct dprc_cfg *cfg,
6775 - int *child_container_id,
6776 - u64 *child_portal_offset)
6777 -{
6778 - struct mc_command cmd = { 0 };
6779 - struct dprc_cmd_create_container *cmd_params;
6780 - struct dprc_rsp_create_container *rsp_params;
6781 - int err;
6782 -
6783 - /* prepare command */
6784 - cmd_params = (struct dprc_cmd_create_container *)cmd.params;
6785 - cmd_params->options = cpu_to_le32(cfg->options);
6786 - cmd_params->icid = cpu_to_le16(cfg->icid);
6787 - cmd_params->portal_id = cpu_to_le32(cfg->portal_id);
6788 - strncpy(cmd_params->label, cfg->label, 16);
6789 - cmd_params->label[15] = '\0';
6790 -
6791 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT,
6792 - cmd_flags, token);
6793 -
6794 - /* send command to mc*/
6795 - err = mc_send_command(mc_io, &cmd);
6796 - if (err)
6797 - return err;
6798 -
6799 - /* retrieve response parameters */
6800 - rsp_params = (struct dprc_rsp_create_container *)cmd.params;
6801 - *child_container_id = le32_to_cpu(rsp_params->child_container_id);
6802 - *child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr);
6803 -
6804 - return 0;
6805 -}
6806 -
6807 -/**
6808 - * dprc_destroy_container() - Destroy child container.
6809 - * @mc_io: Pointer to MC portal's I/O object
6810 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6811 - * @token: Token of DPRC object
6812 - * @child_container_id: ID of the container to destroy
6813 - *
6814 - * This function terminates the child container, so following this call the
6815 - * child container ID becomes invalid.
6816 - *
6817 - * Notes:
6818 - * - All resources and objects of the destroyed container are returned to the
6819 - * parent container or destroyed if were created be the destroyed container.
6820 - * - This function destroy all the child containers of the specified
6821 - * container prior to destroying the container itself.
6822 - *
6823 - * warning: Only the parent container is allowed to destroy a child policy
6824 - * Container 0 can't be destroyed
6825 - *
6826 - * Return: '0' on Success; Error code otherwise.
6827 - *
6828 - */
6829 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
6830 - u32 cmd_flags,
6831 - u16 token,
6832 - int child_container_id)
6833 -{
6834 - struct mc_command cmd = { 0 };
6835 - struct dprc_cmd_destroy_container *cmd_params;
6836 -
6837 - /* prepare command */
6838 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT,
6839 - cmd_flags, token);
6840 - cmd_params = (struct dprc_cmd_destroy_container *)cmd.params;
6841 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6842 -
6843 - /* send command to mc*/
6844 - return mc_send_command(mc_io, &cmd);
6845 -}
6846 -
6847 -/**
6848 * dprc_reset_container - Reset child container.
6849 * @mc_io: Pointer to MC portal's I/O object
6850 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6851 @@ -565,279 +478,6 @@ int dprc_get_attributes(struct fsl_mc_io
6852 attr->icid = le16_to_cpu(rsp_params->icid);
6853 attr->options = le32_to_cpu(rsp_params->options);
6854 attr->portal_id = le32_to_cpu(rsp_params->portal_id);
6855 - attr->version.major = le16_to_cpu(rsp_params->version_major);
6856 - attr->version.minor = le16_to_cpu(rsp_params->version_minor);
6857 -
6858 - return 0;
6859 -}
6860 -
6861 -/**
6862 - * dprc_set_res_quota() - Set allocation policy for a specific resource/object
6863 - * type in a child container
6864 - * @mc_io: Pointer to MC portal's I/O object
6865 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6866 - * @token: Token of DPRC object
6867 - * @child_container_id: ID of the child container
6868 - * @type: Resource/object type
6869 - * @quota: Sets the maximum number of resources of the selected type
6870 - * that the child container is allowed to allocate from its parent;
6871 - * when quota is set to -1, the policy is the same as container's
6872 - * general policy.
6873 - *
6874 - * Allocation policy determines whether or not a container may allocate
6875 - * resources from its parent. Each container has a 'global' allocation policy
6876 - * that is set when the container is created.
6877 - *
6878 - * This function sets allocation policy for a specific resource type.
6879 - * The default policy for all resource types matches the container's 'global'
6880 - * allocation policy.
6881 - *
6882 - * Return: '0' on Success; Error code otherwise.
6883 - *
6884 - * @warning Only the parent container is allowed to change a child policy.
6885 - */
6886 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
6887 - u32 cmd_flags,
6888 - u16 token,
6889 - int child_container_id,
6890 - char *type,
6891 - u16 quota)
6892 -{
6893 - struct mc_command cmd = { 0 };
6894 - struct dprc_cmd_set_res_quota *cmd_params;
6895 -
6896 - /* prepare command */
6897 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_RES_QUOTA,
6898 - cmd_flags, token);
6899 - cmd_params = (struct dprc_cmd_set_res_quota *)cmd.params;
6900 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6901 - cmd_params->quota = cpu_to_le16(quota);
6902 - strncpy(cmd_params->type, type, 16);
6903 - cmd_params->type[15] = '\0';
6904 -
6905 - /* send command to mc*/
6906 - return mc_send_command(mc_io, &cmd);
6907 -}
6908 -
6909 -/**
6910 - * dprc_get_res_quota() - Gets the allocation policy of a specific
6911 - * resource/object type in a child container
6912 - * @mc_io: Pointer to MC portal's I/O object
6913 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6914 - * @token: Token of DPRC object
6915 - * @child_container_id; ID of the child container
6916 - * @type: resource/object type
6917 - * @quota: Returnes the maximum number of resources of the selected type
6918 - * that the child container is allowed to allocate from the parent;
6919 - * when quota is set to -1, the policy is the same as container's
6920 - * general policy.
6921 - *
6922 - * Return: '0' on Success; Error code otherwise.
6923 - */
6924 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
6925 - u32 cmd_flags,
6926 - u16 token,
6927 - int child_container_id,
6928 - char *type,
6929 - u16 *quota)
6930 -{
6931 - struct mc_command cmd = { 0 };
6932 - struct dprc_cmd_get_res_quota *cmd_params;
6933 - struct dprc_rsp_get_res_quota *rsp_params;
6934 - int err;
6935 -
6936 - /* prepare command */
6937 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_QUOTA,
6938 - cmd_flags, token);
6939 - cmd_params = (struct dprc_cmd_get_res_quota *)cmd.params;
6940 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
6941 - strncpy(cmd_params->type, type, 16);
6942 - cmd_params->type[15] = '\0';
6943 -
6944 - /* send command to mc*/
6945 - err = mc_send_command(mc_io, &cmd);
6946 - if (err)
6947 - return err;
6948 -
6949 - /* retrieve response parameters */
6950 - rsp_params = (struct dprc_rsp_get_res_quota *)cmd.params;
6951 - *quota = le16_to_cpu(rsp_params->quota);
6952 -
6953 - return 0;
6954 -}
6955 -
6956 -/**
6957 - * dprc_assign() - Assigns objects or resource to a child container.
6958 - * @mc_io: Pointer to MC portal's I/O object
6959 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
6960 - * @token: Token of DPRC object
6961 - * @container_id: ID of the child container
6962 - * @res_req: Describes the type and amount of resources to
6963 - * assign to the given container
6964 - *
6965 - * Assignment is usually done by a parent (this DPRC) to one of its child
6966 - * containers.
6967 - *
6968 - * According to the DPRC allocation policy, the assigned resources may be taken
6969 - * (allocated) from the container's ancestors, if not enough resources are
6970 - * available in the container itself.
6971 - *
6972 - * The type of assignment depends on the dprc_res_req options, as follows:
6973 - * - DPRC_RES_REQ_OPT_EXPLICIT: indicates that assigned resources should have
6974 - * the explicit base ID specified at the id_base_align field of res_req.
6975 - * - DPRC_RES_REQ_OPT_ALIGNED: indicates that the assigned resources should be
6976 - * aligned to the value given at id_base_align field of res_req.
6977 - * - DPRC_RES_REQ_OPT_PLUGGED: Relevant only for object assignment,
6978 - * and indicates that the object must be set to the plugged state.
6979 - *
6980 - * A container may use this function with its own ID in order to change a
6981 - * object state to plugged or unplugged.
6982 - *
6983 - * If IRQ information has been set in the child DPRC, it will signal an
6984 - * interrupt following every change in its object assignment.
6985 - *
6986 - * Return: '0' on Success; Error code otherwise.
6987 - */
6988 -int dprc_assign(struct fsl_mc_io *mc_io,
6989 - u32 cmd_flags,
6990 - u16 token,
6991 - int container_id,
6992 - struct dprc_res_req *res_req)
6993 -{
6994 - struct mc_command cmd = { 0 };
6995 - struct dprc_cmd_assign *cmd_params;
6996 -
6997 - /* prepare command */
6998 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_ASSIGN,
6999 - cmd_flags, token);
7000 - cmd_params = (struct dprc_cmd_assign *)cmd.params;
7001 - cmd_params->container_id = cpu_to_le32(container_id);
7002 - cmd_params->options = cpu_to_le32(res_req->options);
7003 - cmd_params->num = cpu_to_le32(res_req->num);
7004 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
7005 - strncpy(cmd_params->type, res_req->type, 16);
7006 - cmd_params->type[15] = '\0';
7007 -
7008 - /* send command to mc*/
7009 - return mc_send_command(mc_io, &cmd);
7010 -}
7011 -
7012 -/**
7013 - * dprc_unassign() - Un-assigns objects or resources from a child container
7014 - * and moves them into this (parent) DPRC.
7015 - * @mc_io: Pointer to MC portal's I/O object
7016 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7017 - * @token: Token of DPRC object
7018 - * @child_container_id: ID of the child container
7019 - * @res_req: Describes the type and amount of resources to un-assign from
7020 - * the child container
7021 - *
7022 - * Un-assignment of objects can succeed only if the object is not in the
7023 - * plugged or opened state.
7024 - *
7025 - * Return: '0' on Success; Error code otherwise.
7026 - */
7027 -int dprc_unassign(struct fsl_mc_io *mc_io,
7028 - u32 cmd_flags,
7029 - u16 token,
7030 - int child_container_id,
7031 - struct dprc_res_req *res_req)
7032 -{
7033 - struct mc_command cmd = { 0 };
7034 - struct dprc_cmd_unassign *cmd_params;
7035 -
7036 - /* prepare command */
7037 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_UNASSIGN,
7038 - cmd_flags,
7039 - token);
7040 - cmd_params = (struct dprc_cmd_unassign *)cmd.params;
7041 - cmd_params->child_container_id = cpu_to_le32(child_container_id);
7042 - cmd_params->options = cpu_to_le32(res_req->options);
7043 - cmd_params->num = cpu_to_le32(res_req->num);
7044 - cmd_params->id_base_align = cpu_to_le32(res_req->id_base_align);
7045 - strncpy(cmd_params->type, res_req->type, 16);
7046 - cmd_params->type[15] = '\0';
7047 -
7048 - /* send command to mc*/
7049 - return mc_send_command(mc_io, &cmd);
7050 -}
7051 -
7052 -/**
7053 - * dprc_get_pool_count() - Get the number of dprc's pools
7054 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7055 - * @mc_io: Pointer to MC portal's I/O object
7056 - * @token: Token of DPRC object
7057 - * @pool_count: Returned number of resource pools in the dprc
7058 - *
7059 - * Return: '0' on Success; Error code otherwise.
7060 - */
7061 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
7062 - u32 cmd_flags,
7063 - u16 token,
7064 - int *pool_count)
7065 -{
7066 - struct mc_command cmd = { 0 };
7067 - struct dprc_rsp_get_pool_count *rsp_params;
7068 - int err;
7069 -
7070 - /* prepare command */
7071 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL_COUNT,
7072 - cmd_flags, token);
7073 -
7074 - /* send command to mc*/
7075 - err = mc_send_command(mc_io, &cmd);
7076 - if (err)
7077 - return err;
7078 -
7079 - /* retrieve response parameters */
7080 - rsp_params = (struct dprc_rsp_get_pool_count *)cmd.params;
7081 - *pool_count = le32_to_cpu(rsp_params->pool_count);
7082 -
7083 - return 0;
7084 -}
7085 -
7086 -/**
7087 - * dprc_get_pool() - Get the type (string) of a certain dprc's pool
7088 - * @mc_io: Pointer to MC portal's I/O object
7089 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7090 - * @token: Token of DPRC object
7091 - * @pool_index; Index of the pool to be queried (< pool_count)
7092 - * @type: The type of the pool
7093 - *
7094 - * The pool types retrieved one by one by incrementing
7095 - * pool_index up to (not including) the value of pool_count returned
7096 - * from dprc_get_pool_count(). dprc_get_pool_count() must
7097 - * be called prior to dprc_get_pool().
7098 - *
7099 - * Return: '0' on Success; Error code otherwise.
7100 - */
7101 -int dprc_get_pool(struct fsl_mc_io *mc_io,
7102 - u32 cmd_flags,
7103 - u16 token,
7104 - int pool_index,
7105 - char *type)
7106 -{
7107 - struct mc_command cmd = { 0 };
7108 - struct dprc_cmd_get_pool *cmd_params;
7109 - struct dprc_rsp_get_pool *rsp_params;
7110 - int err;
7111 -
7112 - /* prepare command */
7113 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_POOL,
7114 - cmd_flags,
7115 - token);
7116 - cmd_params = (struct dprc_cmd_get_pool *)cmd.params;
7117 - cmd_params->pool_index = cpu_to_le32(pool_index);
7118 -
7119 - /* send command to mc*/
7120 - err = mc_send_command(mc_io, &cmd);
7121 - if (err)
7122 - return err;
7123 -
7124 - /* retrieve response parameters */
7125 - rsp_params = (struct dprc_rsp_get_pool *)cmd.params;
7126 - strncpy(type, rsp_params->type, 16);
7127 - type[15] = '\0';
7128
7129 return 0;
7130 }
7131 @@ -934,64 +574,6 @@ int dprc_get_obj(struct fsl_mc_io *mc_io
7132 EXPORT_SYMBOL(dprc_get_obj);
7133
7134 /**
7135 - * dprc_get_obj_desc() - Get object descriptor.
7136 - *
7137 - * @mc_io: Pointer to MC portal's I/O object
7138 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7139 - * @token: Token of DPRC object
7140 - * @obj_type: The type of the object to get its descriptor.
7141 - * @obj_id: The id of the object to get its descriptor
7142 - * @obj_desc: The returned descriptor to fill and return to the user
7143 - *
7144 - * Return: '0' on Success; Error code otherwise.
7145 - *
7146 - */
7147 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
7148 - u32 cmd_flags,
7149 - u16 token,
7150 - char *obj_type,
7151 - int obj_id,
7152 - struct dprc_obj_desc *obj_desc)
7153 -{
7154 - struct mc_command cmd = { 0 };
7155 - struct dprc_cmd_get_obj_desc *cmd_params;
7156 - struct dprc_rsp_get_obj_desc *rsp_params;
7157 - int err;
7158 -
7159 - /* prepare command */
7160 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_DESC,
7161 - cmd_flags,
7162 - token);
7163 - cmd_params = (struct dprc_cmd_get_obj_desc *)cmd.params;
7164 - cmd_params->obj_id = cpu_to_le32(obj_id);
7165 - strncpy(cmd_params->type, obj_type, 16);
7166 - cmd_params->type[15] = '\0';
7167 -
7168 - /* send command to mc*/
7169 - err = mc_send_command(mc_io, &cmd);
7170 - if (err)
7171 - return err;
7172 -
7173 - /* retrieve response parameters */
7174 - rsp_params = (struct dprc_rsp_get_obj_desc *)cmd.params;
7175 - obj_desc->id = le32_to_cpu(rsp_params->id);
7176 - obj_desc->vendor = le16_to_cpu(rsp_params->vendor);
7177 - obj_desc->irq_count = rsp_params->irq_count;
7178 - obj_desc->region_count = rsp_params->region_count;
7179 - obj_desc->state = le32_to_cpu(rsp_params->state);
7180 - obj_desc->ver_major = le16_to_cpu(rsp_params->version_major);
7181 - obj_desc->ver_minor = le16_to_cpu(rsp_params->version_minor);
7182 - obj_desc->flags = le16_to_cpu(rsp_params->flags);
7183 - strncpy(obj_desc->type, rsp_params->type, 16);
7184 - obj_desc->type[15] = '\0';
7185 - strncpy(obj_desc->label, rsp_params->label, 16);
7186 - obj_desc->label[15] = '\0';
7187 -
7188 - return 0;
7189 -}
7190 -EXPORT_SYMBOL(dprc_get_obj_desc);
7191 -
7192 -/**
7193 * dprc_set_obj_irq() - Set IRQ information for object to trigger an interrupt.
7194 * @mc_io: Pointer to MC portal's I/O object
7195 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7196 @@ -1130,52 +712,6 @@ int dprc_get_res_count(struct fsl_mc_io
7197 EXPORT_SYMBOL(dprc_get_res_count);
7198
7199 /**
7200 - * dprc_get_res_ids() - Obtains IDs of free resources in the container
7201 - * @mc_io: Pointer to MC portal's I/O object
7202 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7203 - * @token: Token of DPRC object
7204 - * @type: pool type
7205 - * @range_desc: range descriptor
7206 - *
7207 - * Return: '0' on Success; Error code otherwise.
7208 - */
7209 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
7210 - u32 cmd_flags,
7211 - u16 token,
7212 - char *type,
7213 - struct dprc_res_ids_range_desc *range_desc)
7214 -{
7215 - struct mc_command cmd = { 0 };
7216 - struct dprc_cmd_get_res_ids *cmd_params;
7217 - struct dprc_rsp_get_res_ids *rsp_params;
7218 - int err;
7219 -
7220 - /* prepare command */
7221 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS,
7222 - cmd_flags, token);
7223 - cmd_params = (struct dprc_cmd_get_res_ids *)cmd.params;
7224 - cmd_params->iter_status = range_desc->iter_status;
7225 - cmd_params->base_id = cpu_to_le32(range_desc->base_id);
7226 - cmd_params->last_id = cpu_to_le32(range_desc->last_id);
7227 - strncpy(cmd_params->type, type, 16);
7228 - cmd_params->type[15] = '\0';
7229 -
7230 - /* send command to mc*/
7231 - err = mc_send_command(mc_io, &cmd);
7232 - if (err)
7233 - return err;
7234 -
7235 - /* retrieve response parameters */
7236 - rsp_params = (struct dprc_rsp_get_res_ids *)cmd.params;
7237 - range_desc->iter_status = rsp_params->iter_status;
7238 - range_desc->base_id = le32_to_cpu(rsp_params->base_id);
7239 - range_desc->last_id = le32_to_cpu(rsp_params->last_id);
7240 -
7241 - return 0;
7242 -}
7243 -EXPORT_SYMBOL(dprc_get_res_ids);
7244 -
7245 -/**
7246 * dprc_get_obj_region() - Get region information for a specified object.
7247 * @mc_io: Pointer to MC portal's I/O object
7248 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7249 @@ -1216,160 +752,66 @@ int dprc_get_obj_region(struct fsl_mc_io
7250
7251 /* retrieve response parameters */
7252 rsp_params = (struct dprc_rsp_get_obj_region *)cmd.params;
7253 - region_desc->base_offset = le64_to_cpu(rsp_params->base_addr);
7254 + region_desc->base_offset = le32_to_cpu(rsp_params->base_addr);
7255 region_desc->size = le32_to_cpu(rsp_params->size);
7256 + region_desc->type = rsp_params->type;
7257 + region_desc->flags = le32_to_cpu(rsp_params->flags);
7258
7259 return 0;
7260 }
7261 EXPORT_SYMBOL(dprc_get_obj_region);
7262
7263 /**
7264 - * dprc_set_obj_label() - Set object label.
7265 - * @mc_io: Pointer to MC portal's I/O object
7266 + * dprc_get_api_version - Get Data Path Resource Container API version
7267 + * @mc_io: Pointer to Mc portal's I/O object
7268 * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7269 - * @token: Token of DPRC object
7270 - * @obj_type: Object's type
7271 - * @obj_id: Object's ID
7272 - * @label: The required label. The maximum length is 16 chars.
7273 + * @major_ver: Major version of Data Path Resource Container API
7274 + * @minor_ver: Minor version of Data Path Resource Container API
7275 *
7276 * Return: '0' on Success; Error code otherwise.
7277 */
7278 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
7279 - u32 cmd_flags,
7280 - u16 token,
7281 - char *obj_type,
7282 - int obj_id,
7283 - char *label)
7284 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
7285 + u32 cmd_flags,
7286 + u16 *major_ver,
7287 + u16 *minor_ver)
7288 {
7289 struct mc_command cmd = { 0 };
7290 - struct dprc_cmd_set_obj_label *cmd_params;
7291 + int err;
7292
7293 /* prepare command */
7294 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_SET_OBJ_LABEL,
7295 - cmd_flags,
7296 - token);
7297 - cmd_params = (struct dprc_cmd_set_obj_label *)cmd.params;
7298 - cmd_params->obj_id = cpu_to_le32(obj_id);
7299 - strncpy(cmd_params->label, label, 16);
7300 - cmd_params->label[15] = '\0';
7301 - strncpy(cmd_params->obj_type, obj_type, 16);
7302 - cmd_params->obj_type[15] = '\0';
7303 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_API_VERSION,
7304 + cmd_flags, 0);
7305
7306 - /* send command to mc*/
7307 - return mc_send_command(mc_io, &cmd);
7308 -}
7309 -EXPORT_SYMBOL(dprc_set_obj_label);
7310 -
7311 -/**
7312 - * dprc_connect() - Connect two endpoints to create a network link between them
7313 - * @mc_io: Pointer to MC portal's I/O object
7314 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7315 - * @token: Token of DPRC object
7316 - * @endpoint1: Endpoint 1 configuration parameters
7317 - * @endpoint2: Endpoint 2 configuration parameters
7318 - * @cfg: Connection configuration. The connection configuration is ignored for
7319 - * connections made to DPMAC objects, where rate is retrieved from the
7320 - * MAC configuration.
7321 - *
7322 - * Return: '0' on Success; Error code otherwise.
7323 - */
7324 -int dprc_connect(struct fsl_mc_io *mc_io,
7325 - u32 cmd_flags,
7326 - u16 token,
7327 - const struct dprc_endpoint *endpoint1,
7328 - const struct dprc_endpoint *endpoint2,
7329 - const struct dprc_connection_cfg *cfg)
7330 -{
7331 - struct mc_command cmd = { 0 };
7332 - struct dprc_cmd_connect *cmd_params;
7333 + /* send command to mc */
7334 + err = mc_send_command(mc_io, &cmd);
7335 + if (err)
7336 + return err;
7337
7338 - /* prepare command */
7339 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT,
7340 - cmd_flags,
7341 - token);
7342 - cmd_params = (struct dprc_cmd_connect *)cmd.params;
7343 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7344 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7345 - cmd_params->ep2_id = cpu_to_le32(endpoint2->id);
7346 - cmd_params->ep2_interface_id = cpu_to_le32(endpoint2->if_id);
7347 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7348 - cmd_params->ep1_type[15] = '\0';
7349 - cmd_params->max_rate = cpu_to_le32(cfg->max_rate);
7350 - cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate);
7351 - strncpy(cmd_params->ep2_type, endpoint2->type, 16);
7352 - cmd_params->ep2_type[15] = '\0';
7353 + /* retrieve response parameters */
7354 + mc_cmd_read_api_version(&cmd, major_ver, minor_ver);
7355
7356 - /* send command to mc*/
7357 - return mc_send_command(mc_io, &cmd);
7358 + return 0;
7359 }
7360
7361 /**
7362 - * dprc_disconnect() - Disconnect one endpoint to remove its network connection
7363 - * @mc_io: Pointer to MC portal's I/O object
7364 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7365 - * @token: Token of DPRC object
7366 - * @endpoint: Endpoint configuration parameters
7367 + * dprc_get_container_id - Get container ID associated with a given portal.
7368 + * @mc_io: Pointer to Mc portal's I/O object
7369 + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7370 + * @container_id: Requested container id
7371 *
7372 * Return: '0' on Success; Error code otherwise.
7373 */
7374 -int dprc_disconnect(struct fsl_mc_io *mc_io,
7375 - u32 cmd_flags,
7376 - u16 token,
7377 - const struct dprc_endpoint *endpoint)
7378 -{
7379 - struct mc_command cmd = { 0 };
7380 - struct dprc_cmd_disconnect *cmd_params;
7381 -
7382 - /* prepare command */
7383 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT,
7384 - cmd_flags,
7385 - token);
7386 - cmd_params = (struct dprc_cmd_disconnect *)cmd.params;
7387 - cmd_params->id = cpu_to_le32(endpoint->id);
7388 - cmd_params->interface_id = cpu_to_le32(endpoint->if_id);
7389 - strncpy(cmd_params->type, endpoint->type, 16);
7390 - cmd_params->type[15] = '\0';
7391 -
7392 - /* send command to mc*/
7393 - return mc_send_command(mc_io, &cmd);
7394 -}
7395 -
7396 -/**
7397 - * dprc_get_connection() - Get connected endpoint and link status if connection
7398 - * exists.
7399 - * @mc_io: Pointer to MC portal's I/O object
7400 - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_'
7401 - * @token: Token of DPRC object
7402 - * @endpoint1: Endpoint 1 configuration parameters
7403 - * @endpoint2: Returned endpoint 2 configuration parameters
7404 - * @state: Returned link state:
7405 - * 1 - link is up;
7406 - * 0 - link is down;
7407 - * -1 - no connection (endpoint2 information is irrelevant)
7408 - *
7409 - * Return: '0' on Success; -ENAVAIL if connection does not exist.
7410 - */
7411 -int dprc_get_connection(struct fsl_mc_io *mc_io,
7412 - u32 cmd_flags,
7413 - u16 token,
7414 - const struct dprc_endpoint *endpoint1,
7415 - struct dprc_endpoint *endpoint2,
7416 - int *state)
7417 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
7418 + u32 cmd_flags,
7419 + int *container_id)
7420 {
7421 struct mc_command cmd = { 0 };
7422 - struct dprc_cmd_get_connection *cmd_params;
7423 - struct dprc_rsp_get_connection *rsp_params;
7424 int err;
7425
7426 /* prepare command */
7427 - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION,
7428 + cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONT_ID,
7429 cmd_flags,
7430 - token);
7431 - cmd_params = (struct dprc_cmd_get_connection *)cmd.params;
7432 - cmd_params->ep1_id = cpu_to_le32(endpoint1->id);
7433 - cmd_params->ep1_interface_id = cpu_to_le32(endpoint1->if_id);
7434 - strncpy(cmd_params->ep1_type, endpoint1->type, 16);
7435 - cmd_params->ep1_type[15] = '\0';
7436 + 0);
7437
7438 /* send command to mc*/
7439 err = mc_send_command(mc_io, &cmd);
7440 @@ -1377,12 +819,7 @@ int dprc_get_connection(struct fsl_mc_io
7441 return err;
7442
7443 /* retrieve response parameters */
7444 - rsp_params = (struct dprc_rsp_get_connection *)cmd.params;
7445 - endpoint2->id = le32_to_cpu(rsp_params->ep2_id);
7446 - endpoint2->if_id = le32_to_cpu(rsp_params->ep2_interface_id);
7447 - strncpy(endpoint2->type, rsp_params->ep2_type, 16);
7448 - endpoint2->type[15] = '\0';
7449 - *state = le32_to_cpu(rsp_params->state);
7450 + *container_id = (int)mc_cmd_read_object_id(&cmd);
7451
7452 return 0;
7453 }
7454 --- a/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7455 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-allocator.c
7456 @@ -1,7 +1,7 @@
7457 /*
7458 - * Freescale MC object device allocator driver
7459 + * fsl-mc object allocator driver
7460 *
7461 - * Copyright (C) 2013 Freescale Semiconductor, Inc.
7462 + * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
7463 *
7464 * This file is licensed under the terms of the GNU General Public
7465 * License version 2. This program is licensed "as is" without any
7466 @@ -12,9 +12,9 @@
7467 #include <linux/msi.h>
7468 #include "../include/mc-bus.h"
7469 #include "../include/mc-sys.h"
7470 -#include "../include/dpbp-cmd.h"
7471 -#include "../include/dpcon-cmd.h"
7472
7473 +#include "dpbp-cmd.h"
7474 +#include "dpcon-cmd.h"
7475 #include "fsl-mc-private.h"
7476
7477 #define FSL_MC_IS_ALLOCATABLE(_obj_type) \
7478 @@ -23,15 +23,12 @@
7479 strcmp(_obj_type, "dpcon") == 0)
7480
7481 /**
7482 - * fsl_mc_resource_pool_add_device - add allocatable device to a resource
7483 - * pool of a given MC bus
7484 + * fsl_mc_resource_pool_add_device - add allocatable object to a resource
7485 + * pool of a given fsl-mc bus
7486 *
7487 - * @mc_bus: pointer to the MC bus
7488 - * @pool_type: MC bus pool type
7489 - * @mc_dev: Pointer to allocatable MC object device
7490 - *
7491 - * It adds an allocatable MC object device to a container's resource pool of
7492 - * the given resource type
7493 + * @mc_bus: pointer to the fsl-mc bus
7494 + * @pool_type: pool type
7495 + * @mc_dev: pointer to allocatable fsl-mc device
7496 */
7497 static int __must_check fsl_mc_resource_pool_add_device(struct fsl_mc_bus
7498 *mc_bus,
7499 @@ -95,10 +92,10 @@ out:
7500 * fsl_mc_resource_pool_remove_device - remove an allocatable device from a
7501 * resource pool
7502 *
7503 - * @mc_dev: Pointer to allocatable MC object device
7504 + * @mc_dev: pointer to allocatable fsl-mc device
7505 *
7506 - * It permanently removes an allocatable MC object device from the resource
7507 - * pool, the device is currently in, as long as it is in the pool's free list.
7508 + * It permanently removes an allocatable fsl-mc device from the resource
7509 + * pool. It's an error if the device is in use.
7510 */
7511 static int __must_check fsl_mc_resource_pool_remove_device(struct fsl_mc_device
7512 *mc_dev)
7513 @@ -255,17 +252,18 @@ out_unlock:
7514 EXPORT_SYMBOL_GPL(fsl_mc_resource_free);
7515
7516 /**
7517 - * fsl_mc_object_allocate - Allocates a MC object device of the given
7518 - * pool type from a given MC bus
7519 + * fsl_mc_object_allocate - Allocates an fsl-mc object of the given
7520 + * pool type from a given fsl-mc bus instance
7521 *
7522 - * @mc_dev: MC device for which the MC object device is to be allocated
7523 - * @pool_type: MC bus resource pool type
7524 - * @new_mc_dev: Pointer to area where the pointer to the allocated
7525 - * MC object device is to be returned
7526 + * @mc_dev: fsl-mc device which is used in conjunction with the
7527 + * allocated object
7528 + * @pool_type: pool type
7529 + * @new_mc_dev: pointer to area where the pointer to the allocated device
7530 + * is to be returned
7531 *
7532 - * This function allocates a MC object device from the device's parent DPRC,
7533 - * from the corresponding MC bus' pool of allocatable MC object devices of
7534 - * the given resource type. mc_dev cannot be a DPRC itself.
7535 + * Allocatable objects are always used in conjunction with some functional
7536 + * device. This function allocates an object of the specified type from
7537 + * the DPRC containing the functional device.
7538 *
7539 * NOTE: pool_type must be different from FSL_MC_POOL_MCP, since MC
7540 * portals are allocated using fsl_mc_portal_allocate(), instead of
7541 @@ -312,10 +310,9 @@ error:
7542 EXPORT_SYMBOL_GPL(fsl_mc_object_allocate);
7543
7544 /**
7545 - * fsl_mc_object_free - Returns an allocatable MC object device to the
7546 - * corresponding resource pool of a given MC bus.
7547 - *
7548 - * @mc_adev: Pointer to the MC object device
7549 + * fsl_mc_object_free - Returns an fsl-mc object to the resource
7550 + * pool where it came from.
7551 + * @mc_adev: Pointer to the fsl-mc device
7552 */
7553 void fsl_mc_object_free(struct fsl_mc_device *mc_adev)
7554 {
7555 @@ -332,8 +329,14 @@ void fsl_mc_object_free(struct fsl_mc_de
7556 EXPORT_SYMBOL_GPL(fsl_mc_object_free);
7557
7558 /*
7559 - * Initialize the interrupt pool associated with a MC bus.
7560 - * It allocates a block of IRQs from the GIC-ITS
7561 + * A DPRC and the devices in the DPRC all share the same GIC-ITS device
7562 + * ID. A block of IRQs is pre-allocated and maintained in a pool
7563 + * from which devices can allocate them when needed.
7564 + */
7565 +
7566 +/*
7567 + * Initialize the interrupt pool associated with an fsl-mc bus.
7568 + * It allocates a block of IRQs from the GIC-ITS.
7569 */
7570 int fsl_mc_populate_irq_pool(struct fsl_mc_bus *mc_bus,
7571 unsigned int irq_count)
7572 @@ -395,7 +398,7 @@ cleanup_msi_irqs:
7573 EXPORT_SYMBOL_GPL(fsl_mc_populate_irq_pool);
7574
7575 /**
7576 - * Teardown the interrupt pool associated with an MC bus.
7577 + * Teardown the interrupt pool associated with an fsl-mc bus.
7578 * It frees the IRQs that were allocated to the pool, back to the GIC-ITS.
7579 */
7580 void fsl_mc_cleanup_irq_pool(struct fsl_mc_bus *mc_bus)
7581 @@ -422,11 +425,7 @@ void fsl_mc_cleanup_irq_pool(struct fsl_
7582 EXPORT_SYMBOL_GPL(fsl_mc_cleanup_irq_pool);
7583
7584 /**
7585 - * It allocates the IRQs required by a given MC object device. The
7586 - * IRQs are allocated from the interrupt pool associated with the
7587 - * MC bus that contains the device, if the device is not a DPRC device.
7588 - * Otherwise, the IRQs are allocated from the interrupt pool associated
7589 - * with the MC bus that represents the DPRC device itself.
7590 + * Allocate the IRQs required by a given fsl-mc device.
7591 */
7592 int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev)
7593 {
7594 @@ -495,8 +494,7 @@ error_resource_alloc:
7595 EXPORT_SYMBOL_GPL(fsl_mc_allocate_irqs);
7596
7597 /*
7598 - * It frees the IRQs that were allocated for a MC object device, by
7599 - * returning them to the corresponding interrupt pool.
7600 + * Frees the IRQs that were allocated for an fsl-mc device.
7601 */
7602 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev)
7603 {
7604 @@ -605,7 +603,7 @@ static int fsl_mc_allocator_probe(struct
7605 return error;
7606
7607 dev_dbg(&mc_dev->dev,
7608 - "Allocatable MC object device bound to fsl_mc_allocator driver");
7609 + "Allocatable fsl-mc device bound to fsl_mc_allocator driver");
7610 return 0;
7611 }
7612
7613 @@ -627,7 +625,7 @@ static int fsl_mc_allocator_remove(struc
7614 }
7615
7616 dev_dbg(&mc_dev->dev,
7617 - "Allocatable MC object device unbound from fsl_mc_allocator driver");
7618 + "Allocatable fsl-mc device unbound from fsl_mc_allocator driver");
7619 return 0;
7620 }
7621
7622 --- a/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7623 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-bus.c
7624 @@ -1,7 +1,7 @@
7625 /*
7626 * Freescale Management Complex (MC) bus driver
7627 *
7628 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
7629 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
7630 * Author: German Rivera <German.Rivera@freescale.com>
7631 *
7632 * This file is licensed under the terms of the GNU General Public
7633 @@ -9,6 +9,8 @@
7634 * warranty of any kind, whether express or implied.
7635 */
7636
7637 +#define pr_fmt(fmt) "fsl-mc: " fmt
7638 +
7639 #include <linux/module.h>
7640 #include <linux/of_device.h>
7641 #include <linux/of_address.h>
7642 @@ -25,8 +27,6 @@
7643 #include "fsl-mc-private.h"
7644 #include "dprc-cmd.h"
7645
7646 -static struct kmem_cache *mc_dev_cache;
7647 -
7648 /**
7649 * Default DMA mask for devices on a fsl-mc bus
7650 */
7651 @@ -34,7 +34,7 @@ static struct kmem_cache *mc_dev_cache;
7652
7653 /**
7654 * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
7655 - * @root_mc_bus_dev: MC object device representing the root DPRC
7656 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
7657 * @num_translation_ranges: number of entries in addr_translation_ranges
7658 * @translation_ranges: array of bus to system address translation ranges
7659 */
7660 @@ -62,8 +62,8 @@ struct fsl_mc_addr_translation_range {
7661
7662 /**
7663 * fsl_mc_bus_match - device to driver matching callback
7664 - * @dev: the MC object device structure to match against
7665 - * @drv: the device driver to search for matching MC object device id
7666 + * @dev: the fsl-mc device to match against
7667 + * @drv: the device driver to search for matching fsl-mc object type
7668 * structures
7669 *
7670 * Returns 1 on success, 0 otherwise.
7671 @@ -75,8 +75,11 @@ static int fsl_mc_bus_match(struct devic
7672 struct fsl_mc_driver *mc_drv = to_fsl_mc_driver(drv);
7673 bool found = false;
7674
7675 - if (WARN_ON(!fsl_mc_bus_exists()))
7676 + /* When driver_override is set, only bind to the matching driver */
7677 + if (mc_dev->driver_override) {
7678 + found = !strcmp(mc_dev->driver_override, mc_drv->driver.name);
7679 goto out;
7680 + }
7681
7682 if (!mc_drv->match_id_table)
7683 goto out;
7684 @@ -91,7 +94,7 @@ static int fsl_mc_bus_match(struct devic
7685
7686 /*
7687 * Traverse the match_id table of the given driver, trying to find
7688 - * a matching for the given MC object device.
7689 + * a matching for the given device.
7690 */
7691 for (id = mc_drv->match_id_table; id->vendor != 0x0; id++) {
7692 if (id->vendor == mc_dev->obj_desc.vendor &&
7693 @@ -132,23 +135,141 @@ static ssize_t modalias_show(struct devi
7694 }
7695 static DEVICE_ATTR_RO(modalias);
7696
7697 +static ssize_t rescan_store(struct device *dev,
7698 + struct device_attribute *attr,
7699 + const char *buf, size_t count)
7700 +{
7701 + unsigned long val;
7702 + unsigned int irq_count;
7703 + struct fsl_mc_device *root_mc_dev;
7704 + struct fsl_mc_bus *root_mc_bus;
7705 +
7706 + if (!fsl_mc_is_root_dprc(dev))
7707 + return -EINVAL;
7708 +
7709 + root_mc_dev = to_fsl_mc_device(dev);
7710 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7711 +
7712 + if (kstrtoul(buf, 0, &val) < 0)
7713 + return -EINVAL;
7714 +
7715 + if (val) {
7716 + mutex_lock(&root_mc_bus->scan_mutex);
7717 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7718 + mutex_unlock(&root_mc_bus->scan_mutex);
7719 + }
7720 +
7721 + return count;
7722 +}
7723 +static DEVICE_ATTR_WO(rescan);
7724 +
7725 +static ssize_t driver_override_store(struct device *dev,
7726 + struct device_attribute *attr,
7727 + const char *buf, size_t count)
7728 +{
7729 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7730 + const char *driver_override, *old = mc_dev->driver_override;
7731 + char *cp;
7732 +
7733 + if (WARN_ON(dev->bus != &fsl_mc_bus_type))
7734 + return -EINVAL;
7735 +
7736 + if (count >= (PAGE_SIZE - 1))
7737 + return -EINVAL;
7738 +
7739 + driver_override = kstrndup(buf, count, GFP_KERNEL);
7740 + if (!driver_override)
7741 + return -ENOMEM;
7742 +
7743 + cp = strchr(driver_override, '\n');
7744 + if (cp)
7745 + *cp = '\0';
7746 +
7747 + if (strlen(driver_override)) {
7748 + mc_dev->driver_override = driver_override;
7749 + } else {
7750 + kfree(driver_override);
7751 + mc_dev->driver_override = NULL;
7752 + }
7753 +
7754 + kfree(old);
7755 +
7756 + return count;
7757 +}
7758 +
7759 +static ssize_t driver_override_show(struct device *dev,
7760 + struct device_attribute *attr, char *buf)
7761 +{
7762 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7763 +
7764 + return snprintf(buf, PAGE_SIZE, "%s\n", mc_dev->driver_override);
7765 +}
7766 +static DEVICE_ATTR_RW(driver_override);
7767 +
7768 static struct attribute *fsl_mc_dev_attrs[] = {
7769 &dev_attr_modalias.attr,
7770 + &dev_attr_rescan.attr,
7771 + &dev_attr_driver_override.attr,
7772 NULL,
7773 };
7774
7775 ATTRIBUTE_GROUPS(fsl_mc_dev);
7776
7777 +static int scan_fsl_mc_bus(struct device *dev, void *data)
7778 +{
7779 + unsigned int irq_count;
7780 + struct fsl_mc_device *root_mc_dev;
7781 + struct fsl_mc_bus *root_mc_bus;
7782 +
7783 + if (fsl_mc_is_root_dprc(dev)) {
7784 + root_mc_dev = to_fsl_mc_device(dev);
7785 + root_mc_bus = to_fsl_mc_bus(root_mc_dev);
7786 + mutex_lock(&root_mc_bus->scan_mutex);
7787 + dprc_scan_objects(root_mc_dev, NULL, &irq_count);
7788 + mutex_unlock(&root_mc_bus->scan_mutex);
7789 + }
7790 +
7791 + return 0;
7792 +}
7793 +
7794 +static ssize_t bus_rescan_store(struct bus_type *bus,
7795 + const char *buf, size_t count)
7796 +{
7797 + unsigned long val;
7798 +
7799 + if (kstrtoul(buf, 0, &val) < 0)
7800 + return -EINVAL;
7801 +
7802 + if (val)
7803 + bus_for_each_dev(bus, NULL, NULL, scan_fsl_mc_bus);
7804 +
7805 + return count;
7806 +}
7807 +static BUS_ATTR(rescan, (S_IWUSR | S_IWGRP), NULL, bus_rescan_store);
7808 +
7809 +static struct attribute *fsl_mc_bus_attrs[] = {
7810 + &bus_attr_rescan.attr,
7811 + NULL,
7812 +};
7813 +
7814 +static const struct attribute_group fsl_mc_bus_group = {
7815 + .attrs = fsl_mc_bus_attrs,
7816 +};
7817 +
7818 +static const struct attribute_group *fsl_mc_bus_groups[] = {
7819 + &fsl_mc_bus_group,
7820 + NULL,
7821 +};
7822 +
7823 struct bus_type fsl_mc_bus_type = {
7824 .name = "fsl-mc",
7825 .match = fsl_mc_bus_match,
7826 .uevent = fsl_mc_bus_uevent,
7827 .dev_groups = fsl_mc_dev_groups,
7828 + .bus_groups = fsl_mc_bus_groups,
7829 };
7830 EXPORT_SYMBOL_GPL(fsl_mc_bus_type);
7831
7832 -static atomic_t root_dprc_count = ATOMIC_INIT(0);
7833 -
7834 static int fsl_mc_driver_probe(struct device *dev)
7835 {
7836 struct fsl_mc_driver *mc_drv;
7837 @@ -164,8 +285,7 @@ static int fsl_mc_driver_probe(struct de
7838
7839 error = mc_drv->probe(mc_dev);
7840 if (error < 0) {
7841 - dev_err(dev, "MC object device probe callback failed: %d\n",
7842 - error);
7843 + dev_err(dev, "%s failed: %d\n", __func__, error);
7844 return error;
7845 }
7846
7847 @@ -183,9 +303,7 @@ static int fsl_mc_driver_remove(struct d
7848
7849 error = mc_drv->remove(mc_dev);
7850 if (error < 0) {
7851 - dev_err(dev,
7852 - "MC object device remove callback failed: %d\n",
7853 - error);
7854 + dev_err(dev, "%s failed: %d\n", __func__, error);
7855 return error;
7856 }
7857
7858 @@ -232,8 +350,6 @@ int __fsl_mc_driver_register(struct fsl_
7859 return error;
7860 }
7861
7862 - pr_info("MC object device driver %s registered\n",
7863 - mc_driver->driver.name);
7864 return 0;
7865 }
7866 EXPORT_SYMBOL_GPL(__fsl_mc_driver_register);
7867 @@ -249,15 +365,6 @@ void fsl_mc_driver_unregister(struct fsl
7868 EXPORT_SYMBOL_GPL(fsl_mc_driver_unregister);
7869
7870 /**
7871 - * fsl_mc_bus_exists - check if a root dprc exists
7872 - */
7873 -bool fsl_mc_bus_exists(void)
7874 -{
7875 - return atomic_read(&root_dprc_count) > 0;
7876 -}
7877 -EXPORT_SYMBOL_GPL(fsl_mc_bus_exists);
7878 -
7879 -/**
7880 * fsl_mc_get_root_dprc - function to traverse to the root dprc
7881 */
7882 void fsl_mc_get_root_dprc(struct device *dev,
7883 @@ -315,21 +422,6 @@ static int get_dprc_icid(struct fsl_mc_i
7884 return error;
7885 }
7886
7887 -static int get_dprc_version(struct fsl_mc_io *mc_io,
7888 - int container_id, u16 *major, u16 *minor)
7889 -{
7890 - struct dprc_attributes attr;
7891 - int error;
7892 -
7893 - error = get_dprc_attr(mc_io, container_id, &attr);
7894 - if (error == 0) {
7895 - *major = attr.version.major;
7896 - *minor = attr.version.minor;
7897 - }
7898 -
7899 - return error;
7900 -}
7901 -
7902 static int translate_mc_addr(struct fsl_mc_device *mc_dev,
7903 enum dprc_region_type mc_region_type,
7904 u64 mc_offset, phys_addr_t *phys_addr)
7905 @@ -451,18 +543,37 @@ bool fsl_mc_is_root_dprc(struct device *
7906 return dev == root_dprc_dev;
7907 }
7908
7909 +static void fsl_mc_device_release(struct device *dev)
7910 +{
7911 + struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
7912 + struct fsl_mc_bus *mc_bus = NULL;
7913 +
7914 + kfree(mc_dev->regions);
7915 +
7916 + if (strcmp(mc_dev->obj_desc.type, "dprc") == 0)
7917 + mc_bus = to_fsl_mc_bus(mc_dev);
7918 +
7919 + if (mc_bus)
7920 + kfree(mc_bus);
7921 + else
7922 + kfree(mc_dev);
7923 +}
7924 +
7925 /**
7926 - * Add a newly discovered MC object device to be visible in Linux
7927 + * Add a newly discovered fsl-mc device to be visible in Linux
7928 */
7929 int fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
7930 struct fsl_mc_io *mc_io,
7931 struct device *parent_dev,
7932 + const char *driver_override,
7933 struct fsl_mc_device **new_mc_dev)
7934 {
7935 int error;
7936 struct fsl_mc_device *mc_dev = NULL;
7937 struct fsl_mc_bus *mc_bus = NULL;
7938 struct fsl_mc_device *parent_mc_dev;
7939 + struct device *fsl_mc_platform_dev;
7940 + struct device_node *fsl_mc_platform_node;
7941
7942 if (dev_is_fsl_mc(parent_dev))
7943 parent_mc_dev = to_fsl_mc_device(parent_dev);
7944 @@ -473,7 +584,7 @@ int fsl_mc_device_add(struct dprc_obj_de
7945 /*
7946 * Allocate an MC bus device object:
7947 */
7948 - mc_bus = devm_kzalloc(parent_dev, sizeof(*mc_bus), GFP_KERNEL);
7949 + mc_bus = kzalloc(sizeof(*mc_bus), GFP_KERNEL);
7950 if (!mc_bus)
7951 return -ENOMEM;
7952
7953 @@ -482,16 +593,30 @@ int fsl_mc_device_add(struct dprc_obj_de
7954 /*
7955 * Allocate a regular fsl_mc_device object:
7956 */
7957 - mc_dev = kmem_cache_zalloc(mc_dev_cache, GFP_KERNEL);
7958 + mc_dev = kzalloc(sizeof(*mc_dev), GFP_KERNEL);
7959 if (!mc_dev)
7960 return -ENOMEM;
7961 }
7962
7963 mc_dev->obj_desc = *obj_desc;
7964 mc_dev->mc_io = mc_io;
7965 +
7966 + if (driver_override) {
7967 + /*
7968 + * We trust driver_override, so we don't need to use
7969 + * kstrndup() here
7970 + */
7971 + mc_dev->driver_override = kstrdup(driver_override, GFP_KERNEL);
7972 + if (!mc_dev->driver_override) {
7973 + error = -ENOMEM;
7974 + goto error_cleanup_dev;
7975 + }
7976 + }
7977 +
7978 device_initialize(&mc_dev->dev);
7979 mc_dev->dev.parent = parent_dev;
7980 mc_dev->dev.bus = &fsl_mc_bus_type;
7981 + mc_dev->dev.release = fsl_mc_device_release;
7982 dev_set_name(&mc_dev->dev, "%s.%d", obj_desc->type, obj_desc->id);
7983
7984 if (strcmp(obj_desc->type, "dprc") == 0) {
7985 @@ -524,8 +649,6 @@ int fsl_mc_device_add(struct dprc_obj_de
7986 }
7987
7988 mc_io2 = mc_io;
7989 -
7990 - atomic_inc(&root_dprc_count);
7991 }
7992
7993 error = get_dprc_icid(mc_io2, obj_desc->id, &mc_dev->icid);
7994 @@ -533,8 +656,8 @@ int fsl_mc_device_add(struct dprc_obj_de
7995 goto error_cleanup_dev;
7996 } else {
7997 /*
7998 - * A non-DPRC MC object device has to be a child of another
7999 - * MC object (specifically a DPRC object)
8000 + * A non-DPRC object has to be a child of a DPRC, use the
8001 + * parent's ICID and interrupt domain.
8002 */
8003 mc_dev->icid = parent_mc_dev->icid;
8004 mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK;
8005 @@ -556,9 +679,14 @@ int fsl_mc_device_add(struct dprc_obj_de
8006 goto error_cleanup_dev;
8007 }
8008
8009 - /* Objects are coherent, unless 'no shareability' flag set. */
8010 - if (!(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY))
8011 - arch_setup_dma_ops(&mc_dev->dev, 0, 0, NULL, true);
8012 + fsl_mc_platform_dev = &mc_dev->dev;
8013 + while (dev_is_fsl_mc(fsl_mc_platform_dev))
8014 + fsl_mc_platform_dev = fsl_mc_platform_dev->parent;
8015 + fsl_mc_platform_node = fsl_mc_platform_dev->of_node;
8016 +
8017 + /* Set up the iommu configuration for the devices. */
8018 + fsl_mc_dma_configure(mc_dev, fsl_mc_platform_node,
8019 + !(obj_desc->flags & DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY));
8020
8021 /*
8022 * The device-specific probe callback will get invoked by device_add()
8023 @@ -571,9 +699,7 @@ int fsl_mc_device_add(struct dprc_obj_de
8024 goto error_cleanup_dev;
8025 }
8026
8027 - (void)get_device(&mc_dev->dev);
8028 - dev_dbg(parent_dev, "Added MC object device %s\n",
8029 - dev_name(&mc_dev->dev));
8030 + dev_dbg(parent_dev, "added %s\n", dev_name(&mc_dev->dev));
8031
8032 *new_mc_dev = mc_dev;
8033 return 0;
8034 @@ -581,47 +707,34 @@ int fsl_mc_device_add(struct dprc_obj_de
8035 error_cleanup_dev:
8036 kfree(mc_dev->regions);
8037 if (mc_bus)
8038 - devm_kfree(parent_dev, mc_bus);
8039 + kfree(mc_bus);
8040 else
8041 - kmem_cache_free(mc_dev_cache, mc_dev);
8042 + kfree(mc_dev);
8043
8044 return error;
8045 }
8046 EXPORT_SYMBOL_GPL(fsl_mc_device_add);
8047
8048 /**
8049 - * fsl_mc_device_remove - Remove a MC object device from being visible to
8050 + * fsl_mc_device_remove - Remove an fsl-mc device from being visible to
8051 * Linux
8052 *
8053 - * @mc_dev: Pointer to a MC object device object
8054 + * @mc_dev: Pointer to an fsl-mc device
8055 */
8056 void fsl_mc_device_remove(struct fsl_mc_device *mc_dev)
8057 {
8058 - struct fsl_mc_bus *mc_bus = NULL;
8059 -
8060 - kfree(mc_dev->regions);
8061 + kfree(mc_dev->driver_override);
8062 + mc_dev->driver_override = NULL;
8063
8064 /*
8065 * The device-specific remove callback will get invoked by device_del()
8066 */
8067 device_del(&mc_dev->dev);
8068 - put_device(&mc_dev->dev);
8069
8070 - if (strcmp(mc_dev->obj_desc.type, "dprc") == 0) {
8071 - mc_bus = to_fsl_mc_bus(mc_dev);
8072 -
8073 - if (fsl_mc_is_root_dprc(&mc_dev->dev)) {
8074 - if (atomic_read(&root_dprc_count) > 0)
8075 - atomic_dec(&root_dprc_count);
8076 - else
8077 - WARN_ON(1);
8078 - }
8079 - }
8080 + if (strcmp(mc_dev->obj_desc.type, "dprc") != 0)
8081 + mc_dev->dev.iommu_fwspec = NULL;
8082
8083 - if (mc_bus)
8084 - devm_kfree(mc_dev->dev.parent, mc_bus);
8085 - else
8086 - kmem_cache_free(mc_dev_cache, mc_dev);
8087 + put_device(&mc_dev->dev);
8088 }
8089 EXPORT_SYMBOL_GPL(fsl_mc_device_remove);
8090
8091 @@ -629,8 +742,7 @@ static int parse_mc_ranges(struct device
8092 int *paddr_cells,
8093 int *mc_addr_cells,
8094 int *mc_size_cells,
8095 - const __be32 **ranges_start,
8096 - u8 *num_ranges)
8097 + const __be32 **ranges_start)
8098 {
8099 const __be32 *prop;
8100 int range_tuple_cell_count;
8101 @@ -643,8 +755,6 @@ static int parse_mc_ranges(struct device
8102 dev_warn(dev,
8103 "missing or empty ranges property for device tree node '%s'\n",
8104 mc_node->name);
8105 -
8106 - *num_ranges = 0;
8107 return 0;
8108 }
8109
8110 @@ -671,8 +781,7 @@ static int parse_mc_ranges(struct device
8111 return -EINVAL;
8112 }
8113
8114 - *num_ranges = ranges_len / tuple_len;
8115 - return 0;
8116 + return ranges_len / tuple_len;
8117 }
8118
8119 static int get_mc_addr_translation_ranges(struct device *dev,
8120 @@ -680,7 +789,7 @@ static int get_mc_addr_translation_range
8121 **ranges,
8122 u8 *num_ranges)
8123 {
8124 - int error;
8125 + int ret;
8126 int paddr_cells;
8127 int mc_addr_cells;
8128 int mc_size_cells;
8129 @@ -688,16 +797,16 @@ static int get_mc_addr_translation_range
8130 const __be32 *ranges_start;
8131 const __be32 *cell;
8132
8133 - error = parse_mc_ranges(dev,
8134 + ret = parse_mc_ranges(dev,
8135 &paddr_cells,
8136 &mc_addr_cells,
8137 &mc_size_cells,
8138 - &ranges_start,
8139 - num_ranges);
8140 - if (error < 0)
8141 - return error;
8142 + &ranges_start);
8143 + if (ret < 0)
8144 + return ret;
8145
8146 - if (!(*num_ranges)) {
8147 + *num_ranges = ret;
8148 + if (!ret) {
8149 /*
8150 * Missing or empty ranges property ("ranges;") for the
8151 * 'fsl,qoriq-mc' node. In this case, identity mapping
8152 @@ -749,8 +858,6 @@ static int fsl_mc_bus_probe(struct platf
8153 struct mc_version mc_version;
8154 struct resource res;
8155
8156 - dev_info(&pdev->dev, "Root MC bus device probed");
8157 -
8158 mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
8159 if (!mc)
8160 return -ENOMEM;
8161 @@ -783,8 +890,7 @@ static int fsl_mc_bus_probe(struct platf
8162 goto error_cleanup_mc_io;
8163 }
8164
8165 - dev_info(&pdev->dev,
8166 - "Freescale Management Complex Firmware version: %u.%u.%u\n",
8167 + dev_info(&pdev->dev, "MC firmware version: %u.%u.%u\n",
8168 mc_version.major, mc_version.minor, mc_version.revision);
8169
8170 error = get_mc_addr_translation_ranges(&pdev->dev,
8171 @@ -793,16 +899,17 @@ static int fsl_mc_bus_probe(struct platf
8172 if (error < 0)
8173 goto error_cleanup_mc_io;
8174
8175 - error = dpmng_get_container_id(mc_io, 0, &container_id);
8176 + error = dprc_get_container_id(mc_io, 0, &container_id);
8177 if (error < 0) {
8178 dev_err(&pdev->dev,
8179 - "dpmng_get_container_id() failed: %d\n", error);
8180 + "dprc_get_container_id() failed: %d\n", error);
8181 goto error_cleanup_mc_io;
8182 }
8183
8184 memset(&obj_desc, 0, sizeof(struct dprc_obj_desc));
8185 - error = get_dprc_version(mc_io, container_id,
8186 - &obj_desc.ver_major, &obj_desc.ver_minor);
8187 + error = dprc_get_api_version(mc_io, 0,
8188 + &obj_desc.ver_major,
8189 + &obj_desc.ver_minor);
8190 if (error < 0)
8191 goto error_cleanup_mc_io;
8192
8193 @@ -812,7 +919,8 @@ static int fsl_mc_bus_probe(struct platf
8194 obj_desc.irq_count = 1;
8195 obj_desc.region_count = 0;
8196
8197 - error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, &mc_bus_dev);
8198 + error = fsl_mc_device_add(&obj_desc, mc_io, &pdev->dev, NULL,
8199 + &mc_bus_dev);
8200 if (error < 0)
8201 goto error_cleanup_mc_io;
8202
8203 @@ -840,7 +948,6 @@ static int fsl_mc_bus_remove(struct plat
8204 fsl_destroy_mc_io(mc->root_mc_bus_dev->mc_io);
8205 mc->root_mc_bus_dev->mc_io = NULL;
8206
8207 - dev_info(&pdev->dev, "Root MC bus device removed");
8208 return 0;
8209 }
8210
8211 @@ -865,22 +972,12 @@ static int __init fsl_mc_bus_driver_init
8212 {
8213 int error;
8214
8215 - mc_dev_cache = kmem_cache_create("fsl_mc_device",
8216 - sizeof(struct fsl_mc_device), 0, 0,
8217 - NULL);
8218 - if (!mc_dev_cache) {
8219 - pr_err("Could not create fsl_mc_device cache\n");
8220 - return -ENOMEM;
8221 - }
8222 -
8223 error = bus_register(&fsl_mc_bus_type);
8224 if (error < 0) {
8225 - pr_err("fsl-mc bus type registration failed: %d\n", error);
8226 + pr_err("bus type registration failed: %d\n", error);
8227 goto error_cleanup_cache;
8228 }
8229
8230 - pr_info("fsl-mc bus type registered\n");
8231 -
8232 error = platform_driver_register(&fsl_mc_bus_driver);
8233 if (error < 0) {
8234 pr_err("platform_driver_register() failed: %d\n", error);
8235 @@ -914,7 +1011,6 @@ error_cleanup_bus:
8236 bus_unregister(&fsl_mc_bus_type);
8237
8238 error_cleanup_cache:
8239 - kmem_cache_destroy(mc_dev_cache);
8240 return error;
8241 }
8242 postcore_initcall(fsl_mc_bus_driver_init);
8243 --- /dev/null
8244 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-iommu.c
8245 @@ -0,0 +1,104 @@
8246 +/*
8247 + * Copyright 2016-17 NXP
8248 + * Author: Nipun Gupta <nipun.gupta@nxp.com>
8249 + *
8250 + * This file is licensed under the terms of the GNU General Public
8251 + * License version 2. This program is licensed "as is" without any
8252 + * warranty of any kind, whether express or implied.
8253 + */
8254 +
8255 +#include <linux/iommu.h>
8256 +#include <linux/of.h>
8257 +#include <linux/of_iommu.h>
8258 +#include "../include/mc.h"
8259 +
8260 +/* Setup the IOMMU for the DPRC container */
8261 +static const struct iommu_ops
8262 +*fsl_mc_iommu_configure(struct fsl_mc_device *mc_dev,
8263 + struct device_node *fsl_mc_platform_node)
8264 +{
8265 + struct of_phandle_args iommu_spec;
8266 + const struct iommu_ops *ops;
8267 + u32 iommu_phandle;
8268 + struct device_node *iommu_node;
8269 + const __be32 *map = NULL;
8270 + int iommu_cells, map_len, ret;
8271 +
8272 + map = of_get_property(fsl_mc_platform_node, "iommu-map", &map_len);
8273 + if (!map)
8274 + return NULL;
8275 +
8276 + ops = mc_dev->dev.bus->iommu_ops;
8277 + if (!ops || !ops->of_xlate)
8278 + return NULL;
8279 +
8280 + iommu_phandle = be32_to_cpup(map + 1);
8281 + iommu_node = of_find_node_by_phandle(iommu_phandle);
8282 +
8283 + if (of_property_read_u32(iommu_node, "#iommu-cells", &iommu_cells)) {
8284 + pr_err("%s: missing #iommu-cells property\n", iommu_node->name);
8285 + return NULL;
8286 + }
8287 +
8288 + /* Initialize the fwspec */
8289 + ret = iommu_fwspec_init(&mc_dev->dev, &iommu_node->fwnode, ops);
8290 + if (ret)
8291 + return NULL;
8292 +
8293 + /*
8294 + * Fill in the required stream-id before calling the iommu's
8295 + * ops->xlate callback.
8296 + */
8297 + iommu_spec.np = iommu_node;
8298 + iommu_spec.args[0] = mc_dev->icid;
8299 + iommu_spec.args_count = 1;
8300 +
8301 + ret = ops->of_xlate(&mc_dev->dev, &iommu_spec);
8302 + if (ret)
8303 + return NULL;
8304 +
8305 + of_node_put(iommu_spec.np);
8306 +
8307 + return ops;
8308 +}
8309 +
8310 +/* Set up DMA configuration for fsl-mc devices */
8311 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
8312 + struct device_node *fsl_mc_platform_node, int coherent)
8313 +{
8314 + const struct iommu_ops *ops;
8315 +
8316 + ops = fsl_mc_iommu_configure(mc_dev, fsl_mc_platform_node);
8317 +
8318 + mc_dev->dev.coherent_dma_mask = DMA_BIT_MASK(48);
8319 + mc_dev->dev.dma_mask = &mc_dev->dev.coherent_dma_mask;
8320 + arch_setup_dma_ops(&mc_dev->dev, 0,
8321 + mc_dev->dev.coherent_dma_mask + 1, ops, coherent);
8322 +}
8323 +
8324 +/* Macro to get the container device of a MC device */
8325 +#define fsl_mc_cont_dev(_dev) ((to_fsl_mc_device(_dev)->flags & \
8326 + FSL_MC_IS_DPRC) ? (_dev) : ((_dev)->parent))
8327 +
8328 +/* Macro to check if a device is a container device */
8329 +#define is_cont_dev(_dev) (to_fsl_mc_device(_dev)->flags & FSL_MC_IS_DPRC)
8330 +
8331 +/* Get the IOMMU group for device on fsl-mc bus */
8332 +struct iommu_group *fsl_mc_device_group(struct device *dev)
8333 +{
8334 + struct device *cont_dev = fsl_mc_cont_dev(dev);
8335 + struct iommu_group *group;
8336 +
8337 + /* Container device is responsible for creating the iommu group */
8338 + if (is_cont_dev(dev)) {
8339 + group = iommu_group_alloc();
8340 + if (IS_ERR(group))
8341 + return NULL;
8342 + } else {
8343 + get_device(cont_dev);
8344 + group = iommu_group_get(cont_dev);
8345 + put_device(cont_dev);
8346 + }
8347 +
8348 + return group;
8349 +}
8350 --- a/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8351 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-msi.c
8352 @@ -1,7 +1,7 @@
8353 /*
8354 * Freescale Management Complex (MC) bus driver MSI support
8355 *
8356 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8357 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8358 * Author: German Rivera <German.Rivera@freescale.com>
8359 *
8360 * This file is licensed under the terms of the GNU General Public
8361 --- a/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8362 +++ b/drivers/staging/fsl-mc/bus/fsl-mc-private.h
8363 @@ -10,13 +10,15 @@
8364 #ifndef _FSL_MC_PRIVATE_H_
8365 #define _FSL_MC_PRIVATE_H_
8366
8367 +#include "../include/mc.h"
8368 +#include "../include/mc-bus.h"
8369 +
8370 int __must_check fsl_mc_device_add(struct dprc_obj_desc *obj_desc,
8371 struct fsl_mc_io *mc_io,
8372 struct device *parent_dev,
8373 + const char *driver_override,
8374 struct fsl_mc_device **new_mc_dev);
8375
8376 -void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
8377 -
8378 int __init dprc_driver_init(void);
8379
8380 void dprc_driver_exit(void);
8381 --- a/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8382 +++ b/drivers/staging/fsl-mc/bus/irq-gic-v3-its-fsl-mc-msi.c
8383 @@ -1,7 +1,7 @@
8384 /*
8385 * Freescale Management Complex (MC) bus driver MSI support
8386 *
8387 - * Copyright (C) 2015 Freescale Semiconductor, Inc.
8388 + * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
8389 * Author: German Rivera <German.Rivera@freescale.com>
8390 *
8391 * This file is licensed under the terms of the GNU General Public
8392 @@ -20,7 +20,7 @@
8393 #include "fsl-mc-private.h"
8394
8395 static struct irq_chip its_msi_irq_chip = {
8396 - .name = "fsl-mc-bus-msi",
8397 + .name = "ITS-fMSI",
8398 .irq_mask = irq_chip_mask_parent,
8399 .irq_unmask = irq_chip_unmask_parent,
8400 .irq_eoi = irq_chip_eoi_parent,
8401 @@ -52,7 +52,7 @@ static int its_fsl_mc_msi_prepare(struct
8402 return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info);
8403 }
8404
8405 -static struct msi_domain_ops its_fsl_mc_msi_ops = {
8406 +static struct msi_domain_ops its_fsl_mc_msi_ops __ro_after_init = {
8407 .msi_prepare = its_fsl_mc_msi_prepare,
8408 };
8409
8410 @@ -95,8 +95,8 @@ int __init its_fsl_mc_msi_init(void)
8411 continue;
8412 }
8413
8414 - WARN_ON(mc_msi_domain->
8415 - host_data != &its_fsl_mc_msi_domain_info);
8416 + WARN_ON(mc_msi_domain->host_data !=
8417 + &its_fsl_mc_msi_domain_info);
8418
8419 pr_info("fsl-mc MSI: %s domain created\n", np->full_name);
8420 }
8421 --- a/drivers/staging/fsl-mc/bus/mc-io.c
8422 +++ b/drivers/staging/fsl-mc/bus/mc-io.c
8423 @@ -1,4 +1,5 @@
8424 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
8425 +/*
8426 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8427 *
8428 * Redistribution and use in source and binary forms, with or without
8429 * modification, are permitted provided that the following conditions are met:
8430 @@ -11,7 +12,6 @@
8431 * names of any contributors may be used to endorse or promote products
8432 * derived from this software without specific prior written permission.
8433 *
8434 - *
8435 * ALTERNATIVELY, this software may be distributed under the terms of the
8436 * GNU General Public License ("GPL") as published by the Free Software
8437 * Foundation, either version 2 of that License or (at your option) any
8438 --- /dev/null
8439 +++ b/drivers/staging/fsl-mc/bus/mc-ioctl.h
8440 @@ -0,0 +1,22 @@
8441 +/*
8442 + * Freescale Management Complex (MC) ioclt interface
8443 + *
8444 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8445 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8446 + *
8447 + * This file is licensed under the terms of the GNU General Public
8448 + * License version 2. This program is licensed "as is" without any
8449 + * warranty of any kind, whether express or implied.
8450 + */
8451 +#ifndef _FSL_MC_IOCTL_H_
8452 +#define _FSL_MC_IOCTL_H_
8453 +
8454 +#include <linux/ioctl.h>
8455 +#include "../include/mc-sys.h"
8456 +
8457 +#define RESTOOL_IOCTL_TYPE 'R'
8458 +
8459 +#define RESTOOL_SEND_MC_COMMAND \
8460 + _IOWR(RESTOOL_IOCTL_TYPE, 0xE0, struct mc_command)
8461 +
8462 +#endif /* _FSL_MC_IOCTL_H_ */
8463 --- /dev/null
8464 +++ b/drivers/staging/fsl-mc/bus/mc-restool.c
8465 @@ -0,0 +1,405 @@
8466 +/*
8467 + * Freescale Management Complex (MC) restool driver
8468 + *
8469 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
8470 + * Author: Lijun Pan <Lijun.Pan@freescale.com>
8471 + *
8472 + * This file is licensed under the terms of the GNU General Public
8473 + * License version 2. This program is licensed "as is" without any
8474 + * warranty of any kind, whether express or implied.
8475 + */
8476 +
8477 +#include "../include/mc.h"
8478 +#include <linux/module.h>
8479 +#include <linux/fs.h>
8480 +#include <linux/miscdevice.h>
8481 +#include <linux/mm.h>
8482 +#include <linux/slab.h>
8483 +#include <linux/uaccess.h>
8484 +#include <linux/mutex.h>
8485 +#include <linux/platform_device.h>
8486 +#include "mc-ioctl.h"
8487 +#include "../include/mc-sys.h"
8488 +#include "../include/mc-bus.h"
8489 +#include "../include/mc-cmd.h"
8490 +#include "../include/dpmng.h"
8491 +
8492 +/**
8493 + * Maximum number of DPRCs that can be opened at the same time
8494 + */
8495 +#define MAX_DPRC_HANDLES 64
8496 +
8497 +/**
8498 + * restool_misc - information associated with the newly added miscdevice
8499 + * @misc: newly created miscdevice associated with root dprc
8500 + * @miscdevt: device id of this miscdevice
8501 + * @list: a linked list node representing this miscdevcie
8502 + * @static_mc_io: pointer to the static MC I/O object used by the restool
8503 + * @dynamic_instance_count: number of dynamically created instances
8504 + * @static_instance_in_use: static instance is in use or not
8505 + * @mutex: mutex lock to serialze the open/release operations
8506 + * @dev: root dprc associated with this miscdevice
8507 + */
8508 +struct restool_misc {
8509 + struct miscdevice misc;
8510 + dev_t miscdevt;
8511 + struct list_head list;
8512 + struct fsl_mc_io *static_mc_io;
8513 + u32 dynamic_instance_count;
8514 + bool static_instance_in_use;
8515 + struct mutex mutex; /* serialze the open/release operations */
8516 + struct device *dev;
8517 +};
8518 +
8519 +/**
8520 + * struct fsl_mc - Private data of a "fsl,qoriq-mc" platform device
8521 + * @root_mc_bus_dev: fsl-mc device representing the root DPRC
8522 + * @num_translation_ranges: number of entries in addr_translation_ranges
8523 + * @translation_ranges: array of bus to system address translation ranges
8524 + */
8525 +struct fsl_mc {
8526 + struct fsl_mc_device *root_mc_bus_dev;
8527 + u8 num_translation_ranges;
8528 + struct fsl_mc_addr_translation_range *translation_ranges;
8529 +};
8530 +
8531 +/*
8532 + * initialize a global list to link all
8533 + * the miscdevice nodes (struct restool_misc)
8534 + */
8535 +static LIST_HEAD(misc_list);
8536 +static DEFINE_MUTEX(misc_list_mutex);
8537 +
8538 +static int fsl_mc_restool_dev_open(struct inode *inode, struct file *filep)
8539 +{
8540 + struct fsl_mc_device *root_mc_dev;
8541 + int error;
8542 + struct fsl_mc_io *dynamic_mc_io = NULL;
8543 + struct restool_misc *restool_misc = NULL;
8544 + struct restool_misc *restool_misc_cursor;
8545 +
8546 + mutex_lock(&misc_list_mutex);
8547 +
8548 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8549 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8550 + restool_misc = restool_misc_cursor;
8551 + break;
8552 + }
8553 + }
8554 +
8555 + mutex_unlock(&misc_list_mutex);
8556 +
8557 + if (!restool_misc)
8558 + return -EINVAL;
8559 +
8560 + if (WARN_ON(!restool_misc->dev))
8561 + return -EINVAL;
8562 +
8563 + mutex_lock(&restool_misc->mutex);
8564 +
8565 + if (!restool_misc->static_instance_in_use) {
8566 + restool_misc->static_instance_in_use = true;
8567 + filep->private_data = restool_misc->static_mc_io;
8568 + } else {
8569 + dynamic_mc_io = kzalloc(sizeof(*dynamic_mc_io), GFP_KERNEL);
8570 + if (!dynamic_mc_io) {
8571 + error = -ENOMEM;
8572 + goto err_unlock;
8573 + }
8574 +
8575 + root_mc_dev = to_fsl_mc_device(restool_misc->dev);
8576 + error = fsl_mc_portal_allocate(root_mc_dev, 0, &dynamic_mc_io);
8577 + if (error < 0) {
8578 + pr_err("Not able to allocate MC portal\n");
8579 + goto free_dynamic_mc_io;
8580 + }
8581 + ++restool_misc->dynamic_instance_count;
8582 + filep->private_data = dynamic_mc_io;
8583 + }
8584 +
8585 + mutex_unlock(&restool_misc->mutex);
8586 +
8587 + return 0;
8588 +
8589 +free_dynamic_mc_io:
8590 + kfree(dynamic_mc_io);
8591 +err_unlock:
8592 + mutex_unlock(&restool_misc->mutex);
8593 +
8594 + return error;
8595 +}
8596 +
8597 +static int fsl_mc_restool_dev_release(struct inode *inode, struct file *filep)
8598 +{
8599 + struct fsl_mc_io *local_mc_io = filep->private_data;
8600 + struct restool_misc *restool_misc = NULL;
8601 + struct restool_misc *restool_misc_cursor;
8602 +
8603 + if (WARN_ON(!filep->private_data))
8604 + return -EINVAL;
8605 +
8606 + mutex_lock(&misc_list_mutex);
8607 +
8608 + list_for_each_entry(restool_misc_cursor, &misc_list, list) {
8609 + if (restool_misc_cursor->miscdevt == inode->i_rdev) {
8610 + restool_misc = restool_misc_cursor;
8611 + break;
8612 + }
8613 + }
8614 +
8615 + mutex_unlock(&misc_list_mutex);
8616 +
8617 + if (!restool_misc)
8618 + return -EINVAL;
8619 +
8620 + mutex_lock(&restool_misc->mutex);
8621 +
8622 + if (WARN_ON(restool_misc->dynamic_instance_count == 0 &&
8623 + !restool_misc->static_instance_in_use)) {
8624 + mutex_unlock(&restool_misc->mutex);
8625 + return -EINVAL;
8626 + }
8627 +
8628 + /* Globally clean up opened/untracked handles */
8629 + fsl_mc_portal_reset(local_mc_io);
8630 +
8631 + /*
8632 + * must check
8633 + * whether local_mc_io is dynamic or static instance
8634 + * Otherwise it will free up the reserved portal by accident
8635 + * or even not free up the dynamic allocated portal
8636 + * if 2 or more instances running concurrently
8637 + */
8638 + if (local_mc_io == restool_misc->static_mc_io) {
8639 + restool_misc->static_instance_in_use = false;
8640 + } else {
8641 + fsl_mc_portal_free(local_mc_io);
8642 + kfree(filep->private_data);
8643 + --restool_misc->dynamic_instance_count;
8644 + }
8645 +
8646 + filep->private_data = NULL;
8647 + mutex_unlock(&restool_misc->mutex);
8648 +
8649 + return 0;
8650 +}
8651 +
8652 +static int restool_send_mc_command(unsigned long arg,
8653 + struct fsl_mc_io *local_mc_io)
8654 +{
8655 + int error;
8656 + struct mc_command mc_cmd;
8657 +
8658 + if (copy_from_user(&mc_cmd, (void __user *)arg, sizeof(mc_cmd)))
8659 + return -EFAULT;
8660 +
8661 + /*
8662 + * Send MC command to the MC:
8663 + */
8664 + error = mc_send_command(local_mc_io, &mc_cmd);
8665 + if (error < 0)
8666 + return error;
8667 +
8668 + if (copy_to_user((void __user *)arg, &mc_cmd, sizeof(mc_cmd)))
8669 + return -EFAULT;
8670 +
8671 + return 0;
8672 +}
8673 +
8674 +static long
8675 +fsl_mc_restool_dev_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
8676 +{
8677 + int error;
8678 +
8679 + switch (cmd) {
8680 + case RESTOOL_SEND_MC_COMMAND:
8681 + error = restool_send_mc_command(arg, file->private_data);
8682 + break;
8683 + default:
8684 + pr_err("%s: unexpected ioctl call number\n", __func__);
8685 + error = -EINVAL;
8686 + }
8687 +
8688 + return error;
8689 +}
8690 +
8691 +static const struct file_operations fsl_mc_restool_dev_fops = {
8692 + .owner = THIS_MODULE,
8693 + .open = fsl_mc_restool_dev_open,
8694 + .release = fsl_mc_restool_dev_release,
8695 + .unlocked_ioctl = fsl_mc_restool_dev_ioctl,
8696 +};
8697 +
8698 +static int restool_add_device_file(struct device *dev)
8699 +{
8700 + u32 name1 = 0;
8701 + char name2[20] = {0};
8702 + int error;
8703 + struct fsl_mc_device *root_mc_dev;
8704 + struct restool_misc *restool_misc;
8705 +
8706 + if (dev->bus == &platform_bus_type && dev->driver_data) {
8707 + if (sscanf(dev_name(dev), "%x.%s", &name1, name2) != 2)
8708 + return -EINVAL;
8709 +
8710 + if (strcmp(name2, "fsl-mc") == 0)
8711 + pr_debug("platform's root dprc name is: %s\n",
8712 + dev_name(&(((struct fsl_mc *)
8713 + (dev->driver_data))->root_mc_bus_dev->dev)));
8714 + }
8715 +
8716 + if (!fsl_mc_is_root_dprc(dev))
8717 + return 0;
8718 +
8719 + restool_misc = kzalloc(sizeof(*restool_misc), GFP_KERNEL);
8720 + if (!restool_misc)
8721 + return -ENOMEM;
8722 +
8723 + restool_misc->dev = dev;
8724 + root_mc_dev = to_fsl_mc_device(dev);
8725 + error = fsl_mc_portal_allocate(root_mc_dev, 0,
8726 + &restool_misc->static_mc_io);
8727 + if (error < 0) {
8728 + pr_err("Not able to allocate MC portal\n");
8729 + goto free_restool_misc;
8730 + }
8731 +
8732 + restool_misc->misc.minor = MISC_DYNAMIC_MINOR;
8733 + restool_misc->misc.name = dev_name(dev);
8734 + restool_misc->misc.fops = &fsl_mc_restool_dev_fops;
8735 +
8736 + error = misc_register(&restool_misc->misc);
8737 + if (error < 0) {
8738 + pr_err("misc_register() failed: %d\n", error);
8739 + goto free_portal;
8740 + }
8741 +
8742 + restool_misc->miscdevt = restool_misc->misc.this_device->devt;
8743 + mutex_init(&restool_misc->mutex);
8744 + mutex_lock(&misc_list_mutex);
8745 + list_add(&restool_misc->list, &misc_list);
8746 + mutex_unlock(&misc_list_mutex);
8747 +
8748 + pr_info("/dev/%s driver registered\n", dev_name(dev));
8749 +
8750 + return 0;
8751 +
8752 +free_portal:
8753 + fsl_mc_portal_free(restool_misc->static_mc_io);
8754 +free_restool_misc:
8755 + kfree(restool_misc);
8756 +
8757 + return error;
8758 +}
8759 +
8760 +static int restool_bus_notifier(struct notifier_block *nb,
8761 + unsigned long action, void *data)
8762 +{
8763 + int error;
8764 + struct device *dev = data;
8765 +
8766 + switch (action) {
8767 + case BUS_NOTIFY_ADD_DEVICE:
8768 + error = restool_add_device_file(dev);
8769 + if (error)
8770 + return error;
8771 + break;
8772 + case BUS_NOTIFY_DEL_DEVICE:
8773 + case BUS_NOTIFY_REMOVED_DEVICE:
8774 + case BUS_NOTIFY_BIND_DRIVER:
8775 + case BUS_NOTIFY_BOUND_DRIVER:
8776 + case BUS_NOTIFY_UNBIND_DRIVER:
8777 + case BUS_NOTIFY_UNBOUND_DRIVER:
8778 + break;
8779 + default:
8780 + pr_err("%s: unrecognized device action from %s\n", __func__,
8781 + dev_name(dev));
8782 + return -EINVAL;
8783 + }
8784 +
8785 + return 0;
8786 +}
8787 +
8788 +static int add_to_restool(struct device *dev, void *data)
8789 +{
8790 + return restool_add_device_file(dev);
8791 +}
8792 +
8793 +static int __init fsl_mc_restool_driver_init(void)
8794 +{
8795 + int error;
8796 + struct notifier_block *nb;
8797 +
8798 + nb = kzalloc(sizeof(*nb), GFP_KERNEL);
8799 + if (!nb)
8800 + return -ENOMEM;
8801 +
8802 + nb->notifier_call = restool_bus_notifier;
8803 + error = bus_register_notifier(&fsl_mc_bus_type, nb);
8804 + if (error)
8805 + goto free_nb;
8806 +
8807 + /*
8808 + * This driver runs after fsl-mc bus driver runs.
8809 + * Hence, many of the root dprcs are already attached to fsl-mc bus
8810 + * In order to make sure we find all the root dprcs,
8811 + * we need to scan the fsl_mc_bus_type.
8812 + */
8813 + error = bus_for_each_dev(&fsl_mc_bus_type, NULL, NULL, add_to_restool);
8814 + if (error) {
8815 + bus_unregister_notifier(&fsl_mc_bus_type, nb);
8816 + kfree(nb);
8817 + pr_err("restool driver registration failure\n");
8818 + return error;
8819 + }
8820 +
8821 + return 0;
8822 +
8823 +free_nb:
8824 + kfree(nb);
8825 + return error;
8826 +}
8827 +
8828 +module_init(fsl_mc_restool_driver_init);
8829 +
8830 +static void __exit fsl_mc_restool_driver_exit(void)
8831 +{
8832 + struct restool_misc *restool_misc;
8833 + struct restool_misc *restool_misc_tmp;
8834 + char name1[20] = {0};
8835 + u32 name2 = 0;
8836 +
8837 + list_for_each_entry_safe(restool_misc, restool_misc_tmp,
8838 + &misc_list, list) {
8839 + if (sscanf(restool_misc->misc.name, "%4s.%u", name1, &name2)
8840 + != 2)
8841 + continue;
8842 +
8843 + pr_debug("name1=%s,name2=%u\n", name1, name2);
8844 + pr_debug("misc-device: %s\n", restool_misc->misc.name);
8845 + if (strcmp(name1, "dprc") != 0)
8846 + continue;
8847 +
8848 + if (WARN_ON(!restool_misc->static_mc_io))
8849 + return;
8850 +
8851 + if (WARN_ON(restool_misc->dynamic_instance_count != 0))
8852 + return;
8853 +
8854 + if (WARN_ON(restool_misc->static_instance_in_use))
8855 + return;
8856 +
8857 + misc_deregister(&restool_misc->misc);
8858 + pr_info("/dev/%s driver unregistered\n",
8859 + restool_misc->misc.name);
8860 + fsl_mc_portal_free(restool_misc->static_mc_io);
8861 + list_del(&restool_misc->list);
8862 + kfree(restool_misc);
8863 + }
8864 +}
8865 +
8866 +module_exit(fsl_mc_restool_driver_exit);
8867 +
8868 +MODULE_AUTHOR("Freescale Semiconductor Inc.");
8869 +MODULE_DESCRIPTION("Freescale's MC restool driver");
8870 +MODULE_LICENSE("GPL");
8871 --- a/drivers/staging/fsl-mc/bus/mc-sys.c
8872 +++ b/drivers/staging/fsl-mc/bus/mc-sys.c
8873 @@ -1,4 +1,5 @@
8874 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
8875 +/*
8876 + * Copyright 2013-2016 Freescale Semiconductor Inc.
8877 *
8878 * I/O services to send MC commands to the MC hardware
8879 *
8880 @@ -13,7 +14,6 @@
8881 * names of any contributors may be used to endorse or promote products
8882 * derived from this software without specific prior written permission.
8883 *
8884 - *
8885 * ALTERNATIVELY, this software may be distributed under the terms of the
8886 * GNU General Public License ("GPL") as published by the Free Software
8887 * Foundation, either version 2 of that License or (at your option) any
8888 @@ -46,7 +46,7 @@
8889 /**
8890 * Timeout in milliseconds to wait for the completion of an MC command
8891 */
8892 -#define MC_CMD_COMPLETION_TIMEOUT_MS 500
8893 +#define MC_CMD_COMPLETION_TIMEOUT_MS 15000
8894
8895 /*
8896 * usleep_range() min and max values used to throttle down polling
8897 @@ -67,7 +67,7 @@ static u16 mc_cmd_hdr_read_cmdid(struct
8898 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
8899 u16 cmd_id = le16_to_cpu(hdr->cmd_id);
8900
8901 - return (cmd_id & MC_CMD_HDR_CMDID_MASK) >> MC_CMD_HDR_CMDID_SHIFT;
8902 + return cmd_id;
8903 }
8904
8905 static int mc_status_to_error(enum mc_cmd_status status)
8906 @@ -200,7 +200,7 @@ static int mc_polling_wait_preemptible(s
8907
8908 if (time_after_eq(jiffies, jiffies_until_timeout)) {
8909 dev_dbg(mc_io->dev,
8910 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8911 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8912 mc_io->portal_phys_addr,
8913 (unsigned int)mc_cmd_hdr_read_token(cmd),
8914 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8915 @@ -240,7 +240,7 @@ static int mc_polling_wait_atomic(struct
8916 timeout_usecs -= MC_CMD_COMPLETION_POLLING_MAX_SLEEP_USECS;
8917 if (timeout_usecs == 0) {
8918 dev_dbg(mc_io->dev,
8919 - "MC command timed out (portal: %#llx, obj handle: %#x, command: %#x)\n",
8920 + "MC command timed out (portal: %#llx, dprc handle: %#x, command: %#x)\n",
8921 mc_io->portal_phys_addr,
8922 (unsigned int)mc_cmd_hdr_read_token(cmd),
8923 (unsigned int)mc_cmd_hdr_read_cmdid(cmd));
8924 @@ -294,7 +294,7 @@ int mc_send_command(struct fsl_mc_io *mc
8925
8926 if (status != MC_CMD_STATUS_OK) {
8927 dev_dbg(mc_io->dev,
8928 - "MC command failed: portal: %#llx, obj handle: %#x, command: %#x, status: %s (%#x)\n",
8929 + "MC command failed: portal: %#llx, dprc handle: %#x, command: %#x, status: %s (%#x)\n",
8930 mc_io->portal_phys_addr,
8931 (unsigned int)mc_cmd_hdr_read_token(cmd),
8932 (unsigned int)mc_cmd_hdr_read_cmdid(cmd),
8933 --- /dev/null
8934 +++ b/drivers/staging/fsl-mc/include/dpaa2-fd.h
8935 @@ -0,0 +1,706 @@
8936 +/*
8937 + * Copyright 2014-2016 Freescale Semiconductor Inc.
8938 + * Copyright 2016 NXP
8939 + *
8940 + * Redistribution and use in source and binary forms, with or without
8941 + * modification, are permitted provided that the following conditions are met:
8942 + * * Redistributions of source code must retain the above copyright
8943 + * notice, this list of conditions and the following disclaimer.
8944 + * * Redistributions in binary form must reproduce the above copyright
8945 + * notice, this list of conditions and the following disclaimer in the
8946 + * documentation and/or other materials provided with the distribution.
8947 + * * Neither the name of Freescale Semiconductor nor the
8948 + * names of its contributors may be used to endorse or promote products
8949 + * derived from this software without specific prior written permission.
8950 + *
8951 + * ALTERNATIVELY, this software may be distributed under the terms of the
8952 + * GNU General Public License ("GPL") as published by the Free Software
8953 + * Foundation, either version 2 of that License or (at your option) any
8954 + * later version.
8955 + *
8956 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
8957 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
8958 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
8959 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
8960 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
8961 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
8962 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
8963 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8964 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
8965 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8966 + */
8967 +#ifndef __FSL_DPAA2_FD_H
8968 +#define __FSL_DPAA2_FD_H
8969 +
8970 +#include <linux/kernel.h>
8971 +
8972 +/**
8973 + * DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
8974 + *
8975 + * Frame Descriptors (FDs) are used to describe frame data in the DPAA2.
8976 + * Frames can be enqueued and dequeued to Frame Queues (FQs) which are consumed
8977 + * by the various DPAA accelerators (WRIOP, SEC, PME, DCE)
8978 + *
8979 + * There are three types of frames: single, scatter gather, and frame lists.
8980 + *
8981 + * The set of APIs in this file must be used to create, manipulate and
8982 + * query Frame Descriptors.
8983 + */
8984 +
8985 +/**
8986 + * struct dpaa2_fd - Struct describing FDs
8987 + * @words: for easier/faster copying the whole FD structure
8988 + * @addr: address in the FD
8989 + * @len: length in the FD
8990 + * @bpid: buffer pool ID
8991 + * @format_offset: format, offset, and short-length fields
8992 + * @frc: frame context
8993 + * @ctrl: control bits...including dd, sc, va, err, etc
8994 + * @flc: flow context address
8995 + *
8996 + * This structure represents the basic Frame Descriptor used in the system.
8997 + */
8998 +struct dpaa2_fd {
8999 + union {
9000 + u32 words[8];
9001 + struct dpaa2_fd_simple {
9002 + __le64 addr;
9003 + __le32 len;
9004 + __le16 bpid;
9005 + __le16 format_offset;
9006 + __le32 frc;
9007 + __le32 ctrl;
9008 + __le64 flc;
9009 + } simple;
9010 + };
9011 +};
9012 +
9013 +#define FD_SHORT_LEN_FLAG_MASK 0x1
9014 +#define FD_SHORT_LEN_FLAG_SHIFT 14
9015 +#define FD_SHORT_LEN_MASK 0x3FFFF
9016 +#define FD_OFFSET_MASK 0x0FFF
9017 +#define FD_FORMAT_MASK 0x3
9018 +#define FD_FORMAT_SHIFT 12
9019 +#define FD_BPID_MASK 0x3FFF
9020 +#define SG_SHORT_LEN_FLAG_MASK 0x1
9021 +#define SG_SHORT_LEN_FLAG_SHIFT 14
9022 +#define SG_SHORT_LEN_MASK 0x1FFFF
9023 +#define SG_OFFSET_MASK 0x0FFF
9024 +#define SG_FORMAT_MASK 0x3
9025 +#define SG_FORMAT_SHIFT 12
9026 +#define SG_BPID_MASK 0x3FFF
9027 +#define SG_FINAL_FLAG_MASK 0x1
9028 +#define SG_FINAL_FLAG_SHIFT 15
9029 +#define FL_SHORT_LEN_FLAG_MASK 0x1
9030 +#define FL_SHORT_LEN_FLAG_SHIFT 14
9031 +#define FL_SHORT_LEN_MASK 0x3FFFF
9032 +#define FL_OFFSET_MASK 0x0FFF
9033 +#define FL_FORMAT_MASK 0x3
9034 +#define FL_FORMAT_SHIFT 12
9035 +#define FL_BPID_MASK 0x3FFF
9036 +#define FL_FINAL_FLAG_MASK 0x1
9037 +#define FL_FINAL_FLAG_SHIFT 15
9038 +
9039 +/* Error bits in FD CTRL */
9040 +#define FD_CTRL_ERR_MASK 0x000000FF
9041 +#define FD_CTRL_UFD 0x00000004
9042 +#define FD_CTRL_SBE 0x00000008
9043 +#define FD_CTRL_FLC 0x00000010
9044 +#define FD_CTRL_FSE 0x00000020
9045 +#define FD_CTRL_FAERR 0x00000040
9046 +
9047 +/* Annotation bits in FD CTRL */
9048 +#define FD_CTRL_PTA 0x00800000
9049 +#define FD_CTRL_PTV1 0x00400000
9050 +
9051 +enum dpaa2_fd_format {
9052 + dpaa2_fd_single = 0,
9053 + dpaa2_fd_list,
9054 + dpaa2_fd_sg
9055 +};
9056 +
9057 +/**
9058 + * dpaa2_fd_get_addr() - get the addr field of frame descriptor
9059 + * @fd: the given frame descriptor
9060 + *
9061 + * Return the address in the frame descriptor.
9062 + */
9063 +static inline dma_addr_t dpaa2_fd_get_addr(const struct dpaa2_fd *fd)
9064 +{
9065 + return (dma_addr_t)le64_to_cpu(fd->simple.addr);
9066 +}
9067 +
9068 +/**
9069 + * dpaa2_fd_set_addr() - Set the addr field of frame descriptor
9070 + * @fd: the given frame descriptor
9071 + * @addr: the address needs to be set in frame descriptor
9072 + */
9073 +static inline void dpaa2_fd_set_addr(struct dpaa2_fd *fd, dma_addr_t addr)
9074 +{
9075 + fd->simple.addr = cpu_to_le64(addr);
9076 +}
9077 +
9078 +/**
9079 + * dpaa2_fd_get_frc() - Get the frame context in the frame descriptor
9080 + * @fd: the given frame descriptor
9081 + *
9082 + * Return the frame context field in the frame descriptor.
9083 + */
9084 +static inline u32 dpaa2_fd_get_frc(const struct dpaa2_fd *fd)
9085 +{
9086 + return le32_to_cpu(fd->simple.frc);
9087 +}
9088 +
9089 +/**
9090 + * dpaa2_fd_set_frc() - Set the frame context in the frame descriptor
9091 + * @fd: the given frame descriptor
9092 + * @frc: the frame context needs to be set in frame descriptor
9093 + */
9094 +static inline void dpaa2_fd_set_frc(struct dpaa2_fd *fd, u32 frc)
9095 +{
9096 + fd->simple.frc = cpu_to_le32(frc);
9097 +}
9098 +
9099 +/**
9100 + * dpaa2_fd_get_ctrl() - Get the control bits in the frame descriptor
9101 + * @fd: the given frame descriptor
9102 + *
9103 + * Return the control bits field in the frame descriptor.
9104 + */
9105 +static inline u32 dpaa2_fd_get_ctrl(const struct dpaa2_fd *fd)
9106 +{
9107 + return le32_to_cpu(fd->simple.ctrl);
9108 +}
9109 +
9110 +/**
9111 + * dpaa2_fd_set_ctrl() - Set the control bits in the frame descriptor
9112 + * @fd: the given frame descriptor
9113 + * @ctrl: the control bits to be set in the frame descriptor
9114 + */
9115 +static inline void dpaa2_fd_set_ctrl(struct dpaa2_fd *fd, u32 ctrl)
9116 +{
9117 + fd->simple.ctrl = cpu_to_le32(ctrl);
9118 +}
9119 +
9120 +/**
9121 + * dpaa2_fd_get_flc() - Get the flow context in the frame descriptor
9122 + * @fd: the given frame descriptor
9123 + *
9124 + * Return the flow context in the frame descriptor.
9125 + */
9126 +static inline dma_addr_t dpaa2_fd_get_flc(const struct dpaa2_fd *fd)
9127 +{
9128 + return (dma_addr_t)le64_to_cpu(fd->simple.flc);
9129 +}
9130 +
9131 +/**
9132 + * dpaa2_fd_set_flc() - Set the flow context field of frame descriptor
9133 + * @fd: the given frame descriptor
9134 + * @flc_addr: the flow context needs to be set in frame descriptor
9135 + */
9136 +static inline void dpaa2_fd_set_flc(struct dpaa2_fd *fd, dma_addr_t flc_addr)
9137 +{
9138 + fd->simple.flc = cpu_to_le64(flc_addr);
9139 +}
9140 +
9141 +static inline bool dpaa2_fd_short_len(const struct dpaa2_fd *fd)
9142 +{
9143 + return !!((le16_to_cpu(fd->simple.format_offset) >>
9144 + FD_SHORT_LEN_FLAG_SHIFT) & FD_SHORT_LEN_FLAG_MASK);
9145 +}
9146 +
9147 +/**
9148 + * dpaa2_fd_get_len() - Get the length in the frame descriptor
9149 + * @fd: the given frame descriptor
9150 + *
9151 + * Return the length field in the frame descriptor.
9152 + */
9153 +static inline u32 dpaa2_fd_get_len(const struct dpaa2_fd *fd)
9154 +{
9155 + if (dpaa2_fd_short_len(fd))
9156 + return le32_to_cpu(fd->simple.len) & FD_SHORT_LEN_MASK;
9157 +
9158 + return le32_to_cpu(fd->simple.len);
9159 +}
9160 +
9161 +/**
9162 + * dpaa2_fd_set_len() - Set the length field of frame descriptor
9163 + * @fd: the given frame descriptor
9164 + * @len: the length needs to be set in frame descriptor
9165 + */
9166 +static inline void dpaa2_fd_set_len(struct dpaa2_fd *fd, u32 len)
9167 +{
9168 + fd->simple.len = cpu_to_le32(len);
9169 +}
9170 +
9171 +/**
9172 + * dpaa2_fd_get_offset() - Get the offset field in the frame descriptor
9173 + * @fd: the given frame descriptor
9174 + *
9175 + * Return the offset.
9176 + */
9177 +static inline uint16_t dpaa2_fd_get_offset(const struct dpaa2_fd *fd)
9178 +{
9179 + return le16_to_cpu(fd->simple.format_offset) & FD_OFFSET_MASK;
9180 +}
9181 +
9182 +/**
9183 + * dpaa2_fd_set_offset() - Set the offset field of frame descriptor
9184 + * @fd: the given frame descriptor
9185 + * @offset: the offset needs to be set in frame descriptor
9186 + */
9187 +static inline void dpaa2_fd_set_offset(struct dpaa2_fd *fd, uint16_t offset)
9188 +{
9189 + fd->simple.format_offset &= cpu_to_le16(~FD_OFFSET_MASK);
9190 + fd->simple.format_offset |= cpu_to_le16(offset);
9191 +}
9192 +
9193 +/**
9194 + * dpaa2_fd_get_format() - Get the format field in the frame descriptor
9195 + * @fd: the given frame descriptor
9196 + *
9197 + * Return the format.
9198 + */
9199 +static inline enum dpaa2_fd_format dpaa2_fd_get_format(
9200 + const struct dpaa2_fd *fd)
9201 +{
9202 + return (enum dpaa2_fd_format)((le16_to_cpu(fd->simple.format_offset)
9203 + >> FD_FORMAT_SHIFT) & FD_FORMAT_MASK);
9204 +}
9205 +
9206 +/**
9207 + * dpaa2_fd_set_format() - Set the format field of frame descriptor
9208 + * @fd: the given frame descriptor
9209 + * @format: the format needs to be set in frame descriptor
9210 + */
9211 +static inline void dpaa2_fd_set_format(struct dpaa2_fd *fd,
9212 + enum dpaa2_fd_format format)
9213 +{
9214 + fd->simple.format_offset &=
9215 + cpu_to_le16(~(FD_FORMAT_MASK << FD_FORMAT_SHIFT));
9216 + fd->simple.format_offset |= cpu_to_le16(format << FD_FORMAT_SHIFT);
9217 +}
9218 +
9219 +/**
9220 + * dpaa2_fd_get_bpid() - Get the bpid field in the frame descriptor
9221 + * @fd: the given frame descriptor
9222 + *
9223 + * Return the buffer pool id.
9224 + */
9225 +static inline uint16_t dpaa2_fd_get_bpid(const struct dpaa2_fd *fd)
9226 +{
9227 + return le16_to_cpu(fd->simple.bpid) & FD_BPID_MASK;
9228 +}
9229 +
9230 +/**
9231 + * dpaa2_fd_set_bpid() - Set the bpid field of frame descriptor
9232 + * @fd: the given frame descriptor
9233 + * @bpid: buffer pool id to be set
9234 + */
9235 +static inline void dpaa2_fd_set_bpid(struct dpaa2_fd *fd, uint16_t bpid)
9236 +{
9237 + fd->simple.bpid &= cpu_to_le16(~(FD_BPID_MASK));
9238 + fd->simple.bpid |= cpu_to_le16(bpid);
9239 +}
9240 +
9241 +/**
9242 + * struct dpaa2_sg_entry - the scatter-gathering structure
9243 + * @addr: address of the sg entry
9244 + * @len: length in this sg entry
9245 + * @bpid: buffer pool id
9246 + * @format_offset: format and offset fields
9247 + */
9248 +struct dpaa2_sg_entry {
9249 + __le64 addr;
9250 + __le32 len;
9251 + __le16 bpid;
9252 + __le16 format_offset;
9253 +};
9254 +
9255 +enum dpaa2_sg_format {
9256 + dpaa2_sg_single = 0,
9257 + dpaa2_sg_frame_data,
9258 + dpaa2_sg_sgt_ext
9259 +};
9260 +
9261 +/* Accessors for SG entry fields */
9262 +
9263 +/**
9264 + * dpaa2_sg_get_addr() - Get the address from SG entry
9265 + * @sg: the given scatter-gathering object
9266 + *
9267 + * Return the address.
9268 + */
9269 +static inline dma_addr_t dpaa2_sg_get_addr(const struct dpaa2_sg_entry *sg)
9270 +{
9271 + return le64_to_cpu((dma_addr_t)sg->addr);
9272 +}
9273 +
9274 +/**
9275 + * dpaa2_sg_set_addr() - Set the address in SG entry
9276 + * @sg: the given scatter-gathering object
9277 + * @addr: the address to be set
9278 + */
9279 +static inline void dpaa2_sg_set_addr(struct dpaa2_sg_entry *sg, dma_addr_t addr)
9280 +{
9281 + sg->addr = cpu_to_le64(addr);
9282 +}
9283 +
9284 +static inline bool dpaa2_sg_short_len(const struct dpaa2_sg_entry *sg)
9285 +{
9286 + return !!((le16_to_cpu(sg->format_offset) >> SG_SHORT_LEN_FLAG_SHIFT)
9287 + & SG_SHORT_LEN_FLAG_MASK);
9288 +}
9289 +
9290 +/**
9291 + * dpaa2_sg_get_len() - Get the length in SG entry
9292 + * @sg: the given scatter-gathering object
9293 + *
9294 + * Return the length.
9295 + */
9296 +static inline u32 dpaa2_sg_get_len(const struct dpaa2_sg_entry *sg)
9297 +{
9298 + if (dpaa2_sg_short_len(sg))
9299 + return le32_to_cpu(sg->len) & SG_SHORT_LEN_MASK;
9300 +
9301 + return le32_to_cpu(sg->len);
9302 +}
9303 +
9304 +/**
9305 + * dpaa2_sg_set_len() - Set the length in SG entry
9306 + * @sg: the given scatter-gathering object
9307 + * @len: the length to be set
9308 + */
9309 +static inline void dpaa2_sg_set_len(struct dpaa2_sg_entry *sg, u32 len)
9310 +{
9311 + sg->len = cpu_to_le32(len);
9312 +}
9313 +
9314 +/**
9315 + * dpaa2_sg_get_offset() - Get the offset in SG entry
9316 + * @sg: the given scatter-gathering object
9317 + *
9318 + * Return the offset.
9319 + */
9320 +static inline u16 dpaa2_sg_get_offset(const struct dpaa2_sg_entry *sg)
9321 +{
9322 + return le16_to_cpu(sg->format_offset) & SG_OFFSET_MASK;
9323 +}
9324 +
9325 +/**
9326 + * dpaa2_sg_set_offset() - Set the offset in SG entry
9327 + * @sg: the given scatter-gathering object
9328 + * @offset: the offset to be set
9329 + */
9330 +static inline void dpaa2_sg_set_offset(struct dpaa2_sg_entry *sg,
9331 + u16 offset)
9332 +{
9333 + sg->format_offset &= cpu_to_le16(~SG_OFFSET_MASK);
9334 + sg->format_offset |= cpu_to_le16(offset);
9335 +}
9336 +
9337 +/**
9338 + * dpaa2_sg_get_format() - Get the SG format in SG entry
9339 + * @sg: the given scatter-gathering object
9340 + *
9341 + * Return the format.
9342 + */
9343 +static inline enum dpaa2_sg_format
9344 + dpaa2_sg_get_format(const struct dpaa2_sg_entry *sg)
9345 +{
9346 + return (enum dpaa2_sg_format)((le16_to_cpu(sg->format_offset)
9347 + >> SG_FORMAT_SHIFT) & SG_FORMAT_MASK);
9348 +}
9349 +
9350 +/**
9351 + * dpaa2_sg_set_format() - Set the SG format in SG entry
9352 + * @sg: the given scatter-gathering object
9353 + * @format: the format to be set
9354 + */
9355 +static inline void dpaa2_sg_set_format(struct dpaa2_sg_entry *sg,
9356 + enum dpaa2_sg_format format)
9357 +{
9358 + sg->format_offset &= cpu_to_le16(~(SG_FORMAT_MASK << SG_FORMAT_SHIFT));
9359 + sg->format_offset |= cpu_to_le16(format << SG_FORMAT_SHIFT);
9360 +}
9361 +
9362 +/**
9363 + * dpaa2_sg_get_bpid() - Get the buffer pool id in SG entry
9364 + * @sg: the given scatter-gathering object
9365 + *
9366 + * Return the bpid.
9367 + */
9368 +static inline u16 dpaa2_sg_get_bpid(const struct dpaa2_sg_entry *sg)
9369 +{
9370 + return le16_to_cpu(sg->bpid) & SG_BPID_MASK;
9371 +}
9372 +
9373 +/**
9374 + * dpaa2_sg_set_bpid() - Set the buffer pool id in SG entry
9375 + * @sg: the given scatter-gathering object
9376 + * @bpid: the bpid to be set
9377 + */
9378 +static inline void dpaa2_sg_set_bpid(struct dpaa2_sg_entry *sg, u16 bpid)
9379 +{
9380 + sg->bpid &= cpu_to_le16(~(SG_BPID_MASK));
9381 + sg->bpid |= cpu_to_le16(bpid);
9382 +}
9383 +
9384 +/**
9385 + * dpaa2_sg_is_final() - Check final bit in SG entry
9386 + * @sg: the given scatter-gathering object
9387 + *
9388 + * Return bool.
9389 + */
9390 +static inline bool dpaa2_sg_is_final(const struct dpaa2_sg_entry *sg)
9391 +{
9392 + return !!(le16_to_cpu(sg->format_offset) >> SG_FINAL_FLAG_SHIFT);
9393 +}
9394 +
9395 +/**
9396 + * dpaa2_sg_set_final() - Set the final bit in SG entry
9397 + * @sg: the given scatter-gathering object
9398 + * @final: the final boolean to be set
9399 + */
9400 +static inline void dpaa2_sg_set_final(struct dpaa2_sg_entry *sg, bool final)
9401 +{
9402 + sg->format_offset &= cpu_to_le16(~(SG_FINAL_FLAG_MASK
9403 + << SG_FINAL_FLAG_SHIFT));
9404 + sg->format_offset |= cpu_to_le16(final << SG_FINAL_FLAG_SHIFT);
9405 +}
9406 +
9407 +/**
9408 + * struct dpaa2_fl_entry - structure for frame list entry.
9409 + * @addr: address in the FLE
9410 + * @len: length in the FLE
9411 + * @bpid: buffer pool ID
9412 + * @format_offset: format, offset, and short-length fields
9413 + * @frc: frame context
9414 + * @ctrl: control bits...including pta, pvt1, pvt2, err, etc
9415 + * @flc: flow context address
9416 + */
9417 +struct dpaa2_fl_entry {
9418 + __le64 addr;
9419 + __le32 len;
9420 + __le16 bpid;
9421 + __le16 format_offset;
9422 + __le32 frc;
9423 + __le32 ctrl;
9424 + __le64 flc;
9425 +};
9426 +
9427 +enum dpaa2_fl_format {
9428 + dpaa2_fl_single = 0,
9429 + dpaa2_fl_res,
9430 + dpaa2_fl_sg
9431 +};
9432 +
9433 +/**
9434 + * dpaa2_fl_get_addr() - get the addr field of FLE
9435 + * @fle: the given frame list entry
9436 + *
9437 + * Return the address in the frame list entry.
9438 + */
9439 +static inline dma_addr_t dpaa2_fl_get_addr(const struct dpaa2_fl_entry *fle)
9440 +{
9441 + return (dma_addr_t)le64_to_cpu(fle->addr);
9442 +}
9443 +
9444 +/**
9445 + * dpaa2_fl_set_addr() - Set the addr field of FLE
9446 + * @fle: the given frame list entry
9447 + * @addr: the address needs to be set in frame list entry
9448 + */
9449 +static inline void dpaa2_fl_set_addr(struct dpaa2_fl_entry *fle,
9450 + dma_addr_t addr)
9451 +{
9452 + fle->addr = cpu_to_le64(addr);
9453 +}
9454 +
9455 +/**
9456 + * dpaa2_fl_get_frc() - Get the frame context in the FLE
9457 + * @fle: the given frame list entry
9458 + *
9459 + * Return the frame context field in the frame lsit entry.
9460 + */
9461 +static inline u32 dpaa2_fl_get_frc(const struct dpaa2_fl_entry *fle)
9462 +{
9463 + return le32_to_cpu(fle->frc);
9464 +}
9465 +
9466 +/**
9467 + * dpaa2_fl_set_frc() - Set the frame context in the FLE
9468 + * @fle: the given frame list entry
9469 + * @frc: the frame context needs to be set in frame list entry
9470 + */
9471 +static inline void dpaa2_fl_set_frc(struct dpaa2_fl_entry *fle, u32 frc)
9472 +{
9473 + fle->frc = cpu_to_le32(frc);
9474 +}
9475 +
9476 +/**
9477 + * dpaa2_fl_get_ctrl() - Get the control bits in the FLE
9478 + * @fle: the given frame list entry
9479 + *
9480 + * Return the control bits field in the frame list entry.
9481 + */
9482 +static inline u32 dpaa2_fl_get_ctrl(const struct dpaa2_fl_entry *fle)
9483 +{
9484 + return le32_to_cpu(fle->ctrl);
9485 +}
9486 +
9487 +/**
9488 + * dpaa2_fl_set_ctrl() - Set the control bits in the FLE
9489 + * @fle: the given frame list entry
9490 + * @ctrl: the control bits to be set in the frame list entry
9491 + */
9492 +static inline void dpaa2_fl_set_ctrl(struct dpaa2_fl_entry *fle, u32 ctrl)
9493 +{
9494 + fle->ctrl = cpu_to_le32(ctrl);
9495 +}
9496 +
9497 +/**
9498 + * dpaa2_fl_get_flc() - Get the flow context in the FLE
9499 + * @fle: the given frame list entry
9500 + *
9501 + * Return the flow context in the frame list entry.
9502 + */
9503 +static inline dma_addr_t dpaa2_fl_get_flc(const struct dpaa2_fl_entry *fle)
9504 +{
9505 + return (dma_addr_t)le64_to_cpu(fle->flc);
9506 +}
9507 +
9508 +/**
9509 + * dpaa2_fl_set_flc() - Set the flow context field of FLE
9510 + * @fle: the given frame list entry
9511 + * @flc_addr: the flow context needs to be set in frame list entry
9512 + */
9513 +static inline void dpaa2_fl_set_flc(struct dpaa2_fl_entry *fle,
9514 + dma_addr_t flc_addr)
9515 +{
9516 + fle->flc = cpu_to_le64(flc_addr);
9517 +}
9518 +
9519 +static inline bool dpaa2_fl_short_len(const struct dpaa2_fl_entry *fle)
9520 +{
9521 + return !!((le16_to_cpu(fle->format_offset) >>
9522 + FL_SHORT_LEN_FLAG_SHIFT) & FL_SHORT_LEN_FLAG_MASK);
9523 +}
9524 +
9525 +/**
9526 + * dpaa2_fl_get_len() - Get the length in the FLE
9527 + * @fle: the given frame list entry
9528 + *
9529 + * Return the length field in the frame list entry.
9530 + */
9531 +static inline u32 dpaa2_fl_get_len(const struct dpaa2_fl_entry *fle)
9532 +{
9533 + if (dpaa2_fl_short_len(fle))
9534 + return le32_to_cpu(fle->len) & FL_SHORT_LEN_MASK;
9535 +
9536 + return le32_to_cpu(fle->len);
9537 +}
9538 +
9539 +/**
9540 + * dpaa2_fl_set_len() - Set the length field of FLE
9541 + * @fle: the given frame list entry
9542 + * @len: the length needs to be set in frame list entry
9543 + */
9544 +static inline void dpaa2_fl_set_len(struct dpaa2_fl_entry *fle, u32 len)
9545 +{
9546 + fle->len = cpu_to_le32(len);
9547 +}
9548 +
9549 +/**
9550 + * dpaa2_fl_get_offset() - Get the offset field in the frame list entry
9551 + * @fle: the given frame list entry
9552 + *
9553 + * Return the offset.
9554 + */
9555 +static inline u16 dpaa2_fl_get_offset(const struct dpaa2_fl_entry *fle)
9556 +{
9557 + return le16_to_cpu(fle->format_offset) & FL_OFFSET_MASK;
9558 +}
9559 +
9560 +/**
9561 + * dpaa2_fl_set_offset() - Set the offset field of FLE
9562 + * @fle: the given frame list entry
9563 + * @offset: the offset needs to be set in frame list entry
9564 + */
9565 +static inline void dpaa2_fl_set_offset(struct dpaa2_fl_entry *fle, u16 offset)
9566 +{
9567 + fle->format_offset &= cpu_to_le16(~FL_OFFSET_MASK);
9568 + fle->format_offset |= cpu_to_le16(offset);
9569 +}
9570 +
9571 +/**
9572 + * dpaa2_fl_get_format() - Get the format field in the FLE
9573 + * @fle: the given frame list entry
9574 + *
9575 + * Return the format.
9576 + */
9577 +static inline enum dpaa2_fl_format dpaa2_fl_get_format(
9578 + const struct dpaa2_fl_entry *fle)
9579 +{
9580 + return (enum dpaa2_fl_format)((le16_to_cpu(fle->format_offset) >>
9581 + FL_FORMAT_SHIFT) & FL_FORMAT_MASK);
9582 +}
9583 +
9584 +/**
9585 + * dpaa2_fl_set_format() - Set the format field of FLE
9586 + * @fle: the given frame list entry
9587 + * @format: the format needs to be set in frame list entry
9588 + */
9589 +static inline void dpaa2_fl_set_format(struct dpaa2_fl_entry *fle,
9590 + enum dpaa2_fl_format format)
9591 +{
9592 + fle->format_offset &= cpu_to_le16(~(FL_FORMAT_MASK << FL_FORMAT_SHIFT));
9593 + fle->format_offset |= cpu_to_le16(format << FL_FORMAT_SHIFT);
9594 +}
9595 +
9596 +/**
9597 + * dpaa2_fl_get_bpid() - Get the bpid field in the FLE
9598 + * @fle: the given frame list entry
9599 + *
9600 + * Return the buffer pool id.
9601 + */
9602 +static inline u16 dpaa2_fl_get_bpid(const struct dpaa2_fl_entry *fle)
9603 +{
9604 + return le16_to_cpu(fle->bpid) & FL_BPID_MASK;
9605 +}
9606 +
9607 +/**
9608 + * dpaa2_fl_set_bpid() - Set the bpid field of FLE
9609 + * @fle: the given frame list entry
9610 + * @bpid: buffer pool id to be set
9611 + */
9612 +static inline void dpaa2_fl_set_bpid(struct dpaa2_fl_entry *fle, u16 bpid)
9613 +{
9614 + fle->bpid &= cpu_to_le16(~(FL_BPID_MASK));
9615 + fle->bpid |= cpu_to_le16(bpid);
9616 +}
9617 +
9618 +/**
9619 + * dpaa2_fl_is_final() - Check final bit in FLE
9620 + * @fle: the given frame list entry
9621 + *
9622 + * Return bool.
9623 + */
9624 +static inline bool dpaa2_fl_is_final(const struct dpaa2_fl_entry *fle)
9625 +{
9626 + return !!(le16_to_cpu(fle->format_offset) >> FL_FINAL_FLAG_SHIFT);
9627 +}
9628 +
9629 +/**
9630 + * dpaa2_fl_set_final() - Set the final bit in FLE
9631 + * @fle: the given frame list entry
9632 + * @final: the final boolean to be set
9633 + */
9634 +static inline void dpaa2_fl_set_final(struct dpaa2_fl_entry *fle, bool final)
9635 +{
9636 + fle->format_offset &= cpu_to_le16(~(FL_FINAL_FLAG_MASK <<
9637 + FL_FINAL_FLAG_SHIFT));
9638 + fle->format_offset |= cpu_to_le16(final << FL_FINAL_FLAG_SHIFT);
9639 +}
9640 +
9641 +#endif /* __FSL_DPAA2_FD_H */
9642 --- /dev/null
9643 +++ b/drivers/staging/fsl-mc/include/dpaa2-global.h
9644 @@ -0,0 +1,202 @@
9645 +/*
9646 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9647 + * Copyright 2016 NXP
9648 + *
9649 + * Redistribution and use in source and binary forms, with or without
9650 + * modification, are permitted provided that the following conditions are met:
9651 + * * Redistributions of source code must retain the above copyright
9652 + * notice, this list of conditions and the following disclaimer.
9653 + * * Redistributions in binary form must reproduce the above copyright
9654 + * notice, this list of conditions and the following disclaimer in the
9655 + * documentation and/or other materials provided with the distribution.
9656 + * * Neither the name of Freescale Semiconductor nor the
9657 + * names of its contributors may be used to endorse or promote products
9658 + * derived from this software without specific prior written permission.
9659 + *
9660 + * ALTERNATIVELY, this software may be distributed under the terms of the
9661 + * GNU General Public License ("GPL") as published by the Free Software
9662 + * Foundation, either version 2 of that License or (at your option) any
9663 + * later version.
9664 + *
9665 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9666 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9667 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9668 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9669 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9670 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9671 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9672 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9673 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9674 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9675 + */
9676 +#ifndef __FSL_DPAA2_GLOBAL_H
9677 +#define __FSL_DPAA2_GLOBAL_H
9678 +
9679 +#include <linux/types.h>
9680 +#include <linux/cpumask.h>
9681 +#include "dpaa2-fd.h"
9682 +
9683 +struct dpaa2_dq {
9684 + union {
9685 + struct common {
9686 + u8 verb;
9687 + u8 reserved[63];
9688 + } common;
9689 + struct dq {
9690 + u8 verb;
9691 + u8 stat;
9692 + __le16 seqnum;
9693 + __le16 oprid;
9694 + u8 reserved;
9695 + u8 tok;
9696 + __le32 fqid;
9697 + u32 reserved2;
9698 + __le32 fq_byte_cnt;
9699 + __le32 fq_frm_cnt;
9700 + __le64 fqd_ctx;
9701 + u8 fd[32];
9702 + } dq;
9703 + struct scn {
9704 + u8 verb;
9705 + u8 stat;
9706 + u8 state;
9707 + u8 reserved;
9708 + __le32 rid_tok;
9709 + __le64 ctx;
9710 + } scn;
9711 + };
9712 +};
9713 +
9714 +/* Parsing frame dequeue results */
9715 +/* FQ empty */
9716 +#define DPAA2_DQ_STAT_FQEMPTY 0x80
9717 +/* FQ held active */
9718 +#define DPAA2_DQ_STAT_HELDACTIVE 0x40
9719 +/* FQ force eligible */
9720 +#define DPAA2_DQ_STAT_FORCEELIGIBLE 0x20
9721 +/* valid frame */
9722 +#define DPAA2_DQ_STAT_VALIDFRAME 0x10
9723 +/* FQ ODP enable */
9724 +#define DPAA2_DQ_STAT_ODPVALID 0x04
9725 +/* volatile dequeue */
9726 +#define DPAA2_DQ_STAT_VOLATILE 0x02
9727 +/* volatile dequeue command is expired */
9728 +#define DPAA2_DQ_STAT_EXPIRED 0x01
9729 +
9730 +#define DQ_FQID_MASK 0x00FFFFFF
9731 +#define DQ_FRAME_COUNT_MASK 0x00FFFFFF
9732 +
9733 +/**
9734 + * dpaa2_dq_flags() - Get the stat field of dequeue response
9735 + * @dq: the dequeue result.
9736 + */
9737 +static inline u32 dpaa2_dq_flags(const struct dpaa2_dq *dq)
9738 +{
9739 + return dq->dq.stat;
9740 +}
9741 +
9742 +/**
9743 + * dpaa2_dq_is_pull() - Check whether the dq response is from a pull
9744 + * command.
9745 + * @dq: the dequeue result
9746 + *
9747 + * Return 1 for volatile(pull) dequeue, 0 for static dequeue.
9748 + */
9749 +static inline int dpaa2_dq_is_pull(const struct dpaa2_dq *dq)
9750 +{
9751 + return (int)(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_VOLATILE);
9752 +}
9753 +
9754 +/**
9755 + * dpaa2_dq_is_pull_complete() - Check whether the pull command is completed.
9756 + * @dq: the dequeue result
9757 + *
9758 + * Return boolean.
9759 + */
9760 +static inline bool dpaa2_dq_is_pull_complete(const struct dpaa2_dq *dq)
9761 +{
9762 + return !!(dpaa2_dq_flags(dq) & DPAA2_DQ_STAT_EXPIRED);
9763 +}
9764 +
9765 +/**
9766 + * dpaa2_dq_seqnum() - Get the seqnum field in dequeue response
9767 + * @dq: the dequeue result
9768 + *
9769 + * seqnum is valid only if VALIDFRAME flag is TRUE
9770 + *
9771 + * Return seqnum.
9772 + */
9773 +static inline u16 dpaa2_dq_seqnum(const struct dpaa2_dq *dq)
9774 +{
9775 + return le16_to_cpu(dq->dq.seqnum);
9776 +}
9777 +
9778 +/**
9779 + * dpaa2_dq_odpid() - Get the odpid field in dequeue response
9780 + * @dq: the dequeue result
9781 + *
9782 + * odpid is valid only if ODPVALID flag is TRUE.
9783 + *
9784 + * Return odpid.
9785 + */
9786 +static inline u16 dpaa2_dq_odpid(const struct dpaa2_dq *dq)
9787 +{
9788 + return le16_to_cpu(dq->dq.oprid);
9789 +}
9790 +
9791 +/**
9792 + * dpaa2_dq_fqid() - Get the fqid in dequeue response
9793 + * @dq: the dequeue result
9794 + *
9795 + * Return fqid.
9796 + */
9797 +static inline u32 dpaa2_dq_fqid(const struct dpaa2_dq *dq)
9798 +{
9799 + return le32_to_cpu(dq->dq.fqid) & DQ_FQID_MASK;
9800 +}
9801 +
9802 +/**
9803 + * dpaa2_dq_byte_count() - Get the byte count in dequeue response
9804 + * @dq: the dequeue result
9805 + *
9806 + * Return the byte count remaining in the FQ.
9807 + */
9808 +static inline u32 dpaa2_dq_byte_count(const struct dpaa2_dq *dq)
9809 +{
9810 + return le32_to_cpu(dq->dq.fq_byte_cnt);
9811 +}
9812 +
9813 +/**
9814 + * dpaa2_dq_frame_count() - Get the frame count in dequeue response
9815 + * @dq: the dequeue result
9816 + *
9817 + * Return the frame count remaining in the FQ.
9818 + */
9819 +static inline u32 dpaa2_dq_frame_count(const struct dpaa2_dq *dq)
9820 +{
9821 + return le32_to_cpu(dq->dq.fq_frm_cnt) & DQ_FRAME_COUNT_MASK;
9822 +}
9823 +
9824 +/**
9825 + * dpaa2_dq_fd_ctx() - Get the frame queue context in dequeue response
9826 + * @dq: the dequeue result
9827 + *
9828 + * Return the frame queue context.
9829 + */
9830 +static inline u64 dpaa2_dq_fqd_ctx(const struct dpaa2_dq *dq)
9831 +{
9832 + return le64_to_cpu(dq->dq.fqd_ctx);
9833 +}
9834 +
9835 +/**
9836 + * dpaa2_dq_fd() - Get the frame descriptor in dequeue response
9837 + * @dq: the dequeue result
9838 + *
9839 + * Return the frame descriptor.
9840 + */
9841 +static inline const struct dpaa2_fd *dpaa2_dq_fd(const struct dpaa2_dq *dq)
9842 +{
9843 + return (const struct dpaa2_fd *)&dq->dq.fd[0];
9844 +}
9845 +
9846 +#endif /* __FSL_DPAA2_GLOBAL_H */
9847 --- /dev/null
9848 +++ b/drivers/staging/fsl-mc/include/dpaa2-io.h
9849 @@ -0,0 +1,190 @@
9850 +/*
9851 + * Copyright 2014-2016 Freescale Semiconductor Inc.
9852 + * Copyright 2017 NXP
9853 + *
9854 + * Redistribution and use in source and binary forms, with or without
9855 + * modification, are permitted provided that the following conditions are met:
9856 + * * Redistributions of source code must retain the above copyright
9857 + * notice, this list of conditions and the following disclaimer.
9858 + * * Redistributions in binary form must reproduce the above copyright
9859 + * notice, this list of conditions and the following disclaimer in the
9860 + * documentation and/or other materials provided with the distribution.
9861 + * * Neither the name of Freescale Semiconductor nor the
9862 + * names of its contributors may be used to endorse or promote products
9863 + * derived from this software without specific prior written permission.
9864 + *
9865 + * ALTERNATIVELY, this software may be distributed under the terms of the
9866 + * GNU General Public License ("GPL") as published by the Free Software
9867 + * Foundation, either version 2 of that License or (at your option) any
9868 + * later version.
9869 + *
9870 + * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
9871 + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
9872 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
9873 + * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
9874 + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
9875 + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
9876 + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
9877 + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9878 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
9879 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9880 + */
9881 +#ifndef __FSL_DPAA2_IO_H
9882 +#define __FSL_DPAA2_IO_H
9883 +
9884 +#include <linux/types.h>
9885 +#include <linux/cpumask.h>
9886 +
9887 +#include "dpaa2-fd.h"
9888 +#include "dpaa2-global.h"
9889 +
9890 +struct dpaa2_io;
9891 +struct dpaa2_io_store;
9892 +struct device;
9893 +
9894 +/**
9895 + * DOC: DPIO Service
9896 + *
9897 + * The DPIO service provides APIs for users to interact with the datapath
9898 + * by enqueueing and dequeing frame descriptors.
9899 + *
9900 + * The following set of APIs can be used to enqueue and dequeue frames
9901 + * as well as producing notification callbacks when data is available
9902 + * for dequeue.
9903 + */
9904 +
9905 +/**
9906 + * struct dpaa2_io_desc - The DPIO descriptor
9907 + * @receives_notifications: Use notificaton mode. Non-zero if the DPIO
9908 + * has a channel.
9909 + * @has_8prio: Set to non-zero for channel with 8 priority WQs. Ignored
9910 + * unless receives_notification is TRUE.
9911 + * @cpu: The cpu index that at least interrupt handlers will
9912 + * execute on.
9913 + * @stash_affinity: The stash affinity for this portal favour 'cpu'
9914 + * @regs_cena: The cache enabled regs.
9915 + * @regs_cinh: The cache inhibited regs
9916 + * @dpio_id: The dpio index
9917 + * @qman_version: The qman version
9918 + *
9919 + * Describes the attributes and features of the DPIO object.
9920 + */
9921 +struct dpaa2_io_desc {
9922 + int receives_notifications;
9923 + int has_8prio;
9924 + int cpu;
9925 + void *regs_cena;
9926 + void *regs_cinh;
9927 + int dpio_id;
9928 + u32 qman_version;
9929 +};
9930 +
9931 +struct dpaa2_io *dpaa2_io_create(const struct dpaa2_io_desc *desc);
9932 +
9933 +void dpaa2_io_down(struct dpaa2_io *d);
9934 +
9935 +irqreturn_t dpaa2_io_irq(struct dpaa2_io *obj);
9936 +
9937 +/**
9938 + * struct dpaa2_io_notification_ctx - The DPIO notification context structure
9939 + * @cb: The callback to be invoked when the notification arrives
9940 + * @is_cdan: Zero for FQDAN, non-zero for CDAN
9941 + * @id: FQID or channel ID, needed for rearm
9942 + * @desired_cpu: The cpu on which the notifications will show up. -1 means
9943 + * any CPU.
9944 + * @dpio_id: The dpio index
9945 + * @qman64: The 64-bit context value shows up in the FQDAN/CDAN.
9946 + * @node: The list node
9947 + * @dpio_private: The dpio object internal to dpio_service
9948 + *
9949 + * Used when a FQDAN/CDAN registration is made by drivers.
9950 + */
9951 +struct dpaa2_io_notification_ctx {
9952 + void (*cb)(struct dpaa2_io_notification_ctx *);
9953 + int is_cdan;
9954 + u32 id;
9955 + int desired_cpu;
9956 + int dpio_id;
9957 + u64 qman64;
9958 + struct list_head node;
9959 + void *dpio_private;
9960 +};
9961 +
9962 +int dpaa2_io_service_register(struct dpaa2_io *service,
9963 + struct dpaa2_io_notification_ctx *ctx);
9964 +void dpaa2_io_service_deregister(struct dpaa2_io *service,
9965 + struct dpaa2_io_notification_ctx *ctx);
9966 +int dpaa2_io_service_rearm(struct dpaa2_io *service,
9967 + struct dpaa2_io_notification_ctx *ctx);
9968 +
9969 +int dpaa2_io_service_pull_fq(struct dpaa2_io *d, u32 fqid,
9970 + struct dpaa2_io_store *s);
9971 +int dpaa2_io_service_pull_channel(struct dpaa2_io *d, u32 channelid,
9972 + struct dpaa2_io_store *s);
9973 +
9974 +int dpaa2_io_service_enqueue_fq(struct dpaa2_io *d, u32 fqid,
9975 + const struct dpaa2_fd *fd);
9976 +int dpaa2_io_service_enqueue_qd(struct dpaa2_io *d, u32 qdid, u8 prio,
9977 + u16 qdbin, const struct dpaa2_fd *fd);
9978 +int dpaa2_io_service_release(struct dpaa2_io *d, u32 bpid,
9979 + const u64 *buffers, unsigned int num_buffers);
9980 +int dpaa2_io_service_acquire(struct dpaa2_io *d, u32 bpid,
9981 + u64 *buffers, unsigned int num_buffers);
9982 +
9983 +struct dpaa2_io_store *dpaa2_io_store_create(unsigned int max_frames,
9984 + struct device *dev);
9985 +void dpaa2_io_store_destroy(struct dpaa2_io_store *s);
9986 +struct dpaa2_dq *dpaa2_io_store_next(struct dpaa2_io_store *s, int *is_last);
9987 +
9988 +#ifdef CONFIG_FSL_QBMAN_DEBUG
9989 +int dpaa2_io_query_fq_count(struct dpaa2_io *d, uint32_t fqid,
9990 + uint32_t *fcnt, uint32_t *bcnt);
9991 +int dpaa2_io_query_bp_count(struct dpaa2_io *d, uint32_t bpid,
9992 + uint32_t *num);
9993 +#endif
9994 +
9995 +
9996 +/***************/
9997 +/* CSCN */
9998 +/***************/
9999 +
10000 +/**
10001 + * struct dpaa2_cscn - The CSCN message format
10002 + * @verb: identifies the type of message (should be 0x27).
10003 + * @stat: status bits related to dequeuing response (not used)
10004 + * @state: bit 0 = 0/1 if CG is no/is congested
10005 + * @reserved: reserved byte
10006 + * @cgid: congest grp ID - the first 16 bits
10007 + * @ctx: context data
10008 + *
10009 + * Congestion management can be implemented in software through
10010 + * the use of Congestion State Change Notifications (CSCN). These
10011 + * are messages written by DPAA2 hardware to memory whenever the
10012 + * instantaneous count (I_CNT field in the CG) exceeds the
10013 + * Congestion State (CS) entrance threshold, signifying congestion
10014 + * entrance, or when the instantaneous count returns below exit
10015 + * threshold, signifying congestion exit. The format of the message
10016 + * is given by the dpaa2_cscn structure. Bit 0 of the state field
10017 + * represents congestion state written by the hardware.
10018 + */
10019 +struct dpaa2_cscn {
10020 + u8 verb;
10021 + u8 stat;
10022 + u8 state;
10023 + u8 reserved;
10024 + __le32 cgid;
10025 + __le64 ctx;
10026 +};
10027 +
10028 +#define DPAA2_CSCN_SIZE 64
10029 +#define DPAA2_CSCN_ALIGN 16
10030 +
10031 +#define DPAA2_CSCN_STATE_MASK 0x1
10032 +#define DPAA2_CSCN_CONGESTED 1
10033 +
10034 +static inline bool dpaa2_cscn_state_congested(struct dpaa2_cscn *cscn)
10035 +{
10036 + return ((cscn->state & DPAA2_CSCN_STATE_MASK) == DPAA2_CSCN_CONGESTED);
10037 +}
10038 +
10039 +#endif /* __FSL_DPAA2_IO_H */
10040 --- a/drivers/staging/fsl-mc/include/dpbp-cmd.h
10041 +++ /dev/null
10042 @@ -1,185 +0,0 @@
10043 -/* Copyright 2013-2016 Freescale Semiconductor Inc.
10044 - *
10045 - * Redistribution and use in source and binary forms, with or without
10046 - * modification, are permitted provided that the following conditions are met:
10047 - * * Redistributions of source code must retain the above copyright
10048 - * notice, this list of conditions and the following disclaimer.
10049 - * * Redistributions in binary form must reproduce the above copyright
10050 - * notice, this list of conditions and the following disclaimer in the
10051 - * documentation and/or other materials provided with the distribution.
10052 - * * Neither the name of the above-listed copyright holders nor the
10053 - * names of any contributors may be used to endorse or promote products
10054 - * derived from this software without specific prior written permission.
10055 - *
10056 - *
10057 - * ALTERNATIVELY, this software may be distributed under the terms of the
10058 - * GNU General Public License ("GPL") as published by the Free Software
10059 - * Foundation, either version 2 of that License or (at your option) any
10060 - * later version.
10061 - *
10062 - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10063 - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10064 - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10065 - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10066 - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10067 - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10068 - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10069 - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10070 - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10071 - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10072 - * POSSIBILITY OF SUCH DAMAGE.
10073 - */
10074 -#ifndef _FSL_DPBP_CMD_H
10075 -#define _FSL_DPBP_CMD_H
10076 -
10077 -/* DPBP Version */
10078 -#define DPBP_VER_MAJOR 2
10079 -#define DPBP_VER_MINOR 2
10080 -
10081 -/* Command IDs */
10082 -#define DPBP_CMDID_CLOSE 0x800
10083 -#define DPBP_CMDID_OPEN 0x804
10084 -#define DPBP_CMDID_CREATE 0x904
10085 -#define DPBP_CMDID_DESTROY 0x900
10086 -
10087 -#define DPBP_CMDID_ENABLE 0x002
10088 -#define DPBP_CMDID_DISABLE 0x003
10089 -#define DPBP_CMDID_GET_ATTR 0x004
10090 -#define DPBP_CMDID_RESET 0x005
10091 -#define DPBP_CMDID_IS_ENABLED 0x006
10092 -
10093 -#define DPBP_CMDID_SET_IRQ 0x010
10094 -#define DPBP_CMDID_GET_IRQ 0x011
10095 -#define DPBP_CMDID_SET_IRQ_ENABLE 0x012
10096 -#define DPBP_CMDID_GET_IRQ_ENABLE 0x013
10097 -#define DPBP_CMDID_SET_IRQ_MASK 0x014
10098 -#define DPBP_CMDID_GET_IRQ_MASK 0x015
10099 -#define DPBP_CMDID_GET_IRQ_STATUS 0x016
10100 -#define DPBP_CMDID_CLEAR_IRQ_STATUS 0x017
10101 -
10102 -#define DPBP_CMDID_SET_NOTIFICATIONS 0x01b0
10103 -#define DPBP_CMDID_GET_NOTIFICATIONS 0x01b1
10104 -
10105 -struct dpbp_cmd_open {
10106 - __le32 dpbp_id;
10107 -};
10108 -
10109 -#define DPBP_ENABLE 0x1
10110 -
10111 -struct dpbp_rsp_is_enabled {
10112 - u8 enabled;
10113 -};
10114 -
10115 -struct dpbp_cmd_set_irq {
10116 - /* cmd word 0 */
10117 - u8 irq_index;
10118 - u8 pad[3];
10119 - __le32 irq_val;
10120 - /* cmd word 1 */
10121 - __le64 irq_addr;
10122 - /* cmd word 2 */
10123 - __le32 irq_num;
10124 -};
10125 -
10126 -struct dpbp_cmd_get_irq {
10127 - __le32 pad;
10128 - u8 irq_index;
10129 -};
10130 -
10131 -struct dpbp_rsp_get_irq {
10132 - /* response word 0 */
10133 - __le32 irq_val;
10134 - __le32 pad;
10135 - /* response word 1 */
10136 - __le64 irq_addr;
10137 - /* response word 2 */
10138 - __le32 irq_num;
10139 - __le32 type;
10140 -};
10141 -
10142 -struct dpbp_cmd_set_irq_enable {
10143 - u8 enable;
10144 - u8 pad[3];
10145 - u8 irq_index;
10146 -};
10147 -
10148 -struct dpbp_cmd_get_irq_enable {
10149 - __le32 pad;
10150 - u8 irq_index;
10151 -};
10152 -
10153 -struct dpbp_rsp_get_irq_enable {
10154 - u8 enabled;
10155 -};
10156 -
10157 -struct dpbp_cmd_set_irq_mask {
10158 - __le32 mask;
10159 - u8 irq_index;
10160 -};
10161 -
10162 -struct dpbp_cmd_get_irq_mask {
10163 - __le32 pad;
10164 - u8 irq_index;
10165 -};
10166 -
10167 -struct dpbp_rsp_get_irq_mask {
10168 - __le32 mask;
10169 -};
10170 -
10171 -struct dpbp_cmd_get_irq_status {
10172 - __le32 status;
10173 - u8 irq_index;
10174 -};
10175 -
10176 -struct dpbp_rsp_get_irq_status {
10177 - __le32 status;
10178 -};
10179 -
10180 -struct dpbp_cmd_clear_irq_status {
10181 - __le32 status;
10182 - u8 irq_index;
10183 -};
10184 -
10185 -struct dpbp_rsp_get_attributes {
10186 - /* response word 0 */
10187 - __le16 pad;
10188 - __le16 bpid;
10189 - __le32 id;
10190 - /* response word 1 */
10191 - __le16 version_major;
10192 - __le16 version_minor;
10193 -};
10194 -
10195 -struct dpbp_cmd_set_notifications {
10196 - /* cmd word 0 */
10197 - __le32 depletion_entry;
10198 - __le32 depletion_exit;
10199 - /* cmd word 1 */
10200 - __le32 surplus_entry;
10201 - __le32 surplus_exit;
10202 - /* cmd word 2 */
10203 - __le16 options;
10204 - __le16 pad[3];
10205 - /* cmd word 3 */
10206 - __le64 message_ctx;
10207 - /* cmd word 4 */
10208 - __le64 message_iova;
10209 -};
10210 -
10211 -struct dpbp_rsp_get_notifications {
10212 - /* response word 0 */
10213 - __le32 depletion_entry;
10214 - __le32 depletion_exit;
10215 - /* response word 1 */
10216 - __le32 surplus_entry;
10217 - __le32 surplus_exit;
10218 - /* response word 2 */
10219 - __le16 options;
10220 - __le16 pad[3];
10221 - /* response word 3 */
10222 - __le64 message_ctx;
10223 - /* response word 4 */
10224 - __le64 message_iova;
10225 -};
10226 -
10227 -#endif /* _FSL_DPBP_CMD_H */
10228 --- a/drivers/staging/fsl-mc/include/dpbp.h
10229 +++ b/drivers/staging/fsl-mc/include/dpbp.h
10230 @@ -1,4 +1,5 @@
10231 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10232 +/*
10233 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10234 *
10235 * Redistribution and use in source and binary forms, with or without
10236 * modification, are permitted provided that the following conditions are met:
10237 @@ -32,7 +33,8 @@
10238 #ifndef __FSL_DPBP_H
10239 #define __FSL_DPBP_H
10240
10241 -/* Data Path Buffer Pool API
10242 +/*
10243 + * Data Path Buffer Pool API
10244 * Contains initialization APIs and runtime control APIs for DPBP
10245 */
10246
10247 @@ -44,25 +46,8 @@ int dpbp_open(struct fsl_mc_io *mc_io,
10248 u16 *token);
10249
10250 int dpbp_close(struct fsl_mc_io *mc_io,
10251 - u32 cmd_flags,
10252 - u16 token);
10253 -
10254 -/**
10255 - * struct dpbp_cfg - Structure representing DPBP configuration
10256 - * @options: place holder
10257 - */
10258 -struct dpbp_cfg {
10259 - u32 options;
10260 -};
10261 -
10262 -int dpbp_create(struct fsl_mc_io *mc_io,
10263 - u32 cmd_flags,
10264 - const struct dpbp_cfg *cfg,
10265 - u16 *token);
10266 -
10267 -int dpbp_destroy(struct fsl_mc_io *mc_io,
10268 - u32 cmd_flags,
10269 - u16 token);
10270 + u32 cmd_flags,
10271 + u16 token);
10272
10273 int dpbp_enable(struct fsl_mc_io *mc_io,
10274 u32 cmd_flags,
10275 @@ -82,139 +67,24 @@ int dpbp_reset(struct fsl_mc_io *mc_io,
10276 u16 token);
10277
10278 /**
10279 - * struct dpbp_irq_cfg - IRQ configuration
10280 - * @addr: Address that must be written to signal a message-based interrupt
10281 - * @val: Value to write into irq_addr address
10282 - * @irq_num: A user defined number associated with this IRQ
10283 - */
10284 -struct dpbp_irq_cfg {
10285 - u64 addr;
10286 - u32 val;
10287 - int irq_num;
10288 -};
10289 -
10290 -int dpbp_set_irq(struct fsl_mc_io *mc_io,
10291 - u32 cmd_flags,
10292 - u16 token,
10293 - u8 irq_index,
10294 - struct dpbp_irq_cfg *irq_cfg);
10295 -
10296 -int dpbp_get_irq(struct fsl_mc_io *mc_io,
10297 - u32 cmd_flags,
10298 - u16 token,
10299 - u8 irq_index,
10300 - int *type,
10301 - struct dpbp_irq_cfg *irq_cfg);
10302 -
10303 -int dpbp_set_irq_enable(struct fsl_mc_io *mc_io,
10304 - u32 cmd_flags,
10305 - u16 token,
10306 - u8 irq_index,
10307 - u8 en);
10308 -
10309 -int dpbp_get_irq_enable(struct fsl_mc_io *mc_io,
10310 - u32 cmd_flags,
10311 - u16 token,
10312 - u8 irq_index,
10313 - u8 *en);
10314 -
10315 -int dpbp_set_irq_mask(struct fsl_mc_io *mc_io,
10316 - u32 cmd_flags,
10317 - u16 token,
10318 - u8 irq_index,
10319 - u32 mask);
10320 -
10321 -int dpbp_get_irq_mask(struct fsl_mc_io *mc_io,
10322 - u32 cmd_flags,
10323 - u16 token,
10324 - u8 irq_index,
10325 - u32 *mask);
10326 -
10327 -int dpbp_get_irq_status(struct fsl_mc_io *mc_io,
10328 - u32 cmd_flags,
10329 - u16 token,
10330 - u8 irq_index,
10331 - u32 *status);
10332 -
10333 -int dpbp_clear_irq_status(struct fsl_mc_io *mc_io,
10334 - u32 cmd_flags,
10335 - u16 token,
10336 - u8 irq_index,
10337 - u32 status);
10338 -
10339 -/**
10340 * struct dpbp_attr - Structure representing DPBP attributes
10341 * @id: DPBP object ID
10342 - * @version: DPBP version
10343 * @bpid: Hardware buffer pool ID; should be used as an argument in
10344 * acquire/release operations on buffers
10345 */
10346 struct dpbp_attr {
10347 int id;
10348 - /**
10349 - * struct version - Structure representing DPBP version
10350 - * @major: DPBP major version
10351 - * @minor: DPBP minor version
10352 - */
10353 - struct {
10354 - u16 major;
10355 - u16 minor;
10356 - } version;
10357 u16 bpid;
10358 };
10359
10360 -int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10361 - u32 cmd_flags,
10362 - u16 token,
10363 - struct dpbp_attr *attr);
10364 -
10365 -/**
10366 - * DPBP notifications options
10367 - */
10368 -
10369 -/**
10370 - * BPSCN write will attempt to allocate into a cache (coherent write)
10371 - */
10372 -#define DPBP_NOTIF_OPT_COHERENT_WRITE 0x00000001
10373 -
10374 -/**
10375 - * struct dpbp_notification_cfg - Structure representing DPBP notifications
10376 - * towards software
10377 - * @depletion_entry: below this threshold the pool is "depleted";
10378 - * set it to '0' to disable it
10379 - * @depletion_exit: greater than or equal to this threshold the pool exit its
10380 - * "depleted" state
10381 - * @surplus_entry: above this threshold the pool is in "surplus" state;
10382 - * set it to '0' to disable it
10383 - * @surplus_exit: less than or equal to this threshold the pool exit its
10384 - * "surplus" state
10385 - * @message_iova: MUST be given if either 'depletion_entry' or 'surplus_entry'
10386 - * is not '0' (enable); I/O virtual address (must be in DMA-able memory),
10387 - * must be 16B aligned.
10388 - * @message_ctx: The context that will be part of the BPSCN message and will
10389 - * be written to 'message_iova'
10390 - * @options: Mask of available options; use 'DPBP_NOTIF_OPT_<X>' values
10391 - */
10392 -struct dpbp_notification_cfg {
10393 - u32 depletion_entry;
10394 - u32 depletion_exit;
10395 - u32 surplus_entry;
10396 - u32 surplus_exit;
10397 - u64 message_iova;
10398 - u64 message_ctx;
10399 - u16 options;
10400 -};
10401 -
10402 -int dpbp_set_notifications(struct fsl_mc_io *mc_io,
10403 - u32 cmd_flags,
10404 - u16 token,
10405 - struct dpbp_notification_cfg *cfg);
10406 -
10407 -int dpbp_get_notifications(struct fsl_mc_io *mc_io,
10408 - u32 cmd_flags,
10409 - u16 token,
10410 - struct dpbp_notification_cfg *cfg);
10411 -
10412 -/** @} */
10413 +int dpbp_get_attributes(struct fsl_mc_io *mc_io,
10414 + u32 cmd_flags,
10415 + u16 token,
10416 + struct dpbp_attr *attr);
10417 +
10418 +int dpbp_get_api_version(struct fsl_mc_io *mc_io,
10419 + u32 cmd_flags,
10420 + u16 *major_ver,
10421 + u16 *minor_ver);
10422
10423 #endif /* __FSL_DPBP_H */
10424 --- /dev/null
10425 +++ b/drivers/staging/fsl-mc/include/dpcon.h
10426 @@ -0,0 +1,115 @@
10427 +/* Copyright 2013-2016 Freescale Semiconductor Inc.
10428 + *
10429 + * Redistribution and use in source and binary forms, with or without
10430 + * modification, are permitted provided that the following conditions are met:
10431 + * * Redistributions of source code must retain the above copyright
10432 + * notice, this list of conditions and the following disclaimer.
10433 + * * Redistributions in binary form must reproduce the above copyright
10434 + * notice, this list of conditions and the following disclaimer in the
10435 + * documentation and/or other materials provided with the distribution.
10436 + * * Neither the name of the above-listed copyright holders nor the
10437 + * names of any contributors may be used to endorse or promote products
10438 + * derived from this software without specific prior written permission.
10439 + *
10440 + *
10441 + * ALTERNATIVELY, this software may be distributed under the terms of the
10442 + * GNU General Public License ("GPL") as published by the Free Software
10443 + * Foundation, either version 2 of that License or (at your option) any
10444 + * later version.
10445 + *
10446 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10447 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10448 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10449 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10450 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10451 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10452 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10453 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10454 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10455 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10456 + * POSSIBILITY OF SUCH DAMAGE.
10457 + */
10458 +#ifndef __FSL_DPCON_H
10459 +#define __FSL_DPCON_H
10460 +
10461 +/* Data Path Concentrator API
10462 + * Contains initialization APIs and runtime control APIs for DPCON
10463 + */
10464 +
10465 +struct fsl_mc_io;
10466 +
10467 +/** General DPCON macros */
10468 +
10469 +/**
10470 + * Use it to disable notifications; see dpcon_set_notification()
10471 + */
10472 +#define DPCON_INVALID_DPIO_ID (int)(-1)
10473 +
10474 +int dpcon_open(struct fsl_mc_io *mc_io,
10475 + u32 cmd_flags,
10476 + int dpcon_id,
10477 + u16 *token);
10478 +
10479 +int dpcon_close(struct fsl_mc_io *mc_io,
10480 + u32 cmd_flags,
10481 + u16 token);
10482 +
10483 +int dpcon_enable(struct fsl_mc_io *mc_io,
10484 + u32 cmd_flags,
10485 + u16 token);
10486 +
10487 +int dpcon_disable(struct fsl_mc_io *mc_io,
10488 + u32 cmd_flags,
10489 + u16 token);
10490 +
10491 +int dpcon_is_enabled(struct fsl_mc_io *mc_io,
10492 + u32 cmd_flags,
10493 + u16 token,
10494 + int *en);
10495 +
10496 +int dpcon_reset(struct fsl_mc_io *mc_io,
10497 + u32 cmd_flags,
10498 + u16 token);
10499 +
10500 +/**
10501 + * struct dpcon_attr - Structure representing DPCON attributes
10502 + * @id: DPCON object ID
10503 + * @qbman_ch_id: Channel ID to be used by dequeue operation
10504 + * @num_priorities: Number of priorities for the DPCON channel (1-8)
10505 + */
10506 +struct dpcon_attr {
10507 + int id;
10508 + u16 qbman_ch_id;
10509 + u8 num_priorities;
10510 +};
10511 +
10512 +int dpcon_get_attributes(struct fsl_mc_io *mc_io,
10513 + u32 cmd_flags,
10514 + u16 token,
10515 + struct dpcon_attr *attr);
10516 +
10517 +/**
10518 + * struct dpcon_notification_cfg - Structure representing notification params
10519 + * @dpio_id: DPIO object ID; must be configured with a notification channel;
10520 + * to disable notifications set it to 'DPCON_INVALID_DPIO_ID';
10521 + * @priority: Priority selection within the DPIO channel; valid values
10522 + * are 0-7, depending on the number of priorities in that channel
10523 + * @user_ctx: User context value provided with each CDAN message
10524 + */
10525 +struct dpcon_notification_cfg {
10526 + int dpio_id;
10527 + u8 priority;
10528 + u64 user_ctx;
10529 +};
10530 +
10531 +int dpcon_set_notification(struct fsl_mc_io *mc_io,
10532 + u32 cmd_flags,
10533 + u16 token,
10534 + struct dpcon_notification_cfg *cfg);
10535 +
10536 +int dpcon_get_api_version(struct fsl_mc_io *mc_io,
10537 + u32 cmd_flags,
10538 + u16 *major_ver,
10539 + u16 *minor_ver);
10540 +
10541 +#endif /* __FSL_DPCON_H */
10542 --- a/drivers/staging/fsl-mc/include/dpmng.h
10543 +++ b/drivers/staging/fsl-mc/include/dpmng.h
10544 @@ -1,4 +1,5 @@
10545 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10546 +/*
10547 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10548 *
10549 * Redistribution and use in source and binary forms, with or without
10550 * modification, are permitted provided that the following conditions are met:
10551 @@ -32,7 +33,8 @@
10552 #ifndef __FSL_DPMNG_H
10553 #define __FSL_DPMNG_H
10554
10555 -/* Management Complex General API
10556 +/*
10557 + * Management Complex General API
10558 * Contains general API for the Management Complex firmware
10559 */
10560
10561 @@ -58,12 +60,8 @@ struct mc_version {
10562 u32 revision;
10563 };
10564
10565 -int mc_get_version(struct fsl_mc_io *mc_io,
10566 - u32 cmd_flags,
10567 - struct mc_version *mc_ver_info);
10568 -
10569 -int dpmng_get_container_id(struct fsl_mc_io *mc_io,
10570 - u32 cmd_flags,
10571 - int *container_id);
10572 +int mc_get_version(struct fsl_mc_io *mc_io,
10573 + u32 cmd_flags,
10574 + struct mc_version *mc_ver_info);
10575
10576 #endif /* __FSL_DPMNG_H */
10577 --- /dev/null
10578 +++ b/drivers/staging/fsl-mc/include/dpopr.h
10579 @@ -0,0 +1,110 @@
10580 +/*
10581 + * Copyright 2017 NXP
10582 + *
10583 + * Redistribution and use in source and binary forms, with or without
10584 + * modification, are permitted provided that the following conditions are met:
10585 + * * Redistributions of source code must retain the above copyright
10586 + * notice, this list of conditions and the following disclaimer.
10587 + * * Redistributions in binary form must reproduce the above copyright
10588 + * notice, this list of conditions and the following disclaimer in the
10589 + * documentation and/or other materials provided with the distribution.
10590 + * * Neither the name of the above-listed copyright holders nor the
10591 + * names of any contributors may be used to endorse or promote products
10592 + * derived from this software without specific prior written permission.
10593 + *
10594 + *
10595 + * ALTERNATIVELY, this software may be distributed under the terms of the
10596 + * GNU General Public License ("GPL") as published by the Free Software
10597 + * Foundation, either version 2 of that License or (at your option) any
10598 + * later version.
10599 + *
10600 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
10601 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
10602 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
10603 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
10604 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
10605 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
10606 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
10607 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
10608 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
10609 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
10610 + * POSSIBILITY OF SUCH DAMAGE.
10611 + */
10612 +#ifndef __FSL_DPOPR_H_
10613 +#define __FSL_DPOPR_H_
10614 +
10615 +/* Data Path Order Restoration API
10616 + * Contains initialization APIs and runtime APIs for the Order Restoration
10617 + */
10618 +
10619 +/** Order Restoration properties */
10620 +
10621 +/**
10622 + * Create a new Order Point Record option
10623 + */
10624 +#define OPR_OPT_CREATE 0x1
10625 +/**
10626 + * Retire an existing Order Point Record option
10627 + */
10628 +#define OPR_OPT_RETIRE 0x2
10629 +
10630 +/**
10631 + * struct opr_cfg - Structure representing OPR configuration
10632 + * @oprrws: Order point record (OPR) restoration window size (0 to 5)
10633 + * 0 - Window size is 32 frames.
10634 + * 1 - Window size is 64 frames.
10635 + * 2 - Window size is 128 frames.
10636 + * 3 - Window size is 256 frames.
10637 + * 4 - Window size is 512 frames.
10638 + * 5 - Window size is 1024 frames.
10639 + * @oa: OPR auto advance NESN window size (0 disabled, 1 enabled)
10640 + * @olws: OPR acceptable late arrival window size (0 to 3)
10641 + * 0 - Disabled. Late arrivals are always rejected.
10642 + * 1 - Window size is 32 frames.
10643 + * 2 - Window size is the same as the OPR restoration
10644 + * window size configured in the OPRRWS field.
10645 + * 3 - Window size is 8192 frames. Late arrivals are
10646 + * always accepted.
10647 + * @oeane: Order restoration list (ORL) resource exhaustion
10648 + * advance NESN enable (0 disabled, 1 enabled)
10649 + * @oloe: OPR loose ordering enable (0 disabled, 1 enabled)
10650 + */
10651 +struct opr_cfg {
10652 + u8 oprrws;
10653 + u8 oa;
10654 + u8 olws;
10655 + u8 oeane;
10656 + u8 oloe;
10657 +};
10658 +
10659 +/**
10660 + * struct opr_qry - Structure representing OPR configuration
10661 + * @enable: Enabled state
10662 + * @rip: Retirement In Progress
10663 + * @ndsn: Next dispensed sequence number
10664 + * @nesn: Next expected sequence number
10665 + * @ea_hseq: Early arrival head sequence number
10666 + * @hseq_nlis: HSEQ not last in sequence
10667 + * @ea_tseq: Early arrival tail sequence number
10668 + * @tseq_nlis: TSEQ not last in sequence
10669 + * @ea_tptr: Early arrival tail pointer
10670 + * @ea_hptr: Early arrival head pointer
10671 + * @opr_id: Order Point Record ID
10672 + * @opr_vid: Order Point Record Virtual ID
10673 + */
10674 +struct opr_qry {
10675 + char enable;
10676 + char rip;
10677 + u16 ndsn;
10678 + u16 nesn;
10679 + u16 ea_hseq;
10680 + char hseq_nlis;
10681 + u16 ea_tseq;
10682 + char tseq_nlis;
10683 + u16 ea_tptr;
10684 + u16 ea_hptr;
10685 + u16 opr_id;
10686 + u16 opr_vid;
10687 +};
10688 +
10689 +#endif /* __FSL_DPOPR_H_ */
10690 --- a/drivers/staging/fsl-mc/include/dprc.h
10691 +++ b/drivers/staging/fsl-mc/include/dprc.h
10692 @@ -1,4 +1,5 @@
10693 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
10694 +/*
10695 + * Copyright 2013-2016 Freescale Semiconductor Inc.
10696 *
10697 * Redistribution and use in source and binary forms, with or without
10698 * modification, are permitted provided that the following conditions are met:
10699 @@ -34,26 +35,13 @@
10700
10701 #include "mc-cmd.h"
10702
10703 -/* Data Path Resource Container API
10704 +/*
10705 + * Data Path Resource Container API
10706 * Contains DPRC API for managing and querying DPAA resources
10707 */
10708
10709 struct fsl_mc_io;
10710
10711 -/**
10712 - * Set this value as the icid value in dprc_cfg structure when creating a
10713 - * container, in case the ICID is not selected by the user and should be
10714 - * allocated by the DPRC from the pool of ICIDs.
10715 - */
10716 -#define DPRC_GET_ICID_FROM_POOL (u16)(~(0))
10717 -
10718 -/**
10719 - * Set this value as the portal_id value in dprc_cfg structure when creating a
10720 - * container, in case the portal ID is not specifically selected by the
10721 - * user and should be allocated by the DPRC from the pool of portal ids.
10722 - */
10723 -#define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0))
10724 -
10725 int dprc_open(struct fsl_mc_io *mc_io,
10726 u32 cmd_flags,
10727 int container_id,
10728 @@ -63,75 +51,6 @@ int dprc_close(struct fsl_mc_io *mc_io,
10729 u32 cmd_flags,
10730 u16 token);
10731
10732 -/**
10733 - * Container general options
10734 - *
10735 - * These options may be selected at container creation by the container creator
10736 - * and can be retrieved using dprc_get_attributes()
10737 - */
10738 -
10739 -/* Spawn Policy Option allowed - Indicates that the new container is allowed
10740 - * to spawn and have its own child containers.
10741 - */
10742 -#define DPRC_CFG_OPT_SPAWN_ALLOWED 0x00000001
10743 -
10744 -/* General Container allocation policy - Indicates that the new container is
10745 - * allowed to allocate requested resources from its parent container; if not
10746 - * set, the container is only allowed to use resources in its own pools; Note
10747 - * that this is a container's global policy, but the parent container may
10748 - * override it and set specific quota per resource type.
10749 - */
10750 -#define DPRC_CFG_OPT_ALLOC_ALLOWED 0x00000002
10751 -
10752 -/* Object initialization allowed - software context associated with this
10753 - * container is allowed to invoke object initialization operations.
10754 - */
10755 -#define DPRC_CFG_OPT_OBJ_CREATE_ALLOWED 0x00000004
10756 -
10757 -/* Topology change allowed - software context associated with this
10758 - * container is allowed to invoke topology operations, such as attach/detach
10759 - * of network objects.
10760 - */
10761 -#define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008
10762 -
10763 -/* AIOP - Indicates that container belongs to AIOP. */
10764 -#define DPRC_CFG_OPT_AIOP 0x00000020
10765 -
10766 -/* IRQ Config - Indicates that the container allowed to configure its IRQs. */
10767 -#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040
10768 -
10769 -/**
10770 - * struct dprc_cfg - Container configuration options
10771 - * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free
10772 - * ICID value is allocated by the DPRC
10773 - * @portal_id: Portal ID; if set to 'DPRC_GET_PORTAL_ID_FROM_POOL', a free
10774 - * portal ID is allocated by the DPRC
10775 - * @options: Combination of 'DPRC_CFG_OPT_<X>' options
10776 - * @label: Object's label
10777 - */
10778 -struct dprc_cfg {
10779 - u16 icid;
10780 - int portal_id;
10781 - u64 options;
10782 - char label[16];
10783 -};
10784 -
10785 -int dprc_create_container(struct fsl_mc_io *mc_io,
10786 - u32 cmd_flags,
10787 - u16 token,
10788 - struct dprc_cfg *cfg,
10789 - int *child_container_id,
10790 - u64 *child_portal_offset);
10791 -
10792 -int dprc_destroy_container(struct fsl_mc_io *mc_io,
10793 - u32 cmd_flags,
10794 - u16 token,
10795 - int child_container_id);
10796 -
10797 -int dprc_reset_container(struct fsl_mc_io *mc_io,
10798 - u32 cmd_flags,
10799 - u16 token,
10800 - int child_container_id);
10801
10802 /* IRQ */
10803
10804 @@ -139,7 +58,7 @@ int dprc_reset_container(struct fsl_mc_i
10805 #define DPRC_IRQ_INDEX 0
10806
10807 /* Number of dprc's IRQs */
10808 -#define DPRC_NUM_OF_IRQS 1
10809 +#define DPRC_NUM_OF_IRQS 1
10810
10811 /* DPRC IRQ events */
10812
10813 @@ -151,12 +70,14 @@ int dprc_reset_container(struct fsl_mc_i
10814 #define DPRC_IRQ_EVENT_RES_ADDED 0x00000004
10815 /* IRQ event - Indicates that resources removed from the container */
10816 #define DPRC_IRQ_EVENT_RES_REMOVED 0x00000008
10817 -/* IRQ event - Indicates that one of the descendant containers that opened by
10818 +/*
10819 + * IRQ event - Indicates that one of the descendant containers that opened by
10820 * this container is destroyed
10821 */
10822 #define DPRC_IRQ_EVENT_CONTAINER_DESTROYED 0x00000010
10823
10824 -/* IRQ event - Indicates that on one of the container's opened object is
10825 +/*
10826 + * IRQ event - Indicates that on one of the container's opened object is
10827 * destroyed
10828 */
10829 #define DPRC_IRQ_EVENT_OBJ_DESTROYED 0x00000020
10830 @@ -171,59 +92,59 @@ int dprc_reset_container(struct fsl_mc_i
10831 * @irq_num: A user defined number associated with this IRQ
10832 */
10833 struct dprc_irq_cfg {
10834 - phys_addr_t paddr;
10835 - u32 val;
10836 - int irq_num;
10837 -};
10838 -
10839 -int dprc_set_irq(struct fsl_mc_io *mc_io,
10840 - u32 cmd_flags,
10841 - u16 token,
10842 - u8 irq_index,
10843 - struct dprc_irq_cfg *irq_cfg);
10844 -
10845 -int dprc_get_irq(struct fsl_mc_io *mc_io,
10846 - u32 cmd_flags,
10847 - u16 token,
10848 - u8 irq_index,
10849 - int *type,
10850 - struct dprc_irq_cfg *irq_cfg);
10851 -
10852 -int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10853 - u32 cmd_flags,
10854 - u16 token,
10855 - u8 irq_index,
10856 - u8 en);
10857 -
10858 -int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10859 - u32 cmd_flags,
10860 - u16 token,
10861 - u8 irq_index,
10862 - u8 *en);
10863 -
10864 -int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10865 - u32 cmd_flags,
10866 - u16 token,
10867 - u8 irq_index,
10868 - u32 mask);
10869 -
10870 -int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10871 - u32 cmd_flags,
10872 - u16 token,
10873 - u8 irq_index,
10874 - u32 *mask);
10875 -
10876 -int dprc_get_irq_status(struct fsl_mc_io *mc_io,
10877 - u32 cmd_flags,
10878 - u16 token,
10879 - u8 irq_index,
10880 - u32 *status);
10881 -
10882 -int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
10883 - u32 cmd_flags,
10884 - u16 token,
10885 - u8 irq_index,
10886 - u32 status);
10887 + phys_addr_t paddr;
10888 + u32 val;
10889 + int irq_num;
10890 +};
10891 +
10892 +int dprc_set_irq(struct fsl_mc_io *mc_io,
10893 + u32 cmd_flags,
10894 + u16 token,
10895 + u8 irq_index,
10896 + struct dprc_irq_cfg *irq_cfg);
10897 +
10898 +int dprc_get_irq(struct fsl_mc_io *mc_io,
10899 + u32 cmd_flags,
10900 + u16 token,
10901 + u8 irq_index,
10902 + int *type,
10903 + struct dprc_irq_cfg *irq_cfg);
10904 +
10905 +int dprc_set_irq_enable(struct fsl_mc_io *mc_io,
10906 + u32 cmd_flags,
10907 + u16 token,
10908 + u8 irq_index,
10909 + u8 en);
10910 +
10911 +int dprc_get_irq_enable(struct fsl_mc_io *mc_io,
10912 + u32 cmd_flags,
10913 + u16 token,
10914 + u8 irq_index,
10915 + u8 *en);
10916 +
10917 +int dprc_set_irq_mask(struct fsl_mc_io *mc_io,
10918 + u32 cmd_flags,
10919 + u16 token,
10920 + u8 irq_index,
10921 + u32 mask);
10922 +
10923 +int dprc_get_irq_mask(struct fsl_mc_io *mc_io,
10924 + u32 cmd_flags,
10925 + u16 token,
10926 + u8 irq_index,
10927 + u32 *mask);
10928 +
10929 +int dprc_get_irq_status(struct fsl_mc_io *mc_io,
10930 + u32 cmd_flags,
10931 + u16 token,
10932 + u8 irq_index,
10933 + u32 *status);
10934 +
10935 +int dprc_clear_irq_status(struct fsl_mc_io *mc_io,
10936 + u32 cmd_flags,
10937 + u16 token,
10938 + u8 irq_index,
10939 + u32 status);
10940
10941 /**
10942 * struct dprc_attributes - Container attributes
10943 @@ -231,114 +152,23 @@ int dprc_clear_irq_status(struct fsl_mc_
10944 * @icid: Container's ICID
10945 * @portal_id: Container's portal ID
10946 * @options: Container's options as set at container's creation
10947 - * @version: DPRC version
10948 */
10949 struct dprc_attributes {
10950 int container_id;
10951 u16 icid;
10952 int portal_id;
10953 u64 options;
10954 - /**
10955 - * struct version - DPRC version
10956 - * @major: DPRC major version
10957 - * @minor: DPRC minor version
10958 - */
10959 - struct {
10960 - u16 major;
10961 - u16 minor;
10962 - } version;
10963 };
10964
10965 -int dprc_get_attributes(struct fsl_mc_io *mc_io,
10966 - u32 cmd_flags,
10967 - u16 token,
10968 - struct dprc_attributes *attributes);
10969 -
10970 -int dprc_set_res_quota(struct fsl_mc_io *mc_io,
10971 - u32 cmd_flags,
10972 - u16 token,
10973 - int child_container_id,
10974 - char *type,
10975 - u16 quota);
10976 -
10977 -int dprc_get_res_quota(struct fsl_mc_io *mc_io,
10978 - u32 cmd_flags,
10979 - u16 token,
10980 - int child_container_id,
10981 - char *type,
10982 - u16 *quota);
10983 -
10984 -/* Resource request options */
10985 -
10986 -/* Explicit resource ID request - The requested objects/resources
10987 - * are explicit and sequential (in case of resources).
10988 - * The base ID is given at res_req at base_align field
10989 - */
10990 -#define DPRC_RES_REQ_OPT_EXPLICIT 0x00000001
10991 -
10992 -/* Aligned resources request - Relevant only for resources
10993 - * request (and not objects). Indicates that resources base ID should be
10994 - * sequential and aligned to the value given at dprc_res_req base_align field
10995 - */
10996 -#define DPRC_RES_REQ_OPT_ALIGNED 0x00000002
10997 -
10998 -/* Plugged Flag - Relevant only for object assignment request.
10999 - * Indicates that after all objects assigned. An interrupt will be invoked at
11000 - * the relevant GPP. The assigned object will be marked as plugged.
11001 - * plugged objects can't be assigned from their container
11002 - */
11003 -#define DPRC_RES_REQ_OPT_PLUGGED 0x00000004
11004 -
11005 -/**
11006 - * struct dprc_res_req - Resource request descriptor, to be used in assignment
11007 - * or un-assignment of resources and objects.
11008 - * @type: Resource/object type: Represent as a NULL terminated string.
11009 - * This string may received by using dprc_get_pool() to get resource
11010 - * type and dprc_get_obj() to get object type;
11011 - * Note: it is not possible to assign/un-assign DPRC objects
11012 - * @num: Number of resources
11013 - * @options: Request options: combination of DPRC_RES_REQ_OPT_ options
11014 - * @id_base_align: In case of explicit assignment (DPRC_RES_REQ_OPT_EXPLICIT
11015 - * is set at option), this field represents the required base ID
11016 - * for resource allocation; In case of aligned assignment
11017 - * (DPRC_RES_REQ_OPT_ALIGNED is set at option), this field
11018 - * indicates the required alignment for the resource ID(s) -
11019 - * use 0 if there is no alignment or explicit ID requirements
11020 - */
11021 -struct dprc_res_req {
11022 - char type[16];
11023 - u32 num;
11024 - u32 options;
11025 - int id_base_align;
11026 -};
11027 -
11028 -int dprc_assign(struct fsl_mc_io *mc_io,
11029 - u32 cmd_flags,
11030 - u16 token,
11031 - int container_id,
11032 - struct dprc_res_req *res_req);
11033 -
11034 -int dprc_unassign(struct fsl_mc_io *mc_io,
11035 - u32 cmd_flags,
11036 - u16 token,
11037 - int child_container_id,
11038 - struct dprc_res_req *res_req);
11039 -
11040 -int dprc_get_pool_count(struct fsl_mc_io *mc_io,
11041 - u32 cmd_flags,
11042 - u16 token,
11043 - int *pool_count);
11044 -
11045 -int dprc_get_pool(struct fsl_mc_io *mc_io,
11046 - u32 cmd_flags,
11047 - u16 token,
11048 - int pool_index,
11049 - char *type);
11050 +int dprc_get_attributes(struct fsl_mc_io *mc_io,
11051 + u32 cmd_flags,
11052 + u16 token,
11053 + struct dprc_attributes *attributes);
11054
11055 int dprc_get_obj_count(struct fsl_mc_io *mc_io,
11056 - u32 cmd_flags,
11057 - u16 token,
11058 - int *obj_count);
11059 + u32 cmd_flags,
11060 + u16 token,
11061 + int *obj_count);
11062
11063 /* Objects Attributes Flags */
11064
11065 @@ -353,7 +183,7 @@ int dprc_get_obj_count(struct fsl_mc_io
11066 * masters;
11067 * user is responsible for proper memory handling through IOMMU configuration.
11068 */
11069 -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
11070 +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001
11071
11072 /**
11073 * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj()
11074 @@ -381,41 +211,41 @@ struct dprc_obj_desc {
11075 u16 flags;
11076 };
11077
11078 -int dprc_get_obj(struct fsl_mc_io *mc_io,
11079 - u32 cmd_flags,
11080 - u16 token,
11081 - int obj_index,
11082 - struct dprc_obj_desc *obj_desc);
11083 -
11084 -int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
11085 - u32 cmd_flags,
11086 - u16 token,
11087 - char *obj_type,
11088 - int obj_id,
11089 - struct dprc_obj_desc *obj_desc);
11090 -
11091 -int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
11092 - u32 cmd_flags,
11093 - u16 token,
11094 - char *obj_type,
11095 - int obj_id,
11096 - u8 irq_index,
11097 - struct dprc_irq_cfg *irq_cfg);
11098 -
11099 -int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
11100 - u32 cmd_flags,
11101 - u16 token,
11102 - char *obj_type,
11103 - int obj_id,
11104 - u8 irq_index,
11105 - int *type,
11106 - struct dprc_irq_cfg *irq_cfg);
11107 -
11108 -int dprc_get_res_count(struct fsl_mc_io *mc_io,
11109 - u32 cmd_flags,
11110 - u16 token,
11111 - char *type,
11112 - int *res_count);
11113 +int dprc_get_obj(struct fsl_mc_io *mc_io,
11114 + u32 cmd_flags,
11115 + u16 token,
11116 + int obj_index,
11117 + struct dprc_obj_desc *obj_desc);
11118 +
11119 +int dprc_get_obj_desc(struct fsl_mc_io *mc_io,
11120 + u32 cmd_flags,
11121 + u16 token,
11122 + char *obj_type,
11123 + int obj_id,
11124 + struct dprc_obj_desc *obj_desc);
11125 +
11126 +int dprc_set_obj_irq(struct fsl_mc_io *mc_io,
11127 + u32 cmd_flags,
11128 + u16 token,
11129 + char *obj_type,
11130 + int obj_id,
11131 + u8 irq_index,
11132 + struct dprc_irq_cfg *irq_cfg);
11133 +
11134 +int dprc_get_obj_irq(struct fsl_mc_io *mc_io,
11135 + u32 cmd_flags,
11136 + u16 token,
11137 + char *obj_type,
11138 + int obj_id,
11139 + u8 irq_index,
11140 + int *type,
11141 + struct dprc_irq_cfg *irq_cfg);
11142 +
11143 +int dprc_get_res_count(struct fsl_mc_io *mc_io,
11144 + u32 cmd_flags,
11145 + u16 token,
11146 + char *type,
11147 + int *res_count);
11148
11149 /**
11150 * enum dprc_iter_status - Iteration status
11151 @@ -429,27 +259,6 @@ enum dprc_iter_status {
11152 DPRC_ITER_STATUS_LAST = 2
11153 };
11154
11155 -/**
11156 - * struct dprc_res_ids_range_desc - Resource ID range descriptor
11157 - * @base_id: Base resource ID of this range
11158 - * @last_id: Last resource ID of this range
11159 - * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at
11160 - * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE,
11161 - * additional iterations are needed, until the returned marker is
11162 - * DPRC_ITER_STATUS_LAST
11163 - */
11164 -struct dprc_res_ids_range_desc {
11165 - int base_id;
11166 - int last_id;
11167 - enum dprc_iter_status iter_status;
11168 -};
11169 -
11170 -int dprc_get_res_ids(struct fsl_mc_io *mc_io,
11171 - u32 cmd_flags,
11172 - u16 token,
11173 - char *type,
11174 - struct dprc_res_ids_range_desc *range_desc);
11175 -
11176 /* Region flags */
11177 /* Cacheable - Indicates that region should be mapped as cacheable */
11178 #define DPRC_REGION_CACHEABLE 0x00000001
11179 @@ -481,64 +290,27 @@ struct dprc_region_desc {
11180 enum dprc_region_type type;
11181 };
11182
11183 -int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11184 - u32 cmd_flags,
11185 - u16 token,
11186 - char *obj_type,
11187 - int obj_id,
11188 - u8 region_index,
11189 - struct dprc_region_desc *region_desc);
11190 -
11191 -int dprc_set_obj_label(struct fsl_mc_io *mc_io,
11192 - u32 cmd_flags,
11193 - u16 token,
11194 - char *obj_type,
11195 - int obj_id,
11196 - char *label);
11197 +int dprc_get_obj_region(struct fsl_mc_io *mc_io,
11198 + u32 cmd_flags,
11199 + u16 token,
11200 + char *obj_type,
11201 + int obj_id,
11202 + u8 region_index,
11203 + struct dprc_region_desc *region_desc);
11204
11205 -/**
11206 - * struct dprc_endpoint - Endpoint description for link connect/disconnect
11207 - * operations
11208 - * @type: Endpoint object type: NULL terminated string
11209 - * @id: Endpoint object ID
11210 - * @if_id: Interface ID; should be set for endpoints with multiple
11211 - * interfaces ("dpsw", "dpdmux"); for others, always set to 0
11212 - */
11213 -struct dprc_endpoint {
11214 - char type[16];
11215 - int id;
11216 - int if_id;
11217 -};
11218 +int dprc_get_api_version(struct fsl_mc_io *mc_io,
11219 + u32 cmd_flags,
11220 + u16 *major_ver,
11221 + u16 *minor_ver);
11222
11223 -/**
11224 - * struct dprc_connection_cfg - Connection configuration.
11225 - * Used for virtual connections only
11226 - * @committed_rate: Committed rate (Mbits/s)
11227 - * @max_rate: Maximum rate (Mbits/s)
11228 - */
11229 -struct dprc_connection_cfg {
11230 - u32 committed_rate;
11231 - u32 max_rate;
11232 -};
11233 +int dprc_get_container_id(struct fsl_mc_io *mc_io,
11234 + u32 cmd_flags,
11235 + int *container_id);
11236
11237 -int dprc_connect(struct fsl_mc_io *mc_io,
11238 - u32 cmd_flags,
11239 - u16 token,
11240 - const struct dprc_endpoint *endpoint1,
11241 - const struct dprc_endpoint *endpoint2,
11242 - const struct dprc_connection_cfg *cfg);
11243 -
11244 -int dprc_disconnect(struct fsl_mc_io *mc_io,
11245 - u32 cmd_flags,
11246 - u16 token,
11247 - const struct dprc_endpoint *endpoint);
11248 -
11249 -int dprc_get_connection(struct fsl_mc_io *mc_io,
11250 - u32 cmd_flags,
11251 - u16 token,
11252 - const struct dprc_endpoint *endpoint1,
11253 - struct dprc_endpoint *endpoint2,
11254 - int *state);
11255 +int dprc_reset_container(struct fsl_mc_io *mc_io,
11256 + u32 cmd_flags,
11257 + u16 token,
11258 + int child_container_id);
11259
11260 #endif /* _FSL_DPRC_H */
11261
11262 --- a/drivers/staging/fsl-mc/include/mc-bus.h
11263 +++ b/drivers/staging/fsl-mc/include/mc-bus.h
11264 @@ -1,7 +1,7 @@
11265 /*
11266 * Freescale Management Complex (MC) bus declarations
11267 *
11268 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11269 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11270 * Author: German Rivera <German.Rivera@freescale.com>
11271 *
11272 * This file is licensed under the terms of the GNU General Public
11273 @@ -42,8 +42,8 @@ struct msi_domain_info;
11274 */
11275 struct fsl_mc_resource_pool {
11276 enum fsl_mc_pool_type type;
11277 - int16_t max_count;
11278 - int16_t free_count;
11279 + int max_count;
11280 + int free_count;
11281 struct mutex mutex; /* serializes access to free_list */
11282 struct list_head free_list;
11283 struct fsl_mc_bus *mc_bus;
11284 @@ -73,6 +73,7 @@ struct fsl_mc_bus {
11285 int dprc_scan_container(struct fsl_mc_device *mc_bus_dev);
11286
11287 int dprc_scan_objects(struct fsl_mc_device *mc_bus_dev,
11288 + const char *driver_override,
11289 unsigned int *total_irq_count);
11290
11291 int __init dprc_driver_init(void);
11292 --- a/drivers/staging/fsl-mc/include/mc-cmd.h
11293 +++ b/drivers/staging/fsl-mc/include/mc-cmd.h
11294 @@ -1,4 +1,5 @@
11295 -/* Copyright 2013-2015 Freescale Semiconductor Inc.
11296 +/*
11297 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11298 *
11299 * Redistribution and use in source and binary forms, with or without
11300 * modification, are permitted provided that the following conditions are met:
11301 @@ -48,6 +49,15 @@ struct mc_command {
11302 u64 params[MC_CMD_NUM_OF_PARAMS];
11303 };
11304
11305 +struct mc_rsp_create {
11306 + __le32 object_id;
11307 +};
11308 +
11309 +struct mc_rsp_api_ver {
11310 + __le16 major_ver;
11311 + __le16 minor_ver;
11312 +};
11313 +
11314 enum mc_cmd_status {
11315 MC_CMD_STATUS_OK = 0x0, /* Completed successfully */
11316 MC_CMD_STATUS_READY = 0x1, /* Ready to be processed */
11317 @@ -72,11 +82,6 @@ enum mc_cmd_status {
11318 /* Command completion flag */
11319 #define MC_CMD_FLAG_INTR_DIS 0x01
11320
11321 -#define MC_CMD_HDR_CMDID_MASK 0xFFF0
11322 -#define MC_CMD_HDR_CMDID_SHIFT 4
11323 -#define MC_CMD_HDR_TOKEN_MASK 0xFFC0
11324 -#define MC_CMD_HDR_TOKEN_SHIFT 6
11325 -
11326 static inline u64 mc_encode_cmd_header(u16 cmd_id,
11327 u32 cmd_flags,
11328 u16 token)
11329 @@ -84,10 +89,8 @@ static inline u64 mc_encode_cmd_header(u
11330 u64 header = 0;
11331 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&header;
11332
11333 - hdr->cmd_id = cpu_to_le16((cmd_id << MC_CMD_HDR_CMDID_SHIFT) &
11334 - MC_CMD_HDR_CMDID_MASK);
11335 - hdr->token = cpu_to_le16((token << MC_CMD_HDR_TOKEN_SHIFT) &
11336 - MC_CMD_HDR_TOKEN_MASK);
11337 + hdr->cmd_id = cpu_to_le16(cmd_id);
11338 + hdr->token = cpu_to_le16(token);
11339 hdr->status = MC_CMD_STATUS_READY;
11340 if (cmd_flags & MC_CMD_FLAG_PRI)
11341 hdr->flags_hw = MC_CMD_FLAG_PRI;
11342 @@ -102,7 +105,26 @@ static inline u16 mc_cmd_hdr_read_token(
11343 struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header;
11344 u16 token = le16_to_cpu(hdr->token);
11345
11346 - return (token & MC_CMD_HDR_TOKEN_MASK) >> MC_CMD_HDR_TOKEN_SHIFT;
11347 + return token;
11348 +}
11349 +
11350 +static inline u32 mc_cmd_read_object_id(struct mc_command *cmd)
11351 +{
11352 + struct mc_rsp_create *rsp_params;
11353 +
11354 + rsp_params = (struct mc_rsp_create *)cmd->params;
11355 + return le32_to_cpu(rsp_params->object_id);
11356 +}
11357 +
11358 +static inline void mc_cmd_read_api_version(struct mc_command *cmd,
11359 + u16 *major_ver,
11360 + u16 *minor_ver)
11361 +{
11362 + struct mc_rsp_api_ver *rsp_params;
11363 +
11364 + rsp_params = (struct mc_rsp_api_ver *)cmd->params;
11365 + *major_ver = le16_to_cpu(rsp_params->major_ver);
11366 + *minor_ver = le16_to_cpu(rsp_params->minor_ver);
11367 }
11368
11369 #endif /* __FSL_MC_CMD_H */
11370 --- a/drivers/staging/fsl-mc/include/mc-sys.h
11371 +++ b/drivers/staging/fsl-mc/include/mc-sys.h
11372 @@ -1,4 +1,5 @@
11373 -/* Copyright 2013-2014 Freescale Semiconductor Inc.
11374 +/*
11375 + * Copyright 2013-2016 Freescale Semiconductor Inc.
11376 *
11377 * Interface of the I/O services to send MC commands to the MC hardware
11378 *
11379 --- a/drivers/staging/fsl-mc/include/mc.h
11380 +++ b/drivers/staging/fsl-mc/include/mc.h
11381 @@ -1,7 +1,7 @@
11382 /*
11383 * Freescale Management Complex (MC) bus public interface
11384 *
11385 - * Copyright (C) 2014 Freescale Semiconductor, Inc.
11386 + * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
11387 * Author: German Rivera <German.Rivera@freescale.com>
11388 *
11389 * This file is licensed under the terms of the GNU General Public
11390 @@ -81,7 +81,7 @@ enum fsl_mc_pool_type {
11391 */
11392 struct fsl_mc_resource {
11393 enum fsl_mc_pool_type type;
11394 - int32_t id;
11395 + s32 id;
11396 void *data;
11397 struct fsl_mc_resource_pool *parent_pool;
11398 struct list_head node;
11399 @@ -122,6 +122,7 @@ struct fsl_mc_device_irq {
11400 * @regions: pointer to array of MMIO region entries
11401 * @irqs: pointer to array of pointers to interrupts allocated to this device
11402 * @resource: generic resource associated with this MC object device, if any.
11403 + * @driver_override: Driver name to force a match
11404 *
11405 * Generic device object for MC object devices that are "attached" to a
11406 * MC bus.
11407 @@ -154,6 +155,7 @@ struct fsl_mc_device {
11408 struct resource *regions;
11409 struct fsl_mc_device_irq **irqs;
11410 struct fsl_mc_resource *resource;
11411 + const char *driver_override;
11412 };
11413
11414 #define to_fsl_mc_device(_dev) \
11415 @@ -175,6 +177,8 @@ struct fsl_mc_device {
11416 #define fsl_mc_driver_register(drv) \
11417 __fsl_mc_driver_register(drv, THIS_MODULE)
11418
11419 +void fsl_mc_device_remove(struct fsl_mc_device *mc_dev);
11420 +
11421 int __must_check __fsl_mc_driver_register(struct fsl_mc_driver *fsl_mc_driver,
11422 struct module *owner);
11423
11424 @@ -198,4 +202,13 @@ int __must_check fsl_mc_allocate_irqs(st
11425
11426 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
11427
11428 +void fsl_mc_dma_configure(struct fsl_mc_device *mc_dev,
11429 + struct device_node *fsl_mc_platform_node, int coherent);
11430 +
11431 +#ifdef CONFIG_FSL_MC_BUS
11432 +struct iommu_group *fsl_mc_device_group(struct device *dev);
11433 +#else
11434 +#define fsl_mc_device_group(__dev) NULL
11435 +#endif
11436 +
11437 #endif /* _FSL_MC_H_ */
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