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layerscape: clean up kernel patches
[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-4.9 / 808-guts-support-layerscape.patch
1 From d51e307e4ecf51832c9e3bc30acb5dbd559d5f4d Mon Sep 17 00:00:00 2001
2 From: Yangbo Lu <yangbo.lu@nxp.com>
3 Date: Mon, 25 Sep 2017 12:19:34 +0800
4 Subject: [PATCH] guts: support layerscape
5
6 This is a integrated patch for layerscape guts support.
7
8 Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
9 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
10 Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
12 ---
13 drivers/base/soc.c | 12 ++-
14 drivers/soc/fsl/guts.c | 238 +++++++++++++++++++++++++++++++++++++++++++++++
15 include/linux/fsl/guts.h | 125 +++++++++++++++----------
16 3 files changed, 323 insertions(+), 52 deletions(-)
17 create mode 100644 drivers/soc/fsl/guts.c
18
19 --- a/drivers/base/soc.c
20 +++ b/drivers/base/soc.c
21 @@ -167,19 +167,23 @@ static int soc_device_match_one(struct d
22 const struct soc_device_attribute *match = arg;
23
24 if (match->machine &&
25 - !glob_match(match->machine, soc_dev->attr->machine))
26 + (!soc_dev->attr->machine ||
27 + !glob_match(match->machine, soc_dev->attr->machine)))
28 return 0;
29
30 if (match->family &&
31 - !glob_match(match->family, soc_dev->attr->family))
32 + (!soc_dev->attr->family ||
33 + !glob_match(match->family, soc_dev->attr->family)))
34 return 0;
35
36 if (match->revision &&
37 - !glob_match(match->revision, soc_dev->attr->revision))
38 + (!soc_dev->attr->revision ||
39 + !glob_match(match->revision, soc_dev->attr->revision)))
40 return 0;
41
42 if (match->soc_id &&
43 - !glob_match(match->soc_id, soc_dev->attr->soc_id))
44 + (!soc_dev->attr->soc_id ||
45 + !glob_match(match->soc_id, soc_dev->attr->soc_id)))
46 return 0;
47
48 return 1;
49 --- /dev/null
50 +++ b/drivers/soc/fsl/guts.c
51 @@ -0,0 +1,238 @@
52 +/*
53 + * Freescale QorIQ Platforms GUTS Driver
54 + *
55 + * Copyright (C) 2016 Freescale Semiconductor, Inc.
56 + *
57 + * This program is free software; you can redistribute it and/or modify
58 + * it under the terms of the GNU General Public License as published by
59 + * the Free Software Foundation; either version 2 of the License, or
60 + * (at your option) any later version.
61 + */
62 +
63 +#include <linux/io.h>
64 +#include <linux/slab.h>
65 +#include <linux/module.h>
66 +#include <linux/of_fdt.h>
67 +#include <linux/sys_soc.h>
68 +#include <linux/of_address.h>
69 +#include <linux/platform_device.h>
70 +#include <linux/fsl/guts.h>
71 +
72 +struct guts {
73 + struct ccsr_guts __iomem *regs;
74 + bool little_endian;
75 +};
76 +
77 +struct fsl_soc_die_attr {
78 + char *die;
79 + u32 svr;
80 + u32 mask;
81 +};
82 +
83 +static struct guts *guts;
84 +static struct soc_device_attribute soc_dev_attr;
85 +static struct soc_device *soc_dev;
86 +
87 +
88 +/* SoC die attribute definition for QorIQ platform */
89 +static const struct fsl_soc_die_attr fsl_soc_die[] = {
90 + /*
91 + * Power Architecture-based SoCs T Series
92 + */
93 +
94 + /* Die: T4240, SoC: T4240/T4160/T4080 */
95 + { .die = "T4240",
96 + .svr = 0x82400000,
97 + .mask = 0xfff00000,
98 + },
99 + /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
100 + { .die = "T1040",
101 + .svr = 0x85200000,
102 + .mask = 0xfff00000,
103 + },
104 + /* Die: T2080, SoC: T2080/T2081 */
105 + { .die = "T2080",
106 + .svr = 0x85300000,
107 + .mask = 0xfff00000,
108 + },
109 + /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
110 + { .die = "T1024",
111 + .svr = 0x85400000,
112 + .mask = 0xfff00000,
113 + },
114 +
115 + /*
116 + * ARM-based SoCs LS Series
117 + */
118 +
119 + /* Die: LS1043A, SoC: LS1043A/LS1023A */
120 + { .die = "LS1043A",
121 + .svr = 0x87920000,
122 + .mask = 0xffff0000,
123 + },
124 + /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
125 + { .die = "LS2080A",
126 + .svr = 0x87010000,
127 + .mask = 0xff3f0000,
128 + },
129 + /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
130 + { .die = "LS1088A",
131 + .svr = 0x87030000,
132 + .mask = 0xff3f0000,
133 + },
134 + /* Die: LS1012A, SoC: LS1012A */
135 + { .die = "LS1012A",
136 + .svr = 0x87040000,
137 + .mask = 0xffff0000,
138 + },
139 + /* Die: LS1046A, SoC: LS1046A/LS1026A */
140 + { .die = "LS1046A",
141 + .svr = 0x87070000,
142 + .mask = 0xffff0000,
143 + },
144 + /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
145 + { .die = "LS2088A",
146 + .svr = 0x87090000,
147 + .mask = 0xff3f0000,
148 + },
149 + /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
150 + { .die = "LS1021A",
151 + .svr = 0x87000000,
152 + .mask = 0xfff70000,
153 + },
154 + { },
155 +};
156 +
157 +static const struct fsl_soc_die_attr *fsl_soc_die_match(
158 + u32 svr, const struct fsl_soc_die_attr *matches)
159 +{
160 + while (matches->svr) {
161 + if (matches->svr == (svr & matches->mask))
162 + return matches;
163 + matches++;
164 + };
165 + return NULL;
166 +}
167 +
168 +u32 fsl_guts_get_svr(void)
169 +{
170 + u32 svr = 0;
171 +
172 + if (!guts || !guts->regs)
173 + return svr;
174 +
175 + if (guts->little_endian)
176 + svr = ioread32(&guts->regs->svr);
177 + else
178 + svr = ioread32be(&guts->regs->svr);
179 +
180 + return svr;
181 +}
182 +EXPORT_SYMBOL(fsl_guts_get_svr);
183 +
184 +static int fsl_guts_probe(struct platform_device *pdev)
185 +{
186 + struct device_node *np = pdev->dev.of_node;
187 + struct device *dev = &pdev->dev;
188 + struct resource *res;
189 + const struct fsl_soc_die_attr *soc_die;
190 + const char *machine;
191 + u32 svr;
192 +
193 + /* Initialize guts */
194 + guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
195 + if (!guts)
196 + return -ENOMEM;
197 +
198 + guts->little_endian = of_property_read_bool(np, "little-endian");
199 +
200 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
201 + guts->regs = devm_ioremap_resource(dev, res);
202 + if (IS_ERR(guts->regs))
203 + return PTR_ERR(guts->regs);
204 +
205 + /* Register soc device */
206 + machine = of_flat_dt_get_machine_name();
207 + if (machine)
208 + soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
209 +
210 + svr = fsl_guts_get_svr();
211 + soc_die = fsl_soc_die_match(svr, fsl_soc_die);
212 + if (soc_die) {
213 + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
214 + "QorIQ %s", soc_die->die);
215 + } else {
216 + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
217 + }
218 + soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
219 + "svr:0x%08x", svr);
220 + soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
221 + (svr >> 4) & 0xf, svr & 0xf);
222 +
223 + soc_dev = soc_device_register(&soc_dev_attr);
224 + if (IS_ERR(soc_dev))
225 + return PTR_ERR(soc_dev);
226 +
227 + pr_info("Machine: %s\n", soc_dev_attr.machine);
228 + pr_info("SoC family: %s\n", soc_dev_attr.family);
229 + pr_info("SoC ID: %s, Revision: %s\n",
230 + soc_dev_attr.soc_id, soc_dev_attr.revision);
231 + return 0;
232 +}
233 +
234 +static int fsl_guts_remove(struct platform_device *dev)
235 +{
236 + soc_device_unregister(soc_dev);
237 + return 0;
238 +}
239 +
240 +/*
241 + * Table for matching compatible strings, for device tree
242 + * guts node, for Freescale QorIQ SOCs.
243 + */
244 +static const struct of_device_id fsl_guts_of_match[] = {
245 + { .compatible = "fsl,qoriq-device-config-1.0", },
246 + { .compatible = "fsl,qoriq-device-config-2.0", },
247 + { .compatible = "fsl,p1010-guts", },
248 + { .compatible = "fsl,p1020-guts", },
249 + { .compatible = "fsl,p1021-guts", },
250 + { .compatible = "fsl,p1022-guts", },
251 + { .compatible = "fsl,p1023-guts", },
252 + { .compatible = "fsl,p2020-guts", },
253 + { .compatible = "fsl,bsc9131-guts", },
254 + { .compatible = "fsl,bsc9132-guts", },
255 + { .compatible = "fsl,mpc8536-guts", },
256 + { .compatible = "fsl,mpc8544-guts", },
257 + { .compatible = "fsl,mpc8548-guts", },
258 + { .compatible = "fsl,mpc8568-guts", },
259 + { .compatible = "fsl,mpc8569-guts", },
260 + { .compatible = "fsl,mpc8572-guts", },
261 + { .compatible = "fsl,ls1021a-dcfg", },
262 + { .compatible = "fsl,ls1043a-dcfg", },
263 + { .compatible = "fsl,ls1046a-dcfg", },
264 + { .compatible = "fsl,ls2080a-dcfg", },
265 + { .compatible = "fsl,ls1088a-dcfg", },
266 + {}
267 +};
268 +MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
269 +
270 +static struct platform_driver fsl_guts_driver = {
271 + .driver = {
272 + .name = "fsl-guts",
273 + .of_match_table = fsl_guts_of_match,
274 + },
275 + .probe = fsl_guts_probe,
276 + .remove = fsl_guts_remove,
277 +};
278 +
279 +static int __init fsl_guts_init(void)
280 +{
281 + return platform_driver_register(&fsl_guts_driver);
282 +}
283 +core_initcall(fsl_guts_init);
284 +
285 +static void __exit fsl_guts_exit(void)
286 +{
287 + platform_driver_unregister(&fsl_guts_driver);
288 +}
289 +module_exit(fsl_guts_exit);
290 --- a/include/linux/fsl/guts.h
291 +++ b/include/linux/fsl/guts.h
292 @@ -29,83 +29,112 @@
293 * #ifdefs.
294 */
295 struct ccsr_guts {
296 - __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
297 - __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
298 - __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
299 - __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
300 - __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
301 - __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
302 + u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
303 + u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
304 + u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
305 + * Control Register
306 + */
307 + u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
308 + u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
309 + u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
310 u8 res018[0x20 - 0x18];
311 - __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
312 + u32 porcir; /* 0x.0020 - POR Configuration Information
313 + * Register
314 + */
315 u8 res024[0x30 - 0x24];
316 - __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
317 + u32 gpiocr; /* 0x.0030 - GPIO Control Register */
318 u8 res034[0x40 - 0x34];
319 - __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
320 + u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
321 + * Register
322 + */
323 u8 res044[0x50 - 0x44];
324 - __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
325 + u32 gpindr; /* 0x.0050 - General-Purpose Input Data
326 + * Register
327 + */
328 u8 res054[0x60 - 0x54];
329 - __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
330 - __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
331 - __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
332 + u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
333 + * Multiplex Control
334 + */
335 + u32 pmuxcr2; /* 0x.0064 - Alternate function signal
336 + * multiplex control 2
337 + */
338 + u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
339 u8 res06c[0x70 - 0x6c];
340 - __be32 devdisr; /* 0x.0070 - Device Disable Control */
341 + u32 devdisr; /* 0x.0070 - Device Disable Control */
342 #define CCSR_GUTS_DEVDISR_TB1 0x00001000
343 #define CCSR_GUTS_DEVDISR_TB0 0x00004000
344 - __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
345 + u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
346 u8 res078[0x7c - 0x78];
347 - __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
348 - __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
349 - __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
350 - __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
351 - __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
352 - __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
353 - __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
354 - __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
355 - __be32 autorstsr; /* 0x.009c - Automatic reset status register */
356 - __be32 pvr; /* 0x.00a0 - Processor Version Register */
357 - __be32 svr; /* 0x.00a4 - System Version Register */
358 + u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
359 + * Register
360 + */
361 + u32 powmgtcsr; /* 0x.0080 - Power Management Status and
362 + * Control Register
363 + */
364 + u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
365 + * Configuration Register
366 + */
367 + u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
368 + * Configuration Register
369 + */
370 + u32 pmcdr; /* 0x.008c - 4Power management clock disable
371 + * register
372 + */
373 + u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
374 + u32 rstrscr; /* 0x.0094 - Reset Request Status and
375 + * Control Register
376 + */
377 + u32 ectrstcr; /* 0x.0098 - Exception reset control register */
378 + u32 autorstsr; /* 0x.009c - Automatic reset status register */
379 + u32 pvr; /* 0x.00a0 - Processor Version Register */
380 + u32 svr; /* 0x.00a4 - System Version Register */
381 u8 res0a8[0xb0 - 0xa8];
382 - __be32 rstcr; /* 0x.00b0 - Reset Control Register */
383 + u32 rstcr; /* 0x.00b0 - Reset Control Register */
384 u8 res0b4[0xc0 - 0xb4];
385 - __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
386 + u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
387 Called 'elbcvselcr' on 86xx SOCs */
388 u8 res0c4[0x100 - 0xc4];
389 - __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
390 + u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
391 There are 16 registers */
392 u8 res140[0x224 - 0x140];
393 - __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
394 - __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
395 + u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
396 + u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
397 u8 res22c[0x604 - 0x22c];
398 - __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
399 + u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
400 u8 res608[0x800 - 0x608];
401 - __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
402 + u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
403 u8 res804[0x900 - 0x804];
404 - __be32 ircr; /* 0x.0900 - Infrared Control Register */
405 + u32 ircr; /* 0x.0900 - Infrared Control Register */
406 u8 res904[0x908 - 0x904];
407 - __be32 dmacr; /* 0x.0908 - DMA Control Register */
408 + u32 dmacr; /* 0x.0908 - DMA Control Register */
409 u8 res90c[0x914 - 0x90c];
410 - __be32 elbccr; /* 0x.0914 - eLBC Control Register */
411 + u32 elbccr; /* 0x.0914 - eLBC Control Register */
412 u8 res918[0xb20 - 0x918];
413 - __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
414 - __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
415 - __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
416 + u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
417 + u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
418 + u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
419 u8 resb2c[0xe00 - 0xb2c];
420 - __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
421 + u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
422 u8 rese04[0xe10 - 0xe04];
423 - __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
424 + u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
425 u8 rese14[0xe20 - 0xe14];
426 - __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
427 - __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
428 + u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
429 + u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
430 + * register
431 + */
432 u8 rese28[0xf04 - 0xe28];
433 - __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
434 - __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
435 + u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
436 + u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
437 u8 resf0c[0xf2c - 0xf0c];
438 - __be32 itcr; /* 0x.0f2c - Internal transaction control register */
439 + u32 itcr; /* 0x.0f2c - Internal transaction control
440 + * register
441 + */
442 u8 resf30[0xf40 - 0xf30];
443 - __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
444 - __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
445 + u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
446 + u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
447 } __attribute__ ((packed));
448
449 +u32 fsl_guts_get_svr(void);
450
451 /* Alternate function signal multiplex control */
452 #define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
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