d69820d2aadb7c3237dc4810cf4e3fe1daccd877
[openwrt/staging/wigyori.git] / target / linux / oxnas / files / drivers / pci / host / pcie-oxnas.c
1 /*
2 * PCIe driver for PLX NAS782X SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/mbus.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/slab.h>
16 #include <linux/platform_device.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_pci.h>
22 #include <linux/of_platform.h>
23 #include <linux/gpio.h>
24 #include <linux/delay.h>
25 #include <linux/clk.h>
26 #include <linux/regmap.h>
27 #include <linux/reset.h>
28 #include <linux/io.h>
29 #include <linux/sizes.h>
30
31 #define SYS_CTRL_HCSL_CTRL_REGOFFSET 0x114
32
33 static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
34 {
35 u32 val = readl_relaxed(p);
36
37 val &= ~mask;
38 writel_relaxed(val, p);
39 }
40
41 static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
42 {
43 u32 val = readl_relaxed(p);
44
45 val |= mask;
46 writel_relaxed(val, p);
47 }
48
49 static inline void oxnas_register_value_mask(void __iomem *p,
50 unsigned mask, unsigned new_value)
51 {
52 /* TODO sanity check mask & new_value = new_value */
53 u32 val = readl_relaxed(p);
54
55 val &= ~mask;
56 val |= new_value;
57 writel_relaxed(val, p);
58 }
59
60 #define VERSION_ID_MAGIC 0x082510b5
61 #define LINK_UP_TIMEOUT_SECONDS 1
62 #define NUM_CONTROLLERS 1
63
64 enum {
65 PCIE_DEVICE_TYPE_MASK = 0x0F,
66 PCIE_DEVICE_TYPE_ENDPOINT = 0,
67 PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
68 PCIE_DEVICE_TYPE_ROOT = 4,
69
70 PCIE_LTSSM = BIT(4),
71 PCIE_READY_ENTR_L23 = BIT(9),
72 PCIE_LINK_UP = BIT(11),
73 PCIE_OBTRANS = BIT(12),
74 };
75
76 enum {
77 HCSL_BIAS_ON = BIT(0),
78 HCSL_PCIE_EN = BIT(1),
79 HCSL_PCIEA_EN = BIT(2),
80 HCSL_PCIEB_EN = BIT(3),
81 };
82
83 enum {
84 /* pcie phy reg offset */
85 PHY_ADDR = 0,
86 PHY_DATA = 4,
87 /* phy data reg bits */
88 READ_EN = BIT(16),
89 WRITE_EN = BIT(17),
90 CAP_DATA = BIT(18),
91 };
92
93 /* core config registers */
94 enum {
95 PCI_CONFIG_VERSION_DEVICEID = 0,
96 PCI_CONFIG_COMMAND_STATUS = 4,
97 };
98
99 /* inbound config registers */
100 enum {
101 IB_ADDR_XLATE_ENABLE = 0xFC,
102
103 /* bits */
104 ENABLE_IN_ADDR_TRANS = BIT(0),
105 };
106
107 /* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
108 enum {
109 PCIE_POM0_MEM_ADDR = 0,
110 PCIE_POM1_MEM_ADDR = 4,
111 PCIE_IN0_MEM_ADDR = 8,
112 PCIE_IN1_MEM_ADDR = 12,
113 PCIE_IN_IO_ADDR = 16,
114 PCIE_IN_CFG0_ADDR = 20,
115 PCIE_IN_CFG1_ADDR = 24,
116 PCIE_IN_MSG_ADDR = 28,
117 PCIE_IN0_MEM_LIMIT = 32,
118 PCIE_IN1_MEM_LIMIT = 36,
119 PCIE_IN_IO_LIMIT = 40,
120 PCIE_IN_CFG0_LIMIT = 44,
121 PCIE_IN_CFG1_LIMIT = 48,
122 PCIE_IN_MSG_LIMIT = 52,
123 PCIE_AHB_SLAVE_CTRL = 56,
124
125 PCIE_SLAVE_BE_SHIFT = 22,
126 };
127
128 #define ADDR_VAL(val) ((val) & 0xFFFF)
129 #define DATA_VAL(val) ((val) & 0xFFFF)
130
131 #define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
132 #define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
133
134 struct oxnas_pcie_shared {
135 /* seems all access are serialized, no lock required */
136 int refcount;
137 };
138
139 /* Structure representing one PCIe interfaces */
140 struct oxnas_pcie {
141 void __iomem *cfgbase;
142 void __iomem *base;
143 void __iomem *inbound;
144 struct regmap *sys_ctrl;
145 unsigned int outbound_offset;
146 unsigned int pcie_ctrl_offset;
147
148 int haslink;
149 struct platform_device *pdev;
150 struct resource io;
151 struct resource cfg;
152 struct resource pre_mem; /* prefetchable */
153 struct resource non_mem; /* non-prefetchable */
154 struct resource busn; /* max available bus numbers */
155 int card_reset; /* gpio pin, optional */
156 unsigned hcsl_en; /* hcsl pci enable bit */
157 struct clk *clk;
158 struct clk *busclk; /* for pcie bus, actually the PLLB */
159 void *private_data[1];
160 spinlock_t lock;
161 };
162
163 static struct oxnas_pcie_shared pcie_shared = {
164 .refcount = 0,
165 };
166
167 static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
168 {
169 return sys->private_data;
170 }
171
172
173 static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
174 {
175 regmap_update_bits(pcie->sys_ctrl, pcie->outbound_offset + PCIE_AHB_SLAVE_CTRL,
176 PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
177 wmb();
178 }
179
180 static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
181 {
182 unsigned long end;
183 unsigned int val;
184
185 /* Poll for PCIE link up */
186 end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
187 while (!time_after(jiffies, end)) {
188 regmap_read(pcie->sys_ctrl, pcie->pcie_ctrl_offset, &val);
189 if (val & PCIE_LINK_UP)
190 return 1;
191 }
192 return 0;
193 }
194
195 static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
196 {
197 /* We won't have any inbound address translation. This allows PCI
198 * devices to access anywhere in the AHB address map. Might be regarded
199 * as a bit dangerous, but let's get things working before we worry
200 * about that
201 */
202 oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
203 ENABLE_IN_ADDR_TRANS);
204 wmb();
205
206 /*
207 * Program outbound translation windows
208 *
209 * Outbound window is what is referred to as "PCI client" region in HRM
210 *
211 * Could use the larger alternative address space to get >>64M regions
212 * for graphics cards etc., but will not bother at this point.
213 *
214 * IP bug means that AMBA window size must be a power of 2
215 *
216 * Set mem0 window for first 16MB of outbound window non-prefetchable
217 * Set mem1 window for second 16MB of outbound window prefetchable
218 * Set io window for next 16MB of outbound window
219 * Set cfg0 for final 1MB of outbound window
220 *
221 * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
222 * 820 that would need them
223 *
224 * Probably ideally want no offset between mem0 window start as seen by
225 * ARM and as seen on PCI bus and get Linux to assign memory regions to
226 * PCI devices using the same "PCI client" region start address as seen
227 * by ARM
228 */
229
230 /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
231 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_ADDR, pcie->non_mem.start);
232 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN0_MEM_LIMIT, pcie->non_mem.end);
233 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM0_MEM_ADDR, pcie->non_mem.start);
234
235 /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
236 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_ADDR, pcie->pre_mem.start);
237 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN1_MEM_LIMIT, pcie->pre_mem.end);
238 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_POM1_MEM_ADDR, pcie->pre_mem.start);
239
240 /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
241 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_ADDR, pcie->io.start);
242 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_IO_LIMIT, pcie->io.end);
243
244
245 /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
246 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_ADDR, pcie->cfg.start);
247 regmap_write(pcie->sys_ctrl, pcie->outbound_offset + PCIE_IN_CFG0_LIMIT, pcie->cfg.end);
248 wmb();
249
250 /* Enable outbound address translation */
251 regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset, PCIE_OBTRANS, PCIE_OBTRANS);
252 wmb();
253
254 /*
255 * Program PCIe command register for core to:
256 * enable memory space
257 * enable bus master
258 * enable io
259 */
260 writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
261 /* which is which */
262 wmb();
263 }
264
265 static unsigned oxnas_pcie_cfg_to_offset(
266 struct pci_sys_data *sys,
267 unsigned char bus_number,
268 unsigned int devfn,
269 int where)
270 {
271 unsigned int function = PCI_FUNC(devfn);
272 unsigned int slot = PCI_SLOT(devfn);
273 unsigned char bus_number_offset;
274
275 bus_number_offset = bus_number - sys->busnr;
276
277 /*
278 * We'll assume for now that the offset, function, slot, bus encoding
279 * should map onto linear, contiguous addresses in PCIe config space,
280 * albeit that the majority will be unused as only slot 0 is valid for
281 * any PCIe bus and most devices have only function 0
282 *
283 * Could be that PCIe in fact works by not encoding the slot number into
284 * the config space address as it's known that only slot 0 is valid.
285 * We'll have to experiment if/when we get a PCIe switch connected to
286 * the PCIe host
287 */
288 return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
289 (where & ~3);
290 }
291
292 /* PCI configuration space write function */
293 static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
294 int where, int size, u32 val)
295 {
296 unsigned long flags;
297 struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
298 unsigned offset;
299 u32 value;
300 u32 lanes;
301
302 /* Only a single device per bus for PCIe point-to-point links */
303 if (PCI_SLOT(devfn) > 0)
304 return PCIBIOS_DEVICE_NOT_FOUND;
305
306 if (!pcie->haslink)
307 return PCIBIOS_DEVICE_NOT_FOUND;
308
309 offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
310 where);
311
312 value = val << (8 * (where & 3));
313 lanes = (0xf >> (4-size)) << (where & 3);
314 /* it race with mem and io write, but the possibility is low, normally
315 * all config writes happens at driver initialize stage, wont interleave
316 * with others.
317 * and many pcie cards use dword (4bytes) access mem/io access only,
318 * so not bother to copy that ugly work-around now. */
319 spin_lock_irqsave(&pcie->lock, flags);
320 set_out_lanes(pcie, lanes);
321 writel_relaxed(value, pcie->cfgbase + offset);
322 set_out_lanes(pcie, 0xf);
323 spin_unlock_irqrestore(&pcie->lock, flags);
324
325 return PCIBIOS_SUCCESSFUL;
326 }
327
328 /* PCI configuration space read function */
329 static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
330 int size, u32 *val)
331 {
332 struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
333 unsigned offset;
334 u32 value;
335 u32 left_bytes, right_bytes;
336
337 /* Only a single device per bus for PCIe point-to-point links */
338 if (PCI_SLOT(devfn) > 0) {
339 *val = 0xffffffff;
340 return PCIBIOS_DEVICE_NOT_FOUND;
341 }
342
343 if (!pcie->haslink) {
344 *val = 0xffffffff;
345 return PCIBIOS_DEVICE_NOT_FOUND;
346 }
347
348 offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
349 where);
350 value = readl_relaxed(pcie->cfgbase + offset);
351 left_bytes = where & 3;
352 right_bytes = 4 - left_bytes - size;
353 value <<= right_bytes * 8;
354 value >>= (left_bytes + right_bytes) * 8;
355 *val = value;
356
357 return PCIBIOS_SUCCESSFUL;
358 }
359
360 static struct pci_ops oxnas_pcie_ops = {
361 .read = oxnas_pcie_rd_conf,
362 .write = oxnas_pcie_wr_conf,
363 };
364
365 static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
366 {
367 struct oxnas_pcie *pcie = sys_to_pcie(sys);
368
369 pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
370 pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
371 pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
372 pci_add_resource(&sys->resources, &pcie->busn);
373 if (sys->busnr == 0) { /* default one */
374 sys->busnr = pcie->busn.start;
375 }
376 /* do not use devm_ioremap_resource, it does not like cfg resource */
377 pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
378 resource_size(&pcie->cfg));
379 if (!pcie->cfgbase)
380 return -ENOMEM;
381
382 oxnas_pcie_setup_hw(pcie);
383
384 return 1;
385 }
386
387 static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
388 {
389 struct hw_pci hw;
390 int i;
391
392 memset(&hw, 0, sizeof(hw));
393 for (i = 0; i < NUM_CONTROLLERS; i++)
394 pcie->private_data[i] = pcie;
395
396 hw.nr_controllers = NUM_CONTROLLERS;
397 /* I think use stack pointer is a bad idea though it is valid in this case */
398 hw.private_data = pcie->private_data;
399 hw.setup = oxnas_pcie_setup;
400 hw.map_irq = of_irq_parse_and_map_pci;
401 hw.ops = &oxnas_pcie_ops;
402
403 /* pass dev to maintain of tree, interrupt mapping rely on this */
404 pci_common_init_dev(dev, &hw);
405 }
406
407 void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
408 void __iomem *phybase,
409 struct regmap *sys_ctrl)
410 {
411 struct reset_control *rstc;
412 int ret;
413
414 /* generate clocks from HCSL buffers, shared parts */
415 regmap_write(sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET, HCSL_BIAS_ON|HCSL_PCIE_EN);
416
417 /* Ensure PCIe PHY is properly reset */
418 rstc = reset_control_get(&pdev->dev, "phy");
419 if (IS_ERR(rstc)) {
420 ret = PTR_ERR(rstc);
421 } else {
422 ret = reset_control_reset(rstc);
423 reset_control_put(rstc);
424 }
425
426 if (ret) {
427 dev_err(&pdev->dev, "phy reset failed %d\n", ret);
428 return;
429 }
430
431 /* Enable PCIe Pre-Emphasis: What these value means? */
432 writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
433 writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
434 writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
435
436 writel(ADDR_VAL(0x2004), phybase + PHY_ADDR);
437 writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA);
438 writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
439 }
440
441 static int oxnas_pcie_shared_init(struct platform_device *pdev, struct regmap *sys_ctrl)
442 {
443 if (++pcie_shared.refcount == 1) {
444 /* we are the first */
445 struct device_node *np = pdev->dev.of_node;
446 void __iomem *phy = of_iomap(np, 2);
447 if (!phy) {
448 --pcie_shared.refcount;
449 return -ENOMEM;
450 }
451 oxnas_pcie_init_shared_hw(pdev, phy, sys_ctrl);
452 iounmap(phy);
453 return 0;
454 } else {
455 return 0;
456 }
457 }
458
459 #if 0
460 /* maybe we will call it when enter low power state */
461 static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
462 {
463 if (--pcie_shared.refcount == 0) {
464 /* no cleanup needed */;
465 }
466 }
467 #endif
468
469 static int __init
470 oxnas_pcie_map_registers(struct platform_device *pdev,
471 struct device_node *np,
472 struct oxnas_pcie *pcie)
473 {
474 struct resource regs;
475 int ret = 0;
476 u32 outbound_ctrl_offset;
477 u32 pcie_ctrl_offset;
478
479 /* 2 is reserved for shared phy */
480 ret = of_address_to_resource(np, 0, &regs);
481 if (ret)
482 return -EINVAL;
483 pcie->base = devm_ioremap_resource(&pdev->dev, &regs);
484 if (!pcie->base)
485 return -ENOMEM;
486
487 ret = of_address_to_resource(np, 1, &regs);
488 if (ret)
489 return -EINVAL;
490 pcie->inbound = devm_ioremap_resource(&pdev->dev, &regs);
491 if (!pcie->inbound)
492 return -ENOMEM;
493
494
495 if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
496 &outbound_ctrl_offset))
497 return -EINVAL;
498 pcie->outbound_offset = outbound_ctrl_offset;
499
500 if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
501 &pcie_ctrl_offset))
502 return -EINVAL;
503 pcie->pcie_ctrl_offset = pcie_ctrl_offset;
504
505 return 0;
506 }
507
508 static int __init oxnas_pcie_init_res(struct platform_device *pdev,
509 struct oxnas_pcie *pcie,
510 struct device_node *np)
511 {
512 struct of_pci_range range;
513 struct of_pci_range_parser parser;
514 int ret;
515
516 if (of_pci_range_parser_init(&parser, np))
517 return -EINVAL;
518
519 /* Get the I/O and memory ranges from DT */
520 for_each_of_pci_range(&parser, &range) {
521
522 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
523 if (restype == IORESOURCE_IO) {
524 of_pci_range_to_resource(&range, np, &pcie->io);
525 pcie->io.name = "I/O";
526 }
527 if (restype == IORESOURCE_MEM) {
528 if (range.flags & IORESOURCE_PREFETCH) {
529 of_pci_range_to_resource(&range, np, &pcie->pre_mem);
530 pcie->pre_mem.name = "PRE MEM";
531 } else {
532 of_pci_range_to_resource(&range, np, &pcie->non_mem);
533 pcie->non_mem.name = "NON MEM";
534 }
535
536 }
537 if (restype == 0)
538 of_pci_range_to_resource(&range, np, &pcie->cfg);
539 }
540
541 /* Get the bus range */
542 ret = of_pci_parse_bus_range(np, &pcie->busn);
543
544 if (ret) {
545 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
546 ret);
547 return ret;
548 }
549
550 pcie->card_reset = of_get_gpio(np, 0);
551 if (pcie->card_reset < 0)
552 dev_info(&pdev->dev, "card reset gpio pin not exists\n");
553
554 if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
555 return -EINVAL;
556
557 pcie->clk = of_clk_get_by_name(np, "pcie");
558 if (IS_ERR(pcie->clk)) {
559 return PTR_ERR(pcie->clk);
560 }
561
562 pcie->busclk = of_clk_get_by_name(np, "busclk");
563 if (IS_ERR(pcie->busclk)) {
564 clk_put(pcie->clk);
565 return PTR_ERR(pcie->busclk);
566 }
567
568 return 0;
569 }
570
571 static void oxnas_pcie_init_hw(struct platform_device *pdev,
572 struct oxnas_pcie *pcie)
573 {
574 u32 version_id;
575 int ret;
576
577 clk_prepare_enable(pcie->busclk);
578
579 /* reset PCIe cards use hard-wired gpio pin */
580 if (pcie->card_reset >= 0 &&
581 !gpio_direction_output(pcie->card_reset, 0)) {
582 wmb();
583 mdelay(10);
584 /* must tri-state the pin to pull it up */
585 gpio_direction_input(pcie->card_reset);
586 wmb();
587 mdelay(100);
588 }
589
590 regmap_update_bits(pcie->sys_ctrl, SYS_CTRL_HCSL_CTRL_REGOFFSET,
591 BIT(pcie->hcsl_en), BIT(pcie->hcsl_en));
592
593 /* core */
594 ret = device_reset(&pdev->dev);
595 if (ret) {
596 dev_err(&pdev->dev, "core reset failed %d\n", ret);
597 return;
598 }
599
600 /* Start PCIe core clocks */
601 clk_prepare_enable(pcie->clk);
602
603 version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
604 dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
605
606 if (version_id != VERSION_ID_MAGIC) {
607 dev_info(&pdev->dev, "PCIe controller not found\n");
608 pcie->haslink = 0;
609 return;
610 }
611
612 /* allow entry to L23 state */
613 regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
614 PCIE_READY_ENTR_L23, PCIE_READY_ENTR_L23);
615
616 /* Set PCIe core into RootCore mode */
617 regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
618 PCIE_DEVICE_TYPE_MASK, PCIE_DEVICE_TYPE_ROOT);
619 wmb();
620
621 /* Bring up the PCI core */
622 regmap_write_bits(pcie->sys_ctrl, pcie->pcie_ctrl_offset,
623 PCIE_LTSSM, PCIE_LTSSM);
624 wmb();
625 }
626
627 static int __init oxnas_pcie_probe(struct platform_device *pdev)
628 {
629 struct oxnas_pcie *pcie;
630 struct device_node *np = pdev->dev.of_node;
631 int ret;
632
633 pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
634 GFP_KERNEL);
635 if (!pcie)
636 return -ENOMEM;
637
638 pcie->pdev = pdev;
639 pcie->haslink = 1;
640 spin_lock_init(&pcie->lock);
641
642 pcie->sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
643 if (IS_ERR(pcie->sys_ctrl))
644 return PTR_ERR(pcie->sys_ctrl);
645
646 ret = oxnas_pcie_init_res(pdev, pcie, np);
647 if (ret)
648 return ret;
649 if (pcie->card_reset >= 0) {
650 ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
651 dev_name(&pdev->dev));
652 if (ret) {
653 dev_err(&pdev->dev, "cannot request gpio pin %d\n",
654 pcie->card_reset);
655 return ret;
656 }
657 }
658
659 ret = oxnas_pcie_map_registers(pdev, np, pcie);
660 if (ret) {
661 dev_err(&pdev->dev, "cannot map registers\n");
662 goto err_free_gpio;
663 }
664
665 ret = oxnas_pcie_shared_init(pdev, pcie->sys_ctrl);
666 if (ret)
667 goto err_free_gpio;
668
669 /* if hw not found, haslink cleared */
670 oxnas_pcie_init_hw(pdev, pcie);
671
672 if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
673 pcie->haslink = 1;
674 dev_info(&pdev->dev, "link up\n");
675 } else {
676 pcie->haslink = 0;
677 dev_info(&pdev->dev, "link down\n");
678 }
679 /* should we register our controller even when pcie->haslink is 0 ? */
680 /* register the controller with framework */
681 oxnas_pcie_enable(&pdev->dev, pcie);
682
683 return 0;
684
685 err_free_gpio:
686 if (pcie->card_reset)
687 gpio_free(pcie->card_reset);
688
689 return ret;
690 }
691
692 static const struct of_device_id oxnas_pcie_of_match_table[] = {
693 { .compatible = "plxtech,nas782x-pcie", },
694 {},
695 };
696 MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table);
697
698 static struct platform_driver oxnas_pcie_driver = {
699 .driver = {
700 .owner = THIS_MODULE,
701 .name = "oxnas-pcie",
702 .of_match_table =
703 of_match_ptr(oxnas_pcie_of_match_table),
704 },
705 };
706
707 static int __init oxnas_pcie_init(void)
708 {
709 return platform_driver_probe(&oxnas_pcie_driver,
710 oxnas_pcie_probe);
711 }
712
713 subsys_initcall(oxnas_pcie_init);
714
715 MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>");
716 MODULE_DESCRIPTION("NAS782x PCIe driver");
717 MODULE_LICENSE("GPLv2");