oxnas: add SoC restart driver for reboot
[openwrt/staging/wigyori.git] / target / linux / oxnas / files / drivers / power / reset / oxnas-restart.c
1 // SPDX-License-Identifier: (GPL-2.0)
2 /*
3 * oxnas SoC reset driver
4 * based on:
5 * Microsemi MIPS SoC reset driver
6 * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
7 *
8 * License: GPL
9 * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
10 * Copyright (c) 2017 Microsemi Corporation
11 * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
12 */
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/notifier.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/reboot.h>
21 #include <linux/regmap.h>
22
23 /* bit numbers of reset control register */
24 #define SYS_CTRL_RST_SCU 0
25 #define SYS_CTRL_RST_COPRO 1
26 #define SYS_CTRL_RST_ARM0 2
27 #define SYS_CTRL_RST_ARM1 3
28 #define SYS_CTRL_RST_USBHS 4
29 #define SYS_CTRL_RST_USBHSPHYA 5
30 #define SYS_CTRL_RST_MACA 6
31 #define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
32 #define SYS_CTRL_RST_PCIEA 7
33 #define SYS_CTRL_RST_SGDMA 8
34 #define SYS_CTRL_RST_CIPHER 9
35 #define SYS_CTRL_RST_DDR 10
36 #define SYS_CTRL_RST_SATA 11
37 #define SYS_CTRL_RST_SATA_LINK 12
38 #define SYS_CTRL_RST_SATA_PHY 13
39 #define SYS_CTRL_RST_PCIEPHY 14
40 #define SYS_CTRL_RST_STATIC 15
41 #define SYS_CTRL_RST_GPIO 16
42 #define SYS_CTRL_RST_UART1 17
43 #define SYS_CTRL_RST_UART2 18
44 #define SYS_CTRL_RST_MISC 19
45 #define SYS_CTRL_RST_I2S 20
46 #define SYS_CTRL_RST_SD 21
47 #define SYS_CTRL_RST_MACB 22
48 #define SYS_CTRL_RST_PCIEB 23
49 #define SYS_CTRL_RST_VIDEO 24
50 #define SYS_CTRL_RST_DDR_PHY 25
51 #define SYS_CTRL_RST_USBHSPHYB 26
52 #define SYS_CTRL_RST_USBDEV 27
53 #define SYS_CTRL_RST_ARMDBG 29
54 #define SYS_CTRL_RST_PLLA 30
55 #define SYS_CTRL_RST_PLLB 31
56
57 /* bit numbers of clock control register */
58 #define SYS_CTRL_CLK_COPRO 0
59 #define SYS_CTRL_CLK_DMA 1
60 #define SYS_CTRL_CLK_CIPHER 2
61 #define SYS_CTRL_CLK_SD 3
62 #define SYS_CTRL_CLK_SATA 4
63 #define SYS_CTRL_CLK_I2S 5
64 #define SYS_CTRL_CLK_USBHS 6
65 #define SYS_CTRL_CLK_MACA 7
66 #define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
67 #define SYS_CTRL_CLK_PCIEA 8
68 #define SYS_CTRL_CLK_STATIC 9
69 #define SYS_CTRL_CLK_MACB 10
70 #define SYS_CTRL_CLK_PCIEB 11
71 #define SYS_CTRL_CLK_REF600 12
72 #define SYS_CTRL_CLK_USBDEV 13
73 #define SYS_CTRL_CLK_DDR 14
74 #define SYS_CTRL_CLK_DDRPHY 15
75 #define SYS_CTRL_CLK_DDRCK 16
76
77 /* Regmap offsets */
78 #define CLK_SET_REGOFFSET 0x2c
79 #define CLK_CLR_REGOFFSET 0x30
80 #define RST_SET_REGOFFSET 0x34
81 #define RST_CLR_REGOFFSET 0x38
82 #define SECONDARY_SEL_REGOFFSET 0x14
83 #define TERTIARY_SEL_REGOFFSET 0x8c
84 #define QUATERNARY_SEL_REGOFFSET 0x94
85 #define DEBUG_SEL_REGOFFSET 0x9c
86 #define ALTERNATIVE_SEL_REGOFFSET 0xa4
87 #define PULLUP_SEL_REGOFFSET 0xac
88 #define SEC_SECONDARY_SEL_REGOFFSET 0x100014
89 #define SEC_TERTIARY_SEL_REGOFFSET 0x10008c
90 #define SEC_QUATERNARY_SEL_REGOFFSET 0x100094
91 #define SEC_DEBUG_SEL_REGOFFSET 0x10009c
92 #define SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
93 #define SEC_PULLUP_SEL_REGOFFSET 0x1000ac
94
95
96 struct oxnas_restart_context {
97 struct regmap *sys_ctrl;
98 struct notifier_block restart_handler;
99 };
100
101 static int oxnas_restart_handle(struct notifier_block *this,
102 unsigned long mode, void *cmd)
103 {
104 struct oxnas_restart_context *ctx = container_of(this, struct
105 oxnas_restart_context,
106 restart_handler);
107 u32 value;
108
109 /* Assert reset to cores as per power on defaults
110 * Don't touch the DDR interface as things will come to an impromptu stop
111 * NB Possibly should be asserting reset for PLLB, but there are timing
112 * concerns here according to the docs */
113 value = BIT(SYS_CTRL_RST_COPRO) |
114 BIT(SYS_CTRL_RST_USBHS) |
115 BIT(SYS_CTRL_RST_USBHSPHYA) |
116 BIT(SYS_CTRL_RST_MACA) |
117 BIT(SYS_CTRL_RST_PCIEA) |
118 BIT(SYS_CTRL_RST_SGDMA) |
119 BIT(SYS_CTRL_RST_CIPHER) |
120 BIT(SYS_CTRL_RST_SATA) |
121 BIT(SYS_CTRL_RST_SATA_LINK) |
122 BIT(SYS_CTRL_RST_SATA_PHY) |
123 BIT(SYS_CTRL_RST_PCIEPHY) |
124 BIT(SYS_CTRL_RST_STATIC) |
125 BIT(SYS_CTRL_RST_UART1) |
126 BIT(SYS_CTRL_RST_UART2) |
127 BIT(SYS_CTRL_RST_MISC) |
128 BIT(SYS_CTRL_RST_I2S) |
129 BIT(SYS_CTRL_RST_SD) |
130 BIT(SYS_CTRL_RST_MACB) |
131 BIT(SYS_CTRL_RST_PCIEB) |
132 BIT(SYS_CTRL_RST_VIDEO) |
133 BIT(SYS_CTRL_RST_USBHSPHYB) |
134 BIT(SYS_CTRL_RST_USBDEV);
135
136 regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
137
138 /* Release reset to cores as per power on defaults */
139 regmap_write(ctx->sys_ctrl, RST_CLR_REGOFFSET, BIT(SYS_CTRL_RST_GPIO));
140
141 /* Disable clocks to cores as per power-on defaults - must leave DDR
142 * related clocks enabled otherwise we'll stop rather abruptly. */
143 value =
144 BIT(SYS_CTRL_CLK_COPRO) |
145 BIT(SYS_CTRL_CLK_DMA) |
146 BIT(SYS_CTRL_CLK_CIPHER) |
147 BIT(SYS_CTRL_CLK_SD) |
148 BIT(SYS_CTRL_CLK_SATA) |
149 BIT(SYS_CTRL_CLK_I2S) |
150 BIT(SYS_CTRL_CLK_USBHS) |
151 BIT(SYS_CTRL_CLK_MAC) |
152 BIT(SYS_CTRL_CLK_PCIEA) |
153 BIT(SYS_CTRL_CLK_STATIC) |
154 BIT(SYS_CTRL_CLK_MACB) |
155 BIT(SYS_CTRL_CLK_PCIEB) |
156 BIT(SYS_CTRL_CLK_REF600) |
157 BIT(SYS_CTRL_CLK_USBDEV);
158
159 regmap_write(ctx->sys_ctrl, CLK_CLR_REGOFFSET, value);
160
161 /* Enable clocks to cores as per power-on defaults */
162
163 /* Set sys-control pin mux'ing as per power-on defaults */
164 regmap_write(ctx->sys_ctrl, SECONDARY_SEL_REGOFFSET, 0);
165 regmap_write(ctx->sys_ctrl, TERTIARY_SEL_REGOFFSET, 0);
166 regmap_write(ctx->sys_ctrl, QUATERNARY_SEL_REGOFFSET, 0);
167 regmap_write(ctx->sys_ctrl, DEBUG_SEL_REGOFFSET, 0);
168 regmap_write(ctx->sys_ctrl, ALTERNATIVE_SEL_REGOFFSET, 0);
169 regmap_write(ctx->sys_ctrl, PULLUP_SEL_REGOFFSET, 0);
170
171 regmap_write(ctx->sys_ctrl, SEC_SECONDARY_SEL_REGOFFSET, 0);
172 regmap_write(ctx->sys_ctrl, SEC_TERTIARY_SEL_REGOFFSET, 0);
173 regmap_write(ctx->sys_ctrl, SEC_QUATERNARY_SEL_REGOFFSET, 0);
174 regmap_write(ctx->sys_ctrl, SEC_DEBUG_SEL_REGOFFSET, 0);
175 regmap_write(ctx->sys_ctrl, SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
176 regmap_write(ctx->sys_ctrl, SEC_PULLUP_SEL_REGOFFSET, 0);
177
178 /* No need to save any state, as the ROM loader can determine whether
179 * reset is due to power cycling or programatic action, just hit the
180 * (self-clearing) CPU reset bit of the block reset register */
181 value =
182 BIT(SYS_CTRL_RST_SCU) |
183 BIT(SYS_CTRL_RST_ARM0) |
184 BIT(SYS_CTRL_RST_ARM1);
185
186 regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
187
188 pr_emerg("Unable to restart system\n");
189 return NOTIFY_DONE;
190 }
191
192 static int oxnas_restart_probe(struct platform_device *pdev)
193 {
194 struct oxnas_restart_context *ctx;
195 struct regmap *sys_ctrl;
196 struct device *dev = &pdev->dev;
197 int err = 0;
198
199 sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
200 if (IS_ERR(sys_ctrl))
201 return PTR_ERR(sys_ctrl);
202
203 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
204 if (!ctx)
205 return -ENOMEM;
206
207 ctx->sys_ctrl = sys_ctrl;
208 ctx->restart_handler.notifier_call = oxnas_restart_handle;
209 ctx->restart_handler.priority = 192;
210 err = register_restart_handler(&ctx->restart_handler);
211 if (err)
212 dev_err(dev, "can't register restart notifier (err=%d)\n", err);
213
214 return err;
215 }
216
217 static const struct of_device_id oxnas_restart_of_match[] = {
218 { .compatible = "oxsemi,ox820-sys-ctrl" },
219 {}
220 };
221
222 static struct platform_driver oxnas_restart_driver = {
223 .probe = oxnas_restart_probe,
224 .driver = {
225 .name = "oxnas-chip-reset",
226 .of_match_table = oxnas_restart_of_match,
227 },
228 };
229 builtin_platform_driver(oxnas_restart_driver);