target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch

   1 --- a/drivers/pci/host/Kconfig
   2 +++ b/drivers/pci/host/Kconfig
   3 @@ -220,4 +220,9 @@ config VMD
   4           To compile this driver as a module, choose M here: the
   5           module will be called vmd.
   6
   7 +config PCIE_OXNAS
   8 +       bool "PLX Oxnas PCIe controller"
   9 +       depends on ARCH_OXNAS
  10 +       select PCIEPORTBUS
  11 +
  12  endmenu
  13 --- a/drivers/pci/host/Makefile
  14 +++ b/drivers/pci/host/Makefile
  15 @@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera
  16  obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
  17  obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
  18  obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
  19 +obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
  20  obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
  21  obj-$(CONFIG_VMD) += vmd.o
  22
  23 --- a/arch/arm/boot/dts/ox820.dtsi
  24 +++ b/arch/arm/boot/dts/ox820.dtsi
  25 @@ -316,6 +316,89 @@
  26                                 reg = <0x1000 0x1000>,
  27                                       <0x100 0x500>;
  28                         };
  29 +
  30 +                       pcie0: pcie-controller@c00000 {
  31 +                               compatible = "plxtech,nas782x-pcie";
  32 +                               device_type = "pci";
  33 +                               #address-cells = <3>;
  34 +                               #size-cells = <2>;
  35 +
  36 +                               /*              flag & space    bus address     host address    size */
  37 +                               ranges = <      0x82000000      0 0x48000000    0x48000000      0 0x2000000
  38 +                                               0xC2000000      0 0x4A000000    0x4A000000      0 0x1E00000
  39 +                                               0x81000000      0 0x4BE00000    0x4BE00000      0 0x0100000
  40 +                                               0x80000000      0 0x4BF00000    0x4BF00000      0 0x0100000>;
  41 +
  42 +                               bus-range = <0x00 0x7f>;
  43 +
  44 +                               /*      cfg             inbound translator      */
  45 +                               reg =   <0xc00000 0x1000>,      <0xd00000 0x100>;
  46 +
  47 +                               phys = <&pcie_phy>;
  48 +                               phy-names = "pcie-phy";
  49 +
  50 +                               #interrupt-cells = <1>;
  51 +                               /* wild card mask, match all bus address & interrupt specifier */
  52 +                               /* format: bus address mask, interrupt specifier mask */
  53 +                               /* each bit 1 means need match, 0 means ignored when match */
  54 +                               interrupt-map-mask = <0 0 0 0>;
  55 +                               /* format: a list of: bus address, interrupt specifier,
  56 +                                * parent interrupt controller & specifier */
  57 +                               interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
  58 +
  59 +                               gpios = <&gpio1 12 0>;
  60 +                               clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
  61 +                               clock-names = "pcie", "busclk";
  62 +                               resets = <&reset RESET_PCIEA>;
  63 +                               reset-names = "pcie";
  64 +
  65 +                               plxtech,pcie-hcsl-bit = <2>;
  66 +                               plxtech,pcie-ctrl-offset = <0x120>;
  67 +                               plxtech,pcie-outbound-offset = <0x138>;
  68 +                               status = "disabled";
  69 +                       };
  70 +
  71 +                       pcie1: pcie-controller@e00000 {
  72 +                               compatible = "plxtech,nas782x-pcie";
  73 +                               device_type = "pci";
  74 +                               #address-cells = <3>;
  75 +                               #size-cells = <2>;
  76 +
  77 +                               /*              flag & space    bus address     host address    size */
  78 +                               ranges = <      0x82000000      0 0x4C000000    0x4C000000      0 0x2000000
  79 +                                               0xC2000000      0 0x4E000000    0x4E000000      0 0x1E00000
  80 +                                               0x81000000      0 0x4FE00000    0x4FE00000      0 0x0100000
  81 +                                               0x80000000      0 0x4FF00000    0x4FF00000      0 0x0100000>;
  82 +
  83 +                               bus-range = <0x80 0xff>;
  84 +
  85 +                               /*      cfg             inbound translator      */
  86 +                               reg =   <0xe00000 0x1000>,      <0xf00000 0x100>;
  87 +
  88 +                               phys = <&pcie_phy>;
  89 +                               phy-names = "pcie-phy";
  90 +
  91 +                               #interrupt-cells = <1>;
  92 +                               /* wild card mask, match all bus address & interrupt specifier */
  93 +                               /* format: bus address mask, interrupt specifier mask */
  94 +                               /* each bit 1 means need match, 0 means ignored when match */
  95 +                               interrupt-map-mask = <0 0 0 0>;
  96 +                               /* format: a list of: bus address, interrupt specifier,
  97 +                                * parent interrupt controller & specifier */
  98 +                               interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
  99 +
 100 +                               /* gpios = <&gpio1 12 0>; */
 101 +                               clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
 102 +                               clock-names = "pcie", "busclk";
 103 +                               resets = <&reset RESET_PCIEB>;
 104 +                               reset-names = "pcie";
 105 +
 106 +                               plxtech,pcie-hcsl-bit = <3>;
 107 +                               plxtech,pcie-ctrl-offset = <0x124>;
 108 +                               plxtech,pcie-outbound-offset = <0x174>;
 109 +                               status = "disabled";
 110 +                       };
 111 +
 112                 };
 113         };
 114  };