ramips: Add support for Phicomm K2G
[openwrt/staging/wigyori.git] / target / linux / ramips / dts / K2G.dts
1 /dts-v1/;
2
3 #include "mt7620a.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7
8 / {
9 compatible = "phicomm,k2g", "ralink,mt7620a-soc";
10 model = "Phicomm K2G";
11
12 aliases {
13 serial0 = &uartlite;
14 };
15
16 gpio-leds {
17 compatible = "gpio-leds";
18
19 led_blue: blue {
20 label = "k2g:blue:status";
21 gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
22 };
23
24 yellow {
25 label = "k2g:yellow:status";
26 gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
27 };
28
29 red {
30 label = "k2g:red:status";
31 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
32 };
33 };
34
35 gpio-keys-polled {
36 compatible = "gpio-keys-polled";
37 #address-cells = <1>;
38 #size-cells = <0>;
39 poll-interval = <20>;
40
41 reset {
42 label = "reset";
43 gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
44 linux,code = <KEY_RESTART>;
45 };
46 };
47 };
48
49 &spi0 {
50 status = "okay";
51
52 m25p80@0 {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 compatible = "jedec,spi-nor";
56 reg = <0>;
57 spi-max-frequency = <24000000>;
58
59 partitions {
60 compatible = "fixed-partitions";
61 #address-cells = <1>;
62 #size-cells = <1>;
63
64 u-boot@0 {
65 reg = <0x0 0x30000>;
66 read-only;
67 };
68
69 u-boot-env@30000 {
70 reg = <0x30000 0x10000>;
71 read-only;
72 };
73
74 factory: factory@40000 {
75 reg = <0x40000 0x10000>;
76 read-only;
77 };
78
79 permanent_config@50000 {
80 reg = <0x50000 0x50000>;
81 read-only;
82 };
83
84 firmware@a0000 {
85 reg = <0xa0000 0x760000>;
86 };
87 };
88 };
89 };
90
91 &pinctrl {
92 state_default: pinctrl0 {
93 gpio {
94 ralink,group = "i2c", "uartf";
95 ralink,function = "gpio";
96 };
97 };
98 };
99
100 &ethernet {
101 pinctrl-names = "default";
102 pinctrl-0 = <&rgmii2_pins &mdio_pins>;
103 mtd-mac-address = <&factory 0x28>;
104 mediatek,portmap = "llllw";
105
106 port@5 {
107 status = "okay";
108 phy-handle = <&phy5>;
109 phy-mode = "rgmii";
110 };
111
112 mdio-bus {
113 status = "okay";
114
115 phy5: ethernet-phy@5 {
116 reg = <5>;
117 phy-mode = "rgmii";
118 };
119 };
120 };
121
122 &pcie {
123 status = "okay";
124
125 pcie-bridge {
126 mt76@0,0 {
127 reg = <0x0000 0 0 0 0>;
128 device_type = "pci";
129 mediatek,mtd-eeprom = <&factory 0x8000>;
130 ieee80211-freq-limit = <5000000 6000000>;
131 };
132 };
133 };
134
135 &wmac {
136 ralink,mtd-eeprom = <&factory 0>;
137 pinctrl-names = "default";
138 pinctrl-0 = <&pa_pins>;
139 };