target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mt7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         aliases {
  26                 serial0 = &uartlite;
  27         };
  28
  29         cpuclock: cpuclock@0 {
  30                 #clock-cells = <0>;
  31                 compatible = "fixed-clock";
  32
  33                 /* FIXME: there should be way to detect this */
  34                 clock-frequency = <880000000>;
  35         };
  36
  37         sysclock: sysclock@0 {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40
  41                 /* FIXME: there should be way to detect this */
  42                 clock-frequency = <50000000>;
  43         };
  44
  45         palmbus: palmbus@1E000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1E000000 0x100000>;
  48                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc: sysc@0 {
  54                         compatible = "mtk,mt7621-sysc";
  55                         reg = <0x0 0x100>;
  56                 };
  57
  58                 wdt: wdt@100 {
  59                         compatible = "mtk,mt7621-wdt";
  60                         reg = <0x100 0x100>;
  61                 };
  62
  63                 gpio@600 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66
  67                         compatible = "mtk,mt7621-gpio";
  68                         reg = <0x600 0x100>;
  69
  70                         gpio0: bank@0 {
  71                                 reg = <0>;
  72                                 compatible = "mtk,mt7621-gpio-bank";
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                         };
  76
  77                         gpio1: bank@1 {
  78                                 reg = <1>;
  79                                 compatible = "mtk,mt7621-gpio-bank";
  80                                 gpio-controller;
  81                                 #gpio-cells = <2>;
  82                         };
  83
  84                         gpio2: bank@2 {
  85                                 reg = <2>;
  86                                 compatible = "mtk,mt7621-gpio-bank";
  87                                 gpio-controller;
  88                                 #gpio-cells = <2>;
  89                         };
  90                 };
  91
  92                 i2c: i2c@900 {
  93                         compatible = "mediatek,mt7621-i2c";
  94                         reg = <0x900 0x100>;
  95
  96                         clocks = <&sysclock>;
  97
  98                         resets = <&rstctrl 16>;
  99                         reset-names = "i2c";
 100
 101                         #address-cells = <1>;
 102                         #size-cells = <0>;
 103
 104                         status = "disabled";
 105
 106                         pinctrl-names = "default";
 107                         pinctrl-0 = <&i2c_pins>;
 108                 };
 109
 110                 i2s: i2s@a00 {
 111                         compatible = "mediatek,mt7621-i2s";
 112                         reg = <0xa00 0x100>;
 113
 114                         clocks = <&sysclock>;
 115
 116                         resets = <&rstctrl 17>;
 117                         reset-names = "i2s";
 118
 119                         interrupt-parent = <&gic>;
 120                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 121
 122                         txdma-req = <2>;
 123                         rxdma-req = <3>;
 124
 125                         dmas = <&gdma 4>,
 126                                 <&gdma 6>;
 127                         dma-names = "tx", "rx";
 128
 129                         status = "disabled";
 130                 };
 131
 132                 memc: memc@5000 {
 133                         compatible = "mtk,mt7621-memc";
 134                         reg = <0x300 0x100>;
 135                 };
 136
 137                 cpc: cpc@1fbf0000 {
 138                              compatible = "mtk,mt7621-cpc";
 139                              reg = <0x1fbf0000 0x8000>;
 140                 };
 141
 142                 mc: mc@1fbf8000 {
 143                             compatible = "mtk,mt7621-mc";
 144                             reg = <0x1fbf8000 0x8000>;
 145                 };
 146
 147                 uartlite: uartlite@c00 {
 148                         compatible = "ns16550a";
 149                         reg = <0xc00 0x100>;
 150
 151                         clocks = <&sysclock>;
 152                         clock-frequency = <50000000>;
 153
 154                         interrupt-parent = <&gic>;
 155                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 156
 157                         reg-shift = <2>;
 158                         reg-io-width = <4>;
 159                         no-loopback-test;
 160                 };
 161
 162                 spi0: spi@b00 {
 163                         status = "disabled";
 164
 165                         compatible = "ralink,mt7621-spi";
 166                         reg = <0xb00 0x100>;
 167
 168                         clocks = <&sysclock>;
 169
 170                         resets = <&rstctrl 18>;
 171                         reset-names = "spi";
 172
 173                         #address-cells = <1>;
 174                         #size-cells = <0>;
 175
 176                         pinctrl-names = "default";
 177                         pinctrl-0 = <&spi_pins>;
 178                 };
 179
 180                 gdma: gdma@2800 {
 181                         compatible = "ralink,rt3883-gdma";
 182                         reg = <0x2800 0x800>;
 183
 184                         resets = <&rstctrl 14>;
 185                         reset-names = "dma";
 186
 187                         interrupt-parent = <&gic>;
 188                         interrupts = <0 13 4>;
 189
 190                         #dma-cells = <1>;
 191                         #dma-channels = <16>;
 192                         #dma-requests = <16>;
 193
 194                         status = "disabled";
 195                 };
 196
 197                 hsdma: hsdma@7000 {
 198                         compatible = "mediatek,mt7621-hsdma";
 199                         reg = <0x7000 0x1000>;
 200
 201                         resets = <&rstctrl 5>;
 202                         reset-names = "hsdma";
 203
 204                         interrupt-parent = <&gic>;
 205                         interrupts = <0 11 4>;
 206
 207                         #dma-cells = <1>;
 208                         #dma-channels = <1>;
 209                         #dma-requests = <1>;
 210
 211                         status = "disabled";
 212                 };
 213         };
 214
 215         pinctrl: pinctrl {
 216                 compatible = "ralink,rt2880-pinmux";
 217                 pinctrl-names = "default";
 218                 pinctrl-0 = <&state_default>;
 219
 220                 state_default: pinctrl0 {
 221                 };
 222
 223                 i2c_pins: i2c {
 224                         i2c {
 225                                 ralink,group = "i2c";
 226                                 ralink,function = "i2c";
 227                         };
 228                 };
 229
 230                 spi_pins: spi {
 231                         spi {
 232                                 ralink,group = "spi";
 233                                 ralink,function = "spi";
 234                         };
 235                 };
 236
 237                 uart1_pins: uart1 {
 238                         uart1 {
 239                                 ralink,group = "uart1";
 240                                 ralink,function = "uart1";
 241                         };
 242                 };
 243
 244                 uart2_pins: uart2 {
 245                         uart2 {
 246                                 ralink,group = "uart2";
 247                                 ralink,function = "uart2";
 248                         };
 249                 };
 250
 251                 uart3_pins: uart3 {
 252                         uart3 {
 253                                 ralink,group = "uart3";
 254                                 ralink,function = "uart3";
 255                         };
 256                 };
 257
 258                 rgmii1_pins: rgmii1 {
 259                         rgmii1 {
 260                                 ralink,group = "rgmii1";
 261                                 ralink,function = "rgmii1";
 262                         };
 263                 };
 264
 265                 rgmii2_pins: rgmii2 {
 266                         rgmii2 {
 267                                 ralink,group = "rgmii2";
 268                                 ralink,function = "rgmii2";
 269                         };
 270                 };
 271
 272                 mdio_pins: mdio {
 273                         mdio {
 274                                 ralink,group = "mdio";
 275                                 ralink,function = "mdio";
 276                         };
 277                 };
 278
 279                 pcie_pins: pcie {
 280                         pcie {
 281                                 ralink,group = "pcie";
 282                                 ralink,function = "pcie rst";
 283                         };
 284                 };
 285
 286                 nand_pins: nand {
 287                         spi-nand {
 288                                 ralink,group = "spi";
 289                                 ralink,function = "nand1";
 290                         };
 291
 292                         sdhci-nand {
 293                                 ralink,group = "sdhci";
 294                                 ralink,function = "nand2";
 295                         };
 296                 };
 297
 298                 sdhci_pins: sdhci {
 299                         sdhci {
 300                                 ralink,group = "sdhci";
 301                                 ralink,function = "sdhci";
 302                         };
 303                 };
 304         };
 305
 306         rstctrl: rstctrl {
 307                 compatible = "ralink,rt2880-reset";
 308                 #reset-cells = <1>;
 309         };
 310
 311         clkctrl: clkctrl {
 312                 compatible = "ralink,rt2880-clock";
 313                 #clock-cells = <1>;
 314         };
 315
 316         sdhci: sdhci@1E130000 {
 317                 status = "disabled";
 318
 319                 compatible = "ralink,mt7620-sdhci";
 320                 reg = <0x1E130000 0x4000>;
 321
 322                 interrupt-parent = <&gic>;
 323                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 324         };
 325
 326         xhci: xhci@1E1C0000 {
 327                 status = "okay";
 328
 329                 compatible = "mediatek,mt8173-xhci";
 330                 reg = <0x1e1c0000 0x1000
 331                        0x1e1d0700 0x0100>;
 332
 333                 clocks = <&sysclock>;
 334                 clock-names = "sys_ck";
 335
 336                 interrupt-parent = <&gic>;
 337                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 338         };
 339
 340         gic: interrupt-controller@1fbc0000 {
 341                 compatible = "mti,gic";
 342                 reg = <0x1fbc0000 0x2000>;
 343
 344                 interrupt-controller;
 345                 #interrupt-cells = <3>;
 346
 347                 mti,reserved-cpu-vectors = <7>;
 348
 349                 timer {
 350                         compatible = "mti,gic-timer";
 351                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 352                         clocks = <&cpuclock>;
 353                 };
 354         };
 355
 356         nand: nand@1e003000 {
 357                 status = "disabled";
 358
 359                 compatible = "mtk,mt7621-nand";
 360                 bank-width = <2>;
 361                 reg = <0x1e003000 0x800
 362                         0x1e003800 0x800>;
 363                 #address-cells = <1>;
 364                 #size-cells = <1>;
 365         };
 366
 367         ethernet: ethernet@1e100000 {
 368                 compatible = "mediatek,mt7621-eth";
 369                 reg = <0x1e100000 0x10000>;
 370
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373
 374                 resets = <&rstctrl 6 &rstctrl 23>;
 375                 reset-names = "fe", "eth";
 376
 377                 interrupt-parent = <&gic>;
 378                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 379
 380                 mediatek,switch = <&gsw>;
 381
 382                 mdio-bus {
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385
 386                         phy1f: ethernet-phy@1f {
 387                                 reg = <0x1f>;
 388                                 phy-mode = "rgmii";
 389                         };
 390                 };
 391         };
 392
 393         gsw: gsw@1e110000 {
 394                 compatible = "mediatek,mt7621-gsw";
 395                 reg = <0x1e110000 0x8000>;
 396                 interrupt-parent = <&gic>;
 397                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 398         };
 399
 400         pcie: pcie@1e140000 {
 401                 compatible = "mediatek,mt7621-pci";
 402                 reg = <0x1e140000 0x100
 403                         0x1e142000 0x100>;
 404
 405                 #address-cells = <3>;
 406                 #size-cells = <2>;
 407
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&pcie_pins>;
 410
 411                 device_type = "pci";
 412
 413                 bus-range = <0 255>;
 414                 ranges = <
 415                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 416                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 417                 >;
 418
 419                 interrupt-parent = <&gic>;
 420                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 421                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 422                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 423
 424                 status = "disabled";
 425
 426                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 427                 reset-names = "pcie0", "pcie1", "pcie2";
 428                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 429                 clock-names = "pcie0", "pcie1", "pcie2";
 430
 431                 pcie0 {
 432                         reg = <0x0000 0 0 0 0>;
 433
 434                         #address-cells = <3>;
 435                         #size-cells = <2>;
 436
 437                         device_type = "pci";
 438                 };
 439
 440                 pcie1 {
 441                         reg = <0x0800 0 0 0 0>;
 442
 443                         #address-cells = <3>;
 444                         #size-cells = <2>;
 445
 446                         device_type = "pci";
 447                 };
 448
 449                 pcie2 {
 450                         reg = <0x1000 0 0 0 0>;
 451
 452                         #address-cells = <3>;
 453                         #size-cells = <2>;
 454
 455                         device_type = "pci";
 456                 };
 457         };
 458 };