target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mt7621-soc";
   7
   8         cpus {
   9                 #address-cells = <1>;
  10                 #size-cells = <0>;
  11
  12                 cpu@0 {
  13                         device_type = "cpu";
  14                         compatible = "mips,mips1004Kc";
  15                         reg = <0>;
  16                 };
  17
  18                 cpu@1 {
  19                         device_type = "cpu";
  20                         compatible = "mips,mips1004Kc";
  21                         reg = <1>;
  22                 };
  23         };
  24
  25         cpuintc: cpuintc {
  26                 #address-cells = <0>;
  27                 #interrupt-cells = <1>;
  28                 interrupt-controller;
  29                 compatible = "mti,cpu-interrupt-controller";
  30         };
  31
  32         aliases {
  33                 serial0 = &uartlite;
  34         };
  35
  36         cpuclock: cpuclock {
  37                 #clock-cells = <0>;
  38                 compatible = "fixed-clock";
  39
  40                 /* FIXME: there should be way to detect this */
  41                 clock-frequency = <880000000>;
  42         };
  43
  44         sysclock: sysclock {
  45                 #clock-cells = <0>;
  46                 compatible = "fixed-clock";
  47
  48                 /* FIXME: there should be way to detect this */
  49                 clock-frequency = <50000000>;
  50         };
  51
  52
  53
  54         palmbus: palmbus@1E000000 {
  55                 compatible = "palmbus";
  56                 reg = <0x1E000000 0x100000>;
  57                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  58
  59                 #address-cells = <1>;
  60                 #size-cells = <1>;
  61
  62                 sysc: sysc@0 {
  63                         compatible = "mtk,mt7621-sysc";
  64                         reg = <0x0 0x100>;
  65                 };
  66
  67                 wdt: wdt@100 {
  68                         compatible = "mediatek,mt7621-wdt";
  69                         reg = <0x100 0x100>;
  70                 };
  71
  72                 gpio@600 {
  73                         #address-cells = <1>;
  74                         #size-cells = <0>;
  75
  76                         compatible = "mtk,mt7621-gpio";
  77                         reg = <0x600 0x100>;
  78
  79                         gpio0: bank@0 {
  80                                 reg = <0>;
  81                                 compatible = "mtk,mt7621-gpio-bank";
  82                                 gpio-controller;
  83                                 #gpio-cells = <2>;
  84                         };
  85
  86                         gpio1: bank@1 {
  87                                 reg = <1>;
  88                                 compatible = "mtk,mt7621-gpio-bank";
  89                                 gpio-controller;
  90                                 #gpio-cells = <2>;
  91                         };
  92
  93                         gpio2: bank@2 {
  94                                 reg = <2>;
  95                                 compatible = "mtk,mt7621-gpio-bank";
  96                                 gpio-controller;
  97                                 #gpio-cells = <2>;
  98                         };
  99                 };
 100
 101                 i2c: i2c@900 {
 102                         compatible = "mediatek,mt7621-i2c";
 103                         reg = <0x900 0x100>;
 104
 105                         clocks = <&sysclock>;
 106
 107                         resets = <&rstctrl 16>;
 108                         reset-names = "i2c";
 109
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112
 113                         status = "disabled";
 114
 115                         pinctrl-names = "default";
 116                         pinctrl-0 = <&i2c_pins>;
 117                 };
 118
 119                 i2s: i2s@a00 {
 120                         compatible = "mediatek,mt7621-i2s";
 121                         reg = <0xa00 0x100>;
 122
 123                         clocks = <&sysclock>;
 124
 125                         resets = <&rstctrl 17>;
 126                         reset-names = "i2s";
 127
 128                         interrupt-parent = <&gic>;
 129                         interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
 130
 131                         txdma-req = <2>;
 132                         rxdma-req = <3>;
 133
 134                         dmas = <&gdma 4>,
 135                                 <&gdma 6>;
 136                         dma-names = "tx", "rx";
 137
 138                         status = "disabled";
 139                 };
 140
 141                 systick: systick@d00 {
 142                         compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
 143                         reg = <0xd00 0x10>;
 144
 145                         resets = <&rstctrl 28>;
 146                         reset-names = "intc";
 147
 148                         interrupt-parent = <&gic>;
 149                         interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
 150                 };
 151
 152                 memc: memc@5000 {
 153                         compatible = "mtk,mt7621-memc";
 154                         reg = <0x300 0x100>;
 155                 };
 156
 157                 cpc: cpc@1fbf0000 {
 158                         compatible = "mtk,mt7621-cpc";
 159                         reg = <0x1fbf0000 0x8000>;
 160                 };
 161
 162                 mc: mc@1fbf8000 {
 163                         compatible = "mtk,mt7621-mc";
 164                         reg = <0x1fbf8000 0x8000>;
 165                 };
 166
 167                 uartlite: uartlite@c00 {
 168                         compatible = "ns16550a";
 169                         reg = <0xc00 0x100>;
 170
 171                         clocks = <&sysclock>;
 172                         clock-frequency = <50000000>;
 173
 174                         interrupt-parent = <&gic>;
 175                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 176
 177                         reg-shift = <2>;
 178                         reg-io-width = <4>;
 179                         no-loopback-test;
 180                 };
 181
 182                 spi0: spi@b00 {
 183                         status = "disabled";
 184
 185                         compatible = "ralink,mt7621-spi";
 186                         reg = <0xb00 0x100>;
 187
 188                         clocks = <&sysclock>;
 189
 190                         resets = <&rstctrl 18>;
 191                         reset-names = "spi";
 192
 193                         #address-cells = <1>;
 194                         #size-cells = <0>;
 195
 196                         pinctrl-names = "default";
 197                         pinctrl-0 = <&spi_pins>;
 198                 };
 199
 200                 gdma: gdma@2800 {
 201                         compatible = "ralink,rt3883-gdma";
 202                         reg = <0x2800 0x800>;
 203
 204                         resets = <&rstctrl 14>;
 205                         reset-names = "dma";
 206
 207                         interrupt-parent = <&gic>;
 208                         interrupts = <0 13 4>;
 209
 210                         #dma-cells = <1>;
 211                         #dma-channels = <16>;
 212                         #dma-requests = <16>;
 213
 214                         status = "disabled";
 215                 };
 216
 217                 hsdma: hsdma@7000 {
 218                         compatible = "mediatek,mt7621-hsdma";
 219                         reg = <0x7000 0x1000>;
 220
 221                         resets = <&rstctrl 5>;
 222                         reset-names = "hsdma";
 223
 224                         interrupt-parent = <&gic>;
 225                         interrupts = <0 11 4>;
 226
 227                         #dma-cells = <1>;
 228                         #dma-channels = <1>;
 229                         #dma-requests = <1>;
 230
 231                         status = "disabled";
 232                 };
 233         };
 234
 235         pinctrl: pinctrl {
 236                 compatible = "ralink,rt2880-pinmux";
 237                 pinctrl-names = "default";
 238                 pinctrl-0 = <&state_default>;
 239
 240                 state_default: pinctrl0 {
 241                 };
 242
 243                 i2c_pins: i2c {
 244                         i2c {
 245                                 ralink,group = "i2c";
 246                                 ralink,function = "i2c";
 247                         };
 248                 };
 249
 250                 spi_pins: spi {
 251                         spi {
 252                                 ralink,group = "spi";
 253                                 ralink,function = "spi";
 254                         };
 255                 };
 256
 257                 uart1_pins: uart1 {
 258                         uart1 {
 259                                 ralink,group = "uart1";
 260                                 ralink,function = "uart1";
 261                         };
 262                 };
 263
 264                 uart2_pins: uart2 {
 265                         uart2 {
 266                                 ralink,group = "uart2";
 267                                 ralink,function = "uart2";
 268                         };
 269                 };
 270
 271                 uart3_pins: uart3 {
 272                         uart3 {
 273                                 ralink,group = "uart3";
 274                                 ralink,function = "uart3";
 275                         };
 276                 };
 277
 278                 rgmii1_pins: rgmii1 {
 279                         rgmii1 {
 280                                 ralink,group = "rgmii1";
 281                                 ralink,function = "rgmii1";
 282                         };
 283                 };
 284
 285                 rgmii2_pins: rgmii2 {
 286                         rgmii2 {
 287                                 ralink,group = "rgmii2";
 288                                 ralink,function = "rgmii2";
 289                         };
 290                 };
 291
 292                 mdio_pins: mdio {
 293                         mdio {
 294                                 ralink,group = "mdio";
 295                                 ralink,function = "mdio";
 296                         };
 297                 };
 298
 299                 pcie_pins: pcie {
 300                         pcie {
 301                                 ralink,group = "pcie";
 302                                 ralink,function = "pcie rst";
 303                         };
 304                 };
 305
 306                 nand_pins: nand {
 307                         spi-nand {
 308                                 ralink,group = "spi";
 309                                 ralink,function = "nand1";
 310                         };
 311
 312                         sdhci-nand {
 313                                 ralink,group = "sdhci";
 314                                 ralink,function = "nand2";
 315                         };
 316                 };
 317
 318                 sdhci_pins: sdhci {
 319                         sdhci {
 320                                 ralink,group = "sdhci";
 321                                 ralink,function = "sdhci";
 322                         };
 323                 };
 324         };
 325
 326         rstctrl: rstctrl {
 327                 compatible = "ralink,rt2880-reset";
 328                 #reset-cells = <1>;
 329         };
 330
 331         clkctrl: clkctrl {
 332                 compatible = "ralink,rt2880-clock";
 333                 #clock-cells = <1>;
 334         };
 335
 336         sdhci: sdhci@1E130000 {
 337                 status = "disabled";
 338
 339                 compatible = "ralink,mt7620-sdhci";
 340                 reg = <0x1E130000 0x4000>;
 341
 342                 interrupt-parent = <&gic>;
 343                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 344         };
 345
 346         xhci: xhci@1E1C0000 {
 347                 status = "okay";
 348
 349                 compatible = "mediatek,mt8173-xhci";
 350                 reg = <0x1e1c0000 0x1000
 351                        0x1e1d0700 0x0100>;
 352                 reg-names = "mac", "ippc";
 353
 354                 clocks = <&sysclock>;
 355                 clock-names = "sys_ck";
 356
 357                 interrupt-parent = <&gic>;
 358                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 359         };
 360
 361         gic: interrupt-controller@1fbc0000 {
 362                 compatible = "mti,gic";
 363                 reg = <0x1fbc0000 0x2000>;
 364
 365                 interrupt-controller;
 366                 #interrupt-cells = <3>;
 367
 368                 mti,reserved-cpu-vectors = <7>;
 369
 370                 timer {
 371                         compatible = "mti,gic-timer";
 372                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 373                         clocks = <&cpuclock>;
 374                 };
 375         };
 376
 377         nand: nand@1e003000 {
 378                 status = "disabled";
 379
 380                 compatible = "mtk,mt7621-nand";
 381                 bank-width = <2>;
 382                 reg = <0x1e003000 0x800
 383                         0x1e003800 0x800>;
 384         };
 385
 386         ethernet: ethernet@1e100000 {
 387                 compatible = "mediatek,mt7621-eth";
 388                 reg = <0x1e100000 0x10000>;
 389
 390                 #address-cells = <1>;
 391                 #size-cells = <1>;
 392
 393                 resets = <&rstctrl 6 &rstctrl 23>;
 394                 reset-names = "fe", "eth";
 395
 396                 interrupt-parent = <&gic>;
 397                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 398
 399                 mediatek,switch = <&gsw>;
 400
 401                 mdio-bus {
 402                         #address-cells = <1>;
 403                         #size-cells = <0>;
 404
 405                         phy1f: ethernet-phy@1f {
 406                                 reg = <0x1f>;
 407                                 phy-mode = "rgmii";
 408                         };
 409                 };
 410
 411                 hnat: hnat@0 {
 412                         compatible = "mediatek,mt7623-hnat";
 413                         reg = <0 0x10000>;
 414                         mtketh-ppd = "eth0";
 415                         mtketh-lan = "eth0";
 416                         mtketh-wan = "eth0";
 417                         resets = <&rstctrl 0>;
 418                         reset-names = "mtketh";
 419                 };
 420         };
 421
 422         gsw: gsw@1e110000 {
 423                 compatible = "mediatek,mt7621-gsw";
 424                 reg = <0x1e110000 0x8000>;
 425                 interrupt-parent = <&gic>;
 426                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 427         };
 428
 429         pcie: pcie@1e140000 {
 430                 compatible = "mediatek,mt7621-pci";
 431                 reg = <0x1e140000 0x100
 432                         0x1e142000 0x100>;
 433
 434                 #address-cells = <3>;
 435                 #size-cells = <2>;
 436
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&pcie_pins>;
 439
 440                 device_type = "pci";
 441
 442                 bus-range = <0 255>;
 443                 ranges = <
 444                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 445                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 446                 >;
 447
 448                 interrupt-parent = <&gic>;
 449                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 450                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 451                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 452
 453                 status = "disabled";
 454
 455                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 456                 reset-names = "pcie0", "pcie1", "pcie2";
 457                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 458                 clock-names = "pcie0", "pcie1", "pcie2";
 459
 460                 pcie0: pcie@0,0 {
 461                         reg = <0x0000 0 0 0 0>;
 462
 463                         #address-cells = <3>;
 464                         #size-cells = <2>;
 465
 466                         ranges;
 467                 };
 468
 469                 pcie1: pcie@1,0 {
 470                         reg = <0x0800 0 0 0 0>;
 471
 472                         #address-cells = <3>;
 473                         #size-cells = <2>;
 474
 475                         ranges;
 476                 };
 477
 478                 pcie2: pcie@2,0 {
 479                         reg = <0x1000 0 0 0 0>;
 480
 481                         #address-cells = <3>;
 482                         #size-cells = <2>;
 483
 484                         ranges;
 485                 };
 486         };
 487 };