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ramips: pci: sync with staging driver
[openwrt/staging/wigyori.git] / target / linux / ramips / files-4.14 / arch / mips / pci / pci-mt7621.c
1 /**************************************************************************
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
5 *
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 *
28 *
29 **************************************************************************
30 * May 2007 Bruce Chang
31 * Initial Release
32 *
33 * May 2009 Bruce Chang
34 * support RT2880/RT3883 PCIe
35 *
36 * May 2011 Bruce Chang
37 * support RT6855/MT7620 PCIe
38 *
39 **************************************************************************
40 */
41
42 #include <linux/types.h>
43 #include <linux/pci.h>
44 #include <linux/kernel.h>
45 #include <linux/slab.h>
46 #include <linux/version.h>
47 #include <asm/pci.h>
48 #include <asm/io.h>
49 #include <asm/mips-cm.h>
50 #include <linux/init.h>
51 #include <linux/module.h>
52 #include <linux/delay.h>
53 #include <linux/of.h>
54 #include <linux/of_pci.h>
55 #include <linux/platform_device.h>
56
57 #include <ralink_regs.h>
58
59 /*
60 * These functions and structures provide the BIOS scan and mapping of the PCI
61 * devices.
62 */
63
64 #define RALINK_PCIE0_CLK_EN (1<<24)
65 #define RALINK_PCIE1_CLK_EN (1<<25)
66 #define RALINK_PCIE2_CLK_EN (1<<26)
67
68 #define RALINK_PCI_CONFIG_ADDR 0x20
69 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
70 #define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
71 #define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
72 #define RALINK_PCIE0_RST (1<<24)
73 #define RALINK_PCIE1_RST (1<<25)
74 #define RALINK_PCIE2_RST (1<<26)
75 #define RALINK_SYSCTL_BASE 0xBE000000
76
77 #define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
78 #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
79 #define RALINK_PCI_BASE 0xBE140000
80
81 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
82 #define RT6855_PCIE0_OFFSET 0x2000
83 #define RT6855_PCIE1_OFFSET 0x3000
84 #define RT6855_PCIE2_OFFSET 0x4000
85
86 #define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
87 #define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
88 #define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
89 #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
90 #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
91 #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
92 #define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
93 #define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
94
95 #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
96 #define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
97 #define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
98 #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
99 #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
100 #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
101 #define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
102 #define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
103
104 #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
105 #define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
106 #define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
107 #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
108 #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
109 #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
110 #define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
111 #define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
112
113 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
114 #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
115
116 #define MV_WRITE(ofs, data) \
117 *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
118 #define MV_READ(ofs, data) \
119 *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
120 #define MV_READ_DATA(ofs) \
121 le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
122
123 #define MV_WRITE_16(ofs, data) \
124 *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
125 #define MV_READ_16(ofs, data) \
126 *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
127
128 #define MV_WRITE_8(ofs, data) \
129 *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
130 #define MV_READ_8(ofs, data) \
131 *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
132
133 #define RALINK_PCI_MM_MAP_BASE 0x60000000
134 #define RALINK_PCI_IO_MAP_BASE 0x1e160000
135
136 #define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
137
138 #define ASSERT_SYSRST_PCIE(val) \
139 do { \
140 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
141 RALINK_RSTCTRL |= val; \
142 else \
143 RALINK_RSTCTRL &= ~val; \
144 } while(0)
145 #define DEASSERT_SYSRST_PCIE(val) \
146 do { \
147 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
148 RALINK_RSTCTRL &= ~val; \
149 else \
150 RALINK_RSTCTRL |= val; \
151 } while(0)
152 #define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
153 #define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
154 #define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
155 #define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
156 #define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
157 #define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
158 #define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
159 #define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
160 //RALINK_SYSCFG1 bit
161 #define RALINK_PCI_HOST_MODE_EN (1<<7)
162 #define RALINK_PCIE_RC_MODE_EN (1<<8)
163 //RALINK_RSTCTRL bit
164 #define RALINK_PCIE_RST (1<<23)
165 #define RALINK_PCI_RST (1<<24)
166 //RALINK_CLKCFG1 bit
167 #define RALINK_PCI_CLK_EN (1<<19)
168 #define RALINK_PCIE_CLK_EN (1<<21)
169 //RALINK_GPIOMODE bit
170 #define PCI_SLOTx2 (1<<11)
171 #define PCI_SLOTx1 (2<<11)
172 //MTK PCIE PLL bit
173 #define PDRV_SW_SET (1<<31)
174 #define LC_CKDRVPD_ (1<<19)
175
176 #define MEMORY_BASE 0x0
177 static int pcie_link_status = 0;
178
179 #define PCI_ACCESS_READ_1 0
180 #define PCI_ACCESS_READ_2 1
181 #define PCI_ACCESS_READ_4 2
182 #define PCI_ACCESS_WRITE_1 3
183 #define PCI_ACCESS_WRITE_2 4
184 #define PCI_ACCESS_WRITE_4 5
185
186 static int config_access(unsigned char access_type, struct pci_bus *bus,
187 unsigned int devfn, unsigned int where, u32 * data)
188 {
189 unsigned int slot = PCI_SLOT(devfn);
190 u8 func = PCI_FUNC(devfn);
191 uint32_t address_reg, data_reg;
192 unsigned int address;
193
194 address_reg = RALINK_PCI_CONFIG_ADDR;
195 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
196
197 address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
198 MV_WRITE(address_reg, address);
199
200 switch(access_type) {
201 case PCI_ACCESS_WRITE_1:
202 MV_WRITE_8(data_reg+(where&0x3), *data);
203 break;
204 case PCI_ACCESS_WRITE_2:
205 MV_WRITE_16(data_reg+(where&0x3), *data);
206 break;
207 case PCI_ACCESS_WRITE_4:
208 MV_WRITE(data_reg, *data);
209 break;
210 case PCI_ACCESS_READ_1:
211 MV_READ_8( data_reg+(where&0x3), data);
212 break;
213 case PCI_ACCESS_READ_2:
214 MV_READ_16(data_reg+(where&0x3), data);
215 break;
216 case PCI_ACCESS_READ_4:
217 MV_READ(data_reg, data);
218 break;
219 default:
220 printk("no specify access type\n");
221 break;
222 }
223 return 0;
224 }
225
226 static int
227 read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
228 {
229 return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
230 }
231
232 static int
233 read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
234 {
235 return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
236 }
237
238 static int
239 read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
240 {
241 return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
242 }
243
244 static int
245 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
246 {
247 if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
248 return -1;
249
250 return PCIBIOS_SUCCESSFUL;
251 }
252
253 static int
254 write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
255 {
256 if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
257 return -1;
258
259 return PCIBIOS_SUCCESSFUL;
260 }
261
262 static int
263 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
264 {
265 if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
266 return -1;
267
268 return PCIBIOS_SUCCESSFUL;
269 }
270
271 static int
272 pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
273 {
274 switch (size) {
275 case 1:
276 return read_config_byte(bus, devfn, where, (u8 *) val);
277 case 2:
278 return read_config_word(bus, devfn, where, (u16 *) val);
279 default:
280 return read_config_dword(bus, devfn, where, val);
281 }
282 }
283
284 static int
285 pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
286 {
287 switch (size) {
288 case 1:
289 return write_config_byte(bus, devfn, where, (u8) val);
290 case 2:
291 return write_config_word(bus, devfn, where, (u16) val);
292 default:
293 return write_config_dword(bus, devfn, where, val);
294 }
295 }
296
297 struct pci_ops mt7621_pci_ops= {
298 .read = pci_config_read,
299 .write = pci_config_write,
300 };
301
302 static struct resource mt7621_res_pci_mem1;
303 static struct resource mt7621_res_pci_io1;
304 static struct pci_controller mt7621_controller = {
305 .pci_ops = &mt7621_pci_ops,
306 .mem_resource = &mt7621_res_pci_mem1,
307 .io_resource = &mt7621_res_pci_io1,
308 };
309
310 static void
311 read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
312 {
313 unsigned int address_reg, data_reg, address;
314
315 address_reg = RALINK_PCI_CONFIG_ADDR;
316 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
317 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
318 MV_WRITE(address_reg, address);
319 MV_READ(data_reg, val);
320 return;
321 }
322
323 static void
324 write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
325 {
326 unsigned int address_reg, data_reg, address;
327
328 address_reg = RALINK_PCI_CONFIG_ADDR;
329 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
330 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
331 MV_WRITE(address_reg, address);
332 MV_WRITE(data_reg, val);
333 return;
334 }
335
336 int
337 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
338 {
339 u16 cmd;
340 u32 val;
341 int irq;
342
343 if (dev->bus->number == 0) {
344 write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
345 read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
346 printk("BAR0 at slot %d = %x\n", slot, val);
347 }
348
349 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
350 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
351 pci_read_config_word(dev, PCI_COMMAND, &cmd);
352 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
353 pci_write_config_word(dev, PCI_COMMAND, cmd);
354
355 irq = of_irq_parse_and_map_pci(dev, slot, pin);
356
357 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
358 return irq;
359 }
360
361 void
362 set_pcie_phy(u32 *addr, int start_b, int bits, int val)
363 {
364 *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
365 *(unsigned int *)(addr) |= val << start_b;
366 }
367
368 void
369 bypass_pipe_rst(void)
370 {
371 /* PCIe Port 0 */
372 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
373 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
374 /* PCIe Port 1 */
375 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
376 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
377 /* PCIe Port 2 */
378 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
379 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
380 }
381
382 void
383 set_phy_for_ssc(void)
384 {
385 unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
386
387 reg = (reg >> 6) & 0x7;
388 /* Set PCIe Port0 & Port1 PHY to disable SSC */
389 /* Debug Xtal Type */
390 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
391 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
392 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
393 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
394 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
395 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
396 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
397 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
398 printk("***** Xtal 40MHz *****\n");
399 } else { // 25MHz | 20MHz Xtal
400 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
401 if (reg >= 6) {
402 printk("***** Xtal 25MHz *****\n");
403 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
404 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
405 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
406 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
407 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
408 } else {
409 printk("***** Xtal 20MHz *****\n");
410 }
411 }
412 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
413 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
414 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
415 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
416 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
417 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
418 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
419 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
420 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
421 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
422 }
423 /* Enable PHY and disable force mode */
424 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
425 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
426 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
427 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
428
429 /* Set PCIe Port2 PHY to disable SSC */
430 /* Debug Xtal Type */
431 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
432 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
433 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
434 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
435 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
436 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
437 } else { // 25MHz | 20MHz Xtal
438 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
439 if (reg >= 6) { // 25MHz Xtal
440 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
441 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
442 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
443 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
444 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
445 }
446 }
447 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
448 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
449 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
450 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
451 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
452 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
453 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
454 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
455 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
456 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
457 }
458 /* Enable PHY and disable force mode */
459 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
460 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
461 }
462
463 void setup_cm_memory_region(struct resource *mem_resource)
464 {
465 resource_size_t mask;
466 if (mips_cps_numiocu(0)) {
467 /* FIXME: hardware doesn't accept mask values with 1s after
468 * 0s (e.g. 0xffef), so it would be great to warn if that's
469 * about to happen */
470 mask = ~(mem_resource->end - mem_resource->start);
471
472 write_gcr_reg1_base(mem_resource->start);
473 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
474 printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
475 (unsigned long long)read_gcr_reg1_base(),
476 (unsigned long long)read_gcr_reg1_mask());
477 }
478 }
479
480 static int mt7621_pci_probe(struct platform_device *pdev)
481 {
482 unsigned long val = 0;
483
484 iomem_resource.start = 0;
485 iomem_resource.end= ~0;
486 ioport_resource.start= 0;
487 ioport_resource.end = ~0;
488
489 val = RALINK_PCIE0_RST;
490 val |= RALINK_PCIE1_RST;
491 val |= RALINK_PCIE2_RST;
492
493 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
494
495 *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
496 *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
497 mdelay(100);
498 *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
499 mdelay(100);
500 *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
501
502 mdelay(100);
503
504 val = RALINK_PCIE0_RST;
505 val |= RALINK_PCIE1_RST;
506 val |= RALINK_PCIE2_RST;
507
508 DEASSERT_SYSRST_PCIE(val);
509
510 if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
511 bypass_pipe_rst();
512 set_phy_for_ssc();
513
514 read_config(0, 0, 0, 0x70c, &val);
515 printk("Port 0 N_FTS = %x\n", (unsigned int)val);
516
517 read_config(0, 1, 0, 0x70c, &val);
518 printk("Port 1 N_FTS = %x\n", (unsigned int)val);
519
520 read_config(0, 2, 0, 0x70c, &val);
521 printk("Port 2 N_FTS = %x\n", (unsigned int)val);
522
523 RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
524 RALINK_SYSCFG1 &= ~(0x30);
525 RALINK_SYSCFG1 |= (2<<4);
526 RALINK_PCIE_CLK_GEN &= 0x7fffffff;
527 RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
528 RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
529 RALINK_PCIE_CLK_GEN |= 0x80000000;
530 mdelay(50);
531 RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
532
533 /* Use GPIO control instead of PERST_N */
534 *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
535 mdelay(1000);
536
537 if(( RALINK_PCI0_STATUS & 0x1) == 0)
538 {
539 printk("PCIE0 no card, disable it(RST&CLK)\n");
540 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
541 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
542 pcie_link_status &= ~(1<<0);
543 } else {
544 pcie_link_status |= 1<<0;
545 RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
546 }
547
548 if(( RALINK_PCI1_STATUS & 0x1) == 0)
549 {
550 printk("PCIE1 no card, disable it(RST&CLK)\n");
551 ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
552 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
553 pcie_link_status &= ~(1<<1);
554 } else {
555 pcie_link_status |= 1<<1;
556 RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
557 }
558
559 if (( RALINK_PCI2_STATUS & 0x1) == 0) {
560 printk("PCIE2 no card, disable it(RST&CLK)\n");
561 ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
562 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
563 pcie_link_status &= ~(1<<2);
564 } else {
565 pcie_link_status |= 1<<2;
566 RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
567 }
568
569 if (pcie_link_status == 0)
570 return 0;
571
572 /*
573 pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
574 3'b000 x x x
575 3'b001 x x 0
576 3'b010 x 0 x
577 3'b011 x 1 0
578 3'b100 0 x x
579 3'b101 1 x 0
580 3'b110 1 0 x
581 3'b111 2 1 0
582 */
583 switch(pcie_link_status) {
584 case 2:
585 RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
586 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
587 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
588 break;
589 case 4:
590 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
591 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
592 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
593 RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
594 break;
595 case 5:
596 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
597 RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
598 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
599 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
600 break;
601 case 6:
602 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
603 RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
604 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
605 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
606 break;
607 }
608
609 /*
610 ioport_resource.start = mt7621_res_pci_io1.start;
611 ioport_resource.end = mt7621_res_pci_io1.end;
612 */
613
614 RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
615 RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
616
617 //PCIe0
618 if((pcie_link_status & 0x1) != 0) {
619 RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
620 RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
621 RALINK_PCI0_CLASS = 0x06040001;
622 printk("PCIE0 enabled\n");
623 }
624
625 //PCIe1
626 if ((pcie_link_status & 0x2) != 0) {
627 RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
628 RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
629 RALINK_PCI1_CLASS = 0x06040001;
630 printk("PCIE1 enabled\n");
631 }
632
633 //PCIe2
634 if ((pcie_link_status & 0x4) != 0) {
635 RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
636 RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
637 RALINK_PCI2_CLASS = 0x06040001;
638 printk("PCIE2 enabled\n");
639 }
640
641 switch(pcie_link_status) {
642 case 7:
643 read_config(0, 2, 0, 0x4, &val);
644 write_config(0, 2, 0, 0x4, val|0x4);
645 read_config(0, 2, 0, 0x70c, &val);
646 val &= ~(0xff)<<8;
647 val |= 0x50<<8;
648 write_config(0, 2, 0, 0x70c, val);
649 case 3:
650 case 5:
651 case 6:
652 read_config(0, 1, 0, 0x4, &val);
653 write_config(0, 1, 0, 0x4, val|0x4);
654 read_config(0, 1, 0, 0x70c, &val);
655 val &= ~(0xff)<<8;
656 val |= 0x50<<8;
657 write_config(0, 1, 0, 0x70c, val);
658 default:
659 read_config(0, 0, 0, 0x4, &val);
660 write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
661 read_config(0, 0, 0, 0x70c, &val);
662 val &= ~(0xff)<<8;
663 val |= 0x50<<8;
664 write_config(0, 0, 0, 0x70c, val);
665 }
666
667 pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
668 setup_cm_memory_region(mt7621_controller.mem_resource);
669 register_pci_controller(&mt7621_controller);
670 return 0;
671
672 }
673
674 int pcibios_plat_dev_init(struct pci_dev *dev)
675 {
676 return 0;
677 }
678
679 static const struct of_device_id mt7621_pci_ids[] = {
680 { .compatible = "mediatek,mt7621-pci" },
681 {},
682 };
683 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
684
685 static struct platform_driver mt7621_pci_driver = {
686 .probe = mt7621_pci_probe,
687 .driver = {
688 .name = "mt7621-pci",
689 .of_match_table = of_match_ptr(mt7621_pci_ids),
690 },
691 };
692
693 static int __init mt7621_pci_init(void)
694 {
695 return platform_driver_register(&mt7621_pci_driver);
696 }
697
698 arch_initcall(mt7621_pci_init);
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