target/linux/ramips/patches-4.14/0043-spi-add-mt7621-support.patch

   1 From cbd66c626e16743b05af807ad48012c0a097b9fb Mon Sep 17 00:00:00 2001
   2 From: Stefan Roese <sr@denx.de>
   3 Date: Mon, 25 Mar 2019 09:29:25 +0100
   4 Subject: [PATCH] spi: mt7621: Move SPI driver out of staging
   5
   6 This patch moves the MT7621 SPI driver, which is used on some Ralink /
   7 MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to
   8 the source code are done in this patch.
   9
  10 This driver version was tested successfully on an MT7688 based platform
  11 with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so
  12 far).
  13
  14 This patch also documents the devicetree bindings for the MT7621 SPI
  15 device driver.
  16
  17 Signed-off-by: Stefan Roese <sr@denx.de>
  18 Cc: Rob Herring <robh@kernel.org>
  19 Cc: Mark Brown <broonie@kernel.org>
  20 Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  21 Cc: NeilBrown <neil@brown.name>
  22 Cc: Sankalp Negi <sankalpnegi2310@gmail.com>
  23 Cc: Chuanhong Guo <gch981213@gmail.com>
  24 Cc: John Crispin <john@phrozen.org>
  25 Cc: Armando Miraglia <arma2ff0@gmail.com>
  26 Signed-off-by: Mark Brown <broonie@kernel.org>
  27 ---
  28  .../devicetree/bindings/spi/spi-mt7621.txt    | 26 ++++++
  29  drivers/spi/Kconfig                           |  6 ++
  30  drivers/spi/Makefile                          |  1 +
  31  .../{staging/mt7621-spi => spi}/spi-mt7621.c  | 83 +++++++++----------
  32  drivers/staging/Kconfig                       |  2 -
  33  drivers/staging/Makefile                      |  1 -
  34  drivers/staging/mt7621-spi/Kconfig            |  6 --
  35  drivers/staging/mt7621-spi/Makefile           |  1 -
  36  drivers/staging/mt7621-spi/TODO               |  5 --
  37  9 files changed, 74 insertions(+), 57 deletions(-)
  38  create mode 100644 Documentation/devicetree/bindings/spi/spi-mt7621.txt
  39  rename drivers/{staging/mt7621-spi => spi}/spi-mt7621.c (88%)
  40  delete mode 100644 drivers/staging/mt7621-spi/Kconfig
  41  delete mode 100644 drivers/staging/mt7621-spi/Makefile
  42  delete mode 100644 drivers/staging/mt7621-spi/TODO
  43
  44 --- a/drivers/spi/Kconfig
  45 +++ b/drivers/spi/Kconfig
  46 @@ -569,6 +569,12 @@ config SPI_RT2880
  47         help
  48           This selects a driver for the Ralink RT288x/RT305x SPI Controller.
  49
  50 +config SPI_MT7621
  51 +       tristate "MediaTek MT7621 SPI Controller"
  52 +       depends on RALINK
  53 +       help
  54 +         This selects a driver for the MediaTek MT7621 SPI Controller.
  55 +
  56  config SPI_S3C24XX
  57         tristate "Samsung S3C24XX series SPI"
  58         depends on ARCH_S3C24XX
  59 --- a/drivers/spi/Makefile
  60 +++ b/drivers/spi/Makefile
  61 @@ -60,6 +60,7 @@ obj-$(CONFIG_SPI_MPC512x_PSC)         += spi-mp
  62  obj-$(CONFIG_SPI_MPC52xx_PSC)          += spi-mpc52xx-psc.o
  63  obj-$(CONFIG_SPI_MPC52xx)              += spi-mpc52xx.o
  64  obj-$(CONFIG_SPI_MT65XX)                += spi-mt65xx.o
  65 +obj-$(CONFIG_SPI_MT7621)               += spi-mt7621.o
  66  obj-$(CONFIG_SPI_MXS)                  += spi-mxs.o
  67  obj-$(CONFIG_SPI_NUC900)               += spi-nuc900.o
  68  obj-$(CONFIG_SPI_OC_TINY)              += spi-oc-tiny.o
  69 --- /dev/null
  70 +++ b/drivers/spi/spi-mt7621.c
  71 @@ -0,0 +1,416 @@
  72 +// SPDX-License-Identifier: GPL-2.0
  73 +//
  74 +// spi-mt7621.c -- MediaTek MT7621 SPI controller driver
  75 +//
  76 +// Copyright (C) 2011 Sergiy <piratfm@gmail.com>
  77 +// Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
  78 +// Copyright (C) 2014-2015 Felix Fietkau <nbd@nbd.name>
  79 +//
  80 +// Some parts are based on spi-orion.c:
  81 +//   Author: Shadi Ammouri <shadi@marvell.com>
  82 +//   Copyright (C) 2007-2008 Marvell Ltd.
  83 +
  84 +#include <linux/clk.h>
  85 +#include <linux/delay.h>
  86 +#include <linux/io.h>
  87 +#include <linux/module.h>
  88 +#include <linux/of_device.h>
  89 +#include <linux/reset.h>
  90 +#include <linux/spi/spi.h>
  91 +
  92 +#define DRIVER_NAME            "spi-mt7621"
  93 +
  94 +/* in usec */
  95 +#define RALINK_SPI_WAIT_MAX_LOOP 2000
  96 +
  97 +/* SPISTAT register bit field */
  98 +#define SPISTAT_BUSY           BIT(0)
  99 +
 100 +#define MT7621_SPI_TRANS       0x00
 101 +#define SPITRANS_BUSY          BIT(16)
 102 +
 103 +#define MT7621_SPI_OPCODE      0x04
 104 +#define MT7621_SPI_DATA0       0x08
 105 +#define MT7621_SPI_DATA4       0x18
 106 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
 107 +#define SPI_CTL_START          BIT(8)
 108 +
 109 +#define MT7621_SPI_MASTER      0x28
 110 +#define MASTER_MORE_BUFMODE    BIT(2)
 111 +#define MASTER_FULL_DUPLEX     BIT(10)
 112 +#define MASTER_RS_CLK_SEL      GENMASK(27, 16)
 113 +#define MASTER_RS_CLK_SEL_SHIFT        16
 114 +#define MASTER_RS_SLAVE_SEL    GENMASK(31, 29)
 115 +
 116 +#define MT7621_SPI_MOREBUF     0x2c
 117 +#define MT7621_SPI_POLAR       0x38
 118 +#define MT7621_SPI_SPACE       0x3c
 119 +
 120 +#define MT7621_CPHA            BIT(5)
 121 +#define MT7621_CPOL            BIT(4)
 122 +#define MT7621_LSB_FIRST       BIT(3)
 123 +
 124 +struct mt7621_spi {
 125 +       struct spi_controller   *master;
 126 +       void __iomem            *base;
 127 +       unsigned int            sys_freq;
 128 +       unsigned int            speed;
 129 +       struct clk              *clk;
 130 +       int                     pending_write;
 131 +};
 132 +
 133 +static inline struct mt7621_spi *spidev_to_mt7621_spi(struct spi_device *spi)
 134 +{
 135 +       return spi_controller_get_devdata(spi->master);
 136 +}
 137 +
 138 +static inline u32 mt7621_spi_read(struct mt7621_spi *rs, u32 reg)
 139 +{
 140 +       return ioread32(rs->base + reg);
 141 +}
 142 +
 143 +static inline void mt7621_spi_write(struct mt7621_spi *rs, u32 reg, u32 val)
 144 +{
 145 +       iowrite32(val, rs->base + reg);
 146 +}
 147 +
 148 +static void mt7621_spi_set_cs(struct spi_device *spi, int enable)
 149 +{
 150 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 151 +       int cs = spi->chip_select;
 152 +       u32 polar = 0;
 153 +       u32 master;
 154 +
 155 +       /*
 156 +        * Select SPI device 7, enable "more buffer mode" and disable
 157 +        * full-duplex (only half-duplex really works on this chip
 158 +        * reliably)
 159 +        */
 160 +       master = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 161 +       master |= MASTER_RS_SLAVE_SEL | MASTER_MORE_BUFMODE;
 162 +       master &= ~MASTER_FULL_DUPLEX;
 163 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, master);
 164 +
 165 +       rs->pending_write = 0;
 166 +
 167 +       if (enable)
 168 +               polar = BIT(cs);
 169 +       mt7621_spi_write(rs, MT7621_SPI_POLAR, polar);
 170 +}
 171 +
 172 +static int mt7621_spi_prepare(struct spi_device *spi, unsigned int speed)
 173 +{
 174 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 175 +       u32 rate;
 176 +       u32 reg;
 177 +
 178 +       dev_dbg(&spi->dev, "speed:%u\n", speed);
 179 +
 180 +       rate = DIV_ROUND_UP(rs->sys_freq, speed);
 181 +       dev_dbg(&spi->dev, "rate-1:%u\n", rate);
 182 +
 183 +       if (rate > 4097)
 184 +               return -EINVAL;
 185 +
 186 +       if (rate < 2)
 187 +               rate = 2;
 188 +
 189 +       reg = mt7621_spi_read(rs, MT7621_SPI_MASTER);
 190 +       reg &= ~MASTER_RS_CLK_SEL;
 191 +       reg |= (rate - 2) << MASTER_RS_CLK_SEL_SHIFT;
 192 +       rs->speed = speed;
 193 +
 194 +       reg &= ~MT7621_LSB_FIRST;
 195 +       if (spi->mode & SPI_LSB_FIRST)
 196 +               reg |= MT7621_LSB_FIRST;
 197 +
 198 +       /*
 199 +        * This SPI controller seems to be tested on SPI flash only and some
 200 +        * bits are swizzled under other SPI modes probably due to incorrect
 201 +        * wiring inside the silicon. Only mode 0 works correctly.
 202 +        */
 203 +       reg &= ~(MT7621_CPHA | MT7621_CPOL);
 204 +
 205 +       mt7621_spi_write(rs, MT7621_SPI_MASTER, reg);
 206 +
 207 +       return 0;
 208 +}
 209 +
 210 +static inline int mt7621_spi_wait_till_ready(struct mt7621_spi *rs)
 211 +{
 212 +       int i;
 213 +
 214 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 215 +               u32 status;
 216 +
 217 +               status = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 218 +               if ((status & SPITRANS_BUSY) == 0)
 219 +                       return 0;
 220 +               cpu_relax();
 221 +               udelay(1);
 222 +       }
 223 +
 224 +       return -ETIMEDOUT;
 225 +}
 226 +
 227 +static void mt7621_spi_read_half_duplex(struct mt7621_spi *rs,
 228 +                                       int rx_len, u8 *buf)
 229 +{
 230 +       int tx_len;
 231 +
 232 +       /*
 233 +        * Combine with any pending write, and perform one or more half-duplex
 234 +        * transactions reading 'len' bytes. Data to be written is already in
 235 +        * MT7621_SPI_DATA.
 236 +        */
 237 +       tx_len = rs->pending_write;
 238 +       rs->pending_write = 0;
 239 +
 240 +       while (rx_len || tx_len) {
 241 +               int i;
 242 +               u32 val = (min(tx_len, 4) * 8) << 24;
 243 +               int rx = min(rx_len, 32);
 244 +
 245 +               if (tx_len > 4)
 246 +                       val |= (tx_len - 4) * 8;
 247 +               val |= (rx * 8) << 12;
 248 +               mt7621_spi_write(rs, MT7621_SPI_MOREBUF, val);
 249 +
 250 +               tx_len = 0;
 251 +
 252 +               val = mt7621_spi_read(rs, MT7621_SPI_TRANS);
 253 +               val |= SPI_CTL_START;
 254 +               mt7621_spi_write(rs, MT7621_SPI_TRANS, val);
 255 +
 256 +               mt7621_spi_wait_till_ready(rs);
 257 +
 258 +               for (i = 0; i < rx; i++) {
 259 +                       if ((i % 4) == 0)
 260 +                               val = mt7621_spi_read(rs, MT7621_SPI_DATA0 + i);
 261 +                       *buf++ = val & 0xff;
 262 +                       val >>= 8;
 263 +               }
 264 +
 265 +               rx_len -= i;
 266 +       }
 267 +}
 268 +
 269 +static inline void mt7621_spi_flush(struct mt7621_spi *rs)
 270 +{
 271 +       mt7621_spi_read_half_duplex(rs, 0, NULL);
 272 +}
 273 +
 274 +static void mt7621_spi_write_half_duplex(struct mt7621_spi *rs,
 275 +                                        int tx_len, const u8 *buf)
 276 +{
 277 +       int len = rs->pending_write;
 278 +       int val = 0;
 279 +
 280 +       if (len & 3) {
 281 +               val = mt7621_spi_read(rs, MT7621_SPI_OPCODE + (len & ~3));
 282 +               if (len < 4) {
 283 +                       val <<= (4 - len) * 8;
 284 +                       val = swab32(val);
 285 +               }
 286 +       }
 287 +
 288 +       while (tx_len > 0) {
 289 +               if (len >= 36) {
 290 +                       rs->pending_write = len;
 291 +                       mt7621_spi_flush(rs);
 292 +                       len = 0;
 293 +               }
 294 +
 295 +               val |= *buf++ << (8 * (len & 3));
 296 +               len++;
 297 +               if ((len & 3) == 0) {
 298 +                       if (len == 4)
 299 +                               /* The byte-order of the opcode is weird! */
 300 +                               val = swab32(val);
 301 +                       mt7621_spi_write(rs, MT7621_SPI_OPCODE + len - 4, val);
 302 +                       val = 0;
 303 +               }
 304 +               tx_len -= 1;
 305 +       }
 306 +
 307 +       if (len & 3) {
 308 +               if (len < 4) {
 309 +                       val = swab32(val);
 310 +                       val >>= (4 - len) * 8;
 311 +               }
 312 +               mt7621_spi_write(rs, MT7621_SPI_OPCODE + (len & ~3), val);
 313 +       }
 314 +
 315 +       rs->pending_write = len;
 316 +}
 317 +
 318 +static int mt7621_spi_transfer_one_message(struct spi_controller *master,
 319 +                                          struct spi_message *m)
 320 +{
 321 +       struct mt7621_spi *rs = spi_controller_get_devdata(master);
 322 +       struct spi_device *spi = m->spi;
 323 +       unsigned int speed = spi->max_speed_hz;
 324 +       struct spi_transfer *t = NULL;
 325 +       int status = 0;
 326 +
 327 +       mt7621_spi_wait_till_ready(rs);
 328 +
 329 +       list_for_each_entry(t, &m->transfers, transfer_list)
 330 +               if (t->speed_hz < speed)
 331 +                       speed = t->speed_hz;
 332 +
 333 +       if (mt7621_spi_prepare(spi, speed)) {
 334 +               status = -EIO;
 335 +               goto msg_done;
 336 +       }
 337 +
 338 +       /* Assert CS */
 339 +       mt7621_spi_set_cs(spi, 1);
 340 +
 341 +       m->actual_length = 0;
 342 +       list_for_each_entry(t, &m->transfers, transfer_list) {
 343 +               if ((t->rx_buf) && (t->tx_buf)) {
 344 +                       /*
 345 +                        * This controller will shift some extra data out
 346 +                        * of spi_opcode if (mosi_bit_cnt > 0) &&
 347 +                        * (cmd_bit_cnt == 0). So the claimed full-duplex
 348 +                        * support is broken since we have no way to read
 349 +                        * the MISO value during that bit.
 350 +                        */
 351 +                       status = -EIO;
 352 +                       goto msg_done;
 353 +               } else if (t->rx_buf) {
 354 +                       mt7621_spi_read_half_duplex(rs, t->len, t->rx_buf);
 355 +               } else if (t->tx_buf) {
 356 +                       mt7621_spi_write_half_duplex(rs, t->len, t->tx_buf);
 357 +               }
 358 +               m->actual_length += t->len;
 359 +       }
 360 +
 361 +       /* Flush data and deassert CS */
 362 +       mt7621_spi_flush(rs);
 363 +       mt7621_spi_set_cs(spi, 0);
 364 +
 365 +msg_done:
 366 +       m->status = status;
 367 +       spi_finalize_current_message(master);
 368 +
 369 +       return 0;
 370 +}
 371 +
 372 +static int mt7621_spi_setup(struct spi_device *spi)
 373 +{
 374 +       struct mt7621_spi *rs = spidev_to_mt7621_spi(spi);
 375 +
 376 +       if ((spi->max_speed_hz == 0) ||
 377 +           (spi->max_speed_hz > (rs->sys_freq / 2)))
 378 +               spi->max_speed_hz = (rs->sys_freq / 2);
 379 +
 380 +       if (spi->max_speed_hz < (rs->sys_freq / 4097)) {
 381 +               dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
 382 +                       spi->max_speed_hz);
 383 +               return -EINVAL;
 384 +       }
 385 +
 386 +       return 0;
 387 +}
 388 +
 389 +static const struct of_device_id mt7621_spi_match[] = {
 390 +       { .compatible = "ralink,mt7621-spi" },
 391 +       {},
 392 +};
 393 +MODULE_DEVICE_TABLE(of, mt7621_spi_match);
 394 +
 395 +static int mt7621_spi_probe(struct platform_device *pdev)
 396 +{
 397 +       const struct of_device_id *match;
 398 +       struct spi_controller *master;
 399 +       struct mt7621_spi *rs;
 400 +       void __iomem *base;
 401 +       struct resource *r;
 402 +       int status = 0;
 403 +       struct clk *clk;
 404 +       int ret;
 405 +
 406 +       match = of_match_device(mt7621_spi_match, &pdev->dev);
 407 +       if (!match)
 408 +               return -EINVAL;
 409 +
 410 +       r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 411 +       base = devm_ioremap_resource(&pdev->dev, r);
 412 +       if (IS_ERR(base))
 413 +               return PTR_ERR(base);
 414 +
 415 +       clk = devm_clk_get(&pdev->dev, NULL);
 416 +       if (IS_ERR(clk)) {
 417 +               dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
 418 +                       status);
 419 +               return PTR_ERR(clk);
 420 +       }
 421 +
 422 +       status = clk_prepare_enable(clk);
 423 +       if (status)
 424 +               return status;
 425 +
 426 +       master = spi_alloc_master(&pdev->dev, sizeof(*rs));
 427 +       if (!master) {
 428 +               dev_info(&pdev->dev, "master allocation failed\n");
 429 +               return -ENOMEM;
 430 +       }
 431 +
 432 +       master->mode_bits = SPI_LSB_FIRST;
 433 +       master->flags = SPI_CONTROLLER_HALF_DUPLEX;
 434 +       master->setup = mt7621_spi_setup;
 435 +       master->transfer_one_message = mt7621_spi_transfer_one_message;
 436 +       master->bits_per_word_mask = SPI_BPW_MASK(8);
 437 +       master->dev.of_node = pdev->dev.of_node;
 438 +       master->num_chipselect = 2;
 439 +
 440 +       dev_set_drvdata(&pdev->dev, master);
 441 +
 442 +       rs = spi_controller_get_devdata(master);
 443 +       rs->base = base;
 444 +       rs->clk = clk;
 445 +       rs->master = master;
 446 +       rs->sys_freq = clk_get_rate(rs->clk);
 447 +       rs->pending_write = 0;
 448 +       dev_info(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 449 +
 450 +       ret = device_reset(&pdev->dev);
 451 +       if (ret) {
 452 +               dev_err(&pdev->dev, "SPI reset failed!\n");
 453 +               return ret;
 454 +       }
 455 +
 456 +       return devm_spi_register_controller(&pdev->dev, master);
 457 +}
 458 +
 459 +static int mt7621_spi_remove(struct platform_device *pdev)
 460 +{
 461 +       struct spi_controller *master;
 462 +       struct mt7621_spi *rs;
 463 +
 464 +       master = dev_get_drvdata(&pdev->dev);
 465 +       rs = spi_controller_get_devdata(master);
 466 +
 467 +       clk_disable_unprepare(rs->clk);
 468 +
 469 +       return 0;
 470 +}
 471 +
 472 +MODULE_ALIAS("platform:" DRIVER_NAME);
 473 +
 474 +static struct platform_driver mt7621_spi_driver = {
 475 +       .driver = {
 476 +               .name = DRIVER_NAME,
 477 +               .of_match_table = mt7621_spi_match,
 478 +       },
 479 +       .probe = mt7621_spi_probe,
 480 +       .remove = mt7621_spi_remove,
 481 +};
 482 +
 483 +module_platform_driver(mt7621_spi_driver);
 484 +
 485 +MODULE_DESCRIPTION("MT7621 SPI driver");
 486 +MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
 487 +MODULE_LICENSE("GPL");