target/linux/ramips/patches-5.4/0102-staging-mt7621-pci-use-gpios-for-properly-reset.patch

   1 From 227a8bf421ff8b085444e51e471ef06a87228cfd Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Fri, 13 Mar 2020 21:09:08 +0100
   4 Subject: [PATCH] staging: mt7621-pci: use gpios for properly reset
   5
   6 Original driver code was using three gpio's for reset
   7 asserts and deasserts the pcis. Instead of using that
   8 a general reset control with a perst gpio was introduced
   9 and it seems it is partially working but sometimes there
  10 are some unexpected hangs on boot. This commit make use of
  11 the three original gpios using 'reset-gpios' property of
  12 the device tree and removes the reset line and perst gpio.
  13 According to the mediatek aplication note v0.1 there are
  14 three gpios used for pcie ports reset control: gpio#19,
  15 gpio#8 and gpio#7 for slots 0, 1 and 2 respectively.
  16 This schema can be used separately for mt7621A but in some
  17 boards due to pin share issue, if the PCM and I2S function
  18 are enable at the same time, there are no enough GPIO to
  19 control per-port PCIe reset. In those cases gpio#19 is enought
  20 for reset the three ports together. Because of this we just
  21 try to get the three gpios but if some of them fail we are not
  22 failing in boot process, just prints a kernel notice and take
  23 after into account if the descriptor is or not valid in order
  24 to use it. All of them are set as GPIO output low configuration.
  25 The gpio descriptor's API takes device tree property into account
  26 and invert value if the pin is configured as active low.
  27 So we also have to properly request pins from device tree
  28 and set values correct in assert and deassert functions.
  29 After this changes the order to make all assert and
  30 deassert in the 'probe' process makes more sense:
  31 * Parse device tree.
  32 * make assert of the RC's and EP's before doing anything else.
  33 * make deassert of the RC's before initializing the phy.
  34 * Init the phy.
  35 * make deassert of the EP's before initialize pci ports.
  36 * Normal PCI initialization.
  37
  38 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  39 Link: https://lore.kernel.org/r/20200313200913.24321-2-sergio.paracuellos@gmail.com
  40 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  41 ---
  42  drivers/staging/mt7621-pci/pci-mt7621.c | 84 ++++++++++++++++++++-------------
  43  1 file changed, 51 insertions(+), 33 deletions(-)
  44
  45 --- a/drivers/staging/mt7621-pci/pci-mt7621.c
  46 +++ b/drivers/staging/mt7621-pci/pci-mt7621.c
  47 @@ -95,6 +95,7 @@
  48   * @pcie: pointer to PCIe host info
  49   * @phy: pointer to PHY control block
  50   * @pcie_rst: pointer to port reset control
  51 + * @gpio_rst: gpio reset
  52   * @slot: port slot
  53   * @enabled: indicates if port is enabled
  54   */
  55 @@ -104,6 +105,7 @@ struct mt7621_pcie_port {
  56         struct mt7621_pcie *pcie;
  57         struct phy *phy;
  58         struct reset_control *pcie_rst;
  59 +       struct gpio_desc *gpio_rst;
  60         u32 slot;
  61         bool enabled;
  62  };
  63 @@ -117,8 +119,6 @@ struct mt7621_pcie_port {
  64   * @offset: IO / Memory offset
  65   * @dev: Pointer to PCIe device
  66   * @ports: pointer to PCIe port information
  67 - * @perst: gpio reset
  68 - * @rst: pointer to pcie reset
  69   * @resets_inverted: depends on chip revision
  70   * reset lines are inverted.
  71   */
  72 @@ -133,8 +133,6 @@ struct mt7621_pcie {
  73                 resource_size_t io;
  74         } offset;
  75         struct list_head ports;
  76 -       struct gpio_desc *perst;
  77 -       struct reset_control *rst;
  78         bool resets_inverted;
  79  };
  80
  81 @@ -210,16 +208,16 @@ static void write_config(struct mt7621_p
  82         pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
  83  }
  84
  85 -static inline void mt7621_perst_gpio_pcie_assert(struct mt7621_pcie *pcie)
  86 +static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
  87  {
  88 -       gpiod_set_value(pcie->perst, 0);
  89 -       mdelay(PERST_DELAY_US);
  90 +       if (port->gpio_rst)
  91 +               gpiod_set_value(port->gpio_rst, 1);
  92  }
  93
  94 -static inline void mt7621_perst_gpio_pcie_deassert(struct mt7621_pcie *pcie)
  95 +static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
  96  {
  97 -       gpiod_set_value(pcie->perst, 1);
  98 -       mdelay(PERST_DELAY_US);
  99 +       if (port->gpio_rst)
 100 +               gpiod_set_value(port->gpio_rst, 0);
 101  }
 102
 103  static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
 104 @@ -367,6 +365,13 @@ static int mt7621_pcie_parse_port(struct
 105         if (IS_ERR(port->phy))
 106                 return PTR_ERR(port->phy);
 107
 108 +       port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
 109 +                                                      GPIOD_OUT_LOW);
 110 +       if (IS_ERR(port->gpio_rst)) {
 111 +               dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
 112 +               return PTR_ERR(port->gpio_rst);
 113 +       }
 114 +
 115         port->slot = slot;
 116         port->pcie = pcie;
 117
 118 @@ -383,12 +388,6 @@ static int mt7621_pcie_parse_dt(struct m
 119         struct resource regs;
 120         int err;
 121
 122 -       pcie->perst = devm_gpiod_get(dev, "perst", GPIOD_OUT_HIGH);
 123 -       if (IS_ERR(pcie->perst)) {
 124 -               dev_err(dev, "failed to get gpio perst\n");
 125 -               return PTR_ERR(pcie->perst);
 126 -       }
 127 -
 128         err = of_address_to_resource(node, 0, &regs);
 129         if (err) {
 130                 dev_err(dev, "missing \"reg\" property\n");
 131 @@ -399,12 +398,6 @@ static int mt7621_pcie_parse_dt(struct m
 132         if (IS_ERR(pcie->base))
 133                 return PTR_ERR(pcie->base);
 134
 135 -       pcie->rst = devm_reset_control_get_exclusive(dev, "pcie");
 136 -       if (PTR_ERR(pcie->rst) == -EPROBE_DEFER) {
 137 -               dev_err(dev, "failed to get pcie reset control\n");
 138 -               return PTR_ERR(pcie->rst);
 139 -       }
 140 -
 141         for_each_available_child_of_node(node, child) {
 142                 int slot;
 143
 144 @@ -458,16 +451,49 @@ static int mt7621_pcie_init_port(struct
 145         return 0;
 146  }
 147
 148 +static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
 149 +{
 150 +       struct mt7621_pcie_port *port;
 151 +
 152 +       list_for_each_entry(port, &pcie->ports, list) {
 153 +               /* PCIe RC reset assert */
 154 +               mt7621_control_assert(port);
 155 +
 156 +               /* PCIe EP reset assert */
 157 +               mt7621_rst_gpio_pcie_assert(port);
 158 +       }
 159 +
 160 +       mdelay(PERST_DELAY_US);
 161 +}
 162 +
 163 +static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
 164 +{
 165 +       struct mt7621_pcie_port *port;
 166 +
 167 +       list_for_each_entry(port, &pcie->ports, list)
 168 +               mt7621_control_deassert(port);
 169 +}
 170 +
 171 +static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
 172 +{
 173 +       struct mt7621_pcie_port *port;
 174 +
 175 +       list_for_each_entry(port, &pcie->ports, list)
 176 +               mt7621_rst_gpio_pcie_deassert(port);
 177 +
 178 +       mdelay(PERST_DELAY_US);
 179 +}
 180 +
 181  static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
 182  {
 183         struct device *dev = pcie->dev;
 184         struct mt7621_pcie_port *port, *tmp;
 185 -       u32 val = 0;
 186         int err;
 187
 188         rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
 189
 190 -       mt7621_perst_gpio_pcie_assert(pcie);
 191 +       mt7621_pcie_reset_assert(pcie);
 192 +       mt7621_pcie_reset_rc_deassert(pcie);
 193
 194         list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 195                 u32 slot = port->slot;
 196 @@ -476,16 +502,10 @@ static void mt7621_pcie_init_ports(struc
 197                 if (err) {
 198                         dev_err(dev, "Initiating port %d failed\n", slot);
 199                         list_del(&port->list);
 200 -               } else {
 201 -                       val = read_config(pcie, slot, PCIE_FTS_NUM);
 202 -                       dev_info(dev, "Port %d N_FTS = %x\n", slot,
 203 -                                (unsigned int)val);
 204                 }
 205         }
 206
 207 -       reset_control_assert(pcie->rst);
 208 -
 209 -       mt7621_perst_gpio_pcie_deassert(pcie);
 210 +       mt7621_pcie_reset_ep_deassert(pcie);
 211
 212         list_for_each_entry(port, &pcie->ports, list) {
 213                 u32 slot = port->slot;
 214 @@ -499,8 +519,6 @@ static void mt7621_pcie_init_ports(struc
 215                         port->enabled = false;
 216                 }
 217         }
 218 -
 219 -       reset_control_deassert(pcie->rst);
 220  }
 221
 222  static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)