target/linux/ramips/patches-5.4/105-mt7621-memory-detect.patch

   1 From b5a52351a66f3c2a7a207548aa87d78ff2d336c0 Mon Sep 17 00:00:00 2001
   2 From: Chuanhong Guo <gch981213@gmail.com>
   3 Date: Wed, 10 Jul 2019 00:24:48 +0800
   4 Subject: [PATCH] MIPS: ralink: mt7621: add memory detection support
   5
   6 mt7621 has the following memory map:
   7 0x0-0x1c000000: lower 448m memory
   8 0x1c000000-0x2000000: peripheral registers
   9 0x20000000-0x2400000: higher 64m memory
  10
  11 detect_memory_region in arch/mips/kernel/setup.c only add the first
  12 memory region and isn't suitable for 512m memory detection because
  13 it may accidentally read the memory area for peripheral registers.
  14
  15 This commit adds memory detection capability for mt7621:
  16 1. add the highmem area when 512m is detected.
  17 2. guard memcmp from accessing peripheral registers:
  18      This only happens when some weird user decided to change
  19      kernel load address to 256m or higher address. Since this
  20      is a quite unusual case, we just skip 512m testing and return
  21      256m as memory size.
  22
  23 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
  24 ---
  25  arch/mips/include/asm/mach-ralink/mt7621.h |  7 ++---
  26  arch/mips/ralink/mt7621.c                  | 30 +++++++++++++++++++---
  27  2 files changed, 30 insertions(+), 7 deletions(-)
  28
  29 --- a/arch/mips/include/asm/mach-ralink/mt7621.h
  30 +++ b/arch/mips/include/asm/mach-ralink/mt7621.h
  31 @@ -44,9 +44,10 @@
  32  #define CPU_PLL_FBDIV_MASK             0x7f
  33  #define CPU_PLL_FBDIV_SHIFT            4
  34
  35 -#define MT7621_DRAM_BASE                0x0
  36 -#define MT7621_DDR2_SIZE_MIN           32
  37 -#define MT7621_DDR2_SIZE_MAX           256
  38 +#define MT7621_LOWMEM_BASE             0x0
  39 +#define MT7621_LOWMEM_MAX_SIZE         0x1C000000
  40 +#define MT7621_HIGHMEM_BASE            0x20000000
  41 +#define MT7621_HIGHMEM_SIZE            0x4000000
  42
  43  #define MT7621_CHIP_NAME0              0x3637544D
  44  #define MT7621_CHIP_NAME1              0x20203132
  45 --- a/arch/mips/ralink/mt7621.c
  46 +++ b/arch/mips/ralink/mt7621.c
  47 @@ -13,6 +13,7 @@
  48  #include <linux/clk-provider.h>
  49  #include <dt-bindings/clock/mt7621-clk.h>
  50
  51 +#include <asm/bootinfo.h>
  52  #include <asm/mipsregs.h>
  53  #include <asm/smp-ops.h>
  54  #include <asm/mips-cps.h>
  55 @@ -55,6 +56,8 @@
  56  #define MT7621_GPIO_MODE_SDHCI_SHIFT   18
  57  #define MT7621_GPIO_MODE_SDHCI_GPIO    1
  58
  59 +static void *detect_magic __initdata = detect_memory_region;
  60 +
  61  static struct rt2880_pmx_func uart1_grp[] =  { FUNC("uart1", 0, 1, 2) };
  62  static struct rt2880_pmx_func i2c_grp[] =  { FUNC("i2c", 0, 3, 2) };
  63  static struct rt2880_pmx_func uart3_grp[] = {
  64 @@ -139,6 +142,28 @@ static struct clk *__init mt7621_add_sys
  65         return clk;
  66  }
  67
  68 +void __init mt7621_memory_detect(void)
  69 +{
  70 +       void *dm = &detect_magic;
  71 +       phys_addr_t size;
  72 +
  73 +       for (size = 32 * SZ_1M; size < 256 * SZ_1M; size <<= 1) {
  74 +               if (!memcmp(dm, dm + size, sizeof(detect_magic)))
  75 +                       break;
  76 +       }
  77 +
  78 +       if ((size == 256 * SZ_1M) &&
  79 +           (CPHYSADDR(dm + size) < MT7621_LOWMEM_MAX_SIZE) &&
  80 +           memcmp(dm, dm + size, sizeof(detect_magic))) {
  81 +               add_memory_region(MT7621_LOWMEM_BASE, MT7621_LOWMEM_MAX_SIZE,
  82 +                                 BOOT_MEM_RAM);
  83 +               add_memory_region(MT7621_HIGHMEM_BASE, MT7621_HIGHMEM_SIZE,
  84 +                                 BOOT_MEM_RAM);
  85 +       } else {
  86 +               add_memory_region(MT7621_LOWMEM_BASE, size, BOOT_MEM_RAM);
  87 +       }
  88 +}
  89 +
  90  void __init ralink_clk_init(void)
  91  {
  92         u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac;
  93 @@ -317,10 +342,7 @@ void prom_soc_init(struct ralink_soc_inf
  94                 (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK,
  95                 (rev & CHIP_REV_ECO_MASK));
  96
  97 -       soc_info->mem_size_min = MT7621_DDR2_SIZE_MIN;
  98 -       soc_info->mem_size_max = MT7621_DDR2_SIZE_MAX;
  99 -       soc_info->mem_base = MT7621_DRAM_BASE;
 100 -
 101 +       soc_info->mem_detect = mt7621_memory_detect;
 102         rt2880_pinmux_data = mt7621_pinmux_data;
 103
 104
 105 --- a/arch/mips/ralink/common.h
 106 +++ b/arch/mips/ralink/common.h
 107 @@ -17,6 +17,7 @@ struct ralink_soc_info {
 108         unsigned long mem_size;
 109         unsigned long mem_size_min;
 110         unsigned long mem_size_max;
 111 +       void (*mem_detect)(void);
 112  };
 113  extern struct ralink_soc_info soc_info;
 114
 115 --- a/arch/mips/ralink/of.c
 116 +++ b/arch/mips/ralink/of.c
 117 @@ -87,6 +87,8 @@ void __init plat_mem_setup(void)
 118         of_scan_flat_dt(early_init_dt_find_memory, NULL);
 119         if (memory_dtb)
 120                 of_scan_flat_dt(early_init_dt_scan_memory, NULL);
 121 +       else if (soc_info.mem_detect)
 122 +               soc_info.mem_detect();
 123         else if (soc_info.mem_size)
 124                 add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
 125                                   BOOT_MEM_RAM);