-From a3757157751a8a5302ee5e11faf828dc5db02018 Mon Sep 17 00:00:00 2001
+From 825d57369b196b64387348922b47adc5b651622c Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
-Date: Mon, 25 Sep 2017 10:53:50 +0800
-Subject: [PATCH] mtd: spi-nor: support layerscape
+Date: Wed, 17 Jan 2018 14:55:47 +0800
+Subject: [PATCH 05/30] mtd: spi-nor: support layerscape
-This is a integrated patch for layerscape qspi support.
+This is an integrated patch for layerscape qspi support.
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Yunhui Cui <B56489@freescale.com>
case SPI_NOR_NORMAL:
return 0;
}
-@@ -961,6 +973,8 @@ static const struct flash_info spi_nor_i
+@@ -962,6 +974,8 @@ static const struct flash_info spi_nor_i
/* ESMT */
{ "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_HAS_LOCK) },
/* Everspin */
{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
-@@ -1014,12 +1028,15 @@ static const struct flash_info spi_nor_i
+@@ -1015,12 +1029,15 @@ static const struct flash_info spi_nor_i
{ "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
{ "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
{ "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
{ "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
{ "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
{ "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
-@@ -1033,10 +1050,11 @@ static const struct flash_info spi_nor_i
+@@ -1034,10 +1051,11 @@ static const struct flash_info spi_nor_i
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
/* PMC */
{ "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
-@@ -1054,8 +1072,11 @@ static const struct flash_info spi_nor_i
+@@ -1055,8 +1073,11 @@ static const struct flash_info spi_nor_i
{ "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
{ "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
{ "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
{ "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
{ "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
-@@ -1130,6 +1151,9 @@ static const struct flash_info spi_nor_i
+@@ -1131,6 +1152,9 @@ static const struct flash_info spi_nor_i
{ "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
{ "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
{ "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
{ "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
{
"w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64,
-@@ -1192,6 +1216,53 @@ static const struct flash_info *spi_nor_
+@@ -1197,6 +1221,53 @@ static const struct flash_info *spi_nor_
id[0], id[1], id[2]);
return ERR_PTR(-ENODEV);
}
static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
-@@ -1411,7 +1482,7 @@ static int macronix_quad_enable(struct s
+@@ -1416,7 +1487,7 @@ static int macronix_quad_enable(struct s
* Write status Register and configuration register with 2 bytes
* The first byte will be written to the status register, while the
* second byte will be written to the configuration register.
*/
static int write_sr_cr(struct spi_nor *nor, u16 val)
{
-@@ -1459,6 +1530,24 @@ static int spansion_quad_enable(struct s
+@@ -1464,6 +1535,24 @@ static int spansion_quad_enable(struct s
return 0;
}
static int set_quad_mode(struct spi_nor *nor, const struct flash_info *info)
{
int status;
-@@ -1604,9 +1693,25 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1610,9 +1699,25 @@ int spi_nor_scan(struct spi_nor *nor, co
write_sr(nor, 0);
spi_nor_wait_till_ready(nor);
}
mtd->priv = nor;
mtd->type = MTD_NORFLASH;
mtd->writesize = 1;
-@@ -1639,6 +1744,8 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1646,6 +1751,8 @@ int spi_nor_scan(struct spi_nor *nor, co
nor->flags |= SNOR_F_USE_FSR;
if (info->flags & SPI_NOR_HAS_TB)
nor->flags |= SNOR_F_HAS_SR_TB;
#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
/* prefer "small sector" erase if possible */
-@@ -1678,9 +1785,15 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1685,9 +1792,15 @@ int spi_nor_scan(struct spi_nor *nor, co
/* Some devices cannot do fast-read, no matter what DT tells us */
if (info->flags & SPI_NOR_NO_FR)
nor->flash_read = SPI_NOR_NORMAL;
ret = set_quad_mode(nor, info);
if (ret) {
dev_err(dev, "quad mode not supported\n");
-@@ -1693,6 +1806,9 @@ int spi_nor_scan(struct spi_nor *nor, co
+@@ -1700,6 +1813,9 @@ int spi_nor_scan(struct spi_nor *nor, co
/* Default commands */
switch (nor->flash_read) {