reg = <0xc00 0x100>;
clocks = <&sysclock>;
+ clock-frequency = <50000000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+ clkctrl: clkctrl {
+ compatible = "ralink,rt2880-clock";
+ #clock-cells = <1>;
+ };
+
sdhci: sdhci@1E130000 {
compatible = "ralink,mt7620-sdhci";
reg = <0x1E130000 0x4000>;
status = "okay";
+ resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
+ reset-names = "pcie0", "pcie1", "pcie2";
+ clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
+ clock-names = "pcie0", "pcie1", "pcie2";
+
pcie0 {
reg = <0x0000 0 0 0 0>;