X-Git-Url: http://git.openwrt.org/?p=openwrt%2Fstaging%2Fwigyori.git;a=blobdiff_plain;f=target%2Flinux%2Framips%2Fdts%2Fmt7621.dtsi;h=086719a43d4bb7b1188cdc55b1b29a09e929cd8e;hp=31d930d2251b15b245c0ee4366fbb6f58f0797ff;hb=HEAD;hpb=6031ab345df86c285ea55d6523d6888cc596f63d diff --git a/target/linux/ramips/dts/mt7621.dtsi b/target/linux/ramips/dts/mt7621.dtsi index 31d930d225..086719a43d 100644 --- a/target/linux/ramips/dts/mt7621.dtsi +++ b/target/linux/ramips/dts/mt7621.dtsi @@ -1,10 +1,19 @@ +/dts-v1/; + +#include +#include #include +#include / { #address-cells = <1>; #size-cells = <1>; compatible = "mediatek,mt7621-soc"; + aliases { + serial0 = &uartlite; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -29,82 +38,55 @@ compatible = "mti,cpu-interrupt-controller"; }; - aliases { - serial0 = &uartlite; + chosen { + bootargs = "console=ttyS0,57600"; }; - cpuclock: cpuclock { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <880000000>; - }; - - sysclock: sysclock { - #clock-cells = <0>; - compatible = "fixed-clock"; - - /* FIXME: there should be way to detect this */ - clock-frequency = <50000000>; - }; - - - - palmbus: palmbus@1E000000 { + palmbus: palmbus@1e000000 { compatible = "palmbus"; - reg = <0x1E000000 0x100000>; - ranges = <0x0 0x1E000000 0x0FFFFF>; + reg = <0x1e000000 0x100000>; + ranges = <0x0 0x1e000000 0x0fffff>; #address-cells = <1>; #size-cells = <1>; - sysc: sysc@0 { - compatible = "mtk,mt7621-sysc"; + sysc: syscon@0 { + compatible = "mediatek,mt7621-sysc", "syscon"; + #clock-cells = <1>; + #reset-cells = <1>; + ralink,memctl = <&memc>; + clock-output-names = "xtal", "cpu", "bus", + "50m", "125m", "150m", + "250m", "270m"; reg = <0x0 0x100>; }; - wdt: wdt@100 { + wdt: watchdog@100 { compatible = "mediatek,mt7621-wdt"; reg = <0x100 0x100>; + mediatek,sysctl = <&sysc>; }; - gpio@600 { - #address-cells = <1>; - #size-cells = <0>; - - compatible = "mtk,mt7621-gpio"; + gpio: gpio@600 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "mediatek,mt7621-gpio"; + gpio-controller; + gpio-ranges = <&pinctrl 0 0 95>; + interrupt-controller; reg = <0x600 0x100>; - - gpio0: bank@0 { - reg = <0>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio1: bank@1 { - reg = <1>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio2: bank@2 { - reg = <2>; - compatible = "mtk,mt7621-gpio-bank"; - gpio-controller; - #gpio-cells = <2>; - }; + interrupt-parent = <&gic>; + interrupts = ; }; i2c: i2c@900 { compatible = "mediatek,mt7621-i2c"; reg = <0x900 0x100>; - clocks = <&sysclock>; + clocks = <&sysc MT7621_CLK_I2C>; + clock-names = "i2c"; - resets = <&rstctrl 16>; + resets = <&sysc MT7621_RST_I2C>; reset-names = "i2c"; #address-cells = <1>; @@ -120,9 +102,9 @@ compatible = "mediatek,mt7621-i2s"; reg = <0xa00 0x100>; - clocks = <&sysclock>; + clocks = <&sysc MT7621_CLK_I2S>; - resets = <&rstctrl 17>; + resets = <&sysc MT7621_RST_I2S>; reset-names = "i2s"; interrupt-parent = <&gic>; @@ -138,45 +120,65 @@ status = "disabled"; }; - systick: systick@d00 { - compatible = "ralink,mt7621-systick", "ralink,cevt-systick"; - reg = <0xd00 0x10>; + memc: memory-controller@5000 { + compatible = "mediatek,mt7621-memc", "syscon"; + reg = <0x5000 0x1000>; + }; - resets = <&rstctrl 28>; - reset-names = "intc"; + uartlite: uartlite@c00 { + compatible = "ns16550a"; + reg = <0xc00 0x100>; + + clocks = <&sysc MT7621_CLK_UART1>; + + resets = <&sysc MT7621_RST_UART1>; interrupt-parent = <&gic>; - interrupts = ; - }; + interrupts = ; - memc: memc@5000 { - compatible = "mtk,mt7621-memc"; - reg = <0x300 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + no-loopback-test; }; - cpc: cpc@1fbf0000 { - compatible = "mtk,mt7621-cpc"; - reg = <0x1fbf0000 0x8000>; - }; + uartlite2: uartlite2@d00 { + compatible = "ns16550a"; + reg = <0xd00 0x100>; - mc: mc@1fbf8000 { - compatible = "mtk,mt7621-mc"; - reg = <0x1fbf8000 0x8000>; - }; + clocks = <&sysc MT7621_CLK_UART2>; - uartlite: uartlite@c00 { + resets = <&sysc MT7621_RST_UART2>; + + interrupt-parent = <&gic>; + interrupts = ; + + reg-shift = <2>; + reg-io-width = <4>; + + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + + status = "disabled"; + }; + + uartlite3: uartlite3@e00 { compatible = "ns16550a"; - reg = <0xc00 0x100>; + reg = <0xe00 0x100>; + + clocks = <&sysc MT7621_CLK_UART3>; - clocks = <&sysclock>; - clock-frequency = <50000000>; + resets = <&sysc MT7621_RST_UART3>; interrupt-parent = <&gic>; - interrupts = ; + interrupts = ; reg-shift = <2>; reg-io-width = <4>; - no-loopback-test; + + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + + status = "disabled"; }; spi0: spi@b00 { @@ -185,9 +187,10 @@ compatible = "ralink,mt7621-spi"; reg = <0xb00 0x100>; - clocks = <&sysclock>; + clocks = <&sysc MT7621_CLK_SPI>; + clock-names = "spi"; - resets = <&rstctrl 18>; + resets = <&sysc MT7621_RST_SPI>; reset-names = "spi"; #address-cells = <1>; @@ -201,11 +204,11 @@ compatible = "ralink,rt3883-gdma"; reg = <0x2800 0x800>; - resets = <&rstctrl 14>; + resets = <&sysc MT7621_RST_GDMA>; reset-names = "dma"; interrupt-parent = <&gic>; - interrupts = <0 13 4>; + interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; #dma-channels = <16>; @@ -218,11 +221,11 @@ compatible = "mediatek,mt7621-hsdma"; reg = <0x7000 0x1000>; - resets = <&rstctrl 5>; + resets = <&sysc MT7621_RST_HSDMA>; reset-names = "hsdma"; interrupt-parent = <&gic>; - interrupts = <0 11 4>; + interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; #dma-channels = <1>; @@ -240,122 +243,135 @@ state_default: pinctrl0 { }; - i2c_pins: i2c { - i2c { - ralink,group = "i2c"; - ralink,function = "i2c"; + i2c_pins: i2c_pins { + i2c_pins { + groups = "i2c"; + function = "i2c"; }; }; - spi_pins: spi { - spi { - ralink,group = "spi"; - ralink,function = "spi"; + spi_pins: spi_pins { + spi_pins { + groups = "spi"; + function = "spi"; }; }; uart1_pins: uart1 { uart1 { - ralink,group = "uart1"; - ralink,function = "uart1"; + groups = "uart1"; + function = "uart1"; }; }; uart2_pins: uart2 { uart2 { - ralink,group = "uart2"; - ralink,function = "uart2"; + groups = "uart2"; + function = "uart2"; }; }; uart3_pins: uart3 { uart3 { - ralink,group = "uart3"; - ralink,function = "uart3"; + groups = "uart3"; + function = "uart3"; }; }; rgmii1_pins: rgmii1 { rgmii1 { - ralink,group = "rgmii1"; - ralink,function = "rgmii1"; + groups = "rgmii1"; + function = "rgmii1"; }; }; rgmii2_pins: rgmii2 { rgmii2 { - ralink,group = "rgmii2"; - ralink,function = "rgmii2"; + groups = "rgmii2"; + function = "rgmii2"; }; }; mdio_pins: mdio { mdio { - ralink,group = "mdio"; - ralink,function = "mdio"; + groups = "mdio"; + function = "mdio"; }; }; pcie_pins: pcie { pcie { - ralink,group = "pcie"; - ralink,function = "pcie rst"; + groups = "pcie"; + function = "gpio"; }; }; nand_pins: nand { spi-nand { - ralink,group = "spi"; - ralink,function = "nand1"; + groups = "spi"; + function = "nand1"; }; sdhci-nand { - ralink,group = "sdhci"; - ralink,function = "nand2"; + groups = "sdhci"; + function = "nand2"; }; }; sdhci_pins: sdhci { sdhci { - ralink,group = "sdhci"; - ralink,function = "sdhci"; + groups = "sdhci"; + function = "sdhci"; }; }; }; - rstctrl: rstctrl { - compatible = "ralink,rt2880-reset"; - #reset-cells = <1>; - }; - - clkctrl: clkctrl { - compatible = "ralink,rt2880-clock"; - #clock-cells = <1>; - }; - - sdhci: sdhci@1E130000 { + sdhci: sdhci@1e130000 { status = "disabled"; compatible = "ralink,mt7620-sdhci"; - reg = <0x1E130000 0x4000>; + reg = <0x1e130000 0x4000>; interrupt-parent = <&gic>; interrupts = ; + + pinctrl-names = "default"; + pinctrl-0 = <&sdhci_pins>; }; - xhci: xhci@1E1C0000 { - status = "okay"; + xhci: xhci@1e1c0000 { + #address-cells = <1>; + #size-cells = <0>; compatible = "mediatek,mt8173-xhci"; reg = <0x1e1c0000 0x1000 0x1e1d0700 0x0100>; reg-names = "mac", "ippc"; - clocks = <&sysclock>; + clocks = <&sysc MT7621_CLK_XTAL>; clock-names = "sys_ck"; interrupt-parent = <&gic>; interrupts = ; + + /* + * Port 1 of both hubs is one usb slot and referenced here. + * The binding doesn't allow to address individual hubs. + * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci. + */ + xhci_ehci_port1: port@1 { + reg = <1>; + #trigger-source-cells = <0>; + }; + + /* + * Only the second usb hub has a second port. That port serves + * ehci and ohci. + */ + ehci_port2: port@2 { + reg = <2>; + #trigger-source-cells = <0>; + }; }; gic: interrupt-controller@1fbc0000 { @@ -370,67 +386,150 @@ timer { compatible = "mti,gic-timer"; interrupts = ; - clocks = <&cpuclock>; + clocks = <&sysc MT7621_CLK_CPU>; }; }; + cpc: cpc@1fbf0000 { + compatible = "mti,mips-cpc"; + reg = <0x1fbf0000 0x8000>; + }; + + mc: mc@1fbf8000 { + compatible = "mti,mips-cdmm"; + reg = <0x1fbf8000 0x8000>; + }; + nand: nand@1e003000 { status = "disabled"; - compatible = "mtk,mt7621-nand"; - bank-width = <2>; + compatible = "mediatek,mt7621-nfc"; reg = <0x1e003000 0x800 0x1e003800 0x800>; + reg-names = "nfi", "ecc"; + + clocks = <&sysc MT7621_CLK_NAND>; + clock-names = "nfi_clk"; + }; + + crypto: crypto@1e004000 { + compatible = "mediatek,mtk-eip93"; + reg = <0x1e004000 0x1000>; + + interrupt-parent = <&gic>; + interrupts = ; }; ethernet: ethernet@1e100000 { compatible = "mediatek,mt7621-eth"; reg = <0x1e100000 0x10000>; + clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; + clock-names = "fe", "ethif"; + #address-cells = <1>; - #size-cells = <1>; + #size-cells = <0>; - resets = <&rstctrl 6 &rstctrl 23>; + resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; reset-names = "fe", "eth"; interrupt-parent = <&gic>; interrupts = ; - mediatek,switch = <&gsw>; + mediatek,ethsys = <&sysc>; - mdio-bus { - #address-cells = <1>; - #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; - phy1f: ethernet-phy@1f { - reg = <0x1f>; - phy-mode = "rgmii"; + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; }; }; - hnat: hnat@0 { - compatible = "mediatek,mt7623-hnat"; - reg = <0 0x10000>; - mtketh-ppd = "eth0"; - mtketh-lan = "eth0"; - mtketh-wan = "eth0"; - resets = <&rstctrl 0>; - reset-names = "mtketh"; + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + phy-mode = "rgmii"; }; - }; - gsw: gsw@1e110000 { - compatible = "mediatek,mt7621-gsw"; - reg = <0x1e110000 0x8000>; - interrupt-parent = <&gic>; - interrupts = ; + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + switch0: switch@1f { + compatible = "mediatek,mt7621"; + reg = <0x1f>; + mediatek,mcm; + resets = <&sysc MT7621_RST_MCM>; + reset-names = "mcm"; + interrupt-controller; + #interrupt-cells = <1>; + interrupts = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + status = "disabled"; + reg = <0>; + label = "lan0"; + }; + + port@1 { + status = "disabled"; + reg = <1>; + label = "lan1"; + }; + + port@2 { + status = "disabled"; + reg = <2>; + label = "lan2"; + }; + + port@3 { + status = "disabled"; + reg = <3>; + label = "lan3"; + }; + + port@4 { + status = "disabled"; + reg = <4>; + label = "lan4"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "rgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + pause; + }; + }; + }; + }; + }; }; pcie: pcie@1e140000 { compatible = "mediatek,mt7621-pci"; - reg = <0x1e140000 0x100 - 0x1e142000 0x100>; - + reg = <0x1e140000 0x100>, /* host-pci bridge registers */ + <0x1e142000 0x100>, /* pcie port 0 RC control registers */ + <0x1e143000 0x100>, /* pcie port 1 RC control registers */ + <0x1e144000 0x100>; /* pcie port 2 RC control registers */ #address-cells = <3>; #size-cells = <2>; @@ -439,49 +538,76 @@ device_type = "pci"; - bus-range = <0 255>; - ranges = < - 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */ - 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */ - >; - - interrupt-parent = <&gic>; - interrupts = ; + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ status = "disabled"; - resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>; - reset-names = "pcie0", "pcie1", "pcie2"; - clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>; - clock-names = "pcie0", "pcie1", "pcie2"; + #interrupt-cells = <1>; + interrupt-map-mask = <0xF800 0 0 0>; + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, + <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, + <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; pcie0: pcie@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <3>; #size-cells = <2>; - + device_type = "pci"; ranges; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE0>; + clocks = <&sysc MT7621_CLK_PCIE0>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy0"; }; pcie1: pcie@1,0 { reg = <0x0800 0 0 0 0>; - #address-cells = <3>; #size-cells = <2>; - + device_type = "pci"; ranges; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE1>; + clocks = <&sysc MT7621_CLK_PCIE1>; + phys = <&pcie0_phy 1>; + phy-names = "pcie-phy1"; }; pcie2: pcie@2,0 { reg = <0x1000 0 0 0 0>; - #address-cells = <3>; #size-cells = <2>; - + device_type = "pci"; ranges; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; + resets = <&sysc MT7621_RST_PCIE2>; + clocks = <&sysc MT7621_CLK_PCIE2>; + phys = <&pcie2_phy 0>; + phy-names = "pcie-phy2"; }; }; + + pcie0_phy: pcie-phy@1e149000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e149000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + }; + + pcie2_phy: pcie-phy@1e14a000 { + compatible = "mediatek,mt7621-pci-phy"; + reg = <0x1e14a000 0x0700>; + clocks = <&sysc MT7621_CLK_XTAL>; + #phy-cells = <1>; + }; };