oxnas: move PCIe controller outside of simple-bus
authorDaniel Golle <daniel@makrotopia.org>
Sun, 10 Mar 2019 22:04:28 +0000 (23:04 +0100)
committerDaniel Golle <daniel@makrotopia.org>
Sun, 10 Mar 2019 22:04:28 +0000 (23:04 +0100)
Move PCIe controller outside down to SoC level to avoid resource
mapping problems.
Also add more detailed error handling when mapping registers.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
target/linux/oxnas/files/drivers/pci/host/pcie-oxnas.c
target/linux/oxnas/patches-4.14/340-oxnas-pcie.patch
target/linux/oxnas/patches-4.14/500-oxnas-sata.patch

index 68898c3..1dd13f9 100644 (file)
@@ -420,34 +420,51 @@ oxnas_pcie_map_registers(struct platform_device *pdev,
        u32 pcie_ctrl_offset;
 
        ret = of_address_to_resource(np, 0, &regs);
-       if (ret)
+       if (ret) {
+               dev_err(&pdev->dev, "failed to parse base register space\n");
                return -EINVAL;
+       }
+
        pcie->base = devm_ioremap_resource(&pdev->dev, &regs);
-       if (!pcie->base)
+       if (!pcie->base) {
+               dev_err(&pdev->dev, "failed to map base register space\n");
                return -ENOMEM;
+       }
 
        ret = of_address_to_resource(np, 1, &regs);
-       if (ret)
+       if (ret) {
+               dev_err(&pdev->dev, "failed to parse inbound register space\n");
                return -EINVAL;
+       }
+
        pcie->inbound = devm_ioremap_resource(&pdev->dev, &regs);
-       if (!pcie->inbound)
+       if (!pcie->inbound) {
+               dev_err(&pdev->dev, "failed to map inbound register space\n");
                return -ENOMEM;
+       }
 
        pcie->phy = devm_of_phy_get(&pdev->dev, np, NULL);
        if (IS_ERR(pcie->phy)) {
-               if (PTR_ERR(pcie->phy) == -EPROBE_DEFER)
+               if (PTR_ERR(pcie->phy) == -EPROBE_DEFER) {
+                       dev_err(&pdev->dev, "failed to probe phy\n");
                        return PTR_ERR(pcie->phy);
+               }
+               dev_warn(&pdev->dev, "phy not attached\n");
                pcie->phy = NULL;
        }
 
        if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
-                                &outbound_ctrl_offset))
+                                &outbound_ctrl_offset)) {
+               dev_err(&pdev->dev, "failed to parse outbound register offset\n");
                return -EINVAL;
+       }
        pcie->outbound_offset = outbound_ctrl_offset;
 
        if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
-                                &pcie_ctrl_offset))
+                                &pcie_ctrl_offset)) {
+               dev_err(&pdev->dev, "failed to parse pcie-ctrl register offset\n");
                return -EINVAL;
+       }
        pcie->pcie_ctrl_offset = pcie_ctrl_offset;
 
        return 0;
index 2e4b571..a6b7137 100644 (file)
  
 --- a/arch/arm/boot/dts/ox820.dtsi
 +++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -316,6 +316,89 @@
-                               reg = <0x1000 0x1000>,
+@@ -288,7 +288,7 @@
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       compatible = "simple-bus";
+-                      ranges = <0 0x47000000 0x1000000>;
++                      ranges = <0 0x47000000 0x2000>;
+                       scu: scu@0 {
+                               compatible = "arm,arm11mp-scu";
+@@ -317,5 +317,86 @@
                                      <0x100 0x500>;
                        };
-+
-+                      pcie0: pcie-controller@c00000 {
-+                              compatible = "plxtech,nas782x-pcie";
-+                              device_type = "pci";
-+                              #address-cells = <3>;
-+                              #size-cells = <2>;
-+
-+                              /*              flag & space    bus address     host address    size */
-+                              ranges = <      0x82000000      0 0x48000000    0x48000000      0 0x2000000
-+                                              0xC2000000      0 0x4A000000    0x4A000000      0 0x1E00000
-+                                              0x81000000      0 0x4BE00000    0x4BE00000      0 0x0100000
-+                                              0x80000000      0 0x4BF00000    0x4BF00000      0 0x0100000>;
-+
-+                              bus-range = <0x00 0x7f>;
-+
-+                              /*      cfg             inbound translator      */
-+                              reg =   <0xc00000 0x1000>,      <0xd00000 0x100>;
-+
-+                              phys = <&pcie_phy>;
-+                              phy-names = "pcie-phy";
-+
-+                              #interrupt-cells = <1>;
-+                              /* wild card mask, match all bus address & interrupt specifier */
-+                              /* format: bus address mask, interrupt specifier mask */
-+                              /* each bit 1 means need match, 0 means ignored when match */
-+                              interrupt-map-mask = <0 0 0 0>;
-+                              /* format: a list of: bus address, interrupt specifier,
-+                               * parent interrupt controller & specifier */
-+                              interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
-+
-+                              gpios = <&gpio1 12 0>;
-+                              clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
-+                              clock-names = "pcie", "busclk";
-+                              resets = <&reset RESET_PCIEA>;
-+                              reset-names = "pcie";
-+
-+                              plxtech,pcie-hcsl-bit = <2>;
-+                              plxtech,pcie-ctrl-offset = <0x120>;
-+                              plxtech,pcie-outbound-offset = <0x138>;
-+                              status = "disabled";
-+                      };
-+
-+                      pcie1: pcie-controller@e00000 {
-+                              compatible = "plxtech,nas782x-pcie";
-+                              device_type = "pci";
-+                              #address-cells = <3>;
-+                              #size-cells = <2>;
-+
-+                              /*              flag & space    bus address     host address    size */
-+                              ranges = <      0x82000000      0 0x4C000000    0x4C000000      0 0x2000000
-+                                              0xC2000000      0 0x4E000000    0x4E000000      0 0x1E00000
-+                                              0x81000000      0 0x4FE00000    0x4FE00000      0 0x0100000
-+                                              0x80000000      0 0x4FF00000    0x4FF00000      0 0x0100000>;
-+
-+                              bus-range = <0x80 0xff>;
-+
-+                              /*      cfg             inbound translator      */
-+                              reg =   <0xe00000 0x1000>,      <0xf00000 0x100>;
-+
-+                              phys = <&pcie_phy>;
-+                              phy-names = "pcie-phy";
-+
-+                              #interrupt-cells = <1>;
-+                              /* wild card mask, match all bus address & interrupt specifier */
-+                              /* format: bus address mask, interrupt specifier mask */
-+                              /* each bit 1 means need match, 0 means ignored when match */
-+                              interrupt-map-mask = <0 0 0 0>;
-+                              /* format: a list of: bus address, interrupt specifier,
-+                               * parent interrupt controller & specifier */
-+                              interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
-+
-+                              /* gpios = <&gpio1 12 0>; */
-+                              clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
-+                              clock-names = "pcie", "busclk";
-+                              resets = <&reset RESET_PCIEB>;
-+                              reset-names = "pcie";
-+
-+                              plxtech,pcie-hcsl-bit = <3>;
-+                              plxtech,pcie-ctrl-offset = <0x124>;
-+                              plxtech,pcie-outbound-offset = <0x174>;
-+                              status = "disabled";
-+                      };
-+
                };
++
++              pcie0: pcie-controller@47c00000 {
++                      compatible = "plxtech,nas782x-pcie";
++                      device_type = "pci";
++                      #address-cells = <3>;
++                      #size-cells = <2>;
++
++                      /*              flag & space    bus address     host address    size */
++                      ranges = <      0x82000000      0 0x48000000    0x48000000      0 0x2000000
++                                      0xC2000000      0 0x4A000000    0x4A000000      0 0x1E00000
++                                      0x81000000      0 0x4BE00000    0x4BE00000      0 0x0100000
++                                      0x80000000      0 0x4BF00000    0x4BF00000      0 0x0100000>;
++
++                      bus-range = <0x00 0x7f>;
++
++                      /*      cfg                     inbound translator      */
++                      reg =   <0x47c00000 0x1000>,    <0x47d00000 0x100>;
++
++                      phys = <&pcie_phy>;
++                      phy-names = "pcie-phy";
++
++                      #interrupt-cells = <1>;
++                      /* wild card mask, match all bus address & interrupt specifier */
++                      /* format: bus address mask, interrupt specifier mask */
++                      /* each bit 1 means need match, 0 means ignored when match */
++                      interrupt-map-mask = <0 0 0 0>;
++                      /* format: a list of: bus address, interrupt specifier,
++                       * parent interrupt controller & specifier */
++                      interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
++                      gpios = <&gpio1 12 0>;
++                      clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
++                      clock-names = "pcie", "busclk";
++                      resets = <&reset RESET_PCIEA>;
++                      reset-names = "pcie";
++
++                      plxtech,pcie-hcsl-bit = <2>;
++                      plxtech,pcie-ctrl-offset = <0x120>;
++                      plxtech,pcie-outbound-offset = <0x138>;
++                      status = "disabled";
++              };
++
++              pcie1: pcie-controller@47e00000 {
++                      compatible = "plxtech,nas782x-pcie";
++                      device_type = "pci";
++                      #address-cells = <3>;
++                      #size-cells = <2>;
++
++                      /*              flag & space    bus address     host address    size */
++                      ranges = <      0x82000000      0 0x4C000000    0x4C000000      0 0x2000000
++                                      0xC2000000      0 0x4E000000    0x4E000000      0 0x1E00000
++                                      0x81000000      0 0x4FE00000    0x4FE00000      0 0x0100000
++                                      0x80000000      0 0x4FF00000    0x4FF00000      0 0x0100000>;
++
++                      bus-range = <0x80 0xff>;
++
++                      /*      cfg                     inbound translator      */
++                      reg =   <0x47e00000 0x1000>,    <0x47f00000 0x100>;
++
++                      phys = <&pcie_phy>;
++                      phy-names = "pcie-phy";
++
++                      #interrupt-cells = <1>;
++                      /* wild card mask, match all bus address & interrupt specifier */
++                      /* format: bus address mask, interrupt specifier mask */
++                      /* each bit 1 means need match, 0 means ignored when match */
++                      interrupt-map-mask = <0 0 0 0>;
++                      /* format: a list of: bus address, interrupt specifier,
++                       * parent interrupt controller & specifier */
++                      interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
++
++                      /* gpios = <&gpio1 12 0>; */
++                      clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
++                      clock-names = "pcie", "busclk";
++                      resets = <&reset RESET_PCIEB>;
++                      reset-names = "pcie";
++
++                      plxtech,pcie-hcsl-bit = <3>;
++                      plxtech,pcie-ctrl-offset = <0x124>;
++                      plxtech,pcie-outbound-offset = <0x174>;
++                      status = "disabled";
++              };
        };
  };
index 7aa0df9..5fe0746 100644 (file)
@@ -26,9 +26,9 @@
  obj-$(CONFIG_PATA_ALI)                += pata_ali.o
 --- a/arch/arm/boot/dts/ox820.dtsi
 +++ b/arch/arm/boot/dts/ox820.dtsi
-@@ -400,5 +400,20 @@
-                       };
+@@ -398,5 +398,20 @@
+                       plxtech,pcie-outbound-offset = <0x174>;
+                       status = "disabled";
                };
 +
 +              sata: sata@45900000 {