layerscape: add linux 4.9 support
authorYangbo Lu <yangbo.lu@nxp.com>
Wed, 27 Sep 2017 07:31:31 +0000 (15:31 +0800)
committerJohn Crispin <john@phrozen.org>
Sat, 7 Oct 2017 21:13:23 +0000 (23:13 +0200)
This patch is to add linux 4.9 support for layerscape.
All these kernel patches are from NXP LSDK 1709 release.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
32 files changed:
target/linux/layerscape/Makefile
target/linux/layerscape/armv8_32b/config-4.9 [new file with mode: 0644]
target/linux/layerscape/armv8_64b/config-4.9 [new file with mode: 0644]
target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/401-mtd-spi-nor-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/402-mtd-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/601-net-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/701-sdk_dpaa-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/702-pci-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/703-phy-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/704-fsl-mc-layerscape-support.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/705-dpaa2-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/801-ata-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/802-clk-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/803-cpufreq-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/804-crypto-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/805-dma-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/806-flextimer-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/807-gpu-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/808-guts-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/809-i2c-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/810-iommu-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/811-irqchip-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/812-mmc-layerscape-support.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/813-qe-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/814-rtc-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/815-spi-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/816-tty-serial-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/817-usb-support-layerscape.patch [new file with mode: 0644]
target/linux/layerscape/patches-4.9/818-vfio-support-layerscape.patch [new file with mode: 0644]

index 9c92bb4..67da844 100644 (file)
@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 BOARD:=layerscape
 BOARDNAME:=NXP Layerscape
 DEVICE_TYPE:=developerboard
-KERNEL_PATCHVER:=4.4
+KERNEL_PATCHVER:=4.9
 FEATURES:=squashfs nand usb pcie gpio
 SUBTARGETS:=armv8_64b armv8_32b
 MAINTAINER:=Yangbo Lu <yangbo.lu@nxp.com>
diff --git a/target/linux/layerscape/armv8_32b/config-4.9 b/target/linux/layerscape/armv8_32b/config-4.9
new file mode 100644 (file)
index 0000000..ec7d0c1
--- /dev/null
@@ -0,0 +1,1461 @@
+CONFIG_ABX500_CORE=y
+CONFIG_AD525X_DPOT=y
+CONFIG_AD525X_DPOT_I2C=y
+# CONFIG_AD525X_DPOT_SPI is not set
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_AHCI_IMX=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AK8975=y
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_APDS9802ALS=y
+CONFIG_AQUANTIA_PHY=y
+# CONFIG_ARCH_AXXIA is not set
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_HAS_BANDGAP=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+CONFIG_ARCH_MULTI_V6_V7=y
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MXC=y
+CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED=y
+CONFIG_ARCH_NR_GPIO=512
+CONFIG_ARCH_OMAP=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_ARCH_OMAP2PLUS_TYPICAL=y
+CONFIG_ARCH_OMAP3=y
+CONFIG_ARCH_OMAP4=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y
+CONFIG_ARCH_SUPPORTS_UPROBES=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_BUILTIN_BSWAP=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_VIRT=y
+CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARM=y
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
+CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y
+CONFIG_ARM_CPUIDLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_ARM_CRYPTO=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_HAS_SG_CHAIN=y
+CONFIG_ARM_HEAVY_MB=y
+# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
+CONFIG_ARM_IMX6Q_CPUFREQ=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_OMAP2PLUS_CPUFREQ=y
+CONFIG_ARM_PATCH_IDIV=y
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+# CONFIG_ARM_PL172_MPMC is not set
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PSCI=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SCPI_PROTOCOL is not set
+# CONFIG_ARM_SMMU is not set
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ARM_UNWIND=y
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_AT803X_PHY=y
+CONFIG_ATA=y
+CONFIG_ATAGS=y
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_ATH5K_PCI is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_AUTO_ZRELADDR=y
+# CONFIG_AXP20X_POWER is not set
+CONFIG_BACKLIGHT_AS3711=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_TPS65217 is not set
+CONFIG_BATTERY_ACT8945A=y
+CONFIG_BATTERY_SBS=y
+CONFIG_BCMA=y
+CONFIG_BCMA_BLOCKIO=y
+# CONFIG_BCMA_DEBUG is not set
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_BCMA_DRIVER_PCI=y
+CONFIG_BCMA_HOST_PCI=y
+CONFIG_BCMA_HOST_PCI_POSSIBLE=y
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_SFLASH=y
+CONFIG_BCM_NET_PHYLIB=y
+# CONFIG_BLK_CGROUP is not set
+CONFIG_BLK_CMDLINE_PARSER=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+# CONFIG_BLK_DEV_NVME_SCSI is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+# CONFIG_BLK_DEV_SR_VENDOR is not set
+CONFIG_BLK_MQ_PCI=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_BOUNCE=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_BRCMSTB_GISB_ARB=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_BUILD_BIN2C=y
+CONFIG_CACHE_L2X0=y
+# CONFIG_CACHE_L2X0_PMU is not set
+CONFIG_CAN=y
+# CONFIG_CAN_8DEV_USB is not set
+CONFIG_CAN_BCM=y
+CONFIG_CAN_CALC_BITTIMING=y
+# CONFIG_CAN_CC770 is not set
+# CONFIG_CAN_C_CAN is not set
+CONFIG_CAN_DEV=y
+# CONFIG_CAN_EMS_USB is not set
+# CONFIG_CAN_ESD_USB2 is not set
+CONFIG_CAN_FLEXCAN=y
+# CONFIG_CAN_GRCAN is not set
+CONFIG_CAN_GW=y
+# CONFIG_CAN_KVASER_USB is not set
+# CONFIG_CAN_LEDS is not set
+CONFIG_CAN_MCP251X=y
+# CONFIG_CAN_PEAK_USB is not set
+CONFIG_CAN_RAW=y
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_SOFTING is not set
+# CONFIG_CAN_TI_HECC is not set
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_NET_CLASSID is not set
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+# CONFIG_CHARGER_MAX14577 is not set
+CONFIG_CHARGER_TPS65090=y
+# CONFIG_CHARGER_TPS65217 is not set
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_IMX_GPT=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_TI_32K=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_CLK_QORIQ=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=64
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_MAX77686=y
+# CONFIG_COMMON_CLK_PALMAS is not set
+# CONFIG_COMMON_CLK_RK808 is not set
+# CONFIG_COMMON_CLK_S2MPS11 is not set
+CONFIG_COMMON_CLK_TI_ADPLL=y
+CONFIG_COMPACTION=y
+CONFIG_COMPAT_BRK=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+# CONFIG_CORTINA_PHY is not set
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUSETS=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_HAS_ASID=y
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_V7=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+# CONFIG_CRYPTO_AES_ARM_CE is not set
+# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC is not set
+# CONFIG_CRYPTO_DEV_MXC_SCC is not set
+# CONFIG_CRYPTO_DEV_OMAP_AES is not set
+# CONFIG_CRYPTO_DEV_OMAP_DES is not set
+# CONFIG_CRYPTO_DEV_OMAP_SHAM is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+# CONFIG_CRYPTO_GHASH_ARM_CE is not set
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA1_ARM_CE is not set
+# CONFIG_CRYPTO_SHA1_ARM_NEON is not set
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_SHA256_ARM is not set
+# CONFIG_CRYPTO_SHA2_ARM_CE is not set
+# CONFIG_CRYPTO_SHA512_ARM is not set
+# CONFIG_CRYPTO_TLS is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_DEBUG_ALIGN_RODATA=y
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_IMX_UART_PORT=1
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_DEBUG_RODATA=y
+# CONFIG_DEBUG_UART_8250 is not set
+# CONFIG_DEBUG_USER is not set
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_DEVFREQ_GOV_PASSIVE is not set
+# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
+# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
+# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
+# CONFIG_DEVFREQ_GOV_USERSPACE is not set
+# CONFIG_DEVFREQ_THERMAL is not set
+CONFIG_DEVKMEM=y
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMADEVICES=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_OMAP=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_DRM=y
+CONFIG_DRM_BRIDGE=y
+CONFIG_DRM_FBDEV_EMULATION=y
+CONFIG_DRM_FSL_DCU=y
+CONFIG_DRM_GEM_CMA_HELPER=y
+CONFIG_DRM_KMS_CMA_HELPER=y
+CONFIG_DRM_KMS_FB_HELPER=y
+CONFIG_DRM_KMS_HELPER=y
+CONFIG_DRM_PANEL=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_DRM_SII902X=y
+# CONFIG_DRM_VIRTIO_GPU is not set
+CONFIG_DST_CACHE=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_DWMAC_GENERIC=y
+CONFIG_DW_DMAC=y
+CONFIG_DW_DMAC_CORE=y
+CONFIG_DW_WATCHDOG=y
+CONFIG_E1000E=y
+CONFIG_EDAC=y
+CONFIG_EDAC_ATOMIC_SCRUB=y
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_LEGACY_SYSFS=y
+# CONFIG_EDAC_MM_EDAC is not set
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_93CX6=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EFI=y
+# CONFIG_EFIVAR_FS is not set
+CONFIG_EFI_ARMSTUB=y
+# CONFIG_EFI_CAPSULE_LOADER is not set
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_VARS is not set
+CONFIG_ELF_CORE=y
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_EXPORTFS=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+# CONFIG_EXTCON_AXP288 is not set
+# CONFIG_EXTCON_MAX14577 is not set
+# CONFIG_EXTCON_MAX8997 is not set
+# CONFIG_EXTCON_PALMAS is not set
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+CONFIG_FB_EFI=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_MX3=y
+CONFIG_FB_SIMPLE=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FEC=y
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FMAN_ARM=y
+# CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN is not set
+# CONFIG_FMAN_P1023 is not set
+# CONFIG_FMAN_P3040_P4080_P5020 is not set
+# CONFIG_FMAN_PFC is not set
+# CONFIG_FMAN_V3H is not set
+# CONFIG_FMAN_V3L is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FORCE_MAX_ZONEORDER=12
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FREEZER=y
+CONFIG_FSL_BMAN_CONFIG=y
+CONFIG_FSL_BMAN_DEBUGFS=y
+# CONFIG_FSL_BMAN_TEST is not set
+# CONFIG_FSL_DPAA_1588 is not set
+CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
+# CONFIG_FSL_DPAA_CEETM is not set
+CONFIG_FSL_DPAA_CS_THRESHOLD_10G=0x10000000
+CONFIG_FSL_DPAA_CS_THRESHOLD_1G=0x06000000
+# CONFIG_FSL_DPAA_DBG_LOOP is not set
+# CONFIG_FSL_DPAA_ETH_DEBUG is not set
+CONFIG_FSL_DPAA_ETH_DEBUGFS=y
+# CONFIG_FSL_DPAA_ETH_JUMBO_FRAME is not set
+CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128
+CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80
+CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y
+# CONFIG_FSL_DPAA_HOOKS is not set
+CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000
+CONFIG_FSL_DPAA_OFFLINE_PORTS=y
+# CONFIG_FSL_DPAA_TS is not set
+CONFIG_FSL_DPA_CAN_WAIT=y
+CONFIG_FSL_DPA_CAN_WAIT_SYNC=y
+# CONFIG_FSL_DPA_CHECKING is not set
+CONFIG_FSL_DPA_PIRQ_FAST=y
+CONFIG_FSL_DPA_PIRQ_SLOW=y
+CONFIG_FSL_DPA_PORTAL_SHARE=y
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_FM_MAX_FRAME_SIZE=1522
+CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_PQ_MDIO=y
+# CONFIG_FSL_QDMA is not set
+CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2
+CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2
+CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4
+CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W=3
+CONFIG_FSL_QMAN_CONFIG=y
+CONFIG_FSL_QMAN_DEBUGFS=y
+CONFIG_FSL_QMAN_FQD_SZ=10
+# CONFIG_FSL_QMAN_FQ_LOOKUP is not set
+CONFIG_FSL_QMAN_INIT_TIMEOUT=10
+CONFIG_FSL_QMAN_PFDR_SZ=13
+CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH=12
+CONFIG_FSL_QMAN_PIRQ_IPERIOD=100
+CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH=4
+CONFIG_FSL_QMAN_POLL_LIMIT=32
+# CONFIG_FSL_QMAN_TEST is not set
+CONFIG_FSL_SDK_BMAN=y
+CONFIG_FSL_SDK_DPA=y
+CONFIG_FSL_SDK_DPAA_ETH=y
+CONFIG_FSL_SDK_FMAN=y
+# CONFIG_FSL_SDK_FMAN_TEST is not set
+CONFIG_FSL_SDK_QMAN=y
+CONFIG_FSL_USDPAA=y
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTRACE=y
+# CONFIG_FTRACE_SYSCALLS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_PINCONF=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GIANFAR=y
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+# CONFIG_GPIO_AXP209 is not set
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_EM=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MXC=y
+CONFIG_GPIO_OMAP=y
+CONFIG_GPIO_PALMAS=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCF857X=y
+CONFIG_GPIO_PL061=y
+# CONFIG_GPIO_STMPE is not set
+CONFIG_GPIO_SYSCON=y
+# CONFIG_GPIO_TPS65218 is not set
+CONFIG_GPIO_TPS6586X=y
+CONFIG_GPIO_TPS65910=y
+CONFIG_GPIO_TWL4030=y
+CONFIG_GPIO_XILINX=y
+CONFIG_GRACE_PERIOD=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_SMCCC=y
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CBPF_JIT=y
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_RCU_GUP=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IDE=y
+CONFIG_HAVE_IMX_SRC=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_OPROFILE=y
+CONFIG_HAVE_OPTPROBES=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_HAVE_RCU_TABLE_FREE=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SMP=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HDMI=y
+CONFIG_HID=y
+CONFIG_HID_GENERIC=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_HIX5HD2_GMAC=y
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_HUGETLBFS is not set
+CONFIG_HVC_DRIVER=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_OMAP=y
+CONFIG_HW_RANDOM_OMAP3_ROM=y
+CONFIG_HZ_FIXED=0
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_DEMUX_PINCTRL=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_NOMADIK=y
+CONFIG_I2C_OMAP=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SLAVE=y
+CONFIG_I2C_SLAVE_EEPROM=y
+CONFIG_I2C_XILINX=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_ICS932S401=y
+CONFIG_IGB=y
+CONFIG_IGB_HWMON=y
+CONFIG_IIO=y
+CONFIG_IIO_BUFFER=y
+CONFIG_IIO_CONFIGFS=y
+CONFIG_IIO_HRTIMER_TRIGGER=y
+CONFIG_IIO_KFIFO_BUF=y
+CONFIG_IIO_SW_TRIGGER=y
+# CONFIG_IIO_TIGHTLOOP_TRIGGER is not set
+CONFIG_IIO_TRIGGER=y
+CONFIG_IIO_TRIGGERED_BUFFER=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_IMX2_WDT=y
+CONFIG_IMX_DMA=y
+CONFIG_IMX_SDMA=y
+# CONFIG_IMX_WEIM is not set
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG_DESTROY is not set
+CONFIG_INET_ESP=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+# CONFIG_INPUT_AXP20X_PEK is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_JOYDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MATRIXKMAP=y
+# CONFIG_INPUT_MAX8997_HAPTIC is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_IOMMU_HELPER=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_NAT=y
+CONFIG_IP6_NF_TARGET_MASQUERADE=y
+# CONFIG_IP6_NF_TARGET_NPT is not set
+CONFIG_IPC_NS=y
+CONFIG_IPV6=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SUBTREES is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_MROUTE is not set
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IP_VS=y
+# CONFIG_IP_VS_DEBUG is not set
+# CONFIG_IP_VS_DH is not set
+# CONFIG_IP_VS_FO is not set
+# CONFIG_IP_VS_IPV6 is not set
+# CONFIG_IP_VS_LBLC is not set
+# CONFIG_IP_VS_LBLCR is not set
+# CONFIG_IP_VS_LC is not set
+# CONFIG_IP_VS_NFCT is not set
+# CONFIG_IP_VS_NQ is not set
+# CONFIG_IP_VS_OVF is not set
+# CONFIG_IP_VS_PROTO_AH is not set
+# CONFIG_IP_VS_PROTO_AH_ESP is not set
+# CONFIG_IP_VS_PROTO_ESP is not set
+# CONFIG_IP_VS_PROTO_SCTP is not set
+# CONFIG_IP_VS_PROTO_TCP is not set
+# CONFIG_IP_VS_PROTO_UDP is not set
+# CONFIG_IP_VS_RR is not set
+# CONFIG_IP_VS_SED is not set
+# CONFIG_IP_VS_SH is not set
+CONFIG_IP_VS_SH_TAB_BITS=8
+CONFIG_IP_VS_TAB_BITS=12
+# CONFIG_IP_VS_WLC is not set
+# CONFIG_IP_VS_WRR is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_CROSSBAR=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_ISL29003=y
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_KALLSYMS=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_ATKBD=y
+CONFIG_KEYBOARD_BCM=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_IMX is not set
+# CONFIG_KEYBOARD_STMPE is not set
+CONFIG_KEYS=y
+CONFIG_KS8851=y
+CONFIG_KVM=y
+CONFIG_KVM_ARM_HOST=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_MAX8997 is not set
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_CAMERA=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_TRANSIENT=y
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+CONFIG_LIBFDT=y
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCKD=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACH_OMAP3517EVM=y
+CONFIG_MACH_OMAP3_PANDORA=y
+CONFIG_MACH_OMAP_GENERIC=y
+CONFIG_MACVLAN=y
+CONFIG_MACVTAP=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MAILBOX=y
+# CONFIG_MAILBOX_TEST is not set
+CONFIG_MANDATORY_FILE_LOCKING=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MCPM=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+# CONFIG_MDIO_FSL_BACKPLANE is not set
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMCG=y
+# CONFIG_MEMCG_SWAP is not set
+CONFIG_MEMORY=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_ACT8945A=y
+CONFIG_MFD_AS3711=y
+CONFIG_MFD_AS3722=y
+CONFIG_MFD_ATMEL_FLEXCOM=y
+CONFIG_MFD_AXP20X=y
+CONFIG_MFD_AXP20X_I2C=y
+CONFIG_MFD_BCM590XX=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_MAX14577=y
+CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX8907=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_MFD_OMAP_USB_HOST=y
+CONFIG_MFD_PALMAS=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_STMPE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS65217=y
+CONFIG_MFD_TPS65218=y
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+# CONFIG_MFD_TWL4030_AUDIO is not set
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MICREL_PHY=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+# CONFIG_MMC_MXC is not set
+CONFIG_MMC_OMAP=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_AT91=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMU_NOTIFIER=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_REL=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_ELAN_I2C=y
+CONFIG_MOUSE_ELAN_I2C_I2C=y
+# CONFIG_MOUSE_ELAN_I2C_SMBUS is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MSDOS_FS=y
+# CONFIG_MTD_BCM47XXSFLASH is not set
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_BRCMNAND=y
+CONFIG_MTD_NAND_DENALI=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_BLOCK is not set
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MULTI_IRQ_HANDLER=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MVMDIO=y
+CONFIG_MX3_IPU=y
+CONFIG_MX3_IPU_IRQS=4
+CONFIG_NAMESPACES=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEON=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_IPVS=y
+CONFIG_NETFILTER_XT_NAT=y
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
+CONFIG_NETLINK_DIAG=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_KEY=y
+CONFIG_NET_NS=y
+CONFIG_NET_PACKET_ENGINE=y
+CONFIG_NET_PTP_CLASSIFY=y
+CONFIG_NET_SWITCHDEV=y
+# CONFIG_NET_VENDOR_AURORA is not set
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_RTCACHE is not set
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_DEFRAG_IPV6=y
+# CONFIG_NF_LOG_IPV6 is not set
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_IPV4=y
+CONFIG_NF_NAT_IPV6=y
+CONFIG_NF_NAT_MASQUERADE_IPV4=y
+CONFIG_NF_NAT_MASQUERADE_IPV6=y
+CONFIG_NF_NAT_NEEDED=y
+# CONFIG_NF_NAT_REDIRECT is not set
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=16
+CONFIG_NTFS_FS=y
+CONFIG_NVMEM=y
+CONFIG_NVME_CORE=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_DYNAMIC=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OID_REGISTRY=y
+CONFIG_OLD_SIGACTION=y
+CONFIG_OLD_SIGSUSPEND3=y
+# CONFIG_OMAP2PLUS_MBOX is not set
+# CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE is not set
+# CONFIG_OMAP3_SDRC_AC_TIMING is not set
+# CONFIG_OMAP5_ERRATA_801819 is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_CONTROL_PHY=y
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_GPMC=y
+# CONFIG_OMAP_GPMC_DEBUG is not set
+CONFIG_OMAP_INTERCONNECT=y
+CONFIG_OMAP_INTERCONNECT_BARRIER=y
+# CONFIG_OMAP_IOMMU is not set
+CONFIG_OMAP_IRQCHIP=y
+CONFIG_OMAP_MUX=y
+# CONFIG_OMAP_MUX_DEBUG is not set
+CONFIG_OMAP_MUX_WARNINGS=y
+CONFIG_OMAP_OCP2SCP=y
+CONFIG_OMAP_PACKAGE_CBB=y
+CONFIG_OMAP_PM_NOOP=y
+# CONFIG_OMAP_RESET_CLOCKS is not set
+CONFIG_OMAP_USB2=y
+# CONFIG_OMAP_WATCHDOG is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PAGE_COUNTER=y
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PALMAS_GPADC is not set
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARTITION_PERCPU=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+# CONFIG_PCI_DRA7XX is not set
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+CONFIG_PGTABLE_LEVELS=3
+CONFIG_PHYLIB=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_DM816X_USB is not set
+CONFIG_PID_NS=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AS3722=y
+CONFIG_PINCTRL_PALMAS=y
+CONFIG_PL310_ERRATA_588369=y
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_PL310_ERRATA_753970=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_PL320_MBOX=y
+CONFIG_PL330_DMA=y
+# CONFIG_PLAT_VERSATILE_CLCD is not set
+CONFIG_PM=y
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_DEVFREQ=y
+# CONFIG_PM_DEVFREQ_EVENT is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_AVS=y
+# CONFIG_POWER_AVS_OMAP is not set
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AS3722=y
+CONFIG_POWER_RESET_BRCMKONA=y
+CONFIG_POWER_RESET_BRCMSTB=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_PROBE_EVENTS is not set
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_CONSOLE=y
+# CONFIG_PSTORE_LZ4_COMPRESS is not set
+# CONFIG_PSTORE_LZO_COMPRESS is not set
+CONFIG_PSTORE_PMSG=y
+CONFIG_PSTORE_RAM=y
+CONFIG_PSTORE_ZLIB_COMPRESS=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_PTP_1588_CLOCK_DPAA is not set
+CONFIG_PTP_1588_CLOCK_GIANFAR=y
+CONFIG_PWM=y
+# CONFIG_PWM_IMX is not set
+# CONFIG_PWM_OMAP_DMTIMER is not set
+# CONFIG_PWM_STMPE is not set
+CONFIG_PWM_SYSFS=y
+# CONFIG_PWM_TIECAP is not set
+# CONFIG_PWM_TIEHRPWM is not set
+# CONFIG_PWM_TWL is not set
+# CONFIG_PWM_TWL_LED is not set
+CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
+CONFIG_QORIQ_CPUFREQ=y
+# CONFIG_QUICC_ENGINE is not set
+CONFIG_R8169=y
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ACT8865=y
+CONFIG_REGULATOR_ACT8945A=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_AS3711=y
+CONFIG_REGULATOR_AS3722=y
+CONFIG_REGULATOR_AXP20X=y
+CONFIG_REGULATOR_BCM590XX=y
+CONFIG_REGULATOR_DA9210=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_LP872X=y
+# CONFIG_REGULATOR_MAX14577 is not set
+CONFIG_REGULATOR_MAX77686=y
+# CONFIG_REGULATOR_MAX77802 is not set
+CONFIG_REGULATOR_MAX8907=y
+CONFIG_REGULATOR_MAX8973=y
+# CONFIG_REGULATOR_MAX8997 is not set
+# CONFIG_REGULATOR_MAX8998 is not set
+CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_PBIAS=y
+CONFIG_REGULATOR_PWM=y
+# CONFIG_REGULATOR_QCOM_SPMI is not set
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_S2MPA01 is not set
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_S5M8767=y
+CONFIG_REGULATOR_TI_ABB=y
+CONFIG_REGULATOR_TPS51632=y
+CONFIG_REGULATOR_TPS62360=y
+CONFIG_REGULATOR_TPS65090=y
+CONFIG_REGULATOR_TPS65217=y
+CONFIG_REGULATOR_TPS65218=y
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_REGULATOR_TPS65910=y
+CONFIG_REGULATOR_TWL4030=y
+CONFIG_REGULATOR_VEXPRESS=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_ROOT_NFS=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AS3722=y
+# CONFIG_RTC_DRV_CMOS is not set
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1307_HWMON=y
+CONFIG_RTC_DRV_DS3232=y
+# CONFIG_RTC_DRV_EFI is not set
+CONFIG_RTC_DRV_EM3027=y
+# CONFIG_RTC_DRV_IMXDI is not set
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_MAX8907=y
+# CONFIG_RTC_DRV_MAX8997 is not set
+# CONFIG_RTC_DRV_MAX8998 is not set
+# CONFIG_RTC_DRV_MXC is not set
+CONFIG_RTC_DRV_PALMAS=y
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_RTC_DRV_PCF85263=y
+CONFIG_RTC_DRV_PL031=y
+# CONFIG_RTC_DRV_RK808 is not set
+# CONFIG_RTC_DRV_S5M is not set
+CONFIG_RTC_DRV_TPS6586X=y
+CONFIG_RTC_DRV_TPS65910=y
+CONFIG_RTC_DRV_TWL4030=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_MV=y
+CONFIG_SATA_PMP=y
+CONFIG_SATA_SIL24=y
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHED_INFO is not set
+CONFIG_SCSI=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SENSORS_IIO_HWMON=y
+CONFIG_SENSORS_ISL29018=y
+CONFIG_SENSORS_ISL29028=y
+CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_LM95245=y
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_EM=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+# CONFIG_SERIAL_8250_OMAP is not set
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_BCM63XX=y
+CONFIG_SERIAL_BCM63XX_CONSOLE=y
+CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
+CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_MCTRL_GPIO=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_OMAP=y
+CONFIG_SERIAL_OMAP_CONSOLE=y
+CONFIG_SERIAL_ST_ASC=y
+CONFIG_SERIAL_ST_ASC_CONSOLE=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SG_POOL=y
+CONFIG_SG_SPLIT=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_SMSC_PHY=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SOC_AM33XX=y
+CONFIG_SOC_AM43XX=y
+CONFIG_SOC_BRCMSTB=y
+CONFIG_SOC_BUS=y
+CONFIG_SOC_DRA7XX=y
+CONFIG_SOC_HAS_OMAP2_SDRC=y
+CONFIG_SOC_HAS_REALTIME_COUNTER=y
+# CONFIG_SOC_IMX50 is not set
+# CONFIG_SOC_IMX51 is not set
+# CONFIG_SOC_IMX53 is not set
+# CONFIG_SOC_IMX6Q is not set
+# CONFIG_SOC_IMX6SL is not set
+# CONFIG_SOC_IMX6SX is not set
+# CONFIG_SOC_IMX6UL is not set
+# CONFIG_SOC_IMX7D is not set
+# CONFIG_SOC_LS1021A is not set
+CONFIG_SOC_OMAP3430=y
+CONFIG_SOC_OMAP5=y
+CONFIG_SOC_TI81XX=y
+# CONFIG_SOC_VF610 is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_CADENCE=y
+# CONFIG_SPI_CADENCE_QUADSPI is not set
+CONFIG_SPI_FSL_QUADSPI=y
+# CONFIG_SPI_IMX is not set
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_OMAP24XX=y
+CONFIG_SPI_PL022=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_XILINX=y
+CONFIG_SPMI=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+CONFIG_STAGING_BOARD=y
+CONFIG_STMMAC_ETH=y
+CONFIG_STMMAC_PLATFORM=y
+CONFIG_STMPE_I2C=y
+# CONFIG_STMPE_SPI is not set
+CONFIG_STMP_DEVICE=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWPHY=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_SW_SYNC is not set
+CONFIG_SYNC_FILE=y
+# CONFIG_SYN_COOKIES is not set
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_TI_CPPI41 is not set
+CONFIG_TI_CPSW=y
+CONFIG_TI_CPSW_ALE=y
+CONFIG_TI_CPSW_PHY_SEL=y
+CONFIG_TI_DAVINCI_CPDMA=y
+# CONFIG_TI_DAVINCI_EMAC is not set
+CONFIG_TI_DAVINCI_MDIO=y
+CONFIG_TI_DMA_CROSSBAR=y
+CONFIG_TI_EDMA=y
+# CONFIG_TI_EMIF is not set
+CONFIG_TI_PIPE3=y
+# CONFIG_TI_SOC_THERMAL is not set
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TOUCHSCREEN_PROPERTIES=y
+CONFIG_TOUCHSCREEN_STMPE=y
+CONFIG_TRACING_EVENTS_GPIO=y
+CONFIG_TREE_RCU=y
+CONFIG_TUN=y
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_TWL4030_WATCHDOG is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+CONFIG_UCS2_STRING=y
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+CONFIG_UNIX_DIAG=y
+CONFIG_USB=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_OF=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_DUAL_ROLE=y
+# CONFIG_USB_DWC2_PCI is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+# CONFIG_USB_DWC3_GADGET is not set
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PCI=y
+# CONFIG_USB_EHCI_FSL is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+# CONFIG_USB_EHCI_MXC is not set
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_FSL_USB2=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GPIO_VBUS=y
+# CONFIG_USB_HCD_BCMA is not set
+CONFIG_USB_HID=y
+# CONFIG_USB_IMX21_HCD is not set
+CONFIG_USB_ISP1301=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_ISP1760_DUAL_ROLE=y
+# CONFIG_USB_ISP1760_GADGET_ROLE is not set
+CONFIG_USB_ISP1760_HCD=y
+# CONFIG_USB_ISP1760_HOST_ROLE is not set
+CONFIG_USB_ISP1761_UDC=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_CDC_NCM=y
+CONFIG_USB_NET_CDC_SUBSET=y
+CONFIG_USB_NET_CDC_SUBSET_ENABLE=y
+CONFIG_USB_NET_DRIVERS=y
+CONFIG_USB_NET_NET1080=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_ZAURUS=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_OMAP3=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_PHY=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_USERIO is not set
+CONFIG_USER_NS=y
+CONFIG_USE_OF=y
+CONFIG_UTS_NS=y
+CONFIG_VDSO=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_VETH=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VEXPRESS_SYSCFG=y
+CONFIG_VFAT_FS=y
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VHOST=y
+CONFIG_VHOST_NET=y
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+# CONFIG_WKUP_M3_RPROC is not set
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_WLAN_VENDOR_ATH=y
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
+CONFIG_XILINX_WATCHDOG=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/layerscape/armv8_64b/config-4.9 b/target/linux/layerscape/armv8_64b/config-4.9
new file mode 100644 (file)
index 0000000..8fafc1c
--- /dev/null
@@ -0,0 +1,1371 @@
+CONFIG_64BIT=y
+CONFIG_ACPI=y
+CONFIG_ACPI_BUTTON=y
+CONFIG_ACPI_CCA_REQUIRED=y
+CONFIG_ACPI_CONTAINER=y
+# CONFIG_ACPI_CPPC_CPUFREQ is not set
+# CONFIG_ACPI_CUSTOM_DSDT is not set
+# CONFIG_ACPI_DEBUG is not set
+# CONFIG_ACPI_DEBUGGER is not set
+# CONFIG_ACPI_DOCK is not set
+# CONFIG_ACPI_EC_DEBUGFS is not set
+CONFIG_ACPI_FAN=y
+CONFIG_ACPI_GENERIC_GSI=y
+CONFIG_ACPI_HOTPLUG_CPU=y
+CONFIG_ACPI_I2C_OPREGION=y
+CONFIG_ACPI_IORT=y
+CONFIG_ACPI_MCFG=y
+CONFIG_ACPI_NUMA=y
+# CONFIG_ACPI_PCI_SLOT is not set
+CONFIG_ACPI_PROCESSOR=y
+CONFIG_ACPI_PROCESSOR_IDLE=y
+CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y
+CONFIG_ACPI_SPCR_TABLE=y
+CONFIG_ACPI_TABLE_UPGRADE=y
+CONFIG_ACPI_THERMAL=y
+CONFIG_ADVISE_SYSCALLS=y
+CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_QORIQ=y
+CONFIG_AHCI_XGENE=y
+CONFIG_AMD_XGBE=y
+CONFIG_AQUANTIA_PHY=y
+CONFIG_ARCH_CLOCKSOURCE_DATA=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y
+CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
+CONFIG_ARCH_HAS_ELF_RANDOMIZE=y
+CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y
+CONFIG_ARCH_HAS_GIGANTIC_PAGE=y
+CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
+CONFIG_ARCH_HAS_KCOV=y
+CONFIG_ARCH_HAS_SG_CHAIN=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_ARCH_HIBERNATION_HEADER=y
+CONFIG_ARCH_HIBERNATION_POSSIBLE=y
+CONFIG_ARCH_LAYERSCAPE=y
+CONFIG_ARCH_MMAP_RND_BITS=18
+CONFIG_ARCH_MMAP_RND_BITS_MAX=33
+CONFIG_ARCH_MMAP_RND_BITS_MIN=18
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11
+CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y
+CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
+CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
+CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_FRAME_POINTERS=y
+CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
+CONFIG_ARM64=y
+# CONFIG_ARM64_16K_PAGES is not set
+CONFIG_ARM64_4K_PAGES=y
+# CONFIG_ARM64_64K_PAGES is not set
+# CONFIG_ARM64_ACPI_PARKING_PROTOCOL is not set
+CONFIG_ARM64_CONT_SHIFT=4
+CONFIG_ARM64_CRYPTO=y
+CONFIG_ARM64_ERRATUM_819472=y
+CONFIG_ARM64_ERRATUM_824069=y
+CONFIG_ARM64_ERRATUM_826319=y
+CONFIG_ARM64_ERRATUM_827319=y
+CONFIG_ARM64_ERRATUM_832075=y
+CONFIG_ARM64_ERRATUM_834220=y
+CONFIG_ARM64_ERRATUM_843419=y
+CONFIG_ARM64_ERRATUM_845719=y
+CONFIG_ARM64_HW_AFDBM=y
+# CONFIG_ARM64_LSE_ATOMICS is not set
+CONFIG_ARM64_MODULE_CMODEL_LARGE=y
+CONFIG_ARM64_PAGE_SHIFT=12
+CONFIG_ARM64_PAN=y
+# CONFIG_ARM64_PTDUMP is not set
+# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
+CONFIG_ARM64_UAO=y
+CONFIG_ARM64_VA_BITS=48
+# CONFIG_ARM64_VA_BITS_39 is not set
+CONFIG_ARM64_VA_BITS_48=y
+CONFIG_ARM64_VHE=y
+# CONFIG_ARMV8_DEPRECATED is not set
+CONFIG_ARM_AMBA=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
+CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
+CONFIG_ARM_CPUIDLE=y
+# CONFIG_ARM_DT_BL_CPUFREQ is not set
+CONFIG_ARM_GIC=y
+CONFIG_ARM_GIC_V2M=y
+CONFIG_ARM_GIC_V3=y
+CONFIG_ARM_GIC_V3_ITS=y
+# CONFIG_ARM_PL172_MPMC is not set
+CONFIG_ARM_PMU=y
+CONFIG_ARM_PSCI_FW=y
+# CONFIG_ARM_SBSA_WATCHDOG is not set
+CONFIG_ARM_SMMU=y
+CONFIG_ARM_SMMU_V3=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_ARM_TIMER_SP804=y
+CONFIG_ASN1=y
+CONFIG_ASSOCIATIVE_ARRAY=y
+CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH=y
+CONFIG_ATA=y
+CONFIG_ATA_ACPI=y
+CONFIG_ATA_VERBOSE_ERROR=y
+# CONFIG_ATH5K_PCI is not set
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
+CONFIG_AUDIT_COMPAT_GENERIC=y
+CONFIG_AUDIT_GENERIC=y
+CONFIG_AUDIT_TREE=y
+CONFIG_AUDIT_WATCH=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_BACKLIGHT_PWM is not set
+CONFIG_BALLOON_COMPACTION=y
+CONFIG_BATTERY_BQ27XXX=y
+CONFIG_BATTERY_BQ27XXX_I2C=y
+CONFIG_BLK_CGROUP=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+# CONFIG_BLK_DEV_NVME_SCSI is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=262144
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_BLK_MQ_PCI=y
+CONFIG_BLOCK_COMPAT=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_BOUNCE=y
+CONFIG_BPF_JIT=y
+# CONFIG_BPF_SYSCALL is not set
+CONFIG_BRIDGE_EBT_DNAT=y
+CONFIG_BRIDGE_EBT_SNAT=y
+CONFIG_BRIDGE_EBT_T_NAT=y
+CONFIG_BRIDGE_NETFILTER=y
+CONFIG_BRIDGE_NF_EBTABLES=y
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_BTRFS_FS=y
+# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set
+CONFIG_BTRFS_FS_POSIX_ACL=y
+CONFIG_BUILD_BIN2C=y
+CONFIG_CAVIUM_ERRATUM_22375=y
+CONFIG_CAVIUM_ERRATUM_23144=y
+CONFIG_CAVIUM_ERRATUM_23154=y
+CONFIG_CAVIUM_ERRATUM_27456=y
+CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_CEPH_LIB=y
+# CONFIG_CEPH_LIB_PRETTYDEBUG is not set
+# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set
+CONFIG_CFQ_GROUP_IOSCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEVICE=y
+# CONFIG_CGROUP_FREEZER is not set
+CONFIG_CGROUP_HUGETLB=y
+# CONFIG_CGROUP_NET_CLASSID is not set
+CONFIG_CGROUP_PERF=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_WRITEBACK=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_CHROME_PLATFORMS=y
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_CLKSRC_ACPI=y
+CONFIG_CLKSRC_MMIO=y
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_PROBE=y
+CONFIG_CLKSRC_VERSATILE=y
+CONFIG_CLK_QORIQ=y
+CONFIG_CLK_SP810=y
+CONFIG_CLK_VEXPRESS_OSC=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_CLZ_TAB=y
+CONFIG_CMA=y
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+# CONFIG_CMA_DEBUG is not set
+# CONFIG_CMA_DEBUGFS is not set
+CONFIG_CMA_SIZE_MBYTES=16
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_CS2000_CP=y
+# CONFIG_COMMON_CLK_MAX77686 is not set
+CONFIG_COMMON_CLK_PWM=y
+CONFIG_COMMON_CLK_RK808=y
+CONFIG_COMMON_CLK_S2MPS11=y
+CONFIG_COMMON_CLK_VERSATILE=y
+CONFIG_COMMON_CLK_XGENE=y
+CONFIG_COMPACTION=y
+CONFIG_COMPAT=y
+CONFIG_COMPAT_BINFMT_ELF=y
+CONFIG_COMPAT_NETLINK_MESSAGES=y
+CONFIG_COMPAT_OLD_SIGACTION=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_COREDUMP=y
+# CONFIG_CORTINA_PHY is not set
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPUFREQ_DT_PLATDEV=y
+CONFIG_CPUSETS=y
+# CONFIG_CPU_BIG_ENDIAN is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_ATTR_SET=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_GOV_LADDER is not set
+CONFIG_CPU_IDLE_GOV_MENU=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_RMAP=y
+CONFIG_CPU_THERMAL=y
+CONFIG_CRC16=y
+# CONFIG_CRC32_SARWATE is not set
+CONFIG_CRC32_SLICEBY8=y
+CONFIG_CRC7=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CROS_EC_CHARDEV is not set
+CONFIG_CROS_EC_PROTO=y
+# CONFIG_CROS_KBD_LED_BACKLIGHT is not set
+CONFIG_CRYPTO_ABLK_HELPER=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_AES_ARM64_CE=y
+CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
+# CONFIG_CRYPTO_AES_ARM64_NEON_BLK is not set
+CONFIG_CRYPTO_AKCIPHER=y
+CONFIG_CRYPTO_AKCIPHER2=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_AUTHENC=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32_ARM64 is not set
+CONFIG_CRYPTO_CRCT10DIF=y
+CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_DEBUG is not set
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_JR=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+# CONFIG_CRYPTO_DEV_FSL_DPAA2_CAAM is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
+CONFIG_CRYPTO_ECHAINIV=y
+CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_NULL=y
+CONFIG_CRYPTO_NULL2=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_RSA=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA1_ARM64_CE=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA512=y
+# CONFIG_CRYPTO_TLS is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_DCACHE_WORD_ACCESS=y
+# CONFIG_DEBUG_ALIGN_RODATA is not set
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_RODATA=y
+CONFIG_DEBUG_SET_MODULE_RONX=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_LZ4=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
+CONFIG_DECOMPRESS_XZ=y
+CONFIG_DEFAULT_CFQ=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_DEVKMEM=y
+CONFIG_DEVMEM=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_DEV_DAX is not set
+CONFIG_DMADEVICES=y
+CONFIG_DMATEST=y
+CONFIG_DMA_ACPI=y
+CONFIG_DMA_CMA=y
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_ENGINE_RAID=y
+CONFIG_DMA_OF=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_DMA_VIRTUAL_CHANNELS=y
+CONFIG_DMI=y
+CONFIG_DMIID=y
+# CONFIG_DMI_SYSFS is not set
+CONFIG_DNOTIFY=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_DST_CACHE=y
+CONFIG_DTC=y
+CONFIG_DT_IDLE_STATES=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_EDAC_SUPPORT=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EFI=y
+CONFIG_EFIVAR_FS=y
+CONFIG_EFI_ARMSTUB=y
+# CONFIG_EFI_CAPSULE_LOADER is not set
+CONFIG_EFI_ESRT=y
+CONFIG_EFI_PARAMS_FROM_FDT=y
+CONFIG_EFI_RUNTIME_WRAPPERS=y
+CONFIG_EFI_STUB=y
+# CONFIG_EFI_TEST is not set
+# CONFIG_EFI_VARS is not set
+CONFIG_ELF_CORE=y
+# CONFIG_EMBEDDED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+# CONFIG_EVM is not set
+CONFIG_EXPORTFS=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+# CONFIG_EXT2_FS_SECURITY is not set
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_EXTCON=y
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_FAT_FS=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+CONFIG_FB_CMDLINE=y
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_EFI is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_SYS_COPYAREA=y
+CONFIG_FB_SYS_FILLRECT=y
+CONFIG_FB_SYS_FOPS=y
+CONFIG_FB_SYS_IMAGEBLIT=y
+CONFIG_FHANDLE=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_FIXED_PHY=y
+CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FMAN_ARM=y
+# CONFIG_FMAN_MIB_CNT_OVF_IRQ_EN is not set
+# CONFIG_FMAN_P1023 is not set
+# CONFIG_FMAN_P3040_P4080_P5020 is not set
+# CONFIG_FMAN_PFC is not set
+# CONFIG_FMAN_V3H is not set
+# CONFIG_FMAN_V3L is not set
+# CONFIG_FONTS is not set
+CONFIG_FONT_8x16=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_SUPPORT=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FRAME_POINTER=y
+CONFIG_FRAME_WARN=2048
+CONFIG_FREEZER=y
+CONFIG_FSL_BMAN_CONFIG=y
+CONFIG_FSL_BMAN_DEBUGFS=y
+# CONFIG_FSL_BMAN_TEST is not set
+CONFIG_FSL_DPAA2=y
+CONFIG_FSL_DPAA2_ETH=y
+CONFIG_FSL_DPAA2_ETHSW=y
+# CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE is not set
+CONFIG_FSL_DPAA2_EVB=y
+CONFIG_FSL_DPAA2_MAC=y
+# CONFIG_FSL_DPAA2_MAC_NETDEVS is not set
+# CONFIG_FSL_DPAA2_QDMA is not set
+# CONFIG_FSL_DPAA_1588 is not set
+CONFIG_FSL_DPAA_ADVANCED_DRIVERS=y
+# CONFIG_FSL_DPAA_CEETM is not set
+CONFIG_FSL_DPAA_CS_THRESHOLD_10G=0x10000000
+CONFIG_FSL_DPAA_CS_THRESHOLD_1G=0x06000000
+# CONFIG_FSL_DPAA_DBG_LOOP is not set
+# CONFIG_FSL_DPAA_ETH_DEBUG is not set
+CONFIG_FSL_DPAA_ETH_DEBUGFS=y
+# CONFIG_FSL_DPAA_ETH_JUMBO_FRAME is not set
+CONFIG_FSL_DPAA_ETH_MAX_BUF_COUNT=128
+CONFIG_FSL_DPAA_ETH_REFILL_THRESHOLD=80
+CONFIG_FSL_DPAA_ETH_USE_NDO_SELECT_QUEUE=y
+# CONFIG_FSL_DPAA_HOOKS is not set
+CONFIG_FSL_DPAA_INGRESS_CS_THRESHOLD=0x10000000
+CONFIG_FSL_DPAA_OFFLINE_PORTS=y
+# CONFIG_FSL_DPAA_TS is not set
+CONFIG_FSL_DPA_CAN_WAIT=y
+CONFIG_FSL_DPA_CAN_WAIT_SYNC=y
+# CONFIG_FSL_DPA_CHECKING is not set
+CONFIG_FSL_DPA_PIRQ_FAST=y
+CONFIG_FSL_DPA_PIRQ_SLOW=y
+CONFIG_FSL_DPA_PORTAL_SHARE=y
+CONFIG_FSL_EDMA=y
+CONFIG_FSL_ERRATUM_A008585=y
+CONFIG_FSL_FM_MAX_FRAME_SIZE=1522
+CONFIG_FSL_FM_RX_EXTRA_HEADROOM=64
+CONFIG_FSL_GUTS=y
+CONFIG_FSL_IFC=y
+CONFIG_FSL_LS2_CONSOLE=y
+CONFIG_FSL_MC_BUS=y
+CONFIG_FSL_MC_DPIO=y
+CONFIG_FSL_MC_RESTOOL=y
+# CONFIG_FSL_QBMAN_DEBUG is not set
+# CONFIG_FSL_QDMA is not set
+CONFIG_FSL_QMAN_CI_SCHED_CFG_BMAN_W=2
+CONFIG_FSL_QMAN_CI_SCHED_CFG_RW_W=2
+CONFIG_FSL_QMAN_CI_SCHED_CFG_SRCCIV=4
+CONFIG_FSL_QMAN_CI_SCHED_CFG_SRQ_W=3
+CONFIG_FSL_QMAN_CONFIG=y
+CONFIG_FSL_QMAN_DEBUGFS=y
+CONFIG_FSL_QMAN_FQD_SZ=10
+CONFIG_FSL_QMAN_FQ_LOOKUP=y
+CONFIG_FSL_QMAN_INIT_TIMEOUT=10
+CONFIG_FSL_QMAN_PFDR_SZ=13
+CONFIG_FSL_QMAN_PIRQ_DQRR_ITHRESH=12
+CONFIG_FSL_QMAN_PIRQ_IPERIOD=100
+CONFIG_FSL_QMAN_PIRQ_MR_ITHRESH=4
+CONFIG_FSL_QMAN_POLL_LIMIT=32
+# CONFIG_FSL_QMAN_TEST is not set
+CONFIG_FSL_SDK_BMAN=y
+CONFIG_FSL_SDK_DPA=y
+CONFIG_FSL_SDK_DPAA_ETH=y
+CONFIG_FSL_SDK_FMAN=y
+# CONFIG_FSL_SDK_FMAN_TEST is not set
+CONFIG_FSL_SDK_QMAN=y
+CONFIG_FSL_USDPAA=y
+CONFIG_FSL_XGMAC_MDIO=y
+CONFIG_FS_IOMAP=y
+CONFIG_FS_MBCACHE=y
+CONFIG_FS_POSIX_ACL=y
+CONFIG_FTM_ALARM=y
+CONFIG_FUSE_FS=y
+# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_GARP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_GENERIC_CPU_AUTOPROBE=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_GENERIC_EARLY_IOREMAP=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_GENERIC_IO=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_GENERIC_IRQ_MIGRATION=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
+CONFIG_GENERIC_MSI_IRQ=y
+CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_PHY=y
+CONFIG_GENERIC_SCHED_CLOCK=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+# CONFIG_GIANFAR is not set
+CONFIG_GLOB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIOLIB_IRQCHIP=y
+CONFIG_GPIO_ACPI=y
+# CONFIG_GPIO_AMDPT is not set
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_GENERIC=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_MAX77620=y
+CONFIG_GPIO_MPC8XXX=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PL061=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_XGENE=y
+CONFIG_HANDLE_DOMAIN_IRQ=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_HAS_DMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT_MAP=y
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_ARCH_AUDITSYSCALL=y
+CONFIG_HAVE_ARCH_BITREVERSE=y
+CONFIG_HAVE_ARCH_HUGE_VMAP=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_HAVE_ARCH_KASAN=y
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y
+CONFIG_HAVE_ARM_SMCCC=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_HAVE_CC_STACKPROTECTOR=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_HAVE_CMPXCHG_DOUBLE=y
+CONFIG_HAVE_CMPXCHG_LOCAL=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_HAVE_DEBUG_BUGVERBOSE=y
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_EBPF_JIT=y
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_HAVE_GENERIC_RCU_GUP=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_HAVE_KVM_ARCH_TLB_FLUSH_ALL=y
+CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y
+CONFIG_HAVE_KVM_EVENTFD=y
+CONFIG_HAVE_KVM_IRQCHIP=y
+CONFIG_HAVE_KVM_IRQFD=y
+CONFIG_HAVE_KVM_IRQ_ROUTING=y
+CONFIG_HAVE_KVM_MSI=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_HAVE_MEMBLOCK_NODE_MAP=y
+CONFIG_HAVE_MEMORY_PRESENT=y
+CONFIG_HAVE_NET_DSA=y
+CONFIG_HAVE_PATA_PLATFORM=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_HAVE_PERF_REGS=y
+CONFIG_HAVE_PERF_USER_STACK_DUMP=y
+CONFIG_HAVE_RCU_TABLE_FREE=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_UID16=y
+CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y
+CONFIG_HIBERNATE_CALLBACKS=y
+CONFIG_HIBERNATION=y
+CONFIG_HID=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_GENERIC=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HNS=y
+CONFIG_HNS_DSAF=y
+CONFIG_HNS_ENET=y
+CONFIG_HNS_MDIO=y
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_HPET is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_HVC_DRIVER=y
+CONFIG_HVC_IRQ=y
+CONFIG_HVC_XEN=y
+CONFIG_HVC_XEN_FRONTEND=y
+CONFIG_HWMON=y
+CONFIG_HW_CONSOLE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_CAVIUM is not set
+CONFIG_HZ=250
+# CONFIG_HZ_100 is not set
+CONFIG_HZ_250=y
+CONFIG_I2C=y
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CROS_EC_TUNNEL=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_RK3X=y
+CONFIG_I2C_SLAVE=y
+# CONFIG_I2C_SLAVE_EEPROM is not set
+CONFIG_IGB=y
+CONFIG_IGBVF=y
+CONFIG_IGB_HWMON=y
+CONFIG_IIO=y
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
+# CONFIG_IMA is not set
+CONFIG_IMX2_WDT=y
+CONFIG_INET_DIAG=y
+# CONFIG_INET_DIAG_DESTROY is not set
+CONFIG_INET_ESP=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_INPUT=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_INPUT_LEDS=y
+CONFIG_INPUT_MOUSE=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_XEN_KBDDEV_FRONTEND=y
+CONFIG_INTEGRITY=y
+CONFIG_INTEGRITY_AUDIT=y
+# CONFIG_INTEGRITY_SIGNATURE is not set
+CONFIG_IOMMU_API=y
+CONFIG_IOMMU_DMA=y
+CONFIG_IOMMU_HELPER=y
+CONFIG_IOMMU_IOVA=y
+CONFIG_IOMMU_IO_PGTABLE=y
+# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
+CONFIG_IOMMU_SUPPORT=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IPC_NS=y
+CONFIG_IPV6=y
+CONFIG_IPV6_SIT=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_MROUTE is not set
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_IRQCHIP=y
+CONFIG_IRQ_BYPASS_MANAGER=y
+CONFIG_IRQ_DOMAIN=y
+CONFIG_IRQ_DOMAIN_HIERARCHY=y
+CONFIG_IRQ_FORCED_THREADING=y
+CONFIG_IRQ_WORK=y
+# CONFIG_ISDN is not set
+CONFIG_JBD2=y
+# CONFIG_JFFS2_FS is not set
+CONFIG_JUMP_LABEL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KASAN is not set
+CONFIG_KEXEC=y
+CONFIG_KEXEC_CORE=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_CROS_EC is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYS=y
+CONFIG_KSM=y
+CONFIG_KVM=y
+CONFIG_KVM_ARM_HOST=y
+CONFIG_KVM_ARM_PMU=y
+CONFIG_KVM_ARM_VGIC_V3_ITS=y
+CONFIG_KVM_COMPAT=y
+CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y
+CONFIG_KVM_MMIO=y
+CONFIG_KVM_VFIO=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_SYSCON=y
+CONFIG_LEDS_TRIGGER_CPU=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_LIBCRC32C=y
+CONFIG_LIBFDT=y
+# CONFIG_LIQUIDIO is not set
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_LOCK_SPIN_ON_OWNER=y
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LS_SCFG_MSI=y
+CONFIG_LS_SOC_DRIVERS=y
+CONFIG_LZ4_DECOMPRESS=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_MACB=y
+CONFIG_MACVLAN=y
+CONFIG_MACVTAP=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_MANDATORY_FILE_LOCKING=y
+# CONFIG_MAX77620_THERMAL is not set
+# CONFIG_MAX77620_WATCHDOG is not set
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_BOARDINFO=y
+CONFIG_MDIO_BUS_MUX=y
+CONFIG_MDIO_BUS_MUX_MMIOREG=y
+# CONFIG_MDIO_FSL_BACKPLANE is not set
+# CONFIG_MDIO_GPIO is not set
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_SWAP_ENABLED=y
+CONFIG_MEMORY=y
+CONFIG_MEMORY_BALLOON=y
+CONFIG_MEMORY_ISOLATION=y
+CONFIG_MEMTEST=y
+CONFIG_MFD_CORE=y
+CONFIG_MFD_CROS_EC=y
+CONFIG_MFD_CROS_EC_I2C=y
+# CONFIG_MFD_CROS_EC_SPI is not set
+CONFIG_MFD_MAX77620=y
+CONFIG_MFD_RK808=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_VEXPRESS_SYSREG=y
+CONFIG_MICREL_PHY=y
+CONFIG_MIGRATION=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=32
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
+CONFIG_MMC_DW_K3=y
+# CONFIG_MMC_DW_PCI is not set
+CONFIG_MMC_DW_PLTFM=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
+CONFIG_MMC_SDHCI_OF_ESDHC=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SPI=y
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMU_NOTIFIER=y
+CONFIG_MODULES_TREE_LOOKUP=y
+CONFIG_MODULES_USE_ELF_RELA=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_BYD=y
+CONFIG_MOUSE_PS2_CYPRESS=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+CONFIG_MOUSE_PS2_FOCALTECH=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MPILIB=y
+CONFIG_MRP=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+# CONFIG_MTD_CFI_GEOMETRY is not set
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_DATAFLASH=y
+# CONFIG_MTD_DATAFLASH_OTP is not set
+# CONFIG_MTD_DATAFLASH_WRITE_VERIFY is not set
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_DENALI=y
+CONFIG_MTD_NAND_DENALI_DT=y
+CONFIG_MTD_NAND_ECC=y
+CONFIG_MTD_NAND_FSL_IFC=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
+CONFIG_MTD_SST25L=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_MV_XOR_V2=y
+CONFIG_NAMESPACES=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y
+CONFIG_NEED_SG_DMA_LENGTH=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_NETFILTER_INGRESS=y
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_NAT=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+# CONFIG_NETLABEL is not set
+CONFIG_NETLINK_DIAG=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NET_9P=y
+# CONFIG_NET_9P_DEBUG is not set
+CONFIG_NET_9P_VIRTIO=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_FLOW_LIMIT=y
+CONFIG_NET_INGRESS=y
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_KEY=y
+CONFIG_NET_NS=y
+CONFIG_NET_PACKET_ENGINE=y
+CONFIG_NET_PTP_CLASSIFY=y
+# CONFIG_NET_VENDOR_AURORA is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NFT_CHAIN_NAT_IPV4 is not set
+# CONFIG_NFT_CHAIN_ROUTE_IPV4 is not set
+CONFIG_NFT_COMPAT=y
+# CONFIG_NFT_COUNTER is not set
+CONFIG_NFT_CT=y
+# CONFIG_NFT_EXTHDR is not set
+# CONFIG_NFT_HASH is not set
+# CONFIG_NFT_LIMIT is not set
+# CONFIG_NFT_LOG is not set
+CONFIG_NFT_MASQ=y
+# CONFIG_NFT_MASQ_IPV4 is not set
+# CONFIG_NFT_META is not set
+CONFIG_NFT_NAT=y
+# CONFIG_NFT_NUMGEN is not set
+# CONFIG_NFT_QUOTA is not set
+# CONFIG_NFT_REDIR is not set
+# CONFIG_NFT_REJECT is not set
+# CONFIG_NFT_REJECT_IPV4 is not set
+# CONFIG_NFT_SET_HASH is not set
+# CONFIG_NFT_SET_RBTREE is not set
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_NF_CONNTRACK_MARK=y
+# CONFIG_NF_CONNTRACK_RTCACHE is not set
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_DEFRAG_IPV6=y
+# CONFIG_NF_LOG_BRIDGE is not set
+CONFIG_NF_LOG_COMMON=y
+CONFIG_NF_LOG_IPV6=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_IPV4=y
+CONFIG_NF_NAT_IPV6=y
+CONFIG_NF_NAT_MASQUERADE_IPV4=y
+CONFIG_NF_NAT_MASQUERADE_IPV6=y
+CONFIG_NF_NAT_NEEDED=y
+# CONFIG_NF_NAT_REDIRECT is not set
+CONFIG_NF_REJECT_IPV6=y
+CONFIG_NF_TABLES=y
+# CONFIG_NF_TABLES_ARP is not set
+CONFIG_NF_TABLES_BRIDGE=y
+# CONFIG_NF_TABLES_INET is not set
+CONFIG_NF_TABLES_IPV4=y
+# CONFIG_NF_TABLES_IPV6 is not set
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NODES_SHIFT=2
+CONFIG_NO_BOOTMEM=y
+CONFIG_NO_HZ_COMMON=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NR_CPUS=64
+CONFIG_NUMA=y
+CONFIG_NUMA_BALANCING=y
+CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y
+CONFIG_NVMEM=y
+CONFIG_NVME_CORE=y
+CONFIG_OF=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_ADDRESS_PCI=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_GPIO=y
+CONFIG_OF_IOMMU=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_NET=y
+CONFIG_OF_NUMA=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_RESERVED_MEM=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_PACKET_DIAG=y
+CONFIG_PAGE_COUNTER=y
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+CONFIG_PANIC_TIMEOUT=0
+CONFIG_PARAVIRT=y
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_PERCPU=y
+# CONFIG_PATA_ACPI is not set
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PCI=y
+CONFIG_PCIEAER=y
+CONFIG_PCIEASPM=y
+# CONFIG_PCIEASPM_DEBUG is not set
+CONFIG_PCIEASPM_DEFAULT=y
+# CONFIG_PCIEASPM_PERFORMANCE is not set
+# CONFIG_PCIEASPM_POWERSAVE is not set
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIE_DW=y
+CONFIG_PCIE_PME=y
+CONFIG_PCI_ATS=y
+CONFIG_PCI_BUS_ADDR_T_64BIT=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_DOMAINS_GENERIC=y
+CONFIG_PCI_ECAM=y
+CONFIG_PCI_HISI=y
+CONFIG_PCI_HOST_COMMON=y
+CONFIG_PCI_HOST_GENERIC=y
+# CONFIG_PCI_HOST_THUNDER_ECAM is not set
+# CONFIG_PCI_HOST_THUNDER_PEM is not set
+CONFIG_PCI_IOV=y
+CONFIG_PCI_LABEL=y
+CONFIG_PCI_LAYERSCAPE=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MSI_IRQ_DOMAIN=y
+CONFIG_PERF_EVENTS=y
+CONFIG_PGTABLE_LEVELS=4
+CONFIG_PHYLIB=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+# CONFIG_PHY_EXYNOS4210_USB2 is not set
+# CONFIG_PHY_EXYNOS4X12_USB2 is not set
+# CONFIG_PHY_EXYNOS5250_USB2 is not set
+CONFIG_PHY_SAMSUNG_USB2=y
+CONFIG_PHY_XGENE=y
+CONFIG_PID_IN_CONTEXTIDR=y
+CONFIG_PID_NS=y
+CONFIG_PL330_DMA=y
+CONFIG_PM=y
+# CONFIG_PMIC_OPREGION is not set
+CONFIG_PM_CLK=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_OPP=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_STD_PARTITION=""
+CONFIG_PNP=y
+CONFIG_PNPACPI=y
+CONFIG_PNP_DEBUG_MESSAGES=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SYSCON=y
+CONFIG_POWER_RESET_VEXPRESS=y
+CONFIG_POWER_RESET_XGENE=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_PPS=y
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_NOTIFIERS=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_PRINTK_TIME=y
+CONFIG_PRINT_QUOTA_WARNING=y
+CONFIG_PROC_CHILDREN=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_PROFILING=y
+CONFIG_PTP_1588_CLOCK=y
+# CONFIG_PTP_1588_CLOCK_DPAA is not set
+CONFIG_PTP_1588_CLOCK_DPAA2=y
+CONFIG_PWM=y
+# CONFIG_PWM_CROS_EC is not set
+CONFIG_PWM_SYSFS=y
+CONFIG_QCOM_HIDMA=y
+CONFIG_QCOM_HIDMA_MGMT=y
+CONFIG_QCOM_QDF2400_ERRATUM_0065=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QMAN_CEETM_UPDATE_PERIOD=1000
+CONFIG_QORIQ_CPUFREQ=y
+# CONFIG_QUICC_ENGINE is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTACTL=y
+# CONFIG_QUOTA_NETLINK_INTERFACE is not set
+CONFIG_RADIX_TREE_MULTIORDER=y
+CONFIG_RAID6_PQ=y
+# CONFIG_RANDOMIZE_BASE is not set
+CONFIG_RAS=y
+CONFIG_RATIONAL=y
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+# CONFIG_RCU_EXPERT is not set
+CONFIG_RCU_STALL_COMMON=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_GZIP=y
+CONFIG_RD_LZ4=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_RD_XZ=y
+CONFIG_REALTEK_PHY=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_MAX77620=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_QCOM_SPMI=y
+CONFIG_REGULATOR_RK808=y
+# CONFIG_REGULATOR_S2MPA01 is not set
+CONFIG_REGULATOR_S2MPS11=y
+# CONFIG_REGULATOR_S5M8767 is not set
+# CONFIG_REGULATOR_VEXPRESS is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RFS_ACCEL=y
+CONFIG_RPS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_DS1307_HWMON=y
+CONFIG_RTC_DRV_DS3232=y
+CONFIG_RTC_DRV_EFI=y
+CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_PCF2127=y
+CONFIG_RTC_DRV_PCF85263=y
+CONFIG_RTC_DRV_PL031=y
+# CONFIG_RTC_DRV_RK808 is not set
+CONFIG_RTC_DRV_S5M=y
+CONFIG_RTC_I2C_AND_SPI=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_RWSEM_SPIN_ON_OWNER=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_SATA_AHCI=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_PMP=y
+CONFIG_SATA_SIL24=y
+# CONFIG_SATA_ZPODD is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SCHED_INFO=y
+CONFIG_SCHED_MC=y
+CONFIG_SCSI=y
+CONFIG_SCSI_HISI_SAS=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SAS_ATTRS=y
+CONFIG_SCSI_SAS_HOST_SMP=y
+CONFIG_SCSI_SAS_LIBSAS=y
+CONFIG_SECCOMP=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_SECURITY=y
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_SECURITY_LOADPIN is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_YAMA is not set
+CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_FSL=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_PNP=y
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_XILINX_PS_UART=y
+CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIO=y
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SG_POOL=y
+CONFIG_SKY2=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+CONFIG_SMC91X=y
+CONFIG_SMP=y
+CONFIG_SMSC911X=y
+# CONFIG_SMSC911X_ARCH_HOOKS is not set
+CONFIG_SND=y
+# CONFIG_SND_COMPRESS_OFFLOAD is not set
+CONFIG_SND_DMAENGINE_PCM=y
+CONFIG_SND_JACK=y
+CONFIG_SND_JACK_INPUT_DEV=y
+CONFIG_SND_PCM=y
+CONFIG_SND_PCM_TIMER=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_SND_SIMPLE_CARD_UTILS=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AK4613=y
+CONFIG_SND_SOC_FSL_SAI=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SPI=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_TIMER=y
+CONFIG_SOCK_DIAG=y
+CONFIG_SOC_BUS=y
+CONFIG_SOUND=y
+CONFIG_SPARSEMEM=y
+CONFIG_SPARSEMEM_EXTREME=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SPARSEMEM_VMEMMAP=y
+CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
+CONFIG_SPARSE_IRQ=y
+CONFIG_SPI=y
+CONFIG_SPI_FSL_DSPI=y
+CONFIG_SPI_FSL_QUADSPI=y
+CONFIG_SPI_MASTER=y
+CONFIG_SPI_PL022=y
+CONFIG_SPMI=y
+# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
+CONFIG_SQUASHFS_DECOMP_SINGLE=y
+CONFIG_SQUASHFS_FILE_CACHE=y
+# CONFIG_SQUASHFS_FILE_DIRECT is not set
+# CONFIG_SQUASHFS_XZ is not set
+CONFIG_SQUASHFS_ZLIB=y
+CONFIG_SRAM=y
+CONFIG_SRCU=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_SWIOTLB=y
+CONFIG_SWIOTLB_XEN=y
+CONFIG_SWPHY=y
+# CONFIG_SW_SYNC is not set
+CONFIG_SYNC_FILE=y
+# CONFIG_SYN_COOKIES is not set
+CONFIG_SYSCTL_EXCEPTION_TRACE=y
+CONFIG_SYSFS_SYSCALL=y
+CONFIG_SYSVIPC_COMPAT=y
+CONFIG_SYS_HYPERVISOR=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_TASK_XACCT=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_OF=y
+# CONFIG_THUNDER_NIC_BGX is not set
+# CONFIG_THUNDER_NIC_PF is not set
+# CONFIG_THUNDER_NIC_RGX is not set
+# CONFIG_THUNDER_NIC_VF is not set
+CONFIG_TICK_CPU_ACCOUNTING=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y
+# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set
+CONFIG_TRANSPARENT_HUGE_PAGECACHE=y
+CONFIG_TUN=y
+CONFIG_UCS2_STRING=y
+CONFIG_UIO=y
+CONFIG_UIO_AEC=y
+CONFIG_UIO_CIF=y
+CONFIG_UIO_DMEM_GENIRQ=y
+CONFIG_UIO_MF624=y
+CONFIG_UIO_NETX=y
+CONFIG_UIO_PCI_GENERIC=y
+CONFIG_UIO_PDRV_GENIRQ=y
+# CONFIG_UIO_PRUSS is not set
+CONFIG_UIO_SERCOS3=y
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_UNIX_DIAG=y
+CONFIG_USB=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_CHIPIDEA_OF=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_DWC2=y
+CONFIG_USB_DWC2_DUAL_ROLE=y
+# CONFIG_USB_DWC2_PCI is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_DUAL_ROLE=y
+# CONFIG_USB_DWC3_GADGET is not set
+# CONFIG_USB_DWC3_HOST is not set
+CONFIG_USB_DWC3_OF_SIMPLE=y
+CONFIG_USB_DWC3_PCI=y
+# CONFIG_USB_EHCI_FSL is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_HID=y
+CONFIG_USB_HSIC_USB3503=y
+CONFIG_USB_ISP1760=y
+CONFIG_USB_ISP1760_DUAL_ROLE=y
+# CONFIG_USB_ISP1760_GADGET_ROLE is not set
+CONFIG_USB_ISP1760_HCD=y
+# CONFIG_USB_ISP1760_HOST_ROLE is not set
+CONFIG_USB_ISP1761_UDC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PCI=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_OTG=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SUPPORT=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_ULPI=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_XHCI_PLATFORM=y
+# CONFIG_USERIO is not set
+CONFIG_USER_NS=y
+CONFIG_USE_PERCPU_NUMA_NODE_ID=y
+CONFIG_UTS_NS=y
+CONFIG_VEXPRESS_CONFIG=y
+CONFIG_VEXPRESS_SYSCFG=y
+CONFIG_VFAT_FS=y
+CONFIG_VFIO=y
+CONFIG_VFIO_FSL_MC=y
+CONFIG_VFIO_IOMMU_TYPE1=y
+# CONFIG_VFIO_NOIOMMU is not set
+CONFIG_VFIO_PCI=y
+CONFIG_VFIO_PCI_INTX=y
+CONFIG_VFIO_PCI_MMAP=y
+# CONFIG_VFIO_PLATFORM is not set
+CONFIG_VFIO_VIRQFD=y
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_VHOST=y
+CONFIG_VHOST_NET=y
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_VIRTIO=y
+CONFIG_VIRTIO_BALLOON=y
+CONFIG_VIRTIO_BLK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_VIRTIO_MMIO=y
+# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
+CONFIG_VIRTIO_NET=y
+CONFIG_VIRTIO_PCI=y
+CONFIG_VIRTIO_PCI_LEGACY=y
+CONFIG_VIRTUALIZATION=y
+CONFIG_VITESSE_PHY=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WLAN_VENDOR_ADMTEK=y
+CONFIG_WLAN_VENDOR_ATH=y
+CONFIG_WLAN_VENDOR_ATMEL=y
+CONFIG_WLAN_VENDOR_BROADCOM=y
+CONFIG_WLAN_VENDOR_CISCO=y
+CONFIG_WLAN_VENDOR_INTEL=y
+CONFIG_WLAN_VENDOR_INTERSIL=y
+CONFIG_WLAN_VENDOR_MARVELL=y
+CONFIG_WLAN_VENDOR_MEDIATEK=y
+CONFIG_WLAN_VENDOR_RALINK=y
+CONFIG_WLAN_VENDOR_REALTEK=y
+CONFIG_WLAN_VENDOR_RSI=y
+CONFIG_WLAN_VENDOR_ST=y
+CONFIG_WLAN_VENDOR_TI=y
+CONFIG_WLAN_VENDOR_ZYDAS=y
+# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set
+CONFIG_XEN=y
+CONFIG_XENFS=y
+CONFIG_XEN_AUTO_XLATE=y
+CONFIG_XEN_BACKEND=y
+CONFIG_XEN_BALLOON=y
+# CONFIG_XEN_BLKDEV_BACKEND is not set
+CONFIG_XEN_BLKDEV_FRONTEND=y
+CONFIG_XEN_COMPAT_XENFS=y
+CONFIG_XEN_DEV_EVTCHN=y
+CONFIG_XEN_DOM0=y
+CONFIG_XEN_EFI=y
+CONFIG_XEN_FBDEV_FRONTEND=y
+CONFIG_XEN_GNTDEV=y
+CONFIG_XEN_GRANT_DEV_ALLOC=y
+# CONFIG_XEN_NETDEV_BACKEND is not set
+CONFIG_XEN_NETDEV_FRONTEND=y
+CONFIG_XEN_PRIVCMD=y
+CONFIG_XEN_SCRUB_PAGES=y
+# CONFIG_XEN_SCSI_FRONTEND is not set
+CONFIG_XEN_SYS_HYPERVISOR=y
+# CONFIG_XEN_WDT is not set
+CONFIG_XEN_XENBUS_FRONTEND=y
+CONFIG_XFRM_ALGO=y
+CONFIG_XFRM_USER=y
+CONFIG_XFS_FS=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_XFS_RT=y
+CONFIG_XOR_BLOCKS=y
+CONFIG_XPS=y
+CONFIG_XZ_DEC_ARM=y
+CONFIG_XZ_DEC_ARMTHUMB=y
+CONFIG_XZ_DEC_BCJ=y
+CONFIG_XZ_DEC_IA64=y
+CONFIG_XZ_DEC_POWERPC=y
+CONFIG_XZ_DEC_SPARC=y
+CONFIG_XZ_DEC_X86=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch b/target/linux/layerscape/patches-4.9/201-config-support-layerscape.patch
new file mode 100644 (file)
index 0000000..0105f59
--- /dev/null
@@ -0,0 +1,532 @@
+From 11edf9c88acea13d1a02901289060263b4027a77 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Mon, 25 Sep 2017 09:52:26 +0800
+Subject: [PATCH] config: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is a integrated patch for layerscape config/makefile support.
+
+Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
+Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ drivers/base/Kconfig                    |   1 +
+ drivers/crypto/Makefile                 |   2 +-
+ drivers/net/ethernet/freescale/Kconfig  |   4 +-
+ drivers/net/ethernet/freescale/Makefile |   2 +
+ drivers/ptp/Kconfig                     |  29 ++++++
+ drivers/rtc/Kconfig                     |   8 ++
+ drivers/rtc/Makefile                    |   1 +
+ drivers/soc/Kconfig                     |   3 +-
+ drivers/soc/fsl/Kconfig                 |  22 +++++
+ drivers/soc/fsl/Kconfig.arm             |  16 ++++
+ drivers/soc/fsl/Makefile                |   4 +
+ drivers/soc/fsl/layerscape/Kconfig      |  10 +++
+ drivers/soc/fsl/layerscape/Makefile     |   1 +
+ drivers/soc/fsl/rcpm.c                  | 154 ++++++++++++++++++++++++++++++++
+ drivers/staging/Kconfig                 |   4 +
+ drivers/staging/Makefile                |   2 +
+ drivers/staging/fsl-dpaa2/Kconfig       |  41 +++++++++
+ drivers/staging/fsl-dpaa2/Makefile      |   9 ++
+ 18 files changed, 309 insertions(+), 4 deletions(-)
+ create mode 100644 drivers/soc/fsl/Kconfig
+ create mode 100644 drivers/soc/fsl/Kconfig.arm
+ create mode 100644 drivers/soc/fsl/layerscape/Kconfig
+ create mode 100644 drivers/soc/fsl/layerscape/Makefile
+ create mode 100644 drivers/soc/fsl/rcpm.c
+ create mode 100644 drivers/staging/fsl-dpaa2/Kconfig
+ create mode 100644 drivers/staging/fsl-dpaa2/Makefile
+
+diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
+index e1c0e2e0..4211a7fd 100644
+--- a/drivers/base/Kconfig
++++ b/drivers/base/Kconfig
+@@ -237,6 +237,7 @@ config GENERIC_CPU_AUTOPROBE
+ config SOC_BUS
+       bool
++      select GLOB
+ source "drivers/base/regmap/Kconfig"
+diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
+index ad7250fa..6d788fd7 100644
+--- a/drivers/crypto/Makefile
++++ b/drivers/crypto/Makefile
+@@ -3,7 +3,7 @@ obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
+ obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
+ obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o
+ obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/
+-obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/
++obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_COMMON) += caam/
+ obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
+ obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
+ obj-$(CONFIG_CRYPTO_DEV_IMGTEC_HASH) += img-hash.o
+diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
+index d1ca45fb..74a2864e 100644
+--- a/drivers/net/ethernet/freescale/Kconfig
++++ b/drivers/net/ethernet/freescale/Kconfig
+@@ -5,7 +5,7 @@
+ config NET_VENDOR_FREESCALE
+       bool "Freescale devices"
+       default y
+-      depends on FSL_SOC || QUICC_ENGINE || CPM1 || CPM2 || PPC_MPC512x || \
++      depends on FSL_SOC || (QUICC_ENGINE && PPC32) || CPM1 || CPM2 || PPC_MPC512x || \
+                  M523x || M527x || M5272 || M528x || M520x || M532x || \
+                  ARCH_MXC || ARCH_MXS || (PPC_MPC52xx && PPC_BESTCOMM) || \
+                  ARCH_LAYERSCAPE
+@@ -93,4 +93,6 @@ config GIANFAR
+         and MPC86xx family of chips, the eTSEC on LS1021A and the FEC
+         on the 8540.
++source "drivers/net/ethernet/freescale/sdk_fman/Kconfig"
++source "drivers/net/ethernet/freescale/sdk_dpaa/Kconfig"
+ endif # NET_VENDOR_FREESCALE
+diff --git a/drivers/net/ethernet/freescale/Makefile b/drivers/net/ethernet/freescale/Makefile
+index cbe21dc7..a5d4405f 100644
+--- a/drivers/net/ethernet/freescale/Makefile
++++ b/drivers/net/ethernet/freescale/Makefile
+@@ -21,4 +21,6 @@ gianfar_driver-objs := gianfar.o \
+ obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
+ ucc_geth_driver-objs := ucc_geth.o ucc_geth_ethtool.o
++obj-$(if $(CONFIG_FSL_SDK_FMAN),y) += sdk_fman/
++obj-$(if $(CONFIG_FSL_SDK_DPAA_ETH),y) += sdk_dpaa/
+ obj-$(CONFIG_FSL_FMAN) += fman/
+diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
+index ee3de342..4c45beda 100644
+--- a/drivers/ptp/Kconfig
++++ b/drivers/ptp/Kconfig
+@@ -39,6 +39,35 @@ config PTP_1588_CLOCK_GIANFAR
+         To compile this driver as a module, choose M here: the module
+         will be called gianfar_ptp.
++config PTP_1588_CLOCK_DPAA
++      tristate "Freescale DPAA as PTP clock"
++      depends on FSL_SDK_DPAA_ETH
++      select PTP_1588_CLOCK
++        select FSL_DPAA_TS
++        default n
++      help
++        This driver adds support for using the DPAA 1588 timer module
++        as a PTP clock. This clock is only useful if your PTP programs are
++        getting hardware time stamps on the PTP Ethernet packets
++        using the SO_TIMESTAMPING API.
++
++        To compile this driver as a module, choose M here: the module
++        will be called dpaa_ptp.
++
++config PTP_1588_CLOCK_DPAA2
++      tristate "Freescale DPAA2 as PTP clock"
++      depends on FSL_DPAA2_ETH
++      select PTP_1588_CLOCK
++      default y
++      help
++        This driver adds support for using the DPAA2 1588 timer module
++        as a PTP clock. This clock is only useful if your PTP programs are
++        getting hardware time stamps on the PTP Ethernet packets
++        using the SO_TIMESTAMPING API.
++
++        To compile this driver as a module, choose M here: the module
++        will be called dpaa2-rtc.
++
+ config PTP_1588_CLOCK_IXP46X
+       tristate "Intel IXP46x as PTP clock"
+       depends on IXP4XX_ETH
+diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
+index 0723c97e..df610dcd 100644
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -414,6 +414,14 @@ config RTC_DRV_PCF85063
+         This driver can also be built as a module. If so, the module
+         will be called rtc-pcf85063.
++config RTC_DRV_PCF85263
++      tristate "NXP PCF85263"
++      help
++        If you say yes here you get support for the PCF85263 RTC chip
++
++        This driver can also be built as a module. If so, the module
++        will be called rtc-pcf85263.
++
+ config RTC_DRV_PCF8563
+       tristate "Philips PCF8563/Epson RTC8564"
+       help
+diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
+index 1ac694a3..7675b8a7 100644
+--- a/drivers/rtc/Makefile
++++ b/drivers/rtc/Makefile
+@@ -111,6 +111,7 @@ obj-$(CONFIG_RTC_DRV_PCF2127)      += rtc-pcf2127.o
+ obj-$(CONFIG_RTC_DRV_PCF50633)        += rtc-pcf50633.o
+ obj-$(CONFIG_RTC_DRV_PCF85063)        += rtc-pcf85063.o
+ obj-$(CONFIG_RTC_DRV_PCF8523) += rtc-pcf8523.o
++obj-$(CONFIG_RTC_DRV_PCF85263)        += rtc-pcf85263.o
+ obj-$(CONFIG_RTC_DRV_PCF8563) += rtc-pcf8563.o
+ obj-$(CONFIG_RTC_DRV_PCF8583) += rtc-pcf8583.o
+ obj-$(CONFIG_RTC_DRV_PIC32)   += rtc-pic32.o
+diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
+index e6e90e80..f31bceb6 100644
+--- a/drivers/soc/Kconfig
++++ b/drivers/soc/Kconfig
+@@ -1,8 +1,7 @@
+ menu "SOC (System On Chip) specific Drivers"
+ source "drivers/soc/bcm/Kconfig"
+-source "drivers/soc/fsl/qbman/Kconfig"
+-source "drivers/soc/fsl/qe/Kconfig"
++source "drivers/soc/fsl/Kconfig"
+ source "drivers/soc/mediatek/Kconfig"
+ source "drivers/soc/qcom/Kconfig"
+ source "drivers/soc/rockchip/Kconfig"
+diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
+new file mode 100644
+index 00000000..d4cd25f1
+--- /dev/null
++++ b/drivers/soc/fsl/Kconfig
+@@ -0,0 +1,22 @@
++#
++# Freescale SOC drivers
++#
++
++source "drivers/soc/fsl/qbman/Kconfig"
++source "drivers/soc/fsl/qe/Kconfig"
++source "drivers/soc/fsl/ls2-console/Kconfig"
++
++config FSL_GUTS
++      bool
++      select SOC_BUS
++      help
++        The global utilities block controls power management, I/O device
++        enabling, power-onreset(POR) configuration monitoring, alternate
++        function selection for multiplexed signals,and clock control.
++        This driver is to manage and access global utilities block.
++        Initially only reading SVR and registering soc device are supported.
++        Other guts accesses, such as reading RCW, should eventually be moved
++        into this driver as well.
++if ARM || ARM64
++source "drivers/soc/fsl/Kconfig.arm"
++endif
+diff --git a/drivers/soc/fsl/Kconfig.arm b/drivers/soc/fsl/Kconfig.arm
+new file mode 100644
+index 00000000..106c9b98
+--- /dev/null
++++ b/drivers/soc/fsl/Kconfig.arm
+@@ -0,0 +1,16 @@
++#
++# Freescale ARM SOC Drivers
++#
++
++config LS_SOC_DRIVERS
++      bool "Layerscape Soc Drivers"
++      depends on ARCH_LAYERSCAPE || SOC_LS1021A
++      default n
++      help
++      Say y here to enable Freescale Layerscape Soc Device Drivers support.
++      The Soc Drivers provides the device driver that is a specific block
++      or feature on Layerscape platform.
++
++if LS_SOC_DRIVERS
++      source "drivers/soc/fsl/layerscape/Kconfig"
++endif
+diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
+index 75e1f533..b8708569 100644
+--- a/drivers/soc/fsl/Makefile
++++ b/drivers/soc/fsl/Makefile
+@@ -5,3 +5,7 @@
+ obj-$(CONFIG_FSL_DPAA)                 += qbman/
+ obj-$(CONFIG_QUICC_ENGINE)            += qe/
+ obj-$(CONFIG_CPM)                     += qe/
++obj-$(CONFIG_FSL_GUTS)                        += guts.o
++obj-$(CONFIG_FSL_LS2_CONSOLE)         += ls2-console/
++obj-$(CONFIG_SUSPEND)                 += rcpm.o
++obj-$(CONFIG_LS_SOC_DRIVERS)          += layerscape/
+diff --git a/drivers/soc/fsl/layerscape/Kconfig b/drivers/soc/fsl/layerscape/Kconfig
+new file mode 100644
+index 00000000..e1373aa1
+--- /dev/null
++++ b/drivers/soc/fsl/layerscape/Kconfig
+@@ -0,0 +1,10 @@
++#
++# Layerscape Soc drivers
++#
++config  FTM_ALARM
++      bool "FTM alarm driver"
++      default n
++      help
++      Say y here to enable FTM alarm support.  The FTM alarm provides
++      alarm functions for wakeup system from deep sleep.  There is only
++      one FTM can be used in ALARM(FTM 0).
+diff --git a/drivers/soc/fsl/layerscape/Makefile b/drivers/soc/fsl/layerscape/Makefile
+new file mode 100644
+index 00000000..6299aa1d
+--- /dev/null
++++ b/drivers/soc/fsl/layerscape/Makefile
+@@ -0,0 +1 @@
++obj-$(CONFIG_FTM_ALARM) += ftm_alarm.o
+diff --git a/drivers/soc/fsl/rcpm.c b/drivers/soc/fsl/rcpm.c
+new file mode 100644
+index 00000000..a6a31c87
+--- /dev/null
++++ b/drivers/soc/fsl/rcpm.c
+@@ -0,0 +1,154 @@
++/*
++ * Run Control and Power Management (RCPM) driver
++ *
++ * Copyright 2016 NXP
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++#define pr_fmt(fmt) "RCPM: %s: " fmt, __func__
++
++#include <linux/kernel.h>
++#include <linux/io.h>
++#include <linux/of_platform.h>
++#include <linux/of_address.h>
++#include <linux/suspend.h>
++
++/* RCPM register offset */
++#define RCPM_IPPDEXPCR0                       0x140
++
++#define RCPM_WAKEUP_CELL_SIZE 2
++
++struct rcpm_config {
++      int ipp_num;
++      int ippdexpcr_offset;
++      u32 ippdexpcr[2];
++      void *rcpm_reg_base;
++};
++
++static struct rcpm_config *rcpm;
++
++static inline void rcpm_reg_write(u32 offset, u32 value)
++{
++      iowrite32be(value, rcpm->rcpm_reg_base + offset);
++}
++
++static inline u32 rcpm_reg_read(u32 offset)
++{
++      return ioread32be(rcpm->rcpm_reg_base + offset);
++}
++
++static void rcpm_wakeup_fixup(struct device *dev, void *data)
++{
++      struct device_node *node = dev ? dev->of_node : NULL;
++      u32 value[RCPM_WAKEUP_CELL_SIZE];
++      int ret, i;
++
++      if (!dev || !node || !device_may_wakeup(dev))
++              return;
++
++      /*
++       * Get the values in the "rcpm-wakeup" property.
++       * Three values are:
++       * The first is a pointer to the RCPM node.
++       * The second is the value of the ippdexpcr0 register.
++       * The third is the value of the ippdexpcr1 register.
++       */
++      ret = of_property_read_u32_array(node, "fsl,rcpm-wakeup",
++                                       value, RCPM_WAKEUP_CELL_SIZE);
++      if (ret)
++              return;
++
++      pr_debug("wakeup source: the device %s\n", node->full_name);
++
++      for (i = 0; i < rcpm->ipp_num; i++)
++              rcpm->ippdexpcr[i] |= value[i + 1];
++}
++
++static int rcpm_suspend_prepare(void)
++{
++      int i;
++
++      BUG_ON(!rcpm);
++
++      for (i = 0; i < rcpm->ipp_num; i++)
++              rcpm->ippdexpcr[i] = 0;
++
++      dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
++
++      for (i = 0; i < rcpm->ipp_num; i++) {
++              rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
++                             rcpm->ippdexpcr[i]);
++              pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
++      }
++
++      return 0;
++}
++
++static int rcpm_suspend_notifier_call(struct notifier_block *bl,
++                                    unsigned long state,
++                                    void *unused)
++{
++      switch (state) {
++      case PM_SUSPEND_PREPARE:
++              rcpm_suspend_prepare();
++              break;
++      }
++
++      return NOTIFY_DONE;
++}
++
++static struct rcpm_config rcpm_default_config = {
++      .ipp_num = 1,
++      .ippdexpcr_offset = RCPM_IPPDEXPCR0,
++};
++
++static const struct of_device_id rcpm_matches[] = {
++      {
++              .compatible = "fsl,qoriq-rcpm-2.1",
++              .data = &rcpm_default_config,
++      },
++      {}
++};
++
++static struct notifier_block rcpm_suspend_notifier = {
++      .notifier_call = rcpm_suspend_notifier_call,
++};
++
++static int __init layerscape_rcpm_init(void)
++{
++      const struct of_device_id *match;
++      struct device_node *np;
++
++      np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
++      if (!np) {
++              pr_err("Can't find the RCPM node.\n");
++              return -EINVAL;
++      }
++
++      if (match->data)
++              rcpm = (struct rcpm_config *)match->data;
++      else
++              return -EINVAL;
++
++      rcpm->rcpm_reg_base = of_iomap(np, 0);
++      of_node_put(np);
++      if (!rcpm->rcpm_reg_base)
++              return -ENOMEM;
++
++      register_pm_notifier(&rcpm_suspend_notifier);
++
++      pr_info("The RCPM driver initialized.\n");
++
++      return 0;
++}
++
++subsys_initcall(layerscape_rcpm_init);
+diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
+index 58a7b350..f8e54860 100644
+--- a/drivers/staging/Kconfig
++++ b/drivers/staging/Kconfig
+@@ -94,6 +94,8 @@ source "drivers/staging/fbtft/Kconfig"
+ source "drivers/staging/fsl-mc/Kconfig"
++source "drivers/staging/fsl-dpaa2/Kconfig"
++
+ source "drivers/staging/wilc1000/Kconfig"
+ source "drivers/staging/most/Kconfig"
+@@ -106,4 +108,6 @@ source "drivers/staging/greybus/Kconfig"
+ source "drivers/staging/vc04_services/Kconfig"
++source "drivers/staging/fsl_qbman/Kconfig"
++
+ endif # STAGING
+diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
+index 2fa9745d..cbd7b089 100644
+--- a/drivers/staging/Makefile
++++ b/drivers/staging/Makefile
+@@ -36,9 +36,11 @@ obj-$(CONFIG_UNISYSSPAR)    += unisys/
+ obj-$(CONFIG_COMMON_CLK_XLNX_CLKWZRD) += clocking-wizard/
+ obj-$(CONFIG_FB_TFT)          += fbtft/
+ obj-$(CONFIG_FSL_MC_BUS)      += fsl-mc/
++obj-$(CONFIG_FSL_DPAA2)               += fsl-dpaa2/
+ obj-$(CONFIG_WILC1000)                += wilc1000/
+ obj-$(CONFIG_MOST)            += most/
+ obj-$(CONFIG_ISDN_I4L)                += i4l/
+ obj-$(CONFIG_KS7010)          += ks7010/
+ obj-$(CONFIG_GREYBUS)         += greybus/
+ obj-$(CONFIG_BCM2708_VCHIQ)   += vc04_services/
++obj-$(CONFIG_FSL_SDK_DPA)     += fsl_qbman/
+diff --git a/drivers/staging/fsl-dpaa2/Kconfig b/drivers/staging/fsl-dpaa2/Kconfig
+new file mode 100644
+index 00000000..8042d9cc
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/Kconfig
+@@ -0,0 +1,41 @@
++#
++# Freescale DataPath Acceleration Architecture Gen2 (DPAA2) drivers
++#
++
++config FSL_DPAA2
++      bool "Freescale DPAA2 devices"
++      depends on FSL_MC_BUS
++      ---help---
++        Build drivers for Freescale DataPath Acceleration
++        Architecture (DPAA2) family of SoCs.
++
++config FSL_DPAA2_ETH
++      tristate "Freescale DPAA2 Ethernet"
++      depends on FSL_DPAA2 && FSL_MC_DPIO
++      ---help---
++        Ethernet driver for Freescale DPAA2 SoCs, using the
++        Freescale MC bus driver
++
++if FSL_DPAA2_ETH
++config FSL_DPAA2_ETH_USE_ERR_QUEUE
++      bool "Enable Rx error queue"
++      default n
++      ---help---
++        Allow Rx error frames to be enqueued on an error queue
++        and processed by the driver (by default they are dropped
++        in hardware).
++        This may impact performance, recommended for debugging
++        purposes only.
++
++# QBMAN_DEBUG requires some additional DPIO APIs
++config FSL_DPAA2_ETH_DEBUGFS
++      depends on DEBUG_FS && FSL_QBMAN_DEBUG
++      bool "Enable debugfs support"
++      default n
++      ---help---
++        Enable advanced statistics through debugfs interface.
++endif
++
++source "drivers/staging/fsl-dpaa2/mac/Kconfig"
++source "drivers/staging/fsl-dpaa2/evb/Kconfig"
++source "drivers/staging/fsl-dpaa2/ethsw/Kconfig"
+diff --git a/drivers/staging/fsl-dpaa2/Makefile b/drivers/staging/fsl-dpaa2/Makefile
+new file mode 100644
+index 00000000..cbaa8c20
+--- /dev/null
++++ b/drivers/staging/fsl-dpaa2/Makefile
+@@ -0,0 +1,9 @@
++#
++# Freescale DataPath Acceleration Architecture Gen2 (DPAA2) drivers
++#
++
++obj-$(CONFIG_FSL_DPAA2_ETH)   += ethernet/
++obj-$(CONFIG_FSL_DPAA2_MAC)   += mac/
++obj-$(CONFIG_FSL_DPAA2_EVB)   += evb/
++obj-$(CONFIG_FSL_DPAA2_ETHSW) += ethsw/
++obj-$(CONFIG_PTP_1588_CLOCK_DPAA2) += rtc/
+-- 
+2.14.1
+
diff --git a/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch b/target/linux/layerscape/patches-4.9/301-arch-support-layerscape.patch
new file mode 100644 (file)
index 0000000..da3dc12
--- /dev/null
@@ -0,0 +1,461 @@
+From 7edaf7ed8fbd5fb50950a4fc8067a9c14557d010 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Mon, 25 Sep 2017 10:03:52 +0800
+Subject: [PATCH] arch: support layerscape
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is a integrated patch for layerscape arch support.
+
+Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
+Signed-off-by: Nipun Gupta <nipun.gupta@nxp.com>
+Signed-off-by: Zhao Qiang <B45475@freescale.com>
+Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
+Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
+Signed-off-by: Pan Jiafei <Jiafei.Pan@nxp.com>
+Signed-off-by: Po Liu <po.liu@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Jianhua Xie <jianhua.xie@nxp.com>
+Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ arch/arm/include/asm/delay.h          | 16 +++++++++
+ arch/arm/include/asm/io.h             | 31 ++++++++++++++++++
+ arch/arm/include/asm/mach/map.h       |  4 +--
+ arch/arm/include/asm/pgtable.h        |  7 ++++
+ arch/arm/kernel/bios32.c              | 43 ++++++++++++++++++++++++
+ arch/arm/mm/dma-mapping.c             |  1 +
+ arch/arm/mm/ioremap.c                 |  7 ++++
+ arch/arm/mm/mmu.c                     |  9 +++++
+ arch/arm64/include/asm/cache.h        |  2 +-
+ arch/arm64/include/asm/io.h           |  2 ++
+ arch/arm64/include/asm/pci.h          |  4 +++
+ arch/arm64/include/asm/pgtable-prot.h |  1 +
+ arch/arm64/include/asm/pgtable.h      |  5 +++
+ arch/arm64/kernel/pci.c               | 62 +++++++++++++++++++++++++++++++++++
+ arch/arm64/mm/dma-mapping.c           |  6 ++++
+ 15 files changed, 197 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/include/asm/delay.h b/arch/arm/include/asm/delay.h
+index b1ce037e..1445b0ca 100644
+--- a/arch/arm/include/asm/delay.h
++++ b/arch/arm/include/asm/delay.h
+@@ -57,6 +57,22 @@ extern void __bad_udelay(void);
+                       __const_udelay((n) * UDELAY_MULT)) :            \
+         __udelay(n))
++#define spin_event_timeout(condition, timeout, delay)                          \
++({                                                                             \
++      typeof(condition) __ret;                                               \
++      int i = 0;                                                             \
++      while (!(__ret = (condition)) && (i++ < timeout)) {                    \
++              if (delay)                                                     \
++                      udelay(delay);                                         \
++              else                                                           \
++                      cpu_relax();                                           \
++              udelay(1);                                                     \
++      }                                                                      \
++      if (!__ret)                                                            \
++              __ret = (condition);                                           \
++      __ret;                                                                 \
++})
++
+ /* Loop-based definitions for assembly code. */
+ extern void __loop_delay(unsigned long loops);
+ extern void __loop_udelay(unsigned long usecs);
+diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
+index 021692c6..172a4f2e 100644
+--- a/arch/arm/include/asm/io.h
++++ b/arch/arm/include/asm/io.h
+@@ -129,6 +129,7 @@ static inline u32 __raw_readl(const volatile void __iomem *addr)
+ #define MT_DEVICE_NONSHARED   1
+ #define MT_DEVICE_CACHED      2
+ #define MT_DEVICE_WC          3
++#define MT_MEMORY_RW_NS               4
+ /*
+  * types 4 onwards can be found in asm/mach/map.h and are undefined
+  * for ioremap
+@@ -220,6 +221,34 @@ extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
+ #endif
+ #endif
++/* access ports */
++#define setbits32(_addr, _v) iowrite32be(ioread32be(_addr) |  (_v), (_addr))
++#define clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
++
++#define setbits16(_addr, _v) iowrite16be(ioread16be(_addr) |  (_v), (_addr))
++#define clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
++
++#define setbits8(_addr, _v) iowrite8(ioread8(_addr) |  (_v), (_addr))
++#define clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
++
++/* Clear and set bits in one shot.  These macros can be used to clear and
++ * set multiple bits in a register using a single read-modify-write.  These
++ * macros can also be used to set a multiple-bit bit pattern using a mask,
++ * by specifying the mask in the 'clear' parameter and the new bit pattern
++ * in the 'set' parameter.
++ */
++
++#define clrsetbits_be32(addr, clear, set) \
++      iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le32(addr, clear, set) \
++      iowrite32le((ioread32le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_be16(addr, clear, set) \
++      iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_le16(addr, clear, set) \
++      iowrite16le((ioread16le(addr) & ~(clear)) | (set), (addr))
++#define clrsetbits_8(addr, clear, set) \
++      iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
++
+ /*
+  *  IO port access primitives
+  *  -------------------------
+@@ -408,6 +437,8 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size);
+ #define ioremap_wc ioremap_wc
+ #define ioremap_wt ioremap_wc
++void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size);
++
+ void iounmap(volatile void __iomem *iomem_cookie);
+ #define iounmap iounmap
+diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
+index 9b7c328f..27f3df7d 100644
+--- a/arch/arm/include/asm/mach/map.h
++++ b/arch/arm/include/asm/mach/map.h
+@@ -21,9 +21,9 @@ struct map_desc {
+       unsigned int type;
+ };
+-/* types 0-3 are defined in asm/io.h */
++/* types 0-4 are defined in asm/io.h */
+ enum {
+-      MT_UNCACHED = 4,
++      MT_UNCACHED = 5,
+       MT_CACHECLEAN,
+       MT_MINICLEAN,
+       MT_LOW_VECTORS,
+diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
+index a8d656d9..4ab57b37 100644
+--- a/arch/arm/include/asm/pgtable.h
++++ b/arch/arm/include/asm/pgtable.h
+@@ -118,6 +118,13 @@ extern pgprot_t           pgprot_s2_device;
+ #define pgprot_noncached(prot) \
+       __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
++#define pgprot_cached(prot) \
++      __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED)
++
++#define pgprot_cached_ns(prot) \
++      __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_DEV_CACHED | \
++                      L_PTE_MT_DEV_NONSHARED)
++
+ #define pgprot_writecombine(prot) \
+       __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
+diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
+index 2f0e0773..d2f4869a 100644
+--- a/arch/arm/kernel/bios32.c
++++ b/arch/arm/kernel/bios32.c
+@@ -11,6 +11,8 @@
+ #include <linux/slab.h>
+ #include <linux/init.h>
+ #include <linux/io.h>
++#include <linux/of_irq.h>
++#include <linux/pcieport_if.h>
+ #include <asm/mach-types.h>
+ #include <asm/mach/map.h>
+@@ -63,6 +65,47 @@ void pcibios_report_status(u_int status_mask, int warn)
+               pcibios_bus_report_status(bus, status_mask, warn);
+ }
++/*
++ * Check device tree if the service interrupts are there
++ */
++int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
++{
++      int ret, count = 0;
++      struct device_node *np = NULL;
++
++      if (dev->bus->dev.of_node)
++              np = dev->bus->dev.of_node;
++
++      if (np == NULL)
++              return 0;
++
++      if (!IS_ENABLED(CONFIG_OF_IRQ))
++              return 0;
++
++      /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
++       * request irq for aer
++       */
++      if (mask & PCIE_PORT_SERVICE_AER) {
++              ret = of_irq_get_byname(np, "aer");
++              if (ret > 0) {
++                      irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
++                      count++;
++              }
++      }
++
++      if (mask & PCIE_PORT_SERVICE_PME) {
++              ret = of_irq_get_byname(np, "pme");
++              if (ret > 0) {
++                      irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
++                      count++;
++              }
++      }
++
++      /* TODO: add more service interrupts if there it is in the device tree*/
++
++      return count;
++}
++
+ /*
+  * We don't use this to fix the device, but initialisation of it.
+  * It's not the correct use for this, but it works.
+diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
+index ab771000..9b5f4465 100644
+--- a/arch/arm/mm/dma-mapping.c
++++ b/arch/arm/mm/dma-mapping.c
+@@ -2392,6 +2392,7 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+       set_dma_ops(dev, dma_ops);
+ }
++EXPORT_SYMBOL(arch_setup_dma_ops);
+ void arch_teardown_dma_ops(struct device *dev)
+ {
+diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
+index ff0eed23..2f2f4269 100644
+--- a/arch/arm/mm/ioremap.c
++++ b/arch/arm/mm/ioremap.c
+@@ -398,6 +398,13 @@ void __iomem *ioremap_wc(resource_size_t res_cookie, size_t size)
+ }
+ EXPORT_SYMBOL(ioremap_wc);
++void __iomem *ioremap_cache_ns(resource_size_t res_cookie, size_t size)
++{
++      return arch_ioremap_caller(res_cookie, size, MT_MEMORY_RW_NS,
++                                 __builtin_return_address(0));
++}
++EXPORT_SYMBOL(ioremap_cache_ns);
++
+ /*
+  * Remap an arbitrary physical address space into the kernel virtual
+  * address space as memory. Needed when the kernel wants to execute
+diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
+index f7c74135..4a2fb704 100644
+--- a/arch/arm/mm/mmu.c
++++ b/arch/arm/mm/mmu.c
+@@ -313,6 +313,13 @@ static struct mem_type mem_types[] __ro_after_init = {
+               .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
+               .domain    = DOMAIN_KERNEL,
+       },
++      [MT_MEMORY_RW_NS] = {
++              .prot_pte  = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
++                           L_PTE_XN,
++              .prot_l1   = PMD_TYPE_TABLE,
++              .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_XN,
++              .domain    = DOMAIN_KERNEL,
++      },
+       [MT_ROM] = {
+               .prot_sect = PMD_TYPE_SECT,
+               .domain    = DOMAIN_KERNEL,
+@@ -644,6 +651,7 @@ static void __init build_mem_type_table(void)
+       }
+       kern_pgprot |= PTE_EXT_AF;
+       vecs_pgprot |= PTE_EXT_AF;
++      mem_types[MT_MEMORY_RW_NS].prot_pte |= PTE_EXT_AF | cp->pte;
+       /*
+        * Set PXN for user mappings
+@@ -672,6 +680,7 @@ static void __init build_mem_type_table(void)
+       mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
+       mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
+       mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
++      mem_types[MT_MEMORY_RW_NS].prot_sect |= ecc_mask | cp->pmd;
+       mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
+       mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
+       mem_types[MT_ROM].prot_sect |= cp->pmd;
+diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
+index 5082b30b..bde44993 100644
+--- a/arch/arm64/include/asm/cache.h
++++ b/arch/arm64/include/asm/cache.h
+@@ -18,7 +18,7 @@
+ #include <asm/cachetype.h>
+-#define L1_CACHE_SHIFT                7
++#define L1_CACHE_SHIFT                6
+ #define L1_CACHE_BYTES                (1 << L1_CACHE_SHIFT)
+ /*
+diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
+index 0bba427b..36c1fbf3 100644
+--- a/arch/arm64/include/asm/io.h
++++ b/arch/arm64/include/asm/io.h
+@@ -171,6 +171,8 @@ extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size);
+ #define ioremap_nocache(addr, size)   __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
+ #define ioremap_wc(addr, size)                __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
+ #define ioremap_wt(addr, size)                __ioremap((addr), (size), __pgprot(PROT_DEVICE_nGnRE))
++#define ioremap_cache_ns(addr, size)   __ioremap((addr), (size), \
++                                                __pgprot(PROT_NORMAL_NS))
+ #define iounmap                               __iounmap
+ /*
+diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
+index b9a7ba9c..8a189159 100644
+--- a/arch/arm64/include/asm/pci.h
++++ b/arch/arm64/include/asm/pci.h
+@@ -31,6 +31,10 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
+       return -ENODEV;
+ }
++#define HAVE_PCI_MMAP
++extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
++                             enum pci_mmap_state mmap_state,
++                             int write_combine);
+ static inline int pci_proc_domain(struct pci_bus *bus)
+ {
+       return 1;
+diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
+index 2142c772..cdf8b25d 100644
+--- a/arch/arm64/include/asm/pgtable-prot.h
++++ b/arch/arm64/include/asm/pgtable-prot.h
+@@ -42,6 +42,7 @@
+ #define PROT_NORMAL_NC                (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_NC))
+ #define PROT_NORMAL_WT                (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL_WT))
+ #define PROT_NORMAL           (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
++#define PROT_NORMAL_NS         (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL))
+ #define PROT_SECT_DEVICE_nGnRE        (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+ #define PROT_SECT_NORMAL      (PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_NORMAL))
+diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
+index 61e21401..b8c876fb 100644
+--- a/arch/arm64/include/asm/pgtable.h
++++ b/arch/arm64/include/asm/pgtable.h
+@@ -356,6 +356,11 @@ static inline int pmd_protnone(pmd_t pmd)
+       __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRnE) | PTE_PXN | PTE_UXN)
+ #define pgprot_writecombine(prot) \
+       __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC) | PTE_PXN | PTE_UXN)
++#define pgprot_cached(prot) \
++      __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
++                      PTE_PXN | PTE_UXN)
++#define pgprot_cached_ns(prot) \
++      __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
+ #define pgprot_device(prot) \
+       __pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
+ #define __HAVE_PHYS_MEM_ACCESS_PROT
+diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
+index 409abc45..0568ec3a 100644
+--- a/arch/arm64/kernel/pci.c
++++ b/arch/arm64/kernel/pci.c
+@@ -17,6 +17,8 @@
+ #include <linux/mm.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
++#include <linux/of_irq.h>
++#include <linux/pcieport_if.h>
+ #include <linux/pci.h>
+ #include <linux/pci-acpi.h>
+ #include <linux/pci-ecam.h>
+@@ -54,6 +56,66 @@ int pcibios_alloc_irq(struct pci_dev *dev)
+       return 0;
+ }
++/*
++ * Check device tree if the service interrupts are there
++ */
++int pcibios_check_service_irqs(struct pci_dev *dev, int *irqs, int mask)
++{
++      int ret, count = 0;
++      struct device_node *np = NULL;
++
++      if (dev->bus->dev.of_node)
++              np = dev->bus->dev.of_node;
++
++      if (np == NULL)
++              return 0;
++
++      if (!IS_ENABLED(CONFIG_OF_IRQ))
++              return 0;
++
++      /* If root port doesn't support MSI/MSI-X/INTx in RC mode,
++       * request irq for aer
++       */
++      if (mask & PCIE_PORT_SERVICE_AER) {
++              ret = of_irq_get_byname(np, "aer");
++              if (ret > 0) {
++                      irqs[PCIE_PORT_SERVICE_AER_SHIFT] = ret;
++                      count++;
++              }
++      }
++
++      if (mask & PCIE_PORT_SERVICE_PME) {
++              ret = of_irq_get_byname(np, "pme");
++              if (ret > 0) {
++                      irqs[PCIE_PORT_SERVICE_PME_SHIFT] = ret;
++                      count++;
++              }
++      }
++
++      /* TODO: add more service interrupts if there it is in the device tree*/
++
++      return count;
++}
++
++int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
++                      enum pci_mmap_state mmap_state, int write_combine)
++{
++      if (mmap_state == pci_mmap_io)
++              return -EINVAL;
++
++      /*
++       * Mark this as IO
++       */
++      vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
++
++      if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
++                           vma->vm_end - vma->vm_start,
++                           vma->vm_page_prot))
++              return -EAGAIN;
++
++      return 0;
++}
++
+ /*
+  * raw_pci_read/write - Platform-specific PCI config space access.
+  */
+diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
+index b5bf46ce..1ef0d6df 100644
+--- a/arch/arm64/mm/dma-mapping.c
++++ b/arch/arm64/mm/dma-mapping.c
+@@ -30,6 +30,7 @@
+ #include <linux/swiotlb.h>
+ #include <asm/cacheflush.h>
++#include <../../../drivers/staging/fsl-mc/include/mc-bus.h>
+ static int swiotlb __ro_after_init;
+@@ -917,6 +918,10 @@ static int __init __iommu_dma_init(void)
+ #ifdef CONFIG_PCI
+       if (!ret)
+               ret = register_iommu_dma_ops_notifier(&pci_bus_type);
++#endif
++#ifdef CONFIG_FSL_MC_BUS
++      if (!ret)
++              ret = register_iommu_dma_ops_notifier(&fsl_mc_bus_type);
+ #endif
+       return ret;
+ }
+@@ -971,3 +976,4 @@ void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
+       dev->archdata.dma_coherent = coherent;
+       __iommu_setup_dma_ops(dev, dma_base, size, iommu);
+ }
++EXPORT_SYMBOL(arch_setup_dma_ops);
+-- 
+2.14.1
+
diff --git a/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch b/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch
new file mode 100644 (file)
index 0000000..c820c9f
--- /dev/null
@@ -0,0 +1,10085 @@
+From 2b2e3b9a0d2abf276b40843f75d97b623e4ee109 Mon Sep 17 00:00:00 2001
+From: Yangbo Lu <yangbo.lu@nxp.com>
+Date: Mon, 25 Sep 2017 10:02:10 +0800
+Subject: [PATCH] dts: support layercape
+
+This is a integrated patch for layerscape dts support.
+
+Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com>
+Signed-off-by: Alison Wang <b18965@freescale.com>
+Signed-off-by: Li Yang <leoyang.li@nxp.com>
+Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
+Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
+Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com>
+Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
+Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
+Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
+Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
+Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>
+Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
+Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
+Signed-off-by: Changming Huang <jerry.huang@nxp.com>
+Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
+Signed-off-by: Meng Yi <meng.yi@nxp.com>
+Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ arch/arm/boot/dts/alpine.dtsi                      |   2 +-
+ arch/arm/boot/dts/axm55xx.dtsi                     |   2 +-
+ arch/arm/boot/dts/ecx-2000.dts                     |   2 +-
+ arch/arm/boot/dts/imx6ul.dtsi                      |   4 +-
+ arch/arm/boot/dts/keystone.dtsi                    |   4 +-
+ arch/arm/boot/dts/ls1021a-qds.dts                  |  13 +
+ arch/arm/boot/dts/ls1021a-twr.dts                  |  13 +
+ arch/arm/boot/dts/ls1021a.dtsi                     | 155 ++--
+ arch/arm/boot/dts/mt6580.dtsi                      |   2 +-
+ arch/arm/boot/dts/mt6589.dtsi                      |   2 +-
+ arch/arm/boot/dts/mt8127.dtsi                      |   2 +-
+ arch/arm/boot/dts/mt8135.dtsi                      |   2 +-
+ arch/arm/boot/dts/rk3288.dtsi                      |   2 +-
+ arch/arm/boot/dts/sun6i-a31.dtsi                   |   2 +-
+ arch/arm/boot/dts/sun7i-a20.dtsi                   |   4 +-
+ arch/arm/boot/dts/sun8i-a23-a33.dtsi               |   2 +-
+ arch/arm/boot/dts/sun9i-a80.dtsi                   |   2 +-
+ arch/arm64/boot/dts/freescale/Makefile             |  16 +
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 134 +++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts  | 155 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts  |  91 +++
+ arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi     | 517 ++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi |  45 +
+ .../boot/dts/freescale/fsl-ls1043a-qds-sdk.dts     |  69 ++
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts  | 171 +++-
+ .../boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts     |  69 ++
+ .../boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts  | 117 +++
+ arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts  | 113 ++-
+ arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi     | 302 ++++++-
+ arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi |  48 ++
+ .../boot/dts/freescale/fsl-ls1046a-qds-sdk.dts     | 109 +++
+ arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts  | 363 ++++++++
+ .../boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts     |  76 ++
+ .../boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts  | 110 +++
+ arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts  | 218 +++++
+ arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi     | 793 ++++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts  | 173 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts  | 236 ++++++
+ arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi     | 816 ++++++++++++++++++
+ arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts  | 191 ++---
+ arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts  | 169 ++--
+ arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts |   9 +-
+ arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi     | 763 +++--------------
+ arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts  | 161 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts  | 162 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts  | 140 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi     | 195 +++++
+ arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi | 198 +++++
+ arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 161 ++++
+ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi     | 910 +++++++++++++++++++++
+ .../boot/dts/freescale/qoriq-bman1-portals.dtsi    |  81 ++
+ arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi  |  66 ++
+ .../boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi    |  43 +
+ .../boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi    |  43 +
+ .../boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi     |  42 +
+ .../boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi     |  42 +
+ .../boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi     |  42 +
+ .../boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi     |  42 +
+ .../boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi     |  42 +
+ .../boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi     |  42 +
+ .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi      |  47 ++
+ arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi   | 130 +++
+ .../boot/dts/freescale/qoriq-qman1-portals.dtsi    | 104 +++
+ arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi |  10 +
+ arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi |   4 +-
+ arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi |   4 +-
+ 66 files changed, 7778 insertions(+), 1021 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman1-portals.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi
+ create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman1-portals.dtsi
+
+diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi
+index db8752fc..d0eefc3b 100644
+--- a/arch/arm/boot/dts/alpine.dtsi
++++ b/arch/arm/boot/dts/alpine.dtsi
+@@ -93,7 +93,7 @@
+                       interrupt-controller;
+                       reg = <0x0 0xfb001000 0x0 0x1000>,
+                             <0x0 0xfb002000 0x0 0x2000>,
+-                            <0x0 0xfb004000 0x0 0x1000>,
++                            <0x0 0xfb004000 0x0 0x2000>,
+                             <0x0 0xfb006000 0x0 0x2000>;
+                       interrupts =
+                               <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
+index a9d6d593..47799f59 100644
+--- a/arch/arm/boot/dts/axm55xx.dtsi
++++ b/arch/arm/boot/dts/axm55xx.dtsi
+@@ -62,7 +62,7 @@
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x20 0x01001000 0 0x1000>,
+-                    <0x20 0x01002000 0 0x1000>,
++                    <0x20 0x01002000 0 0x2000>,
+                     <0x20 0x01004000 0 0x2000>,
+                     <0x20 0x01006000 0 0x2000>;
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+diff --git a/arch/arm/boot/dts/ecx-2000.dts b/arch/arm/boot/dts/ecx-2000.dts
+index 2ccbb57f..c15e7e0c 100644
+--- a/arch/arm/boot/dts/ecx-2000.dts
++++ b/arch/arm/boot/dts/ecx-2000.dts
+@@ -99,7 +99,7 @@
+                       interrupt-controller;
+                       interrupts = <1 9 0xf04>;
+                       reg = <0xfff11000 0x1000>,
+-                            <0xfff12000 0x1000>,
++                            <0xfff12000 0x2000>,
+                             <0xfff14000 0x2000>,
+                             <0xfff16000 0x2000>;
+               };
+diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
+index c5c05fdc..c1396873 100644
+--- a/arch/arm/boot/dts/imx6ul.dtsi
++++ b/arch/arm/boot/dts/imx6ul.dtsi
+@@ -89,11 +89,11 @@
+       };
+       intc: interrupt-controller@00a01000 {
+-              compatible = "arm,cortex-a7-gic";
++              compatible = "arm,gic-400", "arm,cortex-a7-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x00a01000 0x1000>,
+-                    <0x00a02000 0x1000>,
++                    <0x00a02000 0x2000>,
+                     <0x00a04000 0x2000>,
+                     <0x00a06000 0x2000>;
+       };
+diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
+index 02708ba2..e30c83fc 100644
+--- a/arch/arm/boot/dts/keystone.dtsi
++++ b/arch/arm/boot/dts/keystone.dtsi
+@@ -30,12 +30,12 @@
+       };
+       gic: interrupt-controller {
+-              compatible = "arm,cortex-a15-gic";
++              compatible = "arm,gic-400", "arm,cortex-a15-gic";
+               #interrupt-cells = <3>;
+               interrupt-controller;
+               reg = <0x0 0x02561000 0x0 0x1000>,
+                     <0x0 0x02562000 0x0 0x2000>,
+-                    <0x0 0x02564000 0x0 0x1000>,
++                    <0x0 0x02564000 0x0 0x2000>,
+                     <0x0 0x02566000 0x0 0x2000>;
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+                               IRQ_TYPE_LEVEL_HIGH)>;
+diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts
+index 94087531..5611a9c9 100644
+--- a/arch/arm/boot/dts/ls1021a-qds.dts
++++ b/arch/arm/boot/dts/ls1021a-qds.dts
+@@ -124,6 +124,19 @@
+       };
+ };
++&qspi {
++      num-cs = <2>;
++      status = "okay";
++
++      qflash0: s25fl128s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
+ &enet0 {
+       tbi-handle = <&tbi0>;
+       phy-handle = <&sgmii_phy1c>;
+diff --git a/arch/arm/boot/dts/ls1021a-twr.dts b/arch/arm/boot/dts/ls1021a-twr.dts
+index a8b148ad..907e5392 100644
+--- a/arch/arm/boot/dts/ls1021a-twr.dts
++++ b/arch/arm/boot/dts/ls1021a-twr.dts
+@@ -142,6 +142,19 @@
+       };
+ };
++&qspi {
++      num-cs = <2>;
++      status = "okay";
++
++      qflash0: n25q128a13@0 {
++              compatible = "n25q128a13", "jedec,spi-nor";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
+ &enet0 {
+       tbi-handle = <&tbi1>;
+       phy-handle = <&sgmii_phy2>;
+diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
+index 368e2193..def82fef 100644
+--- a/arch/arm/boot/dts/ls1021a.dtsi
++++ b/arch/arm/boot/dts/ls1021a.dtsi
+@@ -74,17 +74,24 @@
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0xf00>;
+-                      clocks = <&cluster1_clk>;
++                      clocks = <&clockgen 1 0>;
+               };
+               cpu@f01 {
+                       compatible = "arm,cortex-a7";
+                       device_type = "cpu";
+                       reg = <0xf01>;
+-                      clocks = <&cluster1_clk>;
++                      clocks = <&clockgen 1 0>;
+               };
+       };
++      sysclk: sysclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              clock-frequency = <100000000>;
++              clock-output-names = "sysclk";
++      };
++
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -108,11 +115,11 @@
+               ranges;
+               gic: interrupt-controller@1400000 {
+-                      compatible = "arm,cortex-a7-gic";
++                      compatible = "arm,gic-400", "arm,cortex-a7-gic";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x0 0x1401000 0x0 0x1000>,
+-                            <0x0 0x1402000 0x0 0x1000>,
++                            <0x0 0x1402000 0x0 0x2000>,
+                             <0x0 0x1404000 0x0 0x2000>,
+                             <0x0 0x1406000 0x0 0x2000>;
+                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
+@@ -120,14 +127,14 @@
+               };
+               msi1: msi-controller@1570e00 {
+-                      compatible = "fsl,1s1021a-msi";
++                      compatible = "fsl,ls1021a-msi";
+                       reg = <0x0 0x1570e00 0x0 0x8>;
+                       msi-controller;
+                       interrupts =  <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+               };
+               msi2: msi-controller@1570e08 {
+-                      compatible = "fsl,1s1021a-msi";
++                      compatible = "fsl,ls1021a-msi";
+                       reg = <0x0 0x1570e08 0x0 0x8>;
+                       msi-controller;
+                       interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+@@ -137,11 +144,12 @@
+                       compatible = "fsl,ifc", "simple-bus";
+                       reg = <0x0 0x1530000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++                      big-endian;
+               };
+               dcfg: dcfg@1ee0000 {
+                       compatible = "fsl,ls1021a-dcfg", "syscon";
+-                      reg = <0x0 0x1ee0000 0x0 0x10000>;
++                      reg = <0x0 0x1ee0000 0x0 0x1000>;
+                       big-endian;
+               };
+@@ -163,7 +171,7 @@
+                             <0x0 0x20220520 0x0 0x4>;
+                       reg-names = "ahci", "sata-ecc";
+                       interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       dma-coherent;
+                       status = "disabled";
+               };
+@@ -214,41 +222,10 @@
+               };
+               clockgen: clocking@1ee1000 {
+-                      #address-cells = <1>;
+-                      #size-cells = <1>;
+-                      ranges = <0x0 0x0 0x1ee1000 0x10000>;
+-
+-                      sysclk: sysclk {
+-                              compatible = "fixed-clock";
+-                              #clock-cells = <0>;
+-                              clock-output-names = "sysclk";
+-                      };
+-
+-                      cga_pll1: pll@800 {
+-                              compatible = "fsl,qoriq-core-pll-2.0";
+-                              #clock-cells = <1>;
+-                              reg = <0x800 0x10>;
+-                              clocks = <&sysclk>;
+-                              clock-output-names = "cga-pll1", "cga-pll1-div2",
+-                                                   "cga-pll1-div4";
+-                      };
+-
+-                      platform_clk: pll@c00 {
+-                              compatible = "fsl,qoriq-core-pll-2.0";
+-                              #clock-cells = <1>;
+-                              reg = <0xc00 0x10>;
+-                              clocks = <&sysclk>;
+-                              clock-output-names = "platform-clk", "platform-clk-div2";
+-                      };
+-
+-                      cluster1_clk: clk0c0@0 {
+-                              compatible = "fsl,qoriq-core-mux-2.0";
+-                              #clock-cells = <0>;
+-                              reg = <0x0 0x10>;
+-                              clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
+-                              clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
+-                              clock-output-names = "cluster1-clk";
+-                      };
++                      compatible = "fsl,ls1021a-clockgen";
++                      reg = <0x0 0x1ee1000 0x0 0x1000>;
++                      #clock-cells = <2>;
++                      clocks = <&sysclk>;
+               };
+               dspi0: dspi@2100000 {
+@@ -258,7 +235,7 @@
+                       reg = <0x0 0x2100000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "dspi";
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       spi-num-chipselects = <6>;
+                       big-endian;
+                       status = "disabled";
+@@ -271,12 +248,27 @@
+                       reg = <0x0 0x2110000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "dspi";
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       spi-num-chipselects = <6>;
+                       big-endian;
+                       status = "disabled";
+               };
++              qspi: quadspi@1550000 {
++                      compatible = "fsl,ls1021a-qspi";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x1550000 0x0 0x10000>,
++                              <0x0 0x40000000 0x0 0x4000000>;
++                      reg-names = "QuadSPI", "QuadSPI-memory";
++                      interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
++                      clock-names = "qspi_en", "qspi";
++                      clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++                      big-endian;
++                      amba-base = <0x40000000>;
++                      status = "disabled";
++              };
++
+               i2c0: i2c@2180000 {
+                       compatible = "fsl,vf610-i2c";
+                       #address-cells = <1>;
+@@ -284,7 +276,7 @@
+                       reg = <0x0 0x2180000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "i2c";
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       status = "disabled";
+               };
+@@ -295,7 +287,7 @@
+                       reg = <0x0 0x2190000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "i2c";
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       status = "disabled";
+               };
+@@ -306,7 +298,7 @@
+                       reg = <0x0 0x21a0000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "i2c";
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       status = "disabled";
+               };
+@@ -399,7 +391,7 @@
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2960000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+@@ -408,7 +400,7 @@
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2970000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+@@ -417,7 +409,7 @@
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2980000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+@@ -426,7 +418,7 @@
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2990000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
+@@ -435,16 +427,26 @@
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x29a0000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       clock-names = "ipg";
+                       status = "disabled";
+               };
++              ftm0: ftm0@29d0000 {
++                      compatible = "fsl,ftm-alarm";
++                      reg = <0x0 0x29d0000 0x0 0x10000>,
++                            <0x0 0x1ee2140 0x0 0x4>;
++                      reg-names = "ftm", "FlexTimer1";
++                      interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
++                      big-endian;
++                      status = "okay";
++              };
++
+               wdog0: watchdog@2ad0000 {
+                       compatible = "fsl,imx21-wdt";
+                       reg = <0x0 0x2ad0000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>;
+                       clock-names = "wdog-en";
+                       big-endian;
+               };
+@@ -454,8 +456,8 @@
+                       compatible = "fsl,vf610-sai";
+                       reg = <0x0 0x2b50000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>, <&platform_clk 1>,
+-                               <&platform_clk 1>, <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>, <&clockgen 4 1>,
++                               <&clockgen 4 1>, <&clockgen 4 1>;
+                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                       dma-names = "tx", "rx";
+                       dmas = <&edma0 1 47>,
+@@ -468,8 +470,8 @@
+                       compatible = "fsl,vf610-sai";
+                       reg = <0x0 0x2b60000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 1>, <&platform_clk 1>,
+-                               <&platform_clk 1>, <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>, <&clockgen 4 1>,
++                               <&clockgen 4 1>, <&clockgen 4 1>;
+                       clock-names = "bus", "mclk1", "mclk2", "mclk3";
+                       dma-names = "tx", "rx";
+                       dmas = <&edma0 1 45>,
+@@ -489,16 +491,31 @@
+                       dma-channels = <32>;
+                       big-endian;
+                       clock-names = "dmamux0", "dmamux1";
+-                      clocks = <&platform_clk 1>,
+-                               <&platform_clk 1>;
++                      clocks = <&clockgen 4 1>,
++                               <&clockgen 4 1>;
++              };
++
++              qdma: qdma@8390000 {
++                      compatible = "fsl,ls1021a-qdma";
++                      reg = <0x0 0x8388000 0x0 0x1000>, /* Controller regs */
++                            <0x0 0x8389000 0x0 0x1000>, /* Status regs */
++                            <0x0 0x838a000 0x0 0x2000>; /* Block regs */
++                      interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
++                      interrupt-names = "qdma-error", "qdma-queue";
++                      channels = <8>;
++                      queues = <2>;
++                      status-sizes = <64>;
++                      queue-sizes = <64 64>;
++                      big-endian;
+               };
+               dcu: dcu@2ce0000 {
+                       compatible = "fsl,ls1021a-dcu";
+                       reg = <0x0 0x2ce0000 0x0 0x10000>;
+                       interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+-                      clocks = <&platform_clk 0>,
+-                              <&platform_clk 0>;
++                      clocks = <&clockgen 4 0>,
++                              <&clockgen 4 0>;
+                       clock-names = "dcu", "pix";
+                       big-endian;
+                       status = "disabled";
+@@ -626,6 +643,8 @@
+                       interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+                       dr_mode = "host";
+                       snps,quirk-frame-length-adjustment = <0x20>;
++                      configure-gfladj;
++                      dma-coherent;
+                       snps,dis_rxdet_inp3_quirk;
+               };
+@@ -634,7 +653,9 @@
+                       reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
+                              0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg-names = "regs", "config";
+-                      interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
++                      interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
++                                         <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++                      interrupt-names = "pme", "aer";
+                       fsl,pcie-scfg = <&scfg 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+@@ -643,7 +664,7 @@
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-                      msi-parent = <&msi1>;
++                      msi-parent = <&msi1>, <&msi2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0000 0 0 1 &gic GIC_SPI 91  IRQ_TYPE_LEVEL_HIGH>,
+@@ -657,7 +678,9 @@
+                       reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
+                              0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg-names = "regs", "config";
+-                      interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
++                      interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
++                                         <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++                      interrupt-names = "pme", "aer";
+                       fsl,pcie-scfg = <&scfg 1>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+@@ -666,7 +689,7 @@
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-                      msi-parent = <&msi2>;
++                      msi-parent = <&msi1>, <&msi2>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0000 0 0 1 &gic GIC_SPI 92  IRQ_TYPE_LEVEL_HIGH>,
+diff --git a/arch/arm/boot/dts/mt6580.dtsi b/arch/arm/boot/dts/mt6580.dtsi
+index 06fdf6c2..a349dba5 100644
+--- a/arch/arm/boot/dts/mt6580.dtsi
++++ b/arch/arm/boot/dts/mt6580.dtsi
+@@ -91,7 +91,7 @@
+               #interrupt-cells = <3>;
+               interrupt-parent = <&gic>;
+               reg = <0x10211000 0x1000>,
+-                    <0x10212000 0x1000>,
++                    <0x10212000 0x2000>,
+                     <0x10214000 0x2000>,
+                     <0x10216000 0x2000>;
+       };
+diff --git a/arch/arm/boot/dts/mt6589.dtsi b/arch/arm/boot/dts/mt6589.dtsi
+index 88b3cb12..0d6f60af 100644
+--- a/arch/arm/boot/dts/mt6589.dtsi
++++ b/arch/arm/boot/dts/mt6589.dtsi
+@@ -102,7 +102,7 @@
+                       #interrupt-cells = <3>;
+                       interrupt-parent = <&gic>;
+                       reg = <0x10211000 0x1000>,
+-                            <0x10212000 0x1000>,
++                            <0x10212000 0x2000>,
+                             <0x10214000 0x2000>,
+                             <0x10216000 0x2000>;
+               };
+diff --git a/arch/arm/boot/dts/mt8127.dtsi b/arch/arm/boot/dts/mt8127.dtsi
+index 52086c80..916c095d 100644
+--- a/arch/arm/boot/dts/mt8127.dtsi
++++ b/arch/arm/boot/dts/mt8127.dtsi
+@@ -129,7 +129,7 @@
+                       #interrupt-cells = <3>;
+                       interrupt-parent = <&gic>;
+                       reg = <0 0x10211000 0 0x1000>,
+-                            <0 0x10212000 0 0x1000>,
++                            <0 0x10212000 0 0x2000>,
+                             <0 0x10214000 0 0x2000>,
+                             <0 0x10216000 0 0x2000>;
+               };
+diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi
+index 1d7f92bd..a97b4ee4 100644
+--- a/arch/arm/boot/dts/mt8135.dtsi
++++ b/arch/arm/boot/dts/mt8135.dtsi
+@@ -221,7 +221,7 @@
+                       #interrupt-cells = <3>;
+                       interrupt-parent = <&gic>;
+                       reg = <0 0x10211000 0 0x1000>,
+-                            <0 0x10212000 0 0x1000>,
++                            <0 0x10212000 0 0x2000>,
+                             <0 0x10214000 0 0x2000>,
+                             <0 0x10216000 0 0x2000>;
+               };
+diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
+index 17ec2e2d..559fc549 100644
+--- a/arch/arm/boot/dts/rk3288.dtsi
++++ b/arch/arm/boot/dts/rk3288.dtsi
+@@ -1109,7 +1109,7 @@
+               #address-cells = <0>;
+               reg = <0xffc01000 0x1000>,
+-                    <0xffc02000 0x1000>,
++                    <0xffc02000 0x2000>,
+                     <0xffc04000 0x2000>,
+                     <0xffc06000 0x2000>;
+               interrupts = <GIC_PPI 9 0xf04>;
+diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
+index ce196045..97f28399 100644
+--- a/arch/arm/boot/dts/sun6i-a31.dtsi
++++ b/arch/arm/boot/dts/sun6i-a31.dtsi
+@@ -791,7 +791,7 @@
+               gic: interrupt-controller@01c81000 {
+                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       reg = <0x01c81000 0x1000>,
+-                            <0x01c82000 0x1000>,
++                            <0x01c82000 0x2000>,
+                             <0x01c84000 0x2000>,
+                             <0x01c86000 0x2000>;
+                       interrupt-controller;
+diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
+index 94cf5a1c..81e5a44c 100644
+--- a/arch/arm/boot/dts/sun7i-a20.dtsi
++++ b/arch/arm/boot/dts/sun7i-a20.dtsi
+@@ -1685,9 +1685,9 @@
+               };
+               gic: interrupt-controller@01c81000 {
+-                      compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
++                      compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       reg = <0x01c81000 0x1000>,
+-                            <0x01c82000 0x1000>,
++                            <0x01c82000 0x2000>,
+                             <0x01c84000 0x2000>,
+                             <0x01c86000 0x2000>;
+                       interrupt-controller;
+diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+index 300a1bd5..cdff5888 100644
+--- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi
++++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi
+@@ -488,7 +488,7 @@
+               gic: interrupt-controller@01c81000 {
+                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       reg = <0x01c81000 0x1000>,
+-                            <0x01c82000 0x1000>,
++                            <0x01c82000 0x2000>,
+                             <0x01c84000 0x2000>,
+                             <0x01c86000 0x2000>;
+                       interrupt-controller;
+diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi
+index 3c5214cb..ba7e7c71 100644
+--- a/arch/arm/boot/dts/sun9i-a80.dtsi
++++ b/arch/arm/boot/dts/sun9i-a80.dtsi
+@@ -613,7 +613,7 @@
+               gic: interrupt-controller@01c41000 {
+                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+                       reg = <0x01c41000 0x1000>,
+-                            <0x01c42000 0x1000>,
++                            <0x01c42000 0x2000>,
+                             <0x01c44000 0x2000>,
+                             <0x01c46000 0x2000>;
+                       interrupt-controller;
+diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
+index 1b7783db..2d7986a1 100644
+--- a/arch/arm64/boot/dts/freescale/Makefile
++++ b/arch/arm64/boot/dts/freescale/Makefile
+@@ -1,8 +1,24 @@
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb
+ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
+  
+ always                := $(dtb-y)
+ subdir-y      := $(dts-dirs)
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+new file mode 100644
+index 00000000..e1274c18
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
+@@ -0,0 +1,134 @@
++/*
++ * Device Tree file for Freescale LS1012A Freedom Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++      model = "LS1012A Freedom Board";
++      compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
++
++      sys_mclk: clock-mclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              clock-frequency = <25000000>;
++      };
++
++      reg_1p8v: regulator-1p8v {
++              compatible = "regulator-fixed";
++              regulator-name = "1P8V";
++              regulator-min-microvolt = <1800000>;
++              regulator-max-microvolt = <1800000>;
++              regulator-always-on;
++      };
++
++      sound {
++              compatible = "simple-audio-card";
++              simple-audio-card,format = "i2s";
++              simple-audio-card,widgets =
++                      "Microphone", "Microphone Jack",
++                      "Headphone", "Headphone Jack",
++                      "Speaker", "Speaker Ext",
++                      "Line", "Line In Jack";
++              simple-audio-card,routing =
++                      "MIC_IN", "Microphone Jack",
++                      "Microphone Jack", "Mic Bias",
++                      "LINE_IN", "Line In Jack",
++                      "Headphone Jack", "HP_OUT",
++                      "Speaker Ext", "LINE_OUT";
++
++              simple-audio-card,cpu {
++                      sound-dai = <&sai2>;
++                      frame-master;
++                      bitclock-master;
++              };
++
++              simple-audio-card,codec {
++                      sound-dai = <&codec>;
++                      frame-master;
++                      bitclock-master;
++                      system-clock-frequency = <25000000>;
++              };
++      };
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&i2c0 {
++      status = "okay";
++
++      codec: sgtl5000@a {
++              #sound-dai-cells = <0>;
++              compatible = "fsl,sgtl5000";
++              reg = <0xa>;
++              VDDA-supply = <&reg_1p8v>;
++              VDDIO-supply = <&reg_1p8v>;
++              clocks = <&sys_mclk>;
++      };
++};
++
++&qspi {
++      num-cs = <1>;
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fs512s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              m25p,fast-read;
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
++&sai2 {
++      status = "okay";
++};
++
++&sata {
++      status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+new file mode 100644
+index 00000000..1e1b2802
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
+@@ -0,0 +1,155 @@
++/*
++ * Device Tree file for Freescale LS1012A QDS Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++      model = "LS1012A QDS Board";
++      compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
++
++      sys_mclk: clock-mclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              clock-frequency = <24576000>;
++      };
++
++      reg_3p3v: regulator-3p3v {
++              compatible = "regulator-fixed";
++              regulator-name = "3P3V";
++              regulator-min-microvolt = <3300000>;
++              regulator-max-microvolt = <3300000>;
++              regulator-always-on;
++      };
++
++      sound {
++              compatible = "simple-audio-card";
++              simple-audio-card,format = "i2s";
++              simple-audio-card,widgets =
++                      "Microphone", "Microphone Jack",
++                      "Headphone", "Headphone Jack",
++                      "Speaker", "Speaker Ext",
++                      "Line", "Line In Jack";
++              simple-audio-card,routing =
++                      "MIC_IN", "Microphone Jack",
++                      "Microphone Jack", "Mic Bias",
++                      "LINE_IN", "Line In Jack",
++                      "Headphone Jack", "HP_OUT",
++                      "Speaker Ext", "LINE_OUT";
++
++              simple-audio-card,cpu {
++                      sound-dai = <&sai2>;
++                      frame-master;
++                      bitclock-master;
++              };
++
++              simple-audio-card,codec {
++                      sound-dai = <&codec>;
++                      frame-master;
++                      bitclock-master;
++                      system-clock-frequency = <24576000>;
++              };
++      };
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&i2c0 {
++      status = "okay";
++
++      pca9547@77 {
++              compatible = "nxp,pca9547";
++              reg = <0x77>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              i2c@4 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x4>;
++
++                      codec: sgtl5000@a {
++                              #sound-dai-cells = <0>;
++                              compatible = "fsl,sgtl5000";
++                              reg = <0xa>;
++                              VDDA-supply = <&reg_3p3v>;
++                              VDDIO-supply = <&reg_3p3v>;
++                              clocks = <&sys_mclk>;
++                      };
++              };
++      };
++};
++
++&qspi {
++      num-cs = <2>;
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fs512s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              m25p,fast-read;
++              reg = <0>;
++      };
++};
++
++&sai2 {
++      status = "okay";
++};
++
++&sata {
++      status = "okay";
++};
++
++&esdhc0 {
++      status = "okay";
++};
++
++&esdhc1 {
++      status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+new file mode 100644
+index 00000000..90bd2307
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
+@@ -0,0 +1,91 @@
++/*
++ * Device Tree file for Freescale LS1012A RDB Board.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++/dts-v1/;
++
++#include "fsl-ls1012a.dtsi"
++
++/ {
++      model = "LS1012A RDB Board";
++      compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&i2c0 {
++      status = "okay";
++};
++
++&qspi {
++      num-cs = <2>;
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fs512s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              m25p,fast-read;
++              reg = <0>;
++      };
++};
++
++&sata {
++      status = "okay";
++};
++
++&esdhc0 {
++      sd-uhs-sdr104;
++      sd-uhs-sdr50;
++      sd-uhs-sdr25;
++      sd-uhs-sdr12;
++      status = "okay";
++};
++
++&esdhc1 {
++      mmc-hs200-1_8v;
++      status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+new file mode 100644
+index 00000000..9ede9d52
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+@@ -0,0 +1,517 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++      compatible = "fsl,ls1012a";
++      interrupt-parent = <&gic>;
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      aliases {
++              crypto = &crypto;
++              rtic_a = &rtic_a;
++              rtic_b = &rtic_b;
++              rtic_c = &rtic_c;
++              rtic_d = &rtic_d;
++              sec_mon = &sec_mon;
++      };
++
++      cpus {
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              cpu0: cpu@0 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a53";
++                      reg = <0x0>;
++                      clocks = <&clockgen 1 0>;
++                      #cooling-cells = <2>;
++                      cpu-idle-states = <&CPU_PH20>;
++              };
++      };
++
++      idle-states {
++              /*
++               * PSCI node is not added default, U-boot will add missing
++               * parts if it determines to use PSCI.
++               */
++              entry-method = "arm,psci";
++
++              CPU_PH20: cpu-ph20 {
++                      compatible = "arm,idle-state";
++                      idle-state-name = "PH20";
++                      arm,psci-suspend-param = <0x0>;
++                      entry-latency-us = <1000>;
++                      exit-latency-us = <1000>;
++                      min-residency-us = <3000>;
++              };
++      };
++
++      sysclk: sysclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              clock-frequency = <125000000>;
++              clock-output-names = "sysclk";
++      };
++
++      coreclk: coreclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              clock-frequency = <100000000>;
++              clock-output-names = "coreclk";
++      };
++
++      timer {
++              compatible = "arm,armv8-timer";
++              interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
++                           <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
++                           <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
++                           <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
++      };
++
++      pmu {
++              compatible = "arm,armv8-pmuv3";
++              interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
++      };
++
++      gic: interrupt-controller@1400000 {
++              compatible = "arm,gic-400";
++              #interrupt-cells = <3>;
++              interrupt-controller;
++              reg = <0x0 0x1401000 0 0x1000>, /* GICD */
++                    <0x0 0x1402000 0 0x2000>, /* GICC */
++                    <0x0 0x1404000 0 0x2000>, /* GICH */
++                    <0x0 0x1406000 0 0x2000>; /* GICV */
++              interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
++      };
++
++      reboot {
++              compatible = "syscon-reboot";
++              regmap = <&dcfg>;
++              offset = <0xb0>;
++              mask = <0x02>;
++      };
++
++      soc {
++              compatible = "simple-bus";
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              scfg: scfg@1570000 {
++                      compatible = "fsl,ls1012a-scfg", "syscon";
++                      reg = <0x0 0x1570000 0x0 0x10000>;
++                      big-endian;
++              };
++
++              crypto: crypto@1700000 {
++                      compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
++                                   "fsl,sec-v4.0";
++                      fsl,sec-era = <8>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges = <0x0 0x00 0x1700000 0x100000>;
++                      reg = <0x00 0x1700000 0x0 0x100000>;
++                      interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++
++                      sec_jr0: jr@10000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x10000 0x10000>;
++                              interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      sec_jr1: jr@20000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x20000 0x10000>;
++                              interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      sec_jr2: jr@30000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x30000 0x10000>;
++                              interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      sec_jr3: jr@40000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x40000 0x10000>;
++                              interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      rtic@60000 {
++                              compatible = "fsl,sec-v5.4-rtic",
++                                           "fsl,sec-v5.0-rtic",
++                                           "fsl,sec-v4.0-rtic";
++                              #address-cells = <1>;
++                              #size-cells = <1>;
++                              reg = <0x60000 0x100 0x60e00 0x18>;
++                              ranges = <0x0 0x60100 0x500>;
++
++                              rtic_a: rtic-a@0 {
++                                      compatible = "fsl,sec-v5.4-rtic-memory",
++                                                   "fsl,sec-v5.0-rtic-memory",
++                                                   "fsl,sec-v4.0-rtic-memory";
++                                      reg = <0x00 0x20 0x100 0x100>;
++                              };
++
++                              rtic_b: rtic-b@20 {
++                                      compatible = "fsl,sec-v5.4-rtic-memory",
++                                                   "fsl,sec-v5.0-rtic-memory",
++                                                   "fsl,sec-v4.0-rtic-memory";
++                                      reg = <0x20 0x20 0x200 0x100>;
++                              };
++
++                              rtic_c: rtic-c@40 {
++                                      compatible = "fsl,sec-v5.4-rtic-memory",
++                                                   "fsl,sec-v5.0-rtic-memory",
++                                                   "fsl,sec-v4.0-rtic-memory";
++                                      reg = <0x40 0x20 0x300 0x100>;
++                              };
++
++                              rtic_d: rtic-d@60 {
++                                      compatible = "fsl,sec-v5.4-rtic-memory",
++                                                   "fsl,sec-v5.0-rtic-memory",
++                                                   "fsl,sec-v4.0-rtic-memory";
++                                      reg = <0x60 0x20 0x400 0x100>;
++                              };
++                      };
++              };
++
++              sec_mon: sec_mon@1e90000 {
++                      compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
++                                   "fsl,sec-v4.0-mon";
++                      reg = <0x0 0x1e90000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++              dcfg: dcfg@1ee0000 {
++                      compatible = "fsl,ls1012a-dcfg",
++                                   "syscon";
++                      reg = <0x0 0x1ee0000 0x0 0x10000>;
++                      big-endian;
++              };
++
++              clockgen: clocking@1ee1000 {
++                      compatible = "fsl,ls1012a-clockgen";
++                      reg = <0x0 0x1ee1000 0x0 0x1000>;
++                      #clock-cells = <2>;
++                      clocks = <&sysclk &coreclk>;
++                      clock-names = "sysclk", "coreclk";
++              };
++
++              tmu: tmu@1f00000 {
++                      compatible = "fsl,qoriq-tmu";
++                      reg = <0x0 0x1f00000 0x0 0x10000>;
++                      interrupts = <0 33 0x4>;
++                      fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++                      fsl,tmu-calibration = <0x00000000 0x00000026
++                                             0x00000001 0x0000002d
++                                             0x00000002 0x00000032
++                                             0x00000003 0x00000039
++                                             0x00000004 0x0000003f
++                                             0x00000005 0x00000046
++                                             0x00000006 0x0000004d
++                                             0x00000007 0x00000054
++                                             0x00000008 0x0000005a
++                                             0x00000009 0x00000061
++                                             0x0000000a 0x0000006a
++                                             0x0000000b 0x00000071
++
++                                             0x00010000 0x00000025
++                                             0x00010001 0x0000002c
++                                             0x00010002 0x00000035
++                                             0x00010003 0x0000003d
++                                             0x00010004 0x00000045
++                                             0x00010005 0x0000004e
++                                             0x00010006 0x00000057
++                                             0x00010007 0x00000061
++                                             0x00010008 0x0000006b
++                                             0x00010009 0x00000076
++
++                                             0x00020000 0x00000029
++                                             0x00020001 0x00000033
++                                             0x00020002 0x0000003d
++                                             0x00020003 0x00000049
++                                             0x00020004 0x00000056
++                                             0x00020005 0x00000061
++                                             0x00020006 0x0000006d
++
++                                             0x00030000 0x00000021
++                                             0x00030001 0x0000002a
++                                             0x00030002 0x0000003c
++                                             0x00030003 0x0000004e>;
++                      big-endian;
++                      #thermal-sensor-cells = <1>;
++              };
++
++              thermal-zones {
++                      cpu_thermal: cpu-thermal {
++                              polling-delay-passive = <1000>;
++                              polling-delay = <5000>;
++                              thermal-sensors = <&tmu 0>;
++
++                              trips {
++                                      cpu_alert: cpu-alert {
++                                              temperature = <85000>;
++                                              hysteresis = <2000>;
++                                              type = "passive";
++                                      };
++
++                                      cpu_crit: cpu-crit {
++                                              temperature = <95000>;
++                                              hysteresis = <2000>;
++                                              type = "critical";
++                                      };
++                              };
++
++                              cooling-maps {
++                                      map0 {
++                                              trip = <&cpu_alert>;
++                                              cooling-device =
++                                                      <&cpu0 THERMAL_NO_LIMIT
++                                                      THERMAL_NO_LIMIT>;
++                                      };
++                              };
++                      };
++              };
++
++              esdhc0: esdhc@1560000 {
++                      compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
++                      reg = <0x0 0x1560000 0x0 0x10000>;
++                      interrupts = <0 62 0x4>;
++                      clocks = <&clockgen 4 0>;
++                      voltage-ranges = <1800 1800 3300 3300>;
++                      sdhci,auto-cmd12;
++                      big-endian;
++                      bus-width = <4>;
++                      status = "disabled";
++              };
++
++              esdhc1: esdhc@1580000 {
++                      compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
++                      reg = <0x0 0x1580000 0x0 0x10000>;
++                      interrupts = <0 65 0x4>;
++                      clocks = <&clockgen 4 0>;
++                      voltage-ranges = <1800 1800 3300 3300>;
++                      sdhci,auto-cmd12;
++                      big-endian;
++                      broken-cd;
++                      bus-width = <4>;
++                      status = "disabled";
++              };
++
++              ftm0: ftm0@29d0000 {
++                      compatible = "fsl,ftm-alarm";
++                      reg = <0x0 0x29d0000 0x0 0x10000>,
++                            <0x0 0x1ee2140 0x0 0x4>;
++                      reg-names = "ftm", "FlexTimer1";
++                      interrupts = <0 86 0x4>;
++                      big-endian;
++              };
++
++              i2c0: i2c@2180000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2180000 0x0 0x10000>;
++                      interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 0>;
++                      status = "disabled";
++              };
++
++              i2c1: i2c@2190000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2190000 0x0 0x10000>;
++                      interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 0>;
++                      status = "disabled";
++              };
++
++              duart0: serial@21c0500 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x00 0x21c0500 0x0 0x100>;
++                      interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 0>;
++                      status = "disabled";
++              };
++
++              duart1: serial@21c0600 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x00 0x21c0600 0x0 0x100>;
++                      interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 0>;
++                      status = "disabled";
++              };
++
++              gpio0: gpio@2300000 {
++                      compatible = "fsl,qoriq-gpio";
++                      reg = <0x0 0x2300000 0x0 0x10000>;
++                      interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++              };
++
++              gpio1: gpio@2310000 {
++                      compatible = "fsl,qoriq-gpio";
++                      reg = <0x0 0x2310000 0x0 0x10000>;
++                      interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++              };
++
++              qspi: quadspi@1550000 {
++                      compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x1550000 0x0 0x10000>,
++                              <0x0 0x40000000 0x0 0x10000000>;
++                      reg-names = "QuadSPI", "QuadSPI-memory";
++                      interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
++                      clock-names = "qspi_en", "qspi";
++                      clocks = <&clockgen 4 0>, <&clockgen 4 0>;
++                      big-endian;
++                      fsl,qspi-has-second-chip;
++                      status = "disabled";
++              };
++
++              wdog0: wdog@2ad0000 {
++                      compatible = "fsl,ls1012a-wdt",
++                                   "fsl,imx21-wdt";
++                      reg = <0x0 0x2ad0000 0x0 0x10000>;
++                      interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 0>;
++                      big-endian;
++              };
++
++              sai1: sai@2b50000 {
++                      #sound-dai-cells = <0>;
++                      compatible = "fsl,vf610-sai";
++                      reg = <0x0 0x2b50000 0x0 0x10000>;
++                      interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 3>, <&clockgen 4 3>,
++                               <&clockgen 4 3>, <&clockgen 4 3>;
++                      clock-names = "bus", "mclk1", "mclk2", "mclk3";
++                      dma-names = "tx", "rx";
++                      dmas = <&edma0 1 47>,
++                             <&edma0 1 46>;
++                      status = "disabled";
++              };
++
++              sai2: sai@2b60000 {
++                      #sound-dai-cells = <0>;
++                      compatible = "fsl,vf610-sai";
++                      reg = <0x0 0x2b60000 0x0 0x10000>;
++                      interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 3>, <&clockgen 4 3>,
++                               <&clockgen 4 3>, <&clockgen 4 3>;
++                      clock-names = "bus", "mclk1", "mclk2", "mclk3";
++                      dma-names = "tx", "rx";
++                      dmas = <&edma0 1 45>,
++                             <&edma0 1 44>;
++                      status = "disabled";
++              };
++
++              edma0: edma@2c00000 {
++                      #dma-cells = <2>;
++                      compatible = "fsl,vf610-edma";
++                      reg = <0x0 0x2c00000 0x0 0x10000>,
++                            <0x0 0x2c10000 0x0 0x10000>,
++                            <0x0 0x2c20000 0x0 0x10000>;
++                      interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>,
++                                   <0 103 IRQ_TYPE_LEVEL_HIGH>;
++                      interrupt-names = "edma-tx", "edma-err";
++                      dma-channels = <32>;
++                      big-endian;
++                      clock-names = "dmamux0", "dmamux1";
++                      clocks = <&clockgen 4 3>,
++                               <&clockgen 4 3>;
++              };
++
++              usb0: usb3@2f00000 {
++                      compatible = "snps,dwc3";
++                      reg = <0x0 0x2f00000 0x0 0x10000>;
++                      interrupts = <0 60 0x4>;
++                      dr_mode = "host";
++                      snps,quirk-frame-length-adjustment = <0x20>;
++                      snps,dis_rxdet_inp3_quirk;
++              };
++
++              usb1: usb2@8600000 {
++                      compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
++                      reg = <0x0 0x8600000 0x0 0x1000>;
++                      interrupts = <0 139 0x4>;
++                      dr_mode = "host";
++                      phy_type = "ulpi";
++              };
++
++              sata: sata@3200000 {
++                      compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci";
++                      reg = <0x0 0x3200000 0x0 0x10000>,
++                              <0x0 0x20140520 0x0 0x4>;
++                      reg-names = "ahci", "sata-ecc";
++                      interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 0>;
++                      dma-coherent;
++                      status = "disabled";
++              };
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+new file mode 100644
+index 00000000..169e1714
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi
+@@ -0,0 +1,45 @@
++/*
++ * QorIQ FMan v3 device tree nodes for ls1043
++ *
++ * Copyright 2015-2016 Freescale Semiconductor Inc.
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++&soc {
++
++/* include used FMan blocks */
++#include "qoriq-fman3-0.dtsi"
++#include "qoriq-fman3-0-1g-0.dtsi"
++#include "qoriq-fman3-0-1g-1.dtsi"
++#include "qoriq-fman3-0-1g-2.dtsi"
++#include "qoriq-fman3-0-1g-3.dtsi"
++#include "qoriq-fman3-0-1g-4.dtsi"
++#include "qoriq-fman3-0-1g-5.dtsi"
++#include "qoriq-fman3-0-10g-0.dtsi"
++
++};
++
++&fman0 {
++      /* these aliases provide the FMan ports mapping */
++      enet0: ethernet@e0000 {
++      };
++
++      enet1: ethernet@e2000 {
++      };
++
++      enet2: ethernet@e4000 {
++      };
++
++      enet3: ethernet@e6000 {
++      };
++
++      enet4: ethernet@e8000 {
++      };
++
++      enet5: ethernet@ea000 {
++      };
++
++      enet6: ethernet@f0000 {
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+new file mode 100644
+index 00000000..6c13b416
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts
+@@ -0,0 +1,69 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1043a-qds.dts"
++
++&bman_fbpr {
++      compatible = "fsl,bman-fbpr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++      compatible = "fsl,qman-fqd";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++      compatible = "fsl,qman-pfdr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fman0 {
++      compatible = "fsl,fman", "simple-bus";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+index dd9e9194..08abff73 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts
+@@ -1,7 +1,7 @@
+ /*
+  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+  *
+- * Copyright 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+  *
+  * Mingkai Hu <Mingkai.hu@freescale.com>
+  *
+@@ -45,7 +45,7 @@
+  */
+ /dts-v1/;
+-/include/ "fsl-ls1043a.dtsi"
++#include "fsl-ls1043a.dtsi"
+ / {
+       model = "LS1043A QDS Board";
+@@ -60,6 +60,22 @@
+               serial1 = &duart1;
+               serial2 = &duart2;
+               serial3 = &duart3;
++              sgmii_riser_s1_p1 = &sgmii_phy_s1_p1;
++              sgmii_riser_s2_p1 = &sgmii_phy_s2_p1;
++              sgmii_riser_s3_p1 = &sgmii_phy_s3_p1;
++              sgmii_riser_s4_p1 = &sgmii_phy_s4_p1;
++              qsgmii_s1_p1 = &qsgmii_phy_s1_p1;
++              qsgmii_s1_p2 = &qsgmii_phy_s1_p2;
++              qsgmii_s1_p3 = &qsgmii_phy_s1_p3;
++              qsgmii_s1_p4 = &qsgmii_phy_s1_p4;
++              qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
++              qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
++              qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
++              qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
++              emi1_slot1 = &ls1043mdio_s1;
++              emi1_slot2 = &ls1043mdio_s2;
++              emi1_slot3 = &ls1043mdio_s3;
++              emi1_slot4 = &ls1043mdio_s4;
+       };
+       chosen {
+@@ -97,8 +113,11 @@
+       };
+       fpga: board-control@2,0 {
+-              compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus";
+               reg = <0x2 0x0 0x0000100>;
++              ranges = <0 2 0 0x100>;
+       };
+ };
+@@ -181,3 +200,149 @@
+               reg = <0>;
+       };
+ };
++
++#include "fsl-ls1043-post.dtsi"
++
++&fman0 {
++      ethernet@e0000 {
++              phy-handle = <&qsgmii_phy_s2_p1>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@e2000 {
++              phy-handle = <&qsgmii_phy_s2_p2>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@e4000 {
++              phy-handle = <&rgmii_phy1>;
++              phy-connection-type = "rgmii";
++      };
++
++      ethernet@e6000 {
++              phy-handle = <&rgmii_phy2>;
++              phy-connection-type = "rgmii";
++      };
++
++      ethernet@e8000 {
++              phy-handle = <&qsgmii_phy_s2_p3>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@ea000 {
++              phy-handle = <&qsgmii_phy_s2_p4>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@f0000 { /* DTSEC9/10GEC1 */
++              fixed-link = <1 1 10000 0 0>;
++              phy-connection-type = "xgmii";
++      };
++};
++
++&fpga {
++      mdio-mux-emi1 {
++              compatible = "mdio-mux-mmioreg", "mdio-mux";
++              mdio-parent-bus = <&mdio0>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++              reg = <0x54 1>;    /* BRDCFG4 */
++              mux-mask = <0xe0>; /* EMI1 */
++
++              /* On-board RGMII1 PHY */
++              ls1043mdio0: mdio@0 {
++                      reg = <0>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++                      rgmii_phy1: ethernet-phy@1 { /* MAC3 */
++                              reg = <0x1>;
++                      };
++              };
++
++              /* On-board RGMII2 PHY */
++              ls1043mdio1: mdio@1 {
++                      reg = <0x20>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++                      rgmii_phy2: ethernet-phy@2 { /* MAC4 */
++                              reg = <0x2>;
++                      };
++              };
++
++              /* Slot 1 */
++              ls1043mdio_s1: mdio@2 {
++                      reg = <0x40>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      qsgmii_phy_s1_p1: ethernet-phy@4 {
++                              reg = <0x4>;
++                      };
++                      qsgmii_phy_s1_p2: ethernet-phy@5 {
++                              reg = <0x5>;
++                      };
++                      qsgmii_phy_s1_p3: ethernet-phy@6 {
++                              reg = <0x6>;
++                      };
++                      qsgmii_phy_s1_p4: ethernet-phy@7 {
++                              reg = <0x7>;
++                      };
++
++                      sgmii_phy_s1_p1: ethernet-phy@1c {
++                              reg = <0x1c>;
++                      };
++              };
++
++              /* Slot 2 */
++              ls1043mdio_s2: mdio@3 {
++                      reg = <0x60>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      qsgmii_phy_s2_p1: ethernet-phy@8 {
++                              reg = <0x8>;
++                      };
++                      qsgmii_phy_s2_p2: ethernet-phy@9 {
++                              reg = <0x9>;
++                      };
++                      qsgmii_phy_s2_p3: ethernet-phy@a {
++                              reg = <0xa>;
++                      };
++                      qsgmii_phy_s2_p4: ethernet-phy@b {
++                              reg = <0xb>;
++                      };
++
++                      sgmii_phy_s2_p1: ethernet-phy@1c {
++                              reg = <0x1c>;
++                      };
++              };
++
++              /* Slot 3 */
++              ls1043mdio_s3: mdio@4 {
++                      reg = <0x80>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      sgmii_phy_s3_p1: ethernet-phy@1c {
++                              reg = <0x1c>;
++                      };
++              };
++
++              /* Slot 4 */
++              ls1043mdio_s4: mdio@5 {
++                      reg = <0xa0>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      sgmii_phy_s4_p1: ethernet-phy@1c {
++                              reg = <0x1c>;
++                      };
++              };
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+new file mode 100644
+index 00000000..ac4b9a41
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts
+@@ -0,0 +1,69 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1043a-rdb.dts"
++
++&bman_fbpr {
++      compatible = "fsl,bman-fbpr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++      compatible = "fsl,qman-fqd";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++      compatible = "fsl,qman-pfdr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fman0 {
++      compatible = "fsl,fman", "simple-bus";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+new file mode 100644
+index 00000000..4e46a0a5
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts
+@@ -0,0 +1,117 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1043A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include "fsl-ls1043a-rdb-sdk.dts"
++
++&soc {
++      bp7: buffer-pool@7 {
++              compatible = "fsl,p4080-bpool", "fsl,bpool";
++              fsl,bpid = <7>;
++              fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
++              fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
++      };
++
++      bp8: buffer-pool@8 {
++              compatible = "fsl,p4080-bpool", "fsl,bpool";
++              fsl,bpid = <8>;
++              fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
++              fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++      };
++
++      bp9: buffer-pool@9 {
++              compatible = "fsl,p4080-bpool", "fsl,bpool";
++              fsl,bpid = <9>;
++              fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
++              fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++      };
++
++      fsl,dpaa {
++              compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus";
++
++              ethernet@0 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x50 1 0x51 1>;
++                      fsl,qman-frame-queues-tx = <0x70 1 0x71 1>;
++              };
++
++              ethernet@1 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x52 1 0x53 1>;
++                      fsl,qman-frame-queues-tx = <0x72 1 0x73 1>;
++              };
++
++              ethernet@2 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
++                      fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
++              };
++
++              ethernet@3 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
++                      fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
++              };
++
++              ethernet@4 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
++                      fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
++              };
++
++              ethernet@5 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x60 1 0x61 1>;
++                      fsl,qman-frame-queues-tx = <0x80 1 0x81 1>;
++              };
++
++              ethernet@8 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
++                      fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
++
++              };
++              dpa-fman0-oh@2 {
++                      compatible = "fsl,dpa-oh";
++                      /* Define frame queues for the OH port*/
++                      /* <OH Rx error, OH Rx default> */
++                      fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>;
++                      fsl,fman-oh-port = <&fman0_oh2>;
++              };
++      };
++};
++/ {
++      reserved-memory {
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              usdpaa_mem: usdpaa_mem {
++                      compatible = "fsl,usdpaa-mem";
++                      alloc-ranges = <0 0 0x10000 0>;
++                      size = <0 0x10000000>;
++                      alignment = <0 0x10000000>;
++              };
++      };
++};
++
++&fman0 {
++      fman0_oh2: port@83000 {
++              cell-index = <1>;
++              compatible = "fsl,fman-port-oh";
++              reg = <0x83000 0x1000>;
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+index d2313e05..f92ae325 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts
+@@ -1,7 +1,7 @@
+ /*
+  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+  *
+- * Copyright 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+  *
+  * Mingkai Hu <Mingkai.hu@freescale.com>
+  *
+@@ -45,7 +45,7 @@
+  */
+ /dts-v1/;
+-/include/ "fsl-ls1043a.dtsi"
++#include "fsl-ls1043a.dtsi"
+ / {
+       model = "LS1043A RDB Board";
+@@ -86,6 +86,10 @@
+               compatible = "pericom,pt7c4338";
+               reg = <0x68>;
+       };
++      rtc@51 {
++              compatible = "nxp,pcf85263";
++              reg = <0x51>;
++      };
+ };
+ &ifc {
+@@ -130,6 +134,38 @@
+               reg = <0>;
+               spi-max-frequency = <1000000>; /* input clock */
+       };
++
++      slic@2 {
++              compatible = "maxim,ds26522";
++              reg = <2>;
++              spi-max-frequency = <2000000>;
++              fsl,spi-cs-sck-delay = <100>;
++              fsl,spi-sck-cs-delay = <50>;
++      };
++
++      slic@3 {
++              compatible = "maxim,ds26522";
++              reg = <3>;
++              spi-max-frequency = <2000000>;
++              fsl,spi-cs-sck-delay = <100>;
++              fsl,spi-sck-cs-delay = <50>;
++      };
++};
++
++&uqe {
++      ucc_hdlc: ucc@2000 {
++              compatible = "fsl,ucc-hdlc";
++              rx-clock-name = "clk8";
++              tx-clock-name = "clk9";
++              fsl,rx-sync-clock = "rsync_pin";
++              fsl,tx-sync-clock = "tsync_pin";
++              fsl,tx-timeslot-mask = <0xfffffffe>;
++              fsl,rx-timeslot-mask = <0xfffffffe>;
++              fsl,tdm-framer-type = "e1";
++              fsl,tdm-id = <0>;
++              fsl,siram-entry-id = <0>;
++              fsl,tdm-interface;
++      };
+ };
+ &duart0 {
+@@ -139,3 +175,76 @@
+ &duart1 {
+       status = "okay";
+ };
++
++#include "fsl-ls1043-post.dtsi"
++
++&fman0 {
++      ethernet@e0000 {
++              phy-handle = <&qsgmii_phy1>;
++              phy-connection-type = "qsgmii";
++      };
++
++      ethernet@e2000 {
++              phy-handle = <&qsgmii_phy2>;
++              phy-connection-type = "qsgmii";
++      };
++
++      ethernet@e4000 {
++              phy-handle = <&rgmii_phy1>;
++              phy-connection-type = "rgmii-txid";
++      };
++
++      ethernet@e6000 {
++              phy-handle = <&rgmii_phy2>;
++              phy-connection-type = "rgmii-txid";
++      };
++
++      ethernet@e8000 {
++              phy-handle = <&qsgmii_phy3>;
++              phy-connection-type = "qsgmii";
++      };
++
++      ethernet@ea000 {
++              phy-handle = <&qsgmii_phy4>;
++              phy-connection-type = "qsgmii";
++      };
++
++      ethernet@f0000 { /* 10GEC1 */
++              phy-handle = <&aqr105_phy>;
++              phy-connection-type = "xgmii";
++      };
++
++      mdio@fc000 {
++              rgmii_phy1: ethernet-phy@1 {
++                      reg = <0x1>;
++              };
++
++              rgmii_phy2: ethernet-phy@2 {
++                      reg = <0x2>;
++              };
++
++              qsgmii_phy1: ethernet-phy@4 {
++                      reg = <0x4>;
++              };
++
++              qsgmii_phy2: ethernet-phy@5 {
++                      reg = <0x5>;
++              };
++
++              qsgmii_phy3: ethernet-phy@6 {
++                      reg = <0x6>;
++              };
++
++              qsgmii_phy4: ethernet-phy@7 {
++                      reg = <0x7>;
++              };
++      };
++
++      mdio@fd000 {
++              aqr105_phy: ethernet-phy@1 {
++                      compatible = "ethernet-phy-ieee802.3-c45";
++                      interrupts = <0 132 4>;
++                      reg = <0x1>;
++              };
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+index 97d331ec..8b27faaf 100644
+--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+@@ -1,7 +1,7 @@
+ /*
+  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+  *
+- * Copyright 2014-2015, Freescale Semiconductor
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
+  *
+  * Mingkai Hu <Mingkai.hu@freescale.com>
+  *
+@@ -44,12 +44,25 @@
+  *     OTHER DEALINGS IN THE SOFTWARE.
+  */
++#include <dt-bindings/thermal/thermal.h>
++
+ / {
+       compatible = "fsl,ls1043a";
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
++      aliases {
++              fman0 = &fman0;
++              ethernet0 = &enet0;
++              ethernet1 = &enet1;
++              ethernet2 = &enet2;
++              ethernet3 = &enet3;
++              ethernet4 = &enet4;
++              ethernet5 = &enet5;
++              ethernet6 = &enet6;
++      };
++
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+@@ -66,6 +79,8 @@
+                       reg = <0x0>;
+                       clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
++                      #cooling-cells = <2>;
++                      cpu-idle-states = <&CPU_PH20>;
+               };
+               cpu1: cpu@1 {
+@@ -74,6 +89,7 @@
+                       reg = <0x1>;
+                       clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
++                      cpu-idle-states = <&CPU_PH20>;
+               };
+               cpu2: cpu@2 {
+@@ -82,6 +98,7 @@
+                       reg = <0x2>;
+                       clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
++                      cpu-idle-states = <&CPU_PH20>;
+               };
+               cpu3: cpu@3 {
+@@ -90,6 +107,7 @@
+                       reg = <0x3>;
+                       clocks = <&clockgen 1 0>;
+                       next-level-cache = <&l2>;
++                      cpu-idle-states = <&CPU_PH20>;
+               };
+               l2: l2-cache {
+@@ -97,12 +115,56 @@
+               };
+       };
++      idle-states {
++              /*
++               * PSCI node is not added default, U-boot will add missing
++               * parts if it determines to use PSCI.
++               */
++              entry-method = "arm,psci";
++
++              CPU_PH20: cpu-ph20 {
++                      compatible = "arm,idle-state";
++                      idle-state-name = "PH20";
++                      arm,psci-suspend-param = <0x0>;
++                      entry-latency-us = <1000>;
++                      exit-latency-us = <1000>;
++                      min-residency-us = <3000>;
++              };
++      };
++
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x0 0x80000000 0 0x80000000>;
+                     /* DRAM space 1, size: 2GiB DRAM */
+       };
++      reserved-memory {
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              bman_fbpr: bman-fbpr {
++                      compatible = "shared-dma-pool";
++                      size = <0 0x1000000>;
++                      alignment = <0 0x1000000>;
++                      no-map;
++              };
++
++              qman_fqd: qman-fqd {
++                      compatible = "shared-dma-pool";
++                      size = <0 0x400000>;
++                      alignment = <0 0x400000>;
++                      no-map;
++              };
++
++              qman_pfdr: qman-pfdr {
++                      compatible = "shared-dma-pool";
++                      size = <0 0x2000000>;
++                      alignment = <0 0x2000000>;
++                      no-map;
++              };
++      };
++
+       sysclk: sysclk {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+@@ -149,7 +211,7 @@
+               interrupts = <1 9 0xf08>;
+       };
+-      soc {
++      soc: soc {
+               compatible = "simple-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+@@ -213,13 +275,14 @@
+               dcfg: dcfg@1ee0000 {
+                       compatible = "fsl,ls1043a-dcfg", "syscon";
+-                      reg = <0x0 0x1ee0000 0x0 0x10000>;
++                      reg = <0x0 0x1ee0000 0x0 0x1000>;
+                       big-endian;
+               };
+               ifc: ifc@1530000 {
+                       compatible = "fsl,ifc", "simple-bus";
+                       reg = <0x0 0x1530000 0x0 0x10000>;
++                      big-endian;
+                       interrupts = <0 43 0x4>;
+               };
+@@ -255,6 +318,103 @@
+                       big-endian;
+               };
++              tmu: tmu@1f00000 {
++                      compatible = "fsl,qoriq-tmu";
++                      reg = <0x0 0x1f00000 0x0 0x10000>;
++                      interrupts = <0 33 0x4>;
++                      fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++                      fsl,tmu-calibration = <0x00000000 0x00000026
++                                             0x00000001 0x0000002d
++                                             0x00000002 0x00000032
++                                             0x00000003 0x00000039
++                                             0x00000004 0x0000003f
++                                             0x00000005 0x00000046
++                                             0x00000006 0x0000004d
++                                             0x00000007 0x00000054
++                                             0x00000008 0x0000005a
++                                             0x00000009 0x00000061
++                                             0x0000000a 0x0000006a
++                                             0x0000000b 0x00000071
++
++                                             0x00010000 0x00000025
++                                             0x00010001 0x0000002c
++                                             0x00010002 0x00000035
++                                             0x00010003 0x0000003d
++                                             0x00010004 0x00000045
++                                             0x00010005 0x0000004e
++                                             0x00010006 0x00000057
++                                             0x00010007 0x00000061
++                                             0x00010008 0x0000006b
++                                             0x00010009 0x00000076
++
++                                             0x00020000 0x00000029
++                                             0x00020001 0x00000033
++                                             0x00020002 0x0000003d
++                                             0x00020003 0x00000049
++                                             0x00020004 0x00000056
++                                             0x00020005 0x00000061
++                                             0x00020006 0x0000006d
++
++                                             0x00030000 0x00000021
++                                             0x00030001 0x0000002a
++                                             0x00030002 0x0000003c
++                                             0x00030003 0x0000004e>;
++                      #thermal-sensor-cells = <1>;
++              };
++
++              thermal-zones {
++                      cpu_thermal: cpu-thermal {
++                              polling-delay-passive = <1000>;
++                              polling-delay = <5000>;
++
++                              thermal-sensors = <&tmu 3>;
++
++                              trips {
++                                      cpu_alert: cpu-alert {
++                                              temperature = <85000>;
++                                              hysteresis = <2000>;
++                                              type = "passive";
++                                      };
++                                      cpu_crit: cpu-crit {
++                                              temperature = <95000>;
++                                              hysteresis = <2000>;
++                                              type = "critical";
++                                      };
++                              };
++
++                              cooling-maps {
++                                      map0 {
++                                              trip = <&cpu_alert>;
++                                              cooling-device =
++                                                      <&cpu0 THERMAL_NO_LIMIT
++                                                      THERMAL_NO_LIMIT>;
++                                      };
++                              };
++                      };
++              };
++
++              qman: qman@1880000 {
++                      compatible = "fsl,qman";
++                      reg = <0x00 0x1880000 0x0 0x10000>;
++                      interrupts = <0 45 0x4>;
++                      memory-region = <&qman_fqd &qman_pfdr>;
++              };
++
++              bman: bman@1890000 {
++                      compatible = "fsl,bman";
++                      reg = <0x00 0x1890000 0x0 0x10000>;
++                      interrupts = <0 45 0x4>;
++                      memory-region = <&bman_fbpr>;
++              };
++
++              bportals: bman-portals@508000000 {
++                      ranges = <0x0 0x5 0x08000000 0x8000000>;
++              };
++
++              qportals: qman-portals@500000000 {
++                      ranges = <0x0 0x5 0x00000000 0x8000000>;
++              };
++
+               dspi0: dspi@2100000 {
+                       compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
+                       #address-cells = <1>;
+@@ -396,6 +556,72 @@
+                       #interrupt-cells = <2>;
+               };
++              uqe: uqe@2400000 {
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      device_type = "qe";
++                      compatible = "fsl,qe", "simple-bus";
++                      ranges = <0x0 0x0 0x2400000 0x40000>;
++                      reg = <0x0 0x2400000 0x0 0x480>;
++                      brg-frequency = <100000000>;
++                      bus-frequency = <200000000>;
++
++                      fsl,qe-num-riscs = <1>;
++                      fsl,qe-num-snums = <28>;
++
++                      qeic: qeic@80 {
++                              compatible = "fsl,qe-ic";
++                              reg = <0x80 0x80>;
++                              #address-cells = <0>;
++                              interrupt-controller;
++                              #interrupt-cells = <1>;
++                              interrupts = <0 77 0x04 0 77 0x04>;
++                      };
++
++                      si1: si@700 {
++                              #address-cells = <1>;
++                              #size-cells = <0>;
++                              compatible = "fsl,ls1043-qe-si",
++                                              "fsl,t1040-qe-si";
++                              reg = <0x700 0x80>;
++                      };
++
++                      siram1: siram@1000 {
++                              #address-cells = <1>;
++                              #size-cells = <1>;
++                              compatible = "fsl,ls1043-qe-siram",
++                                              "fsl,t1040-qe-siram";
++                              reg = <0x1000 0x800>;
++                      };
++
++                      ucc@2000 {
++                              cell-index = <1>;
++                              reg = <0x2000 0x200>;
++                              interrupts = <32>;
++                              interrupt-parent = <&qeic>;
++                      };
++
++                      ucc@2200 {
++                              cell-index = <3>;
++                              reg = <0x2200 0x200>;
++                              interrupts = <34>;
++                              interrupt-parent = <&qeic>;
++                      };
++
++                      muram@10000 {
++                              #address-cells = <1>;
++                              #size-cells = <1>;
++                              compatible = "fsl,qe-muram", "fsl,cpm-muram";
++                              ranges = <0x0 0x10000 0x6000>;
++
++                              data-only@0 {
++                                      compatible = "fsl,qe-muram-data",
++                                      "fsl,cpm-muram-data";
++                                      reg = <0x0 0x6000>;
++                              };
++                      };
++              };
++
+               lpuart0: serial@2950000 {
+                       compatible = "fsl,ls1021a-lpuart";
+                       reg = <0x0 0x2950000 0x0 0x1000>;
+@@ -450,6 +676,16 @@
+                       status = "disabled";
+               };
++              ftm0: ftm0@29d0000 {
++                      compatible = "fsl,ftm-alarm";
++                      reg = <0x0 0x29d0000 0x0 0x10000>,
++                            <0x0 0x1ee2140 0x0 0x4>;
++                      reg-names = "ftm", "FlexTimer1";
++                      interrupts = <0 86 0x4>;
++                      big-endian;
++                      status = "okay";
++              };
++
+               wdog0: wdog@2ad0000 {
+                       compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
+                       reg = <0x0 0x2ad0000 0x0 0x10000>;
+@@ -482,6 +718,8 @@
+                       dr_mode = "host";
+                       snps,quirk-frame-length-adjustment = <0x20>;
+                       snps,dis_rxdet_inp3_quirk;
++                      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++                      snps,dma-snooping;
+               };
+               usb1: usb3@3000000 {
+@@ -491,6 +729,9 @@
+                       dr_mode = "host";
+                       snps,quirk-frame-length-adjustment = <0x20>;
+                       snps,dis_rxdet_inp3_quirk;
++                      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++                      snps,dma-snooping;
++                      configure-gfladj;
+               };
+               usb2: usb3@3100000 {
+@@ -500,32 +741,52 @@
+                       dr_mode = "host";
+                       snps,quirk-frame-length-adjustment = <0x20>;
+                       snps,dis_rxdet_inp3_quirk;
++                      snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
++                      snps,dma-snooping;
++                      configure-gfladj;
+               };
+               sata: sata@3200000 {
+                       compatible = "fsl,ls1043a-ahci";
+-                      reg = <0x0 0x3200000 0x0 0x10000>;
++                      reg = <0x0 0x3200000 0x0 0x10000>,
++                              <0x0 0x20140520 0x0 0x4>;
++                      reg-names = "ahci", "sata-ecc";
+                       interrupts = <0 69 0x4>;
+                       clocks = <&clockgen 4 0>;
+                       dma-coherent;
+               };
++              qdma: qdma@8380000 {
++                      compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
++                      reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
++                            <0x0 0x8390000 0x0 0x10000>, /* Status regs */
++                            <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
++                      interrupts = <0 152 0x4>,
++                                   <0 39 0x4>;
++                      interrupt-names = "qdma-error", "qdma-queue";
++                      channels = <8>;
++                      queues = <2>;
++                      status-sizes = <64>;
++                      queue-sizes = <64 64>;
++                      big-endian;
++              };
++
+               msi1: msi-controller1@1571000 {
+-                      compatible = "fsl,1s1043a-msi";
++                      compatible = "fsl,ls1043a-msi";
+                       reg = <0x0 0x1571000 0x0 0x8>;
+                       msi-controller;
+                       interrupts = <0 116 0x4>;
+               };
+               msi2: msi-controller2@1572000 {
+-                      compatible = "fsl,1s1043a-msi";
++                      compatible = "fsl,ls1043a-msi";
+                       reg = <0x0 0x1572000 0x0 0x8>;
+                       msi-controller;
+                       interrupts = <0 126 0x4>;
+               };
+               msi3: msi-controller3@1573000 {
+-                      compatible = "fsl,1s1043a-msi";
++                      compatible = "fsl,ls1043a-msi";
+                       reg = <0x0 0x1573000 0x0 0x8>;
+                       msi-controller;
+                       interrupts = <0 160 0x4>;
+@@ -536,9 +797,9 @@
+                       reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
+                              0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg-names = "regs", "config";
+-                      interrupts = <0 118 0x4>, /* controller interrupt */
+-                                   <0 117 0x4>; /* PME interrupt */
+-                      interrupt-names = "intr", "pme";
++                      interrupts = <0 117 0x4>, /* PME interrupt */
++                                   <0 118 0x4>; /* aer interrupt */
++                      interrupt-names = "pme", "aer";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+@@ -547,7 +808,7 @@
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-                      msi-parent = <&msi1>;
++                      msi-parent = <&msi1>, <&msi2>, <&msi3>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
+@@ -561,9 +822,9 @@
+                       reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
+                              0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg-names = "regs", "config";
+-                      interrupts = <0 128 0x4>,
+-                                   <0 127 0x4>;
+-                      interrupt-names = "intr", "pme";
++                      interrupts = <0 127 0x4>,
++                                   <0 128 0x4>;
++                      interrupt-names = "pme", "aer";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+@@ -572,7 +833,7 @@
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-                      msi-parent = <&msi2>;
++                      msi-parent = <&msi1>, <&msi2>, <&msi3>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0000 0 0 1 &gic 0 120  0x4>,
+@@ -586,9 +847,9 @@
+                       reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
+                              0x50 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg-names = "regs", "config";
+-                      interrupts = <0 162 0x4>,
+-                                   <0 161 0x4>;
+-                      interrupt-names = "intr", "pme";
++                      interrupts = <0 161 0x4>,
++                                   <0 162 0x4>;
++                      interrupt-names = "pme", "aer";
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+@@ -597,7 +858,7 @@
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+-                      msi-parent = <&msi3>;
++                      msi-parent = <&msi1>, <&msi2>, <&msi3>;
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
+@@ -608,3 +869,6 @@
+       };
+ };
++
++#include "qoriq-qman1-portals.dtsi"
++#include "qoriq-bman1-portals.dtsi"
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+new file mode 100644
+index 00000000..f5017dba
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi
+@@ -0,0 +1,48 @@
++/*
++ * QorIQ FMan v3 device tree nodes for ls1046
++ *
++ * Copyright 2015-2016 Freescale Semiconductor Inc.
++ *
++ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
++ */
++
++&soc {
++
++/* include used FMan blocks */
++#include "qoriq-fman3-0.dtsi"
++#include "qoriq-fman3-0-1g-0.dtsi"
++#include "qoriq-fman3-0-1g-1.dtsi"
++#include "qoriq-fman3-0-1g-2.dtsi"
++#include "qoriq-fman3-0-1g-3.dtsi"
++#include "qoriq-fman3-0-1g-4.dtsi"
++#include "qoriq-fman3-0-1g-5.dtsi"
++#include "qoriq-fman3-0-10g-0.dtsi"
++#include "qoriq-fman3-0-10g-1.dtsi"
++};
++
++&fman0 {
++      /* these aliases provide the FMan ports mapping */
++      enet0: ethernet@e0000 {
++      };
++
++      enet1: ethernet@e2000 {
++      };
++
++      enet2: ethernet@e4000 {
++      };
++
++      enet3: ethernet@e6000 {
++      };
++
++      enet4: ethernet@e8000 {
++      };
++
++      enet5: ethernet@ea000 {
++      };
++
++      enet6: ethernet@f0000 {
++      };
++
++      enet7: ethernet@f2000 {
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+new file mode 100644
+index 00000000..c375af47
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts
+@@ -0,0 +1,109 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1046a-qds.dts"
++
++&bman_fbpr {
++      compatible = "fsl,bman-fbpr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++      compatible = "fsl,qman-fqd";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++      compatible = "fsl,qman-pfdr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fsldpaa {
++      ethernet@9 {
++              compatible = "fsl,dpa-ethernet";
++              fsl,fman-mac = <&enet7>;
++      };
++};
++
++&fman0 {
++      compatible = "fsl,fman", "simple-bus";
++};
++
++&dspi {
++      bus-num = <0>;
++      status = "okay";
++
++      flash@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "n25q128a11", "jedec,spi-nor";
++              reg = <0>;
++              spi-max-frequency = <10000000>;
++      };
++
++      flash@1 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "sst25wf040b", "jedec,spi-nor";
++              spi-cpol;
++              spi-cpha;
++              reg = <1>;
++              spi-max-frequency = <10000000>;
++      };
++
++      flash@2 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "en25s64", "jedec,spi-nor";
++              spi-cpol;
++              spi-cpha;
++              reg = <2>;
++              spi-max-frequency = <10000000>;
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+new file mode 100644
+index 00000000..3b8e9b7e
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+@@ -0,0 +1,363 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * Shaohui Xie <Shaohui.Xie@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1046a.dtsi"
++
++/ {
++      model = "LS1046A QDS Board";
++      compatible = "fsl,ls1046a-qds", "fsl,ls1046a";
++
++      aliases {
++              gpio0 = &gpio0;
++              gpio1 = &gpio1;
++              gpio2 = &gpio2;
++              gpio3 = &gpio3;
++              serial0 = &duart0;
++              serial1 = &duart1;
++              serial2 = &duart2;
++              serial3 = &duart3;
++
++              emi1_slot1 = &ls1046mdio_s1;
++              emi1_slot2 = &ls1046mdio_s2;
++              emi1_slot4 = &ls1046mdio_s4;
++
++              sgmii_s1_p1 = &sgmii_phy_s1_p1;
++              sgmii_s1_p2 = &sgmii_phy_s1_p2;
++              sgmii_s1_p3 = &sgmii_phy_s1_p3;
++              sgmii_s1_p4 = &sgmii_phy_s1_p4;
++              sgmii_s4_p1 = &sgmii_phy_s4_p1;
++              qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
++              qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
++              qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
++              qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
++      };
++
++      chosen {
++              stdout-path = "serial0:115200n8";
++      };
++};
++
++&dspi {
++      bus-num = <0>;
++      status = "okay";
++
++      flash@0 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "n25q128a11", "jedec,spi-nor";
++              reg = <0>;
++              spi-max-frequency = <10000000>;
++      };
++
++      flash@1 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "sst25wf040b", "jedec,spi-nor";
++              spi-cpol;
++              spi-cpha;
++              reg = <1>;
++              spi-max-frequency = <10000000>;
++      };
++
++      flash@2 {
++              #address-cells = <1>;
++              #size-cells = <1>;
++              compatible = "en25s64", "jedec,spi-nor";
++              spi-cpol;
++              spi-cpha;
++              reg = <2>;
++              spi-max-frequency = <10000000>;
++      };
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&duart1 {
++      status = "okay";
++};
++
++&i2c0 {
++      status = "okay";
++
++      pca9547@77 {
++              compatible = "nxp,pca9547";
++              reg = <0x77>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              i2c@2 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x2>;
++
++                      ina220@40 {
++                              compatible = "ti,ina220";
++                              reg = <0x40>;
++                              shunt-resistor = <1000>;
++                      };
++
++                      ina220@41 {
++                              compatible = "ti,ina220";
++                              reg = <0x41>;
++                              shunt-resistor = <1000>;
++                      };
++              };
++
++              i2c@3 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x3>;
++
++                      rtc@51 {
++                              compatible = "nxp,pcf2129";
++                              reg = <0x51>;
++                              /* IRQ10_B */
++                              interrupts = <0 150 0x4>;
++                      };
++
++                      eeprom@56 {
++                              compatible = "atmel,24c512";
++                              reg = <0x56>;
++                      };
++
++                      eeprom@57 {
++                              compatible = "atmel,24c512";
++                              reg = <0x57>;
++                      };
++
++                      temp-sensor@4c {
++                              compatible = "adi,adt7461a";
++                              reg = <0x4c>;
++                      };
++              };
++      };
++};
++
++&ifc {
++      #address-cells = <2>;
++      #size-cells = <1>;
++      /* NOR, NAND Flashes and FPGA on board */
++      ranges = <0x0 0x0 0x0 0x60000000 0x08000000
++                0x1 0x0 0x0 0x7e800000 0x00010000
++                0x2 0x0 0x0 0x7fb00000 0x00000100>;
++      status = "okay";
++
++      nor@0,0 {
++              compatible = "cfi-flash";
++              reg = <0x0 0x0 0x8000000>;
++              bank-width = <2>;
++              device-width = <1>;
++      };
++
++      nand@1,0 {
++              compatible = "fsl,ifc-nand";
++              reg = <0x1 0x0 0x10000>;
++      };
++
++      fpga: board-control@2,0 {
++              compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus";
++              reg = <0x2 0x0 0x0000100>;
++              ranges = <0 2 0 0x100>;
++      };
++};
++
++&lpuart0 {
++      status = "okay";
++};
++
++&qspi {
++      num-cs = <2>;
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fl128s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++};
++
++#include "fsl-ls1046-post.dtsi"
++
++&fman0 {
++      ethernet@e0000 {
++              phy-handle = <&qsgmii_phy_s2_p1>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@e2000 {
++              phy-handle = <&sgmii_phy_s4_p1>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@e4000 {
++              phy-handle = <&rgmii_phy1>;
++              phy-connection-type = "rgmii";
++      };
++
++      ethernet@e6000 {
++              phy-handle = <&rgmii_phy2>;
++              phy-connection-type = "rgmii";
++      };
++
++      ethernet@e8000 {
++              phy-handle = <&sgmii_phy_s1_p3>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@ea000 {
++              phy-handle = <&sgmii_phy_s1_p4>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@f0000 { /* DTSEC9/10GEC1 */
++              phy-handle = <&sgmii_phy_s1_p1>;
++              phy-connection-type = "xgmii";
++      };
++
++      ethernet@f2000 { /* DTSEC10/10GEC2 */
++              phy-handle = <&sgmii_phy_s1_p2>;
++              phy-connection-type = "xgmii";
++      };
++};
++
++&fpga {
++      #address-cells = <1>;
++      #size-cells = <1>;
++      mdio-mux-emi1 {
++              compatible = "mdio-mux-mmioreg", "mdio-mux";
++              mdio-parent-bus = <&mdio0>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++              reg = <0x54 1>;    /* BRDCFG4 */
++              mux-mask = <0xe0>; /* EMI1 */
++
++              /* On-board RGMII1 PHY */
++              ls1046mdio0: mdio@0 {
++                      reg = <0>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++                      rgmii_phy1: ethernet-phy@1 { /* MAC3 */
++                              reg = <0x1>;
++                      };
++              };
++
++              /* On-board RGMII2 PHY */
++              ls1046mdio1: mdio@1 {
++                      reg = <0x20>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++
++                      rgmii_phy2: ethernet-phy@2 { /* MAC4 */
++                              reg = <0x2>;
++                      };
++              };
++
++              /* Slot 1 */
++              ls1046mdio_s1: mdio@2 {
++                      reg = <0x40>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      sgmii_phy_s1_p1: ethernet-phy@1c {
++                              reg = <0x1c>;
++                      };
++
++                      sgmii_phy_s1_p2: ethernet-phy@1d {
++                              reg = <0x1d>;
++                      };
++
++                      sgmii_phy_s1_p3: ethernet-phy@1e {
++                              reg = <0x1e>;
++                      };
++
++                      sgmii_phy_s1_p4: ethernet-phy@1f {
++                              reg = <0x1f>;
++                      };
++              };
++
++              /* Slot 2 */
++              ls1046mdio_s2: mdio@3 {
++                      reg = <0x60>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      qsgmii_phy_s2_p1: ethernet-phy@8 {
++                              reg = <0x8>;
++                      };
++                      qsgmii_phy_s2_p2: ethernet-phy@9 {
++                              reg = <0x9>;
++                      };
++                      qsgmii_phy_s2_p3: ethernet-phy@a {
++                              reg = <0xa>;
++                      };
++                      qsgmii_phy_s2_p4: ethernet-phy@b {
++                              reg = <0xb>;
++                      };
++              };
++
++              /* Slot 4 */
++              ls1046mdio_s4: mdio@5 {
++                      reg = <0x80>;
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      status = "disabled";
++
++                      sgmii_phy_s4_p1: ethernet-phy@1c {
++                              reg = <0x1c>;
++                      };
++              };
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+new file mode 100644
+index 00000000..bfe2f36c
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts
+@@ -0,0 +1,76 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2014-2015 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <Mingkai.hu@freescale.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include "fsl-ls1046a-rdb.dts"
++
++&bman_fbpr {
++      compatible = "fsl,bman-fbpr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_fqd {
++      compatible = "fsl,qman-fqd";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++&qman_pfdr {
++      compatible = "fsl,qman-pfdr";
++      alloc-ranges = <0 0 0x10000 0>;
++};
++
++&soc {
++#include "qoriq-dpaa-eth.dtsi"
++#include "qoriq-fman3-0-6oh.dtsi"
++};
++
++&fsldpaa {
++      ethernet@9 {
++              compatible = "fsl,dpa-ethernet";
++              fsl,fman-mac = <&enet7>;
++      };
++};
++
++&fman0 {
++      compatible = "fsl,fman", "simple-bus";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+new file mode 100644
+index 00000000..54336aa6
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts
+@@ -0,0 +1,110 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#include "fsl-ls1046a-rdb-sdk.dts"
++
++&soc {
++      bp7: buffer-pool@7 {
++              compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++              fsl,bpid = <7>;
++              fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>;
++              fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>;
++      };
++
++      bp8: buffer-pool@8 {
++              compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++              fsl,bpid = <8>;
++              fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>;
++              fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++      };
++
++      bp9: buffer-pool@9 {
++              compatible = "fsl,ls1046a-bpool", "fsl,bpool";
++              fsl,bpid = <9>;
++              fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>;
++              fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>;
++      };
++
++      fsl,dpaa {
++              compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus";
++
++              ethernet@2 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x54 1 0x55 1>;
++                      fsl,qman-frame-queues-tx = <0x74 1 0x75 1>;
++              };
++
++              ethernet@3 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x56 1 0x57 1>;
++                      fsl,qman-frame-queues-tx = <0x76 1 0x77 1>;
++              };
++
++              ethernet@4 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x58 1 0x59 1>;
++                      fsl,qman-frame-queues-tx = <0x78 1 0x79 1>;
++              };
++
++              ethernet@5 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>;
++                      fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>;
++              };
++
++              ethernet@8 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>;
++                      fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>;
++              };
++
++              ethernet@9 {
++                      compatible = "fsl,dpa-ethernet-init";
++                      fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>;
++                      fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>;
++                      fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>;
++              };
++
++              dpa-fman0-oh@2 {
++                      compatible = "fsl,dpa-oh";
++                      /* Define frame queues for the OH port*/
++                      /* <OH Rx error, OH Rx default> */
++                      fsl,qman-frame-queues-oh = <0x60 1 0x61 1>;
++                      fsl,fman-oh-port = <&fman0_oh2>;
++              };
++      };
++};
++/ {
++      reserved-memory {
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              usdpaa_mem: usdpaa_mem {
++                      compatible = "fsl,usdpaa-mem";
++                      alloc-ranges = <0 0 0x10000 0>;
++                      size = <0 0x10000000>;
++                      alignment = <0 0x10000000>;
++              };
++      };
++};
++
++&fman0 {
++      fman0_oh2: port@83000 {
++              cell-index = <1>;
++              compatible = "fsl,fman-port-oh";
++              reg = <0x83000 0x1000>;
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+new file mode 100644
+index 00000000..be9b62ca
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+@@ -0,0 +1,218 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <mingkai.hu@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1046a.dtsi"
++
++/ {
++      model = "LS1046A RDB Board";
++      compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
++
++      aliases {
++              serial0 = &duart0;
++              serial1 = &duart1;
++              serial2 = &duart2;
++              serial3 = &duart3;
++      };
++
++      chosen {
++              stdout-path = "serial0:115200n8";
++      };
++};
++
++&esdhc {
++      mmc-hs200-1_8v;
++      sd-uhs-sdr104;
++      sd-uhs-sdr50;
++      sd-uhs-sdr25;
++      sd-uhs-sdr12;
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&duart1 {
++      status = "okay";
++};
++
++&i2c0 {
++      status = "okay";
++
++      ina220@40 {
++              compatible = "ti,ina220";
++              reg = <0x40>;
++              shunt-resistor = <1000>;
++      };
++
++      temp-sensor@4c {
++              compatible = "adi,adt7461";
++              reg = <0x4c>;
++      };
++
++      eeprom@56 {
++              compatible = "atmel,24c512";
++              reg = <0x52>;
++      };
++
++      eeprom@57 {
++              compatible = "atmel,24c512";
++              reg = <0x53>;
++      };
++};
++
++&i2c3 {
++      status = "okay";
++
++      rtc@51 {
++              compatible = "nxp,pcf2129";
++              reg = <0x51>;
++      };
++};
++
++&ifc {
++      #address-cells = <2>;
++      #size-cells = <1>;
++      /* NAND Flashe and CPLD on board */
++      ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
++                0x2 0x0 0x0 0x7fb00000 0x00000100>;
++      status = "okay";
++
++      nand@0,0 {
++              compatible = "fsl,ifc-nand";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              reg = <0x0 0x0 0x10000>;
++      };
++
++      cpld: board-control@2,0 {
++              compatible = "fsl,ls1046ardb-cpld";
++              reg = <0x2 0x0 0x0000100>;
++      };
++};
++
++&qspi {
++      num-cs = <2>;
++      bus-num = <0>;
++      status = "okay";
++
++      qflash0: s25fs512s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++
++      qflash1: s25fs512s@1 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              reg = <1>;
++      };
++};
++
++#include "fsl-ls1046-post.dtsi"
++
++&fman0 {
++      ethernet@e4000 {
++              phy-handle = <&rgmii_phy1>;
++              phy-connection-type = "rgmii";
++      };
++
++      ethernet@e6000 {
++              phy-handle = <&rgmii_phy2>;
++              phy-connection-type = "rgmii";
++      };
++
++      ethernet@e8000 {
++              phy-handle = <&sgmii_phy1>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@ea000 {
++              phy-handle = <&sgmii_phy2>;
++              phy-connection-type = "sgmii";
++      };
++
++      ethernet@f0000 { /* 10GEC1 */
++              phy-handle = <&aqr106_phy>;
++              phy-connection-type = "xgmii";
++      };
++
++      ethernet@f2000 { /* 10GEC2 */
++              fixed-link = <0 1 1000 0 0>;
++              phy-connection-type = "xgmii";
++      };
++
++      mdio@fc000 {
++              rgmii_phy1: ethernet-phy@1 {
++                      reg = <0x1>;
++              };
++
++              rgmii_phy2: ethernet-phy@2 {
++                      reg = <0x2>;
++              };
++
++              sgmii_phy1: ethernet-phy@3 {
++                      reg = <0x3>;
++              };
++
++              sgmii_phy2: ethernet-phy@4 {
++                      reg = <0x4>;
++              };
++      };
++
++      mdio@fd000 {
++              aqr106_phy: ethernet-phy@0 {
++                      compatible = "ethernet-phy-ieee802.3-c45";
++                      interrupts = <0 131 4>;
++                      reg = <0x0>;
++              };
++      };
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+new file mode 100644
+index 00000000..6b87266f
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+@@ -0,0 +1,793 @@
++/*
++ * Device Tree Include file for Freescale Layerscape-1046A family SoC.
++ *
++ * Copyright 2016 Freescale Semiconductor, Inc.
++ *
++ * Mingkai Hu <mingkai.hu@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/thermal/thermal.h>
++
++/ {
++      compatible = "fsl,ls1046a";
++      interrupt-parent = <&gic>;
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      aliases {
++              crypto = &crypto;
++              fman0 = &fman0;
++              ethernet0 = &enet0;
++              ethernet1 = &enet1;
++              ethernet2 = &enet2;
++              ethernet3 = &enet3;
++              ethernet4 = &enet4;
++              ethernet5 = &enet5;
++              ethernet6 = &enet6;
++              ethernet7 = &enet7;
++      };
++
++      cpus {
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              cpu0: cpu@0 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a72";
++                      reg = <0x0>;
++                      clocks = <&clockgen 1 0>;
++                      next-level-cache = <&l2>;
++                      cpu-idle-states = <&CPU_PH20>;
++                      #cooling-cells = <2>;
++              };
++
++              cpu1: cpu@1 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a72";
++                      reg = <0x1>;
++                      clocks = <&clockgen 1 0>;
++                      next-level-cache = <&l2>;
++                      cpu-idle-states = <&CPU_PH20>;
++              };
++
++              cpu2: cpu@2 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a72";
++                      reg = <0x2>;
++                      clocks = <&clockgen 1 0>;
++                      next-level-cache = <&l2>;
++                      cpu-idle-states = <&CPU_PH20>;
++              };
++
++              cpu3: cpu@3 {
++                      device_type = "cpu";
++                      compatible = "arm,cortex-a72";
++                      reg = <0x3>;
++                      clocks = <&clockgen 1 0>;
++                      next-level-cache = <&l2>;
++                      cpu-idle-states = <&CPU_PH20>;
++              };
++
++              l2: l2-cache {
++                      compatible = "cache";
++              };
++      };
++
++      idle-states {
++              /*
++               * PSCI node is not added default, U-boot will add missing
++               * parts if it determines to use PSCI.
++               */
++              entry-method = "arm,psci";
++
++              CPU_PH20: cpu-ph20 {
++                      compatible = "arm,idle-state";
++                      idle-state-name = "PH20";
++                      arm,psci-suspend-param = <0x0>;
++                      entry-latency-us = <1000>;
++                      exit-latency-us = <1000>;
++                      min-residency-us = <3000>;
++              };
++      };
++
++      memory@80000000 {
++              device_type = "memory";
++      };
++
++      sysclk: sysclk {
++              compatible = "fixed-clock";
++              #clock-cells = <0>;
++              clock-frequency = <100000000>;
++              clock-output-names = "sysclk";
++      };
++
++      reboot {
++              compatible ="syscon-reboot";
++              regmap = <&dcfg>;
++              offset = <0xb0>;
++              mask = <0x02>;
++      };
++
++      timer {
++              compatible = "arm,armv8-timer";
++              interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
++                                        IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
++                                        IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
++                                        IRQ_TYPE_LEVEL_LOW)>,
++                           <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
++                                        IRQ_TYPE_LEVEL_LOW)>;
++      };
++
++      pmu {
++              compatible = "arm,cortex-a72-pmu";
++              interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
++                           <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
++                           <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++                           <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++              interrupt-affinity = <&cpu0>,
++                                   <&cpu1>,
++                                   <&cpu2>,
++                                   <&cpu3>;
++      };
++
++      gic: interrupt-controller@1400000 {
++              compatible = "arm,gic-400";
++              #interrupt-cells = <3>;
++              interrupt-controller;
++              reg = <0x0 0x1410000 0 0x10000>, /* GICD */
++                    <0x0 0x1420000 0 0x20000>, /* GICC */
++                    <0x0 0x1440000 0 0x20000>, /* GICH */
++                    <0x0 0x1460000 0 0x20000>; /* GICV */
++              interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
++                                       IRQ_TYPE_LEVEL_LOW)>;
++      };
++
++      soc: soc {
++              compatible = "simple-bus";
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              ddr: memory-controller@1080000 {
++                      compatible = "fsl,qoriq-memory-controller";
++                      reg = <0x0 0x1080000 0x0 0x1000>;
++                      interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
++                      big-endian;
++              };
++
++              ifc: ifc@1530000 {
++                      compatible = "fsl,ifc", "simple-bus";
++                      reg = <0x0 0x1530000 0x0 0x10000>;
++                      big-endian;
++                      interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++              qspi: quadspi@1550000 {
++                      compatible = "fsl,ls1021a-qspi";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x1550000 0x0 0x10000>,
++                              <0x0 0x40000000 0x0 0x10000000>;
++                      reg-names = "QuadSPI", "QuadSPI-memory";
++                      interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
++                      clock-names = "qspi_en", "qspi";
++                      clocks = <&clockgen 4 1>, <&clockgen 4 1>;
++                      big-endian;
++                      fsl,qspi-has-second-chip;
++                      status = "disabled";
++              };
++
++              esdhc: esdhc@1560000 {
++                      compatible = "fsl,ls1046a-esdhc", "fsl,esdhc";
++                      reg = <0x0 0x1560000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 2 1>;
++                      voltage-ranges = <1800 1800 3300 3300>;
++                      sdhci,auto-cmd12;
++                      big-endian;
++                      bus-width = <4>;
++              };
++
++              scfg: scfg@1570000 {
++                      compatible = "fsl,ls1046a-scfg", "syscon";
++                      reg = <0x0 0x1570000 0x0 0x10000>;
++                      big-endian;
++              };
++
++              crypto: crypto@1700000 {
++                      compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
++                                   "fsl,sec-v4.0";
++                      fsl,sec-era = <8>;
++                      #address-cells = <1>;
++                      #size-cells = <1>;
++                      ranges = <0x0 0x00 0x1700000 0x100000>;
++                      reg = <0x00 0x1700000 0x0 0x100000>;
++                      interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
++
++                      sec_jr0: jr@10000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x10000 0x10000>;
++                              interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      sec_jr1: jr@20000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x20000 0x10000>;
++                              interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      sec_jr2: jr@30000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x30000 0x10000>;
++                              interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      sec_jr3: jr@40000 {
++                              compatible = "fsl,sec-v5.4-job-ring",
++                                           "fsl,sec-v5.0-job-ring",
++                                           "fsl,sec-v4.0-job-ring";
++                              reg        = <0x40000 0x10000>;
++                              interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++              };
++
++              qman: qman@1880000 {
++                      compatible = "fsl,qman";
++                      reg = <0x00 0x1880000 0x0 0x10000>;
++                      interrupts = <0 45 0x4>;
++                      memory-region = <&qman_fqd &qman_pfdr>;
++
++              };
++
++              bman: bman@1890000 {
++                      compatible = "fsl,bman";
++                      reg = <0x00 0x1890000 0x0 0x10000>;
++                      interrupts = <0 45 0x4>;
++                      memory-region = <&bman_fbpr>;
++
++              };
++
++              qportals: qman-portals@500000000 {
++                      ranges = <0x0 0x5 0x00000000 0x8000000>;
++              };
++
++              bportals: bman-portals@508000000 {
++                      ranges = <0x0 0x5 0x08000000 0x8000000>;
++              };
++
++              dcfg: dcfg@1ee0000 {
++                      compatible = "fsl,ls1046a-dcfg", "syscon";
++                      reg = <0x0 0x1ee0000 0x0 0x1000>;
++                      big-endian;
++              };
++
++              clockgen: clocking@1ee1000 {
++                      compatible = "fsl,ls1046a-clockgen";
++                      reg = <0x0 0x1ee1000 0x0 0x1000>;
++                      #clock-cells = <2>;
++                      clocks = <&sysclk>;
++              };
++
++              tmu: tmu@1f00000 {
++                      compatible = "fsl,qoriq-tmu";
++                      reg = <0x0 0x1f00000 0x0 0x10000>;
++                      interrupts = <0 33 0x4>;
++                      fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
++                      fsl,tmu-calibration =
++                              /* Calibration data group 1 */
++                              <0x00000000 0x00000026
++                              0x00000001 0x0000002d
++                              0x00000002 0x00000032
++                              0x00000003 0x00000039
++                              0x00000004 0x0000003f
++                              0x00000005 0x00000046
++                              0x00000006 0x0000004d
++                              0x00000007 0x00000054
++                              0x00000008 0x0000005a
++                              0x00000009 0x00000061
++                              0x0000000a 0x0000006a
++                              0x0000000b 0x00000071
++                              /* Calibration data group 2 */
++                              0x00010000 0x00000025
++                              0x00010001 0x0000002c
++                              0x00010002 0x00000035
++                              0x00010003 0x0000003d
++                              0x00010004 0x00000045
++                              0x00010005 0x0000004e
++                              0x00010006 0x00000057
++                              0x00010007 0x00000061
++                              0x00010008 0x0000006b
++                              0x00010009 0x00000076
++                              /* Calibration data group 3 */
++                              0x00020000 0x00000029
++                              0x00020001 0x00000033
++                              0x00020002 0x0000003d
++                              0x00020003 0x00000049
++                              0x00020004 0x00000056
++                              0x00020005 0x00000061
++                              0x00020006 0x0000006d
++                              /* Calibration data group 4 */
++                              0x00030000 0x00000021
++                              0x00030001 0x0000002a
++                              0x00030002 0x0000003c
++                              0x00030003 0x0000004e>;
++                      big-endian;
++                      #thermal-sensor-cells = <1>;
++              };
++
++              thermal-zones {
++                      cpu_thermal: cpu-thermal {
++                              polling-delay-passive = <1000>;
++                              polling-delay = <5000>;
++                              thermal-sensors = <&tmu 3>;
++
++                              trips {
++                                      cpu_alert: cpu-alert {
++                                              temperature = <85000>;
++                                              hysteresis = <2000>;
++                                              type = "passive";
++                                      };
++
++                                      cpu_crit: cpu-crit {
++                                              temperature = <95000>;
++                                              hysteresis = <2000>;
++                                              type = "critical";
++                                      };
++                              };
++
++                              cooling-maps {
++                                      map0 {
++                                              trip = <&cpu_alert>;
++                                              cooling-device =
++                                                      <&cpu0 THERMAL_NO_LIMIT
++                                                      THERMAL_NO_LIMIT>;
++                                      };
++                              };
++                      };
++              };
++
++              dspi: dspi@2100000 {
++                      compatible = "fsl,ls1021a-v1.0-dspi";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2100000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
++                      clock-names = "dspi";
++                      clocks = <&clockgen 4 1>;
++                      spi-num-chipselects = <5>;
++                      big-endian;
++                      status = "disabled";
++              };
++
++              i2c0: i2c@2180000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2180000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      dmas = <&edma0 1 39>,
++                             <&edma0 1 38>;
++                      dma-names = "tx", "rx";
++                      status = "disabled";
++              };
++
++              i2c1: i2c@2190000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x2190000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      status = "disabled";
++              };
++
++              i2c2: i2c@21a0000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x21a0000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      status = "disabled";
++              };
++
++              i2c3: i2c@21b0000 {
++                      compatible = "fsl,vf610-i2c";
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x0 0x21b0000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      status = "disabled";
++              };
++
++              duart0: serial@21c0500 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x00 0x21c0500 0x0 0x100>;
++                      interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++              };
++
++              duart1: serial@21c0600 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x00 0x21c0600 0x0 0x100>;
++                      interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++              };
++
++              duart2: serial@21d0500 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x0 0x21d0500 0x0 0x100>;
++                      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++              };
++
++              duart3: serial@21d0600 {
++                      compatible = "fsl,ns16550", "ns16550a";
++                      reg = <0x0 0x21d0600 0x0 0x100>;
++                      interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++              };
++
++              gpio0: gpio@2300000 {
++                      compatible = "fsl,qoriq-gpio";
++                      reg = <0x0 0x2300000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++              };
++
++              gpio1: gpio@2310000 {
++                      compatible = "fsl,qoriq-gpio";
++                      reg = <0x0 0x2310000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++              };
++
++              gpio2: gpio@2320000 {
++                      compatible = "fsl,qoriq-gpio";
++                      reg = <0x0 0x2320000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++              };
++
++              gpio3: gpio@2330000 {
++                      compatible = "fsl,qoriq-gpio";
++                      reg = <0x0 0x2330000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
++                      gpio-controller;
++                      #gpio-cells = <2>;
++                      interrupt-controller;
++                      #interrupt-cells = <2>;
++              };
++
++              lpuart0: serial@2950000 {
++                      compatible = "fsl,ls1021a-lpuart";
++                      reg = <0x0 0x2950000 0x0 0x1000>;
++                      interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 0>;
++                      clock-names = "ipg";
++                      status = "disabled";
++              };
++
++              lpuart1: serial@2960000 {
++                      compatible = "fsl,ls1021a-lpuart";
++                      reg = <0x0 0x2960000 0x0 0x1000>;
++                      interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      clock-names = "ipg";
++                      status = "disabled";
++              };
++
++              lpuart2: serial@2970000 {
++                      compatible = "fsl,ls1021a-lpuart";
++                      reg = <0x0 0x2970000 0x0 0x1000>;
++                      interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      clock-names = "ipg";
++                      status = "disabled";
++              };
++
++              lpuart3: serial@2980000 {
++                      compatible = "fsl,ls1021a-lpuart";
++                      reg = <0x0 0x2980000 0x0 0x1000>;
++                      interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      clock-names = "ipg";
++                      status = "disabled";
++              };
++
++              lpuart4: serial@2990000 {
++                      compatible = "fsl,ls1021a-lpuart";
++                      reg = <0x0 0x2990000 0x0 0x1000>;
++                      interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      clock-names = "ipg";
++                      status = "disabled";
++              };
++
++              lpuart5: serial@29a0000 {
++                      compatible = "fsl,ls1021a-lpuart";
++                      reg = <0x0 0x29a0000 0x0 0x1000>;
++                      interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      clock-names = "ipg";
++                      status = "disabled";
++              };
++
++              ftm0: ftm0@29d0000 {
++                      compatible = "fsl,ftm-alarm";
++                      reg = <0x0 0x29d0000 0x0 0x10000>,
++                            <0x0 0x1ee2140 0x0 0x4>;
++                      reg-names = "ftm", "FlexTimer1";
++                      interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
++                      big-endian;
++              };
++
++              wdog0: watchdog@2ad0000 {
++                      compatible = "fsl,imx21-wdt";
++                      reg = <0x0 0x2ad0000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      big-endian;
++              };
++
++              edma0: edma@2c00000 {
++                      #dma-cells = <2>;
++                      compatible = "fsl,vf610-edma";
++                      reg = <0x0 0x2c00000 0x0 0x10000>,
++                            <0x0 0x2c10000 0x0 0x10000>,
++                            <0x0 0x2c20000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
++                      interrupt-names = "edma-tx", "edma-err";
++                      dma-channels = <32>;
++                      big-endian;
++                      clock-names = "dmamux0", "dmamux1";
++                      clocks = <&clockgen 4 1>,
++                               <&clockgen 4 1>;
++              };
++
++              usb0: usb@2f00000 {
++                      compatible = "snps,dwc3";
++                      reg = <0x0 0x2f00000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
++                      dr_mode = "host";
++                      snps,quirk-frame-length-adjustment = <0x20>;
++                      snps,dis_rxdet_inp3_quirk;
++              };
++
++              usb1: usb@3000000 {
++                      compatible = "snps,dwc3";
++                      reg = <0x0 0x3000000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
++                      dr_mode = "host";
++                      snps,quirk-frame-length-adjustment = <0x20>;
++                      snps,dis_rxdet_inp3_quirk;
++              };
++
++              usb2: usb@3100000 {
++                      compatible = "snps,dwc3";
++                      reg = <0x0 0x3100000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++                      dr_mode = "host";
++                      snps,quirk-frame-length-adjustment = <0x20>;
++                      snps,dis_rxdet_inp3_quirk;
++              };
++
++              sata: sata@3200000 {
++                      compatible = "fsl,ls1046a-ahci";
++                      reg = <0x0 0x3200000 0x0 0x10000>,
++                              <0x0 0x20140520 0x0 0x4>;
++                      reg-names = "ahci", "sata-ecc";
++                      interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
++                      clocks = <&clockgen 4 1>;
++                      dma-coherent;
++              };
++
++              qdma: qdma@8380000 {
++                      compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
++                      reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
++                            <0x0 0x8390000 0x0 0x10000>, /* Status regs */
++                            <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
++                      interrupts = <0 153 0x4>,
++                                   <0 39 0x4>;
++                      interrupt-names = "qdma-error", "qdma-queue";
++                      channels = <8>;
++                      queues = <2>;
++                      status-sizes = <64>;
++                      queue-sizes = <64 64>;
++                      big-endian;
++              };
++
++              msi1: msi-controller@1580000 {
++                      compatible = "fsl,ls1046a-msi";
++                      msi-controller;
++                      reg = <0x0 0x1580000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++              msi2: msi-controller@1590000 {
++                      compatible = "fsl,ls1046a-msi";
++                      msi-controller;
++                      reg = <0x0 0x1590000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++              msi3: msi-controller@15a0000 {
++                      compatible = "fsl,ls1046a-msi";
++                      msi-controller;
++                      reg = <0x0 0x15a0000 0x0 0x10000>;
++                      interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++              pcie@3400000 {
++                      compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++                      reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
++                             0x40 0x00000000 0x0 0x00002000>; /* configuration space */
++                      reg-names = "regs", "config";
++                      interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
++                                   <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
++                      interrupt-names = "pme", "aer";
++                      #address-cells = <3>;
++                      #size-cells = <2>;
++                      device_type = "pci";
++                      dma-coherent;
++                      num-lanes = <4>;
++                      bus-range = <0x0 0xff>;
++                      ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
++                                0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++                      msi-parent = <&msi1>, <&msi2>, <&msi3>;
++                      #interrupt-cells = <1>;
++                      interrupt-map-mask = <0 0 0 7>;
++                      interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++              pcie@3500000 {
++                      compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++                      reg = <0x00 0x03500000 0x0 0x00100000   /* controller registers */
++                             0x48 0x00000000 0x0 0x00002000>; /* configuration space */
++                      reg-names = "regs", "config";
++                      interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
++                      interrupt-names = "pme", "aer";
++                      #address-cells = <3>;
++                      #size-cells = <2>;
++                      device_type = "pci";
++                      dma-coherent;
++                      num-lanes = <2>;
++                      bus-range = <0x0 0xff>;
++                      ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
++                                0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++                      msi-parent = <&msi1>, <&msi2>, <&msi3>;
++                      #interrupt-cells = <1>;
++                      interrupt-map-mask = <0 0 0 7>;
++                      interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++              pcie@3600000 {
++                      compatible = "fsl,ls1046a-pcie", "snps,dw-pcie";
++                      reg = <0x00 0x03600000 0x0 0x00100000   /* controller registers */
++                             0x50 0x00000000 0x0 0x00002000>; /* configuration space */
++                      reg-names = "regs", "config";
++                      interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
++                                   <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
++                      interrupt-names = "pme", "aer";
++                      #address-cells = <3>;
++                      #size-cells = <2>;
++                      device_type = "pci";
++                      dma-coherent;
++                      num-lanes = <2>;
++                      bus-range = <0x0 0xff>;
++                      ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000   /* downstream I/O */
++                                0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
++                      msi-parent = <&msi1>, <&msi2>, <&msi3>;
++                      #interrupt-cells = <1>;
++                      interrupt-map-mask = <0 0 0 7>;
++                      interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
++                                      <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
++              };
++
++      };
++
++      reserved-memory {
++              #address-cells = <2>;
++              #size-cells = <2>;
++              ranges;
++
++              bman_fbpr: bman-fbpr {
++                      compatible = "shared-dma-pool";
++                      size = <0 0x1000000>;
++                      alignment = <0 0x1000000>;
++                      no-map;
++              };
++              qman_fqd: qman-fqd {
++                      compatible = "shared-dma-pool";
++                      size = <0 0x800000>;
++                      alignment = <0 0x800000>;
++                      no-map;
++              };
++              qman_pfdr: qman-pfdr {
++                      compatible = "shared-dma-pool";
++                      size = <0 0x2000000>;
++                      alignment = <0 0x2000000>;
++                      no-map;
++              };
++      };
++};
++
++#include "qoriq-qman1-portals.dtsi"
++#include "qoriq-bman1-portals.dtsi"
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+new file mode 100644
+index 00000000..f61ec261
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts
+@@ -0,0 +1,173 @@
++/*
++ * Device Tree file for NXP LS1088A QDS Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Harninder Rai <harninder.rai@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1088a.dtsi"
++
++/ {
++      model = "LS1088A QDS Board";
++      compatible = "fsl,ls1088a-qds", "fsl,ls1088a";
++};
++
++&i2c0 {
++      status = "okay";
++
++      i2c-switch@77 {
++              compatible = "nxp,pca9547";
++              reg = <0x77>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              i2c@2 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x2>;
++
++                      ina220@40 {
++                              compatible = "ti,ina220";
++                              reg = <0x40>;
++                              shunt-resistor = <1000>;
++                      };
++
++                      ina220@41 {
++                              compatible = "ti,ina220";
++                              reg = <0x41>;
++                              shunt-resistor = <1000>;
++                      };
++              };
++
++              i2c@3 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x3>;
++
++                      temp-sensor@4c {
++                              compatible = "adi,adt7461a";
++                              reg = <0x4c>;
++                      };
++
++                      rtc@51 {
++                              compatible = "nxp,pcf2129";
++                              reg = <0x51>;
++                              /* IRQ10_B */
++                              interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++
++                      eeprom@56 {
++                              compatible = "atmel,24c512";
++                              reg = <0x56>;
++                      };
++
++                      eeprom@57 {
++                              compatible = "atmel,24c512";
++                              reg = <0x57>;
++                      };
++              };
++      };
++};
++
++&qspi {
++      status = "okay";
++      qflash0: s25fs512s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              m25p,fast-read;
++              reg = <0>;
++      };
++
++      qflash1: s25fs512s@1 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              spi-max-frequency = <20000000>;
++              m25p,fast-read;
++              reg = <1>;
++      };
++};
++
++&ifc {
++      status = "okay";
++
++      ranges = <0 0 0x5 0x80000000 0x08000000
++                2 0 0x5 0x30000000 0x00010000
++                3 0 0x5 0x20000000 0x00010000>;
++
++      nor@0,0 {
++              compatible = "cfi-flash";
++              reg = <0x0 0x0 0x8000000>;
++              bank-width = <2>;
++              device-width = <1>;
++      };
++
++      nand@2,0 {
++              compatible = "fsl,ifc-nand";
++              reg = <0x2 0x0 0x10000>;
++      };
++
++      fpga: board-control@3,0 {
++              compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis";
++              reg = <0x3 0x0 0x0000100>;
++      };
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&duart1 {
++      status = "okay";
++};
++
++&esdhc {
++      status = "okay";
++};
++
++&sata {
++      status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+new file mode 100644
+index 00000000..a4cbc2d5
+--- /dev/null
++++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
+@@ -0,0 +1,236 @@
++/*
++ * Device Tree file for NXP LS1088A RDB Board.
++ *
++ * Copyright 2017 NXP
++ *
++ * Harninder Rai <harninder.rai@nxp.com>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPLv2 or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This library is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This library is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++
++#include "fsl-ls1088a.dtsi"
++
++/ {
++      model = "L1088A RDB Board";
++      compatible = "fsl,ls1088a-rdb", "fsl,ls1088a";
++};
++
++&i2c0 {
++      status = "okay";
++
++      i2c-switch@77 {
++              compatible = "nxp,pca9547";
++              reg = <0x77>;
++              #address-cells = <1>;
++              #size-cells = <0>;
++
++              i2c@2 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x2>;
++
++                      ina220@40 {
++                              compatible = "ti,ina220";
++                              reg = <0x40>;
++                              shunt-resistor = <1000>;
++                      };
++              };
++
++              i2c@3 {
++                      #address-cells = <1>;
++                      #size-cells = <0>;
++                      reg = <0x3>;
++
++                      temp-sensor@4c {
++                              compatible = "adi,adt7461a";
++                              reg = <0x4c>;
++                      };
++
++                      rtc@51 {
++                              compatible = "nxp,pcf2129";
++                              reg = <0x51>;
++                              /* IRQ10_B */
++                              interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
++                      };
++              };
++      };
++};
++
++&qspi {
++      status = "okay";
++      qflash0: s25fs512s@0 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              m25p,fast-read;
++              spi-max-frequency = <20000000>;
++              reg = <0>;
++      };
++
++      qflash1: s25fs512s@1 {
++              compatible = "spansion,m25p80";
++              #address-cells = <1>;
++              #size-cells = <1>;
++              m25p,fast-read;
++              spi-max-frequency = <20000000>;
++              reg = <1>;
++      };
++};
++
++&ifc {
++      status = "okay";
++
++      ranges = <0 0 0x5 0x30000000 0x00010000
++                2 0 0x5 0x20000000 0x00010000>;
++
++      nand@0,0 {
++              compatible = "fsl,ifc-nand";
++              reg = <0x0 0x0 0x10000>;
++      };
++
++      fpga: board-control@2,0 {
++              compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis";
++              reg = <0x2 0x0 0x0000100>;
++      };
++};
++
++&duart0 {
++      status = "okay";
++};
++
++&duart1 {
++      status = "okay";
++};
++
++&usb0 {
++      status = "okay";
++};
++
++&usb1 {
++      status = "okay";
++};
++
++&esdhc {
++      status = "okay";
++};
++
++&sata {
++      status = "okay";
++};
++
++&emdio1 {
++      /* Freescale F104 PHY1 */
++      mdio1_phy1: emdio1_phy@1 {
++              reg = <0x1c>;
++              phy-connection-type = "qsgmii";
++      };
++      mdio1_phy2: emdio1_phy@2 {
++              reg = <0x1d>;
++              phy-connection-type = "qsgmii";
++      };
++      mdio1_phy3: emdio1_phy@3 {
++              reg = <0x1e>;
++              phy-connection-type = "qsgmii";
++      };
++      mdio1_phy4: emdio1_phy@4 {
++              reg = <0x1f>;
++              phy-connection-type = "qsgmii";
++      };
++      /* F104 PHY2 */
++      mdio1_phy5: emdio1_phy@5 {
++              reg = <0x0c>;
++              phy-connection-type = "qsgmii";
++      };
++      mdio1_phy6: emdio1_phy@6 {
++              reg = <0x0d>;
++              phy-connection-type = "qsgmii";
++      };
++      mdio1_phy7: emdio1_phy@7 {
++              reg = <0x0e>;
++              phy-connection-type = "qsgmii";
++      };
++      mdio1_phy8: emdio1_phy@8 {
++              reg = <0x0f>;
++              phy-connection-type = "qsgmii";
++      };
++};
++
++&emdio2 {
++      /* Aquantia AQR105 10G PHY */
++      mdio2_phy1: emdio2_phy@1 {
++              compatible = "ethernet-phy-ieee802.3-c45";
++              interrupts = <0 2 0x4>;
++              reg = <0x0>;
++              phy-connection-type = "xfi";
++      };
++};
++
++/* DPMAC connections to external PHYs
++ * based on LS1088A RM RevC - $24.1.2 SerDes Options
++ */
++/* DPMAC1 is 10G SFP+, fixed link */
++&dpmac2 {
++      phy-handle = <&mdio2_phy1>;
++};
++&dpmac3 {
++      phy-handle = <&mdio1_phy5>;