Cc: Helmut Schaa <helmut.schaa@googlemail.com>,
linux-wireless@vger.kernel.org,
Kalle Valo <kvalo@codeaurora.org>
+Content-Type: text/plain; charset="UTF-8"
+Content-Transfer-Encoding: quoted-printable
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Tomislav Po=C5=BEega <pozega.tomislav@gmail.com>
+[pozega.tomislav@gmail.com: use chanreg and dccal helpers.]
+
---
drivers/net/wireless/ralink/rt2x00/rt2800.h | 1 +
drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 70 +++++++++++++++++++++++++-
* EEPROM LNA
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-@@ -4290,6 +4290,61 @@ static void rt2800_config_channel(struct
+@@ -4290,6 +4290,45 @@ static void rt2800_config_channel(struct
rt2800_iq_calibrate(rt2x00dev, rf->channel);
}
+ reg |= 0x00000101;
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
+
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 43, 0x73);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 43, 0x73);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 44, 0x73);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 44, 0x73);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 45, 0x73);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0x73);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 46, 0x27);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 46, 0x27);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0xC8);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0xC8);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 48, 0xA4);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 48, 0xA4);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 49, 0x05);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 49, 0x05);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x27);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 55, 0xC8);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 55, 0xC8);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 56, 0xA4);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 56, 0xA4);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 57, 0x05);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 57, 0x05);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 58, 0x27);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 58, 0x27);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 59, 0xC8);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 59, 0xC8);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 60, 0xA4);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 60, 0xA4);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 4, 61, 0x05);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 6, 61, 0x05);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 5, 05, 0x00);
-+ rt2800_rfcsr_write_bank(rt2x00dev, 7, 05, 0x00);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
++ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
++ rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
+
+ rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
+ 0x36303636);
bbp = rt2800_bbp_read(rt2x00dev, 4);
rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
rt2800_bbp_write(rt2x00dev, 4, bbp);
-@@ -9487,7 +9542,8 @@ static int rt2800_init_eeprom(struct rt2
+@@ -9487,7 +9526,8 @@ static int rt2800_init_eeprom(struct rt2
*/
eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
if (rt2x00_get_field16(eeprom,
EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
__set_bit(CAPABILITY_EXTERNAL_PA_TX0,
-@@ -9498,6 +9554,18 @@ static int rt2800_init_eeprom(struct rt2
+@@ -9498,6 +9538,18 @@ static int rt2800_init_eeprom(struct rt2
&rt2x00dev->cap_flags);
}
+++ /dev/null
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-Date: Thu, 18 May 2017 12:42:14 +0200
-Message-ID: <CAKR_QVJBSKw2uCY4RbHZPvbGkMcvnBh+j6F+9t93mG3BakjX3Q@mail.gmail.com>
-Subject: [PATCH] rt2x00: remove unneccesary code
-To: linux-wireless <linux-wireless@vger.kernel.org>,
- Linux Kernel Mailing List <linux-kernel@vger.kernel.org>, Arnd Bergmann <arnd@arndb.de>,
- Jes Sorensen <jes.sorensen@gmail.com>, Stanislaw Gruszka <sgruszka@redhat.com>,
- David Miller <davem@davemloft.net>, Helmut Schaa <helmut.schaa@googlemail.com>,
- Kalle Valo <kvalo@codeaurora.org>, Daniel Golle <daniel@makrotopia.org>,
- Mathias Kresin <dev@kresin.me>, Johannes Berg <johannes.berg@intel.com>,
- Serge Vasilugin <vasilugin@yandex.ru>, Roman Yeryomin <roman@advem.lv>,
- Networking <netdev@vger.kernel.org>
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-
---94eb2c1905d2dc6361054fca0e62
-Content-Type: text/plain; charset="UTF-8"
-Content-Transfer-Encoding: quoted-printable
-
-Use chanreg and dccal helpers to reduce the size of ePA code.
-
-Signed-off-by: Tomislav Po=C5=BEega <pozega.tomislav@gmail.com>
-Signed-off-by: Daniel Golle <daniel@makrotopia.org>
-[daniel@makrotopia.org: fixed white-space so patch applies]
----
-
---- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-@@ -4303,38 +4303,22 @@ static void rt2800_config_channel(struct
- reg |= 0x00000101;
- rt2800_register_write(rt2x00dev, RF_BYPASS3, reg);
-
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 43, 0x73);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 43, 0x73);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 44, 0x73);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 44, 0x73);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 45, 0x73);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0x73);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 46, 0x27);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 46, 0x27);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0xC8);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0xC8);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 48, 0xA4);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 48, 0xA4);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 49, 0x05);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 49, 0x05);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x27);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 55, 0xC8);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 55, 0xC8);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 56, 0xA4);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 56, 0xA4);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 57, 0x05);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 57, 0x05);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 58, 0x27);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 58, 0x27);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 59, 0xC8);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 59, 0xC8);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 60, 0xA4);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 60, 0xA4);
-- rt2800_rfcsr_write_bank(rt2x00dev, 4, 61, 0x05);
-- rt2800_rfcsr_write_bank(rt2x00dev, 6, 61, 0x05);
-- rt2800_rfcsr_write_bank(rt2x00dev, 5, 05, 0x00);
-- rt2800_rfcsr_write_bank(rt2x00dev, 7, 05, 0x00);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0x73);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0x73);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0x73);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0xC8);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xA4);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x05);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xC8);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xA4);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x05);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x27);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0xC8);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xA4);
-+ rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x05);
-+ rt2800_rfcsr_write_dccal(rt2x00dev, 05, 0x00);
-
- rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
- 0x36303636);
--- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
+++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
-@@ -9000,6 +9000,957 @@ restore_value:
+@@ -9000,6 +9000,954 @@ restore_value:
}
EXPORT_SYMBOL_GPL(rt2800_rxiq_calibration);
+ for (record_index = 0; record_index < 13; record_index++) {
+ bank = rf_record[chain_index][record_index].bank;
+ rf_register = rf_record[chain_index][record_index].reg;
-+ value = rf_record[chain_index][record_index].value;
++ value = rf_record[chain_index][record_index].value;
+ rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
+ rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n", bank, rf_register, value);
+ }
+ rt2800_bbp_write(rt2x00dev, 159, tidxi);
+ rt2800_bbp_write(rt2x00dev, 159, tidxi);
+ rt2800_bbp_write(rt2x00dev, 159, tidxi);
-+
++
+ macvalue = rt2800_register_read(rt2x00dev, 0x057C);
-+
++
+ fftout_i = (macvalue >> 16);
+ fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
+ fftout_q = (macvalue & 0xffff);
+ ptmp = (fftout_i * fftout_i);
+ ptmp = ptmp + (fftout_q * fftout_q);
+ ptmp = ptmp >> 1;
-+ pint = pint + ptmp;
-+
++ pint = pint + ptmp;
+ }
+
+ return pint;
+}
+EXPORT_SYMBOL_GPL(rt2800_write_dc);
+
-+static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
++static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
+{
+ u32 p0 = 0, p1 = 0, pf = 0;
+ char idx0 = 0, idx1 = 0;
+
+ for (bidx = 5; bidx >= 0; bidx--) {
+ for (iorq = 0; iorq <= 1; iorq++) {
-+ rt2x00_dbg(rt2x00dev, "\n========================================================\n");
++ rt2x00_dbg(rt2x00dev, "\n========================================================\n");
+
+ if (idxf[iorq] == 0x20) {
+ idx0 = 0x20;
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
+
-+ rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", alc_idx, iorq, idxf[iorq]);
++ rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n", alc_idx, iorq, idxf[iorq]);
+ rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x !\n", p0, p1, pf, idx0, idx1, ibit);
+
+ if ((bidx != 5) && (pf <= p0) && (pf < p1)) {
+}
+EXPORT_SYMBOL_GPL(rt2800_loft_search);
+
-+static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
++static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
+{
+ u32 p0 = 0, p1 = 0, pf = 0;
+ char perr = 0, gerr = 0, iq_err = 0;
+ pf = p1;
+ iq_err = idx1;
+ }
-+
++
+ bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 : (gop == 0) ? 0x46 : 0x47;
+
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
+ gerr = iq_err;
+ else
+ perr = iq_err;
-+
++
+ rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n", pf, gerr & 0x0F, perr & 0x3F);
+
+ }
+
+ if (bidx > 0)
+ ibit = (ibit >> 1);
-+ }
++ }
+ gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
+ perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
-+
++
+ gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
+ gsta = gerr - 1;
+ gend = gerr + 2;
-+
++
+ perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
+ psta = perr - 1;
+ pend = perr + 2;
+ bbp = (ch_idx == 0) ? 0x28 : 0x46;
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
+ rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
-+
++
+ bbp = (ch_idx == 0) ? 0x29 : 0x47;
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
+ rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
-+
++
+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
+ if ((gef == gsta) && (pef == psta)) {
+ pf = p1;
+ }
+ rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n", p1, pf, gef & 0x0F, pef & 0x3F);
+ }
-+
++
+ ges[ch_idx] = gerr & 0x0F;
+ pes[ch_idx] = perr & 0x3F;
-+
++
+ rt2x00_info(rt2x00dev, "IQCalibration Done! CH = %u, (gain=%2x, phase=%2x)\n", ch_idx, gerr & 0x0F, perr & 0x3F);
+
+ return;
+ u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
+ u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30, 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
+
-+ u8 vga_gain[] = {14, 14};
++ u8 vga_gain[] = {14, 14};
+ u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
+ u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
+ u8 bbpr30, rfb0r39, rfb0r42;
+ udelay(50);
+ else
+ break;
-+ }
++ }
+
+ for (ch_idx = 0; ch_idx < 2; ch_idx++) {
+ rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0x05);
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
-+
++
+ rt2800_bbp_write(rt2x00dev, 158, 0x01);
+ if (ch_idx == 0)
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
+ else
+ rt2800_bbp_write(rt2x00dev, 159, 0x01);
-+
++
+ vga_gain[ch_idx] = 18;
+ for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
+ rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
+ macvalue = (0x0000F1F1);
+ rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
+
-+ if (rf_alc_idx == 0) {
++ if (rf_alc_idx == 0) {
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
+ for (;vga_gain[ch_idx] > 0;vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
+ rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
+ p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
+ p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
-+ rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
-+ if ((p0 < 7000*7000) && (p1 < (7000*7000))) {
++ rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
++ if ((p0 < 7000*7000) && (p1 < (7000*7000))) {
+ break;
+ }
+ }
+
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
+ rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
-+
-+ rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
++
++ rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
+
+ if (vga_gain[ch_idx] < 0)
+ vga_gain[ch_idx] = 0;
-+ }
++ }
+
+ rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
-+
++
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
-+
++
+ rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
+ }
+ }
+ rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0xb1);
-+ bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
-+ bbp = bbp & 0x3F;
++ bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
++ bbp = bbp & 0x3F;
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
+ rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0xb2);
-+ bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
-+ bbp = bbp & 0x3F;
++ bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
++ bbp = bbp & 0x3F;
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
+ rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0xb8);
-+ bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
-+ bbp = bbp & 0x3F;
++ bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
++ bbp = bbp & 0x3F;
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
+ rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0xb9);
-+ bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
-+ bbp = bbp & 0x3F;
++ bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
++ bbp = bbp & 0x3F;
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
+ rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
-+ }
++ }
+ }
+
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
+ rt2800_rf_configrecover(rt2x00dev, rf_store);
+
+ rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
-+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
-+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
++ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
++ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
+ udelay(1);
+ macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
+ macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
+
-+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
-+ bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
-+ bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
-+ bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
-+ bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
-+ }
++ bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
++ bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
++ bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
++ bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
+ mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
+
+ macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
+ udelay(1);
-+
++
+ rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
+
+ if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+ bbp = (ch_idx == 0) ? 0x28 : 0x46;
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
-+
++
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+ rt2800_bbp_write(rt2x00dev, 23, 0x06);
+ rt2800_bbp_write(rt2x00dev, 24, 0x06);
+ rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
+ rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
+ rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
-+
++
+ bbp = (ch_idx == 0) ? 0x29 : 0x47;
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+ if (vga_gain[ch_idx] > 18)
+ vga_gain[ch_idx] = 18;
-+ rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
++ rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n",vga_gain[ch_idx], rfvga_gain_table[vga_gain[ch_idx]]);
+
+ bbp = (ch_idx == 0) ? 0x29 : 0x47;
+ rt2800_bbp_write(rt2x00dev, 158, bbp);
+ rt2800_bbp_write(rt2x00dev, 159, 0x00);
+
+ rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
-+ }
++ }
+
+ rt2800_bbp_write(rt2x00dev, 23, 0x00);
+ rt2800_bbp_write(rt2x00dev, 24, 0x00);
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0x29);
-+ bbp = per[CHAIN_0] & 0x3F;
++ bbp = per[CHAIN_0] & 0x3F;
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0x46);
-+ bbp = ger[CHAIN_1] & 0x0F;
++ bbp = ger[CHAIN_1] & 0x0F;
+ rt2800_bbp_write(rt2x00dev, 159, bbp);
+
+ rt2800_bbp_write(rt2x00dev, 158, 0x47);
-+ bbp = per[CHAIN_1] & 0x3F;
-+ rt2800_bbp_write(rt2x00dev, 159, bbp);
-+
++ bbp = per[CHAIN_1] & 0x3F;
++ rt2800_bbp_write(rt2x00dev, 159, bbp);
++
+ if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
+ rt2800_bbp_write(rt2x00dev, 1, bbpr1);
+ rt2800_bbp_write(rt2x00dev, 241, bbpr241);
+ rt2800_rf_configrecover(rt2x00dev, rf_store);
+
+ rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
-+ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
++ rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
+ rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
+ rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
+ udelay(1);
static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
bool set_bw, bool is_ht40)
{
-@@ -9612,6 +10563,7 @@ static void rt2800_init_rfcsr_6352(struc
+@@ -9612,6 +10560,7 @@ static void rt2800_init_rfcsr_6352(struc
rt2800_rxdcoc_calibration(rt2x00dev);
rt2800_bw_filter_calibration(rt2x00dev, true);
rt2800_bw_filter_calibration(rt2x00dev, false);
#define STA_IDS_SIZE (WCID_END - WCID_START + 2)
+#define CHAIN_0 0x0
+#define CHAIN_1 0x1
-+#define RF_ALC_NUM 6
++#define RF_ALC_NUM 6
+#define CHAIN_NUM 2
+
+typedef struct rf_reg_pair {
projects / openwrt / staging / wigyori.git / commitdiff