cns3xxx: update patches for 4.14
authorKoen Vandeputte <koen.vandeputte@ncentric.com>
Thu, 11 Jan 2018 15:04:36 +0000 (16:04 +0100)
committerJohn Crispin <john@phrozen.org>
Wed, 17 Jan 2018 10:07:17 +0000 (11:07 +0100)
Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
target/linux/cns3xxx/patches-4.14/000-cns3xxx_arch_include.patch
target/linux/cns3xxx/patches-4.14/001-arm_openwrt_machtypes.patch
target/linux/cns3xxx/patches-4.14/075-spi_support.patch
target/linux/cns3xxx/patches-4.14/090-timers.patch
target/linux/cns3xxx/patches-4.14/200-broadcom_phy_reinit.patch
target/linux/cns3xxx/patches-4.14/210-dwc2_defaults.patch

index f98fe0c..3ae7590 100644 (file)
@@ -1,6 +1,7 @@
 --- a/arch/arm/mach-cns3xxx/Makefile
 +++ b/arch/arm/mach-cns3xxx/Makefile
-@@ -1,3 +1,5 @@
+@@ -1,4 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0
 +ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 +
  obj-$(CONFIG_ARCH_CNS3XXX)            += cns3xxx.o
index 32f977f..17a83ea 100644 (file)
@@ -1,7 +1,10 @@
 --- a/arch/arm/tools/mach-types
 +++ b/arch/arm/tools/mach-types
-@@ -1006,3 +1006,4 @@ eco5_bx2         MACH_ECO5_BX2           ECO5_BX2                4572
- eukrea_cpuimx28sd     MACH_EUKREA_CPUIMX28SD  EUKREA_CPUIMX28SD       4573
- domotab                       MACH_DOMOTAB            DOMOTAB                 4574
- pfla03                        MACH_PFLA03             PFLA03                  4575
+@@ -448,6 +448,7 @@ gplugd                     MACH_GPLUGD             GPLUGD                  2625
+ qsd8x50a_st1_5                MACH_QSD8X50A_ST1_5     QSD8X50A_ST1_5          2627
+ mx23evk                       MACH_MX23EVK            MX23EVK                 2629
+ ap4evb                        MACH_AP4EVB             AP4EVB                  2630
 +gw2388                        MACH_GW2388             GW2388                  2635
+ mityomapl138          MACH_MITYOMAPL138       MITYOMAPL138            2650
+ guruplug              MACH_GURUPLUG           GURUPLUG                2659
+ spear310              MACH_SPEAR310           SPEAR310                2660
index aeda7a3..8a51eb3 100644 (file)
@@ -1,6 +1,6 @@
 --- a/drivers/spi/Kconfig
 +++ b/drivers/spi/Kconfig
-@@ -199,6 +199,13 @@ config SPI_CLPS711X
+@@ -206,6 +206,13 @@ config SPI_CLPS711X
          This enables dedicated general purpose SPI/Microwire1-compatible
          master mode interface (SSI1) for CLPS711X-based CPUs.
  
@@ -16,7 +16,7 @@
        depends on (M520x || M523x || M5249 || M525x || M527x || M528x || M532x)
 --- a/drivers/spi/Makefile
 +++ b/drivers/spi/Makefile
-@@ -29,6 +29,7 @@ obj-$(CONFIG_SPI_BITBANG)            += spi-bitban
+@@ -31,6 +31,7 @@ obj-$(CONFIG_SPI_BITBANG)            += spi-bitban
  obj-$(CONFIG_SPI_BUTTERFLY)           += spi-butterfly.o
  obj-$(CONFIG_SPI_CADENCE)             += spi-cadence.o
  obj-$(CONFIG_SPI_CLPS711X)            += spi-clps711x.o
@@ -26,7 +26,7 @@
  obj-$(CONFIG_SPI_DLN2)                        += spi-dln2.o
 --- a/include/linux/spi/spi.h
 +++ b/include/linux/spi/spi.h
-@@ -763,6 +763,10 @@ struct spi_transfer {
+@@ -799,6 +799,10 @@ struct spi_transfer {
        u32             speed_hz;
  
        struct list_head transfer_list;
  /**
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -985,6 +985,9 @@ static int spi_transfer_one_message(stru
+@@ -1021,6 +1021,9 @@ static int spi_transfer_one_message(stru
        list_for_each_entry(xfer, &msg->transfers, transfer_list) {
                trace_spi_transfer_start(msg, xfer);
  
 +              xfer->last_in_message_list =
 +                      list_is_last(&xfer->transfer_list, &msg->transfers);
 +
-               spi_statistics_add_transfer_stats(statm, xfer, master);
-               spi_statistics_add_transfer_stats(stats, xfer, master);
+               spi_statistics_add_transfer_stats(statm, xfer, ctlr);
+               spi_statistics_add_transfer_stats(stats, xfer, ctlr);
  
index 6f7713f..34a4934 100644 (file)
@@ -30,7 +30,7 @@
        twd_local_timer_register(&cns3xx_twd_local_timer);
  }
  
-+static cycle_t cns3xxx_get_cycles(struct clocksource *cs)
++static u64 cns3xxx_get_cycles(struct clocksource *cs)
 +{
 +  u64 val;
 +
index 0352a89..6880533 100644 (file)
@@ -1,14 +1,15 @@
 --- a/drivers/net/phy/broadcom.c
 +++ b/drivers/net/phy/broadcom.c
-@@ -420,6 +420,11 @@ static int bcm5481_config_aneg(struct ph
-               /* Write bits 14:0. */
-               reg |= (1 << 15);
-               phy_write(phydev, 0x18, reg);
-+      } else {
-+              phy_write(phydev, 0x18, 0xf1e7);
-+              phy_write(phydev, 0x1c, 0x8e00);
+@@ -417,7 +417,11 @@ static int bcm5481_config_aneg(struct ph
+       ret = genphy_config_aneg(phydev);
+       /* Then we can set up the delay. */
+-      bcm5481x_config(phydev);
++      //bcm5481x_config(phydev);
 +
-+              phy_write(phydev, 0x1c, 0xa41f);
-       }
++      phy_write(phydev, 0x18, 0xf1e7);
++      phy_write(phydev, 0x1c, 0x8e00);
++      phy_write(phydev, 0x1c, 0xa41f);
  
        if (of_property_read_bool(np, "enet-phy-lane-swap")) {
+               /* Lane Swap - Undocumented register...magic! */
index 9cd05ea..67f152f 100644 (file)
@@ -1,47 +1,63 @@
---- a/drivers/usb/dwc2/platform.c
-+++ b/drivers/usb/dwc2/platform.c
-@@ -308,6 +308,34 @@ static int __dwc2_lowlevel_hw_enable(str
-       return ret;
+--- a/drivers/usb/dwc2/params.c
++++ b/drivers/usb/dwc2/params.c
+@@ -136,6 +136,36 @@ static void dwc2_set_stm32f4x9_fsotg_par
+       p->activate_stm_fs_transceiver = true;
  }
  
-+static const struct dwc2_core_params params_cns3xxx = {
-+      .otg_cap                        = 2,    /* non-HNP/non-SRP capable */
-+      .otg_ver                        = 0,    /* 1.3 */
-+      .dma_enable                     = 1,
-+      .dma_desc_enable                = 0,
-+      .speed                          = 0,    /* High Speed */
-+      .enable_dynamic_fifo            = 1,
-+      .en_multiple_tx_fifo            = 1,
-+      .host_rx_fifo_size              = 658,  /* 774 DWORDs */
-+      .host_nperio_tx_fifo_size       = 128,  /* 256 DWORDs */
-+      .host_perio_tx_fifo_size        = 658,  /* 512 DWORDs */
-+      .max_transfer_size              = 65535,
-+      .max_packet_count               = 511,
-+      .host_channels                  = 16,
-+      .phy_type                       = 1,    /* UTMI */
-+      .phy_utmi_width                 = 16,   /* 8 bits */
-+      .phy_ulpi_ddr                   = 0,    /* Single */
-+      .phy_ulpi_ext_vbus              = 0,
-+      .i2c_enable                     = 0,
-+      .ulpi_fs_ls                     = 0,
-+      .host_support_fs_ls_low_power   = 0,
-+      .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
-+      .ts_dline                       = 0,
-+      .reload_ctl                     = 0,
-+      .ahbcfg                         = 0x10,
-+      .uframe_sched                   = 0,
-+};
++static void dwc2_set_cns3xxx_params(struct dwc2_hsotg *hsotg)
++{
++      struct dwc2_core_params *p = &hsotg->params;
 +
- /**
-  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
-  * @hsotg: The driver state
-@@ -552,6 +580,9 @@ static int dwc2_driver_probe(struct plat
-               /* Default all params to autodetect */
-               dwc2_set_all_params(&defparams, -1);
-               params = &defparams;
-+#ifdef CONFIG_ARCH_CNS3XXX
-+              params = &params_cns3xxx;
-+#endif
++      p->otg_cap                      = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;    /* non-HNP/non-SRP capable */
++      p->host_dma                     = 1;
++      p->dma_desc_enable              = 0;
++      p->speed                        = DWC2_SPEED_PARAM_HIGH;        /* High Speed */
++      p->enable_dynamic_fifo          = 1;
++      p->en_multiple_tx_fifo          = 1;
++      p->host_rx_fifo_size            = 658;  /* 774 DWORDs */
++      p->host_nperio_tx_fifo_size     = 128;  /* 256 DWORDs */
++      p->host_perio_tx_fifo_size      = 658;  /* 512 DWORDs */
++      p->max_transfer_size            = 65535,
++      p->max_packet_count             = 511;
++      p->host_channels                = 16;
++      p->phy_type                     = DWC2_PHY_TYPE_PARAM_UTMI;     /* UTMI */
++      p->phy_utmi_width               = 16;   /* 8 bits */
++      p->phy_ulpi_ddr                 = 0;    /* Single */
++      p->phy_ulpi_ext_vbus            = 0;
++      p->i2c_enable                   = 0;
++      p->ulpi_fs_ls                   = 0;
++      p->host_support_fs_ls_low_power = 0;
++      p->host_ls_low_power_phy_clk    = 0;    /* 48 MHz */
++      p->ts_dline                     = 0;
++      p->reload_ctl                   = 0;
++      p->ahbcfg                       = 0x10;
++      p->uframe_sched                 = false;
++}
++
+ const struct of_device_id dwc2_of_match_table[] = {
+       { .compatible = "brcm,bcm2835-usb", .data = dwc2_set_bcm_params },
+       { .compatible = "hisilicon,hi6220-usb", .data = dwc2_set_his_params  },
+@@ -710,17 +740,23 @@ int dwc2_get_hwparams(struct dwc2_hsotg
+ int dwc2_init_params(struct dwc2_hsotg *hsotg)
+ {
++      /*
+       const struct of_device_id *match;
+       void (*set_params)(void *data);
++      */
+       dwc2_set_default_params(hsotg);
+       dwc2_get_device_properties(hsotg);
++      /*
+       match = of_match_device(dwc2_of_match_table, hsotg->dev);
+       if (match && match->data) {
+               set_params = match->data;
+               set_params(hsotg);
+       }
++      */
++
++      dwc2_set_cns3xxx_params(hsotg);
+       dwc2_check_params(hsotg);
  
-               /*
-                * Disable descriptor dma mode by default as the HW can support