oxnas: add SoC restart driver for reboot
authorDaniel Golle <daniel@makrotopia.org>
Sun, 3 Mar 2019 01:30:21 +0000 (02:30 +0100)
committerDaniel Golle <daniel@makrotopia.org>
Sun, 3 Mar 2019 01:46:05 +0000 (02:46 +0100)
Refresh oxnas kernel config while at it.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
target/linux/oxnas/config-4.14
target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c [new file with mode: 0644]
target/linux/oxnas/patches-4.14/150-oxnas-restart.patch [new file with mode: 0644]

index 40a0fcf..9932f47 100644 (file)
@@ -12,6 +12,11 @@ CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
 CONFIG_ARCH_HIBERNATION_POSSIBLE=y
 CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
 CONFIG_ARCH_MULTIPLATFORM=y
+CONFIG_ARCH_MULTI_CPU_AUTO=y
+# CONFIG_ARCH_MULTI_V4 is not set
+# CONFIG_ARCH_MULTI_V4T is not set
+CONFIG_ARCH_MULTI_V4_V5=y
+CONFIG_ARCH_MULTI_V5=y
 CONFIG_ARCH_NR_GPIO=0
 CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
 # CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT is not set
@@ -25,13 +30,13 @@ CONFIG_ARCH_USE_BUILTIN_BSWAP=y
 CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y
 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y
 CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_ARCH_WANT_LIBATA_LEDS=y
 CONFIG_ARM=y
 CONFIG_ARM_APPENDED_DTB=y
 CONFIG_ARM_ATAG_DTB_COMPAT=y
 # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND is not set
 # CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
 CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
-CONFIG_ARM_CPUIDLE=y
 CONFIG_ARM_CPU_SUSPEND=y
 CONFIG_ARM_HAS_SG_CHAIN=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
@@ -43,7 +48,6 @@ CONFIG_ARM_TIMER_SP804=y
 CONFIG_ARM_UNWIND=y
 CONFIG_ATAGS=y
 CONFIG_AUTO_ZRELADDR=y
-CONFIG_BINARY_PRINTF=y
 CONFIG_BLK_CMDLINE_PARSER=y
 CONFIG_BLK_DEBUG_FS=y
 CONFIG_BLK_DEV_BSG=y
@@ -51,9 +55,9 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_BLK_MQ_PCI=y
 CONFIG_BLK_SCSI_REQUEST=y
 # CONFIG_BPF_SYSCALL is not set
+# CONFIG_CACHE_L2X0 is not set
 CONFIG_CLKDEV_LOOKUP=y
 CONFIG_CLKSRC_MMIO=y
 CONFIG_CLONE_BACKWARDS=y
@@ -71,16 +75,34 @@ CONFIG_CMDLINE_PARTITION=y
 CONFIG_COMMON_CLK=y
 CONFIG_COMMON_CLK_OXNAS=y
 CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_CONTEXT_SWITCH_TRACER=y
 CONFIG_COREDUMP=y
 CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_ARM926T=y
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_PM=y
+CONFIG_CPU_THUMB_CAPABLE=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_USE_DOMAINS=y
 CONFIG_CRASH_CORE=y
 CONFIG_CRC16=y
 # CONFIG_CRC32_SARWATE is not set
 CONFIG_CRC32_SLICEBY8=y
 CONFIG_CROSS_MEMORY_ATTACH=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_WORKQUEUE=y
 CONFIG_DEBUG_ALIGN_RODATA=y
 CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+# CONFIG_DEBUG_UART_8250 is not set
 # CONFIG_DEBUG_USER is not set
 CONFIG_DECOMPRESS_BZIP2=y
 CONFIG_DECOMPRESS_GZIP=y
@@ -96,17 +118,19 @@ CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_DMA_CMA=y
 CONFIG_DNOTIFY=y
 CONFIG_DTC=y
-CONFIG_DT_IDLE_STATES=y
 CONFIG_DUMMY_CONSOLE=y
 # CONFIG_DWMAC_DWC_QOS_ETH is not set
 CONFIG_DWMAC_GENERIC=y
 CONFIG_DWMAC_OXNAS=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_EDAC_SUPPORT is not set
+CONFIG_EDAC_ATOMIC_SCRUB=y
+CONFIG_EDAC_SUPPORT=y
 CONFIG_ELF_CORE=y
+CONFIG_FAT_FS=y
 CONFIG_FIXED_PHY=y
 CONFIG_FIX_EARLYCON_MEM=y
+CONFIG_FREEZER=y
 CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_GENERIC_ATOMIC64=y
 CONFIG_GENERIC_BUG=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_GENERIC_CPU_AUTOPROBE=y
@@ -115,15 +139,12 @@ CONFIG_GENERIC_IDLE_POLL_SETUP=y
 CONFIG_GENERIC_IO=y
 CONFIG_GENERIC_IRQ_SHOW=y
 CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
-CONFIG_GENERIC_MSI_IRQ=y
-CONFIG_GENERIC_MSI_IRQ_DOMAIN=y
 CONFIG_GENERIC_PCI_IOMAP=y
 CONFIG_GENERIC_PINCONF=y
 CONFIG_GENERIC_SCHED_CLOCK=y
 CONFIG_GENERIC_SMP_IDLE_THREAD=y
 CONFIG_GENERIC_STRNCPY_FROM_USER=y
 CONFIG_GENERIC_STRNLEN_USER=y
-CONFIG_GLOB=y
 CONFIG_GPIOLIB=y
 CONFIG_GPIOLIB_IRQCHIP=y
 CONFIG_GPIO_GENERIC=y
@@ -158,7 +179,6 @@ CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
 CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_HAVE_IDE=y
 CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
 CONFIG_HAVE_MEMBLOCK=y
 CONFIG_HAVE_MOD_ARCH_SPECIFIC=y
@@ -195,11 +215,9 @@ CONFIG_IOMMU_SUPPORT=y
 CONFIG_IOSCHED_CFQ=y
 CONFIG_IRQCHIP=y
 CONFIG_IRQ_DOMAIN=y
-CONFIG_IRQ_DOMAIN_HIERARCHY=y
 CONFIG_IRQ_FORCED_THREADING=y
 CONFIG_IRQ_WORK=y
 # CONFIG_ISDN is not set
-CONFIG_JBD2=y
 # CONFIG_JFFS2_FS is not set
 CONFIG_KALLSYMS=y
 CONFIG_KERNEL_GZIP=y
@@ -218,35 +236,34 @@ CONFIG_LEGACY_PTY_COUNT=256
 CONFIG_LIBFDT=y
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_LZ4_DECOMPRESS=y
-CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+# CONFIG_MACH_OX810SE is not set
 CONFIG_MDIO_BUS=y
 CONFIG_MDIO_DEVICE=y
 CONFIG_MEMORY_ISOLATION=y
 CONFIG_MFD_SYSCON=y
+CONFIG_MIGHT_HAVE_PCI=y
 CONFIG_MIGRATION=y
 CONFIG_MODULES_TREE_LOOKUP=y
 CONFIG_MODULES_USE_ELF_REL=y
 CONFIG_MULTI_IRQ_HANDLER=y
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_NEED_KUSER_HELPERS=y
+CONFIG_NEED_PER_CPU_KM=y
 CONFIG_NET_PTP_CLASSIFY=y
 CONFIG_NLS=y
-CONFIG_NOP_TRACER=y
 CONFIG_NO_BOOTMEM=y
 CONFIG_NO_HZ=y
 CONFIG_NO_HZ_COMMON=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
-CONFIG_OF_ADDRESS_PCI=y
 CONFIG_OF_EARLY_FLATTREE=y
 CONFIG_OF_FLATTREE=y
 CONFIG_OF_GPIO=y
 CONFIG_OF_IRQ=y
 CONFIG_OF_MDIO=y
 CONFIG_OF_NET=y
-CONFIG_OF_PCI=y
-CONFIG_OF_PCI_IRQ=y
 CONFIG_OF_RESERVED_MEM=y
 CONFIG_OLD_SIGACTION=y
 CONFIG_OLD_SIGSUSPEND3=y
@@ -255,6 +272,8 @@ CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PANIC_ON_OOPS is not set
 CONFIG_PANIC_ON_OOPS_VALUE=0
 CONFIG_PANIC_TIMEOUT=0
+# CONFIG_PCI_DOMAINS_GENERIC is not set
+# CONFIG_PCI_SYSCALL is not set
 CONFIG_PERF_EVENTS=y
 CONFIG_PERF_USE_VMALLOC=y
 CONFIG_PGTABLE_LEVELS=2
@@ -266,11 +285,14 @@ CONFIG_PM=y
 CONFIG_PM_CLK=y
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_OXNAS=y
 CONFIG_PPS=y
-CONFIG_PROBE_EVENTS=y
 CONFIG_PTP_1588_CLOCK=y
 CONFIG_RAS=y
 CONFIG_RATIONAL=y
+# CONFIG_RCU_NEED_SEGCBLIST is not set
+# CONFIG_RCU_STALL_COMMON is not set
 CONFIG_RCU_TRACE=y
 CONFIG_RD_BZIP2=y
 CONFIG_RD_GZIP=y
@@ -283,7 +305,6 @@ CONFIG_REGMAP=y
 CONFIG_REGMAP_MMIO=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RESET_OXNAS=y
-CONFIG_RING_BUFFER=y
 CONFIG_RWSEM_XCHGADD_ALGORITHM=y
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHED_INFO is not set
@@ -300,6 +321,7 @@ CONFIG_SIMPLE_PM_BUS=y
 CONFIG_SLUB_DEBUG=y
 CONFIG_SOCK_DIAG=y
 CONFIG_SPARSE_IRQ=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
 CONFIG_SRCU=y
 CONFIG_STACKTRACE=y
 # CONFIG_STAGING is not set
@@ -314,10 +336,10 @@ CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_TICK_CPU_ACCOUNTING=y
 CONFIG_TIMER_OF=y
 CONFIG_TIMER_PROBE=y
+CONFIG_TINY_SRCU=y
+CONFIG_TRACE_CLOCK=y
 CONFIG_UEVENT_HELPER_PATH=""
 CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
-CONFIG_UPROBES=y
-CONFIG_UPROBE_EVENTS=y
 CONFIG_USB_SUPPORT=y
 # CONFIG_USERIO is not set
 CONFIG_USE_OF=y
@@ -342,5 +364,4 @@ CONFIG_XZ_DEC_SPARC=y
 CONFIG_XZ_DEC_X86=y
 CONFIG_ZBOOT_ROM_BSS=0
 CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZLIB_DEFLATE=y
 CONFIG_ZLIB_INFLATE=y
diff --git a/target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c b/target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c
new file mode 100644 (file)
index 0000000..5664914
--- /dev/null
@@ -0,0 +1,229 @@
+// SPDX-License-Identifier: (GPL-2.0)
+/*
+ * oxnas SoC reset driver
+ * based on:
+ * Microsemi MIPS SoC reset driver
+ * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
+ *
+ * License: GPL
+ * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
+ * Copyright (c) 2017 Microsemi Corporation
+ * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/notifier.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reboot.h>
+#include <linux/regmap.h>
+
+/* bit numbers of reset control register */
+#define SYS_CTRL_RST_SCU                0
+#define SYS_CTRL_RST_COPRO              1
+#define SYS_CTRL_RST_ARM0               2
+#define SYS_CTRL_RST_ARM1               3
+#define SYS_CTRL_RST_USBHS              4
+#define SYS_CTRL_RST_USBHSPHYA          5
+#define SYS_CTRL_RST_MACA               6
+#define SYS_CTRL_RST_MAC                SYS_CTRL_RST_MACA
+#define SYS_CTRL_RST_PCIEA              7
+#define SYS_CTRL_RST_SGDMA              8
+#define SYS_CTRL_RST_CIPHER             9
+#define SYS_CTRL_RST_DDR                10
+#define SYS_CTRL_RST_SATA               11
+#define SYS_CTRL_RST_SATA_LINK          12
+#define SYS_CTRL_RST_SATA_PHY           13
+#define SYS_CTRL_RST_PCIEPHY            14
+#define SYS_CTRL_RST_STATIC             15
+#define SYS_CTRL_RST_GPIO               16
+#define SYS_CTRL_RST_UART1              17
+#define SYS_CTRL_RST_UART2              18
+#define SYS_CTRL_RST_MISC               19
+#define SYS_CTRL_RST_I2S                20
+#define SYS_CTRL_RST_SD                 21
+#define SYS_CTRL_RST_MACB               22
+#define SYS_CTRL_RST_PCIEB              23
+#define SYS_CTRL_RST_VIDEO              24
+#define SYS_CTRL_RST_DDR_PHY            25
+#define SYS_CTRL_RST_USBHSPHYB          26
+#define SYS_CTRL_RST_USBDEV             27
+#define SYS_CTRL_RST_ARMDBG             29
+#define SYS_CTRL_RST_PLLA               30
+#define SYS_CTRL_RST_PLLB               31
+
+/* bit numbers of clock control register */
+#define SYS_CTRL_CLK_COPRO              0
+#define SYS_CTRL_CLK_DMA                1
+#define SYS_CTRL_CLK_CIPHER             2
+#define SYS_CTRL_CLK_SD                 3
+#define SYS_CTRL_CLK_SATA               4
+#define SYS_CTRL_CLK_I2S                5
+#define SYS_CTRL_CLK_USBHS              6
+#define SYS_CTRL_CLK_MACA               7
+#define SYS_CTRL_CLK_MAC                SYS_CTRL_CLK_MACA
+#define SYS_CTRL_CLK_PCIEA              8
+#define SYS_CTRL_CLK_STATIC             9
+#define SYS_CTRL_CLK_MACB               10
+#define SYS_CTRL_CLK_PCIEB              11
+#define SYS_CTRL_CLK_REF600             12
+#define SYS_CTRL_CLK_USBDEV             13
+#define SYS_CTRL_CLK_DDR                14
+#define SYS_CTRL_CLK_DDRPHY             15
+#define SYS_CTRL_CLK_DDRCK              16
+
+/* Regmap offsets */
+#define CLK_SET_REGOFFSET               0x2c
+#define CLK_CLR_REGOFFSET               0x30
+#define RST_SET_REGOFFSET               0x34
+#define RST_CLR_REGOFFSET               0x38
+#define SECONDARY_SEL_REGOFFSET         0x14
+#define TERTIARY_SEL_REGOFFSET          0x8c
+#define QUATERNARY_SEL_REGOFFSET        0x94
+#define DEBUG_SEL_REGOFFSET             0x9c
+#define ALTERNATIVE_SEL_REGOFFSET       0xa4
+#define PULLUP_SEL_REGOFFSET            0xac
+#define SEC_SECONDARY_SEL_REGOFFSET     0x100014
+#define SEC_TERTIARY_SEL_REGOFFSET      0x10008c
+#define SEC_QUATERNARY_SEL_REGOFFSET    0x100094
+#define SEC_DEBUG_SEL_REGOFFSET         0x10009c
+#define SEC_ALTERNATIVE_SEL_REGOFFSET   0x1000a4
+#define SEC_PULLUP_SEL_REGOFFSET        0x1000ac
+
+
+struct oxnas_restart_context {
+       struct regmap *sys_ctrl;
+       struct notifier_block restart_handler;
+};
+
+static int oxnas_restart_handle(struct notifier_block *this,
+                                unsigned long mode, void *cmd)
+{
+       struct oxnas_restart_context *ctx = container_of(this, struct
+                                                       oxnas_restart_context,
+                                                       restart_handler);
+       u32 value;
+
+       /* Assert reset to cores as per power on defaults
+        * Don't touch the DDR interface as things will come to an impromptu stop
+        * NB Possibly should be asserting reset for PLLB, but there are timing
+        *    concerns here according to the docs */
+       value = BIT(SYS_CTRL_RST_COPRO)         |
+               BIT(SYS_CTRL_RST_USBHS)         |
+               BIT(SYS_CTRL_RST_USBHSPHYA)     |
+               BIT(SYS_CTRL_RST_MACA)          |
+               BIT(SYS_CTRL_RST_PCIEA)         |
+               BIT(SYS_CTRL_RST_SGDMA)         |
+               BIT(SYS_CTRL_RST_CIPHER)        |
+               BIT(SYS_CTRL_RST_SATA)          |
+               BIT(SYS_CTRL_RST_SATA_LINK)     |
+               BIT(SYS_CTRL_RST_SATA_PHY)      |
+               BIT(SYS_CTRL_RST_PCIEPHY)       |
+               BIT(SYS_CTRL_RST_STATIC)        |
+               BIT(SYS_CTRL_RST_UART1)         |
+               BIT(SYS_CTRL_RST_UART2)         |
+               BIT(SYS_CTRL_RST_MISC)          |
+               BIT(SYS_CTRL_RST_I2S)           |
+               BIT(SYS_CTRL_RST_SD)            |
+               BIT(SYS_CTRL_RST_MACB)          |
+               BIT(SYS_CTRL_RST_PCIEB)         |
+               BIT(SYS_CTRL_RST_VIDEO)         |
+               BIT(SYS_CTRL_RST_USBHSPHYB)     |
+               BIT(SYS_CTRL_RST_USBDEV);
+
+       regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
+
+       /* Release reset to cores as per power on defaults */
+       regmap_write(ctx->sys_ctrl, RST_CLR_REGOFFSET, BIT(SYS_CTRL_RST_GPIO));
+
+       /* Disable clocks to cores as per power-on defaults - must leave DDR
+        * related clocks enabled otherwise we'll stop rather abruptly. */
+       value =
+               BIT(SYS_CTRL_CLK_COPRO)         |
+               BIT(SYS_CTRL_CLK_DMA)           |
+               BIT(SYS_CTRL_CLK_CIPHER)        |
+               BIT(SYS_CTRL_CLK_SD)            |
+               BIT(SYS_CTRL_CLK_SATA)          |
+               BIT(SYS_CTRL_CLK_I2S)           |
+               BIT(SYS_CTRL_CLK_USBHS)         |
+               BIT(SYS_CTRL_CLK_MAC)           |
+               BIT(SYS_CTRL_CLK_PCIEA)         |
+               BIT(SYS_CTRL_CLK_STATIC)        |
+               BIT(SYS_CTRL_CLK_MACB)          |
+               BIT(SYS_CTRL_CLK_PCIEB)         |
+               BIT(SYS_CTRL_CLK_REF600)        |
+               BIT(SYS_CTRL_CLK_USBDEV);
+
+       regmap_write(ctx->sys_ctrl, CLK_CLR_REGOFFSET, value);
+
+       /* Enable clocks to cores as per power-on defaults */
+
+       /* Set sys-control pin mux'ing as per power-on defaults */
+       regmap_write(ctx->sys_ctrl, SECONDARY_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, TERTIARY_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, QUATERNARY_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, DEBUG_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, ALTERNATIVE_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, PULLUP_SEL_REGOFFSET, 0);
+
+       regmap_write(ctx->sys_ctrl, SEC_SECONDARY_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, SEC_TERTIARY_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, SEC_QUATERNARY_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, SEC_DEBUG_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
+       regmap_write(ctx->sys_ctrl, SEC_PULLUP_SEL_REGOFFSET, 0);
+
+       /* No need to save any state, as the ROM loader can determine whether
+        * reset is due to power cycling or programatic action, just hit the
+        * (self-clearing) CPU reset bit of the block reset register */
+       value =
+               BIT(SYS_CTRL_RST_SCU) |
+               BIT(SYS_CTRL_RST_ARM0) |
+               BIT(SYS_CTRL_RST_ARM1);
+
+       regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
+
+       pr_emerg("Unable to restart system\n");
+       return NOTIFY_DONE;
+}
+
+static int oxnas_restart_probe(struct platform_device *pdev)
+{
+       struct oxnas_restart_context *ctx;
+       struct regmap *sys_ctrl;
+       struct device *dev = &pdev->dev;
+       int err = 0;
+
+       sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
+       if (IS_ERR(sys_ctrl))
+               return PTR_ERR(sys_ctrl);
+
+       ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+       if (!ctx)
+               return -ENOMEM;
+
+       ctx->sys_ctrl = sys_ctrl;
+       ctx->restart_handler.notifier_call = oxnas_restart_handle;
+       ctx->restart_handler.priority = 192;
+       err = register_restart_handler(&ctx->restart_handler);
+       if (err)
+               dev_err(dev, "can't register restart notifier (err=%d)\n", err);
+
+       return err;
+}
+
+static const struct of_device_id oxnas_restart_of_match[] = {
+       { .compatible = "oxsemi,ox820-sys-ctrl" },
+       {}
+};
+
+static struct platform_driver oxnas_restart_driver = {
+       .probe = oxnas_restart_probe,
+       .driver = {
+               .name = "oxnas-chip-reset",
+               .of_match_table = oxnas_restart_of_match,
+       },
+};
+builtin_platform_driver(oxnas_restart_driver);
diff --git a/target/linux/oxnas/patches-4.14/150-oxnas-restart.patch b/target/linux/oxnas/patches-4.14/150-oxnas-restart.patch
new file mode 100644 (file)
index 0000000..dafa967
--- /dev/null
@@ -0,0 +1,25 @@
+--- a/drivers/power/reset/Kconfig
++++ b/drivers/power/reset/Kconfig
+@@ -113,6 +113,12 @@ config POWER_RESET_MSM
+       help
+         Power off and restart support for Qualcomm boards.
++config POWER_RESET_OXNAS
++      bool "OXNAS SoC restart driver"
++      depends on ARCH_OXNAS
++      help
++        Restart support for OXNAS boards.
++
+ config POWER_RESET_PIIX4_POWEROFF
+       tristate "Intel PIIX4 power-off driver"
+       depends on PCI
+--- a/drivers/power/reset/Makefile
++++ b/drivers/power/reset/Makefile
+@@ -12,6 +12,7 @@ obj-$(CONFIG_POWER_RESET_GPIO_RESTART) +
+ obj-$(CONFIG_POWER_RESET_HISI) += hisi-reboot.o
+ obj-$(CONFIG_POWER_RESET_IMX) += imx-snvs-poweroff.o
+ obj-$(CONFIG_POWER_RESET_MSM) += msm-poweroff.o
++obj-$(CONFIG_POWER_RESET_OXNAS) += oxnas-restart.o
+ obj-$(CONFIG_POWER_RESET_PIIX4_POWEROFF) += piix4-poweroff.o
+ obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o
+ obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o