From 4076d12f41e7fd338e9140c1f431002f4ffaf953 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Fri, 11 Dec 2015 15:03:08 +0000 Subject: [PATCH] ramips: Fix CM_GCR_CPC_BASE_CPCBASE_{MSK, SHF} values Update CM_GCR_CPC_BASE_CPCBASE_{MSK,SHF} to match datasheet Signed-off-by: Nikolay Martynov SVN-Revision: 47840 --- .../patches-4.3/0059-correct-CPC_BASE_MASK.patch | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 target/linux/ramips/patches-4.3/0059-correct-CPC_BASE_MASK.patch diff --git a/target/linux/ramips/patches-4.3/0059-correct-CPC_BASE_MASK.patch b/target/linux/ramips/patches-4.3/0059-correct-CPC_BASE_MASK.patch new file mode 100644 index 0000000000..b267137187 --- /dev/null +++ b/target/linux/ramips/patches-4.3/0059-correct-CPC_BASE_MASK.patch @@ -0,0 +1,13 @@ +--- a/arch/mips/include/asm/mips-cm.h ++++ b/arch/mips/include/asm/mips-cm.h +@@ -270,8 +270,8 @@ BUILD_CM_Cx_R_(tcid_8_priority, 0x80) + #define CM_GCR_GIC_BASE_GICEN_MSK (_ULCAST_(0x1) << 0) + + /* GCR_CPC_BASE register fields */ +-#define CM_GCR_CPC_BASE_CPCBASE_SHF 17 +-#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x7fff) << 17) ++#define CM_GCR_CPC_BASE_CPCBASE_SHF 15 ++#define CM_GCR_CPC_BASE_CPCBASE_MSK (_ULCAST_(0x1ffff) << 15) + #define CM_GCR_CPC_BASE_CPCEN_SHF 0 + #define CM_GCR_CPC_BASE_CPCEN_MSK (_ULCAST_(0x1) << 0) + -- 2.30.2