packages: clean up the package folder
[openwrt/staging/yousong.git] / package / kernel / lantiq / ltq-ptm / src / ifxmips_ptm_ar9.c
1 /******************************************************************************
2 **
3 ** FILE NAME : ifxmips_ptm_ar9.c
4 ** PROJECT : UEIP
5 ** MODULES : PTM
6 **
7 ** DATE : 7 Jul 2009
8 ** AUTHOR : Xu Liang
9 ** DESCRIPTION : PTM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
13 **
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
18 **
19 ** HISTORY
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
23
24
25
26 /*
27 * ####################################
28 * Head File
29 * ####################################
30 */
31
32 /*
33 * Common Head File
34 */
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <asm/delay.h>
44
45 /*
46 * Chip Specific Head File
47 */
48 #include "ifxmips_ptm_adsl.h"
49 #include "ifxmips_ptm_fw_ar9.h"
50
51 #include <lantiq_soc.h>
52
53
54 /*
55 * ####################################
56 * Definition
57 * ####################################
58 */
59
60 /*
61 * EMA Settings
62 */
63 #define EMA_CMD_BUF_LEN 0x0040
64 #define EMA_CMD_BASE_ADDR (0x00001B80 << 2)
65 #define EMA_DATA_BUF_LEN 0x0100
66 #define EMA_DATA_BASE_ADDR (0x00001C00 << 2)
67 #define EMA_WRITE_BURST 0x2
68 #define EMA_READ_BURST 0x2
69
70
71
72 /*
73 * ####################################
74 * Declaration
75 * ####################################
76 */
77
78 /*
79 * Hardware Init/Uninit Functions
80 */
81 static inline void init_pmu(void);
82 static inline void uninit_pmu(void);
83 static inline void reset_ppe(void);
84 static inline void init_ema(void);
85 static inline void init_mailbox(void);
86 static inline void init_atm_tc(void);
87 static inline void clear_share_buffer(void);
88
89
90
91 /*
92 * ####################################
93 * Local Variable
94 * ####################################
95 */
96
97
98
99 /*
100 * ####################################
101 * Local Function
102 * ####################################
103 */
104
105 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
106 #define IFX_PMU_MODULE_PPE_TC BIT(21)
107 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
108 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
109 #define IFX_PMU_MODULE_TPE BIT(13)
110 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
111
112
113 static inline void init_pmu(void)
114 {
115 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
116 IFX_PMU_MODULE_PPE_TC |
117 IFX_PMU_MODULE_PPE_EMA |
118 IFX_PMU_MODULE_TPE |
119 IFX_PMU_MODULE_DSL_DFE);
120
121 }
122
123 static inline void uninit_pmu(void)
124 {
125 ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |
126 IFX_PMU_MODULE_PPE_TC |
127 IFX_PMU_MODULE_PPE_EMA |
128 IFX_PMU_MODULE_TPE |
129 IFX_PMU_MODULE_DSL_DFE);
130
131 }
132
133 static inline void reset_ppe(void)
134 {
135 #ifdef MODULE
136 // reset PPE
137 // ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
138 #endif
139 }
140
141 static inline void init_ema(void)
142 {
143 // Configure share buffer master selection
144 IFX_REG_W32(1, SB_MST_PRI0);
145 IFX_REG_W32(1, SB_MST_PRI1);
146
147 // EMA Settings
148 IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
149 IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
150 IFX_REG_W32(0x000000FF, EMA_IER);
151 IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
152 }
153
154 static inline void init_mailbox(void)
155 {
156 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
157 IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
158 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
159 IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
160 }
161
162 static inline void init_atm_tc(void)
163 {
164 IFX_REG_W32(0x0, RFBI_CFG);
165 IFX_REG_W32(0x1800, SFSM_DBA0);
166 IFX_REG_W32(0x1921, SFSM_DBA1);
167 IFX_REG_W32(0x1A42, SFSM_CBA0);
168 IFX_REG_W32(0x1A53, SFSM_CBA1);
169 IFX_REG_W32(0x14011, SFSM_CFG0);
170 IFX_REG_W32(0x14011, SFSM_CFG1);
171 IFX_REG_W32(0x1000, FFSM_DBA0);
172 IFX_REG_W32(0x1700, FFSM_DBA1);
173 IFX_REG_W32(0x3000C, FFSM_CFG0);
174 IFX_REG_W32(0x3000C, FFSM_CFG1);
175 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
176 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
177
178 /*
179 * 0. Backup port2 value to temp
180 * 1. Disable CPU port2 in switch (link and learning)
181 * 2. wait for a while
182 * 3. Configure DM register and counter
183 * 4. restore temp to CPU port2 in switch
184 * This code will cause network to stop working if there are heavy
185 * traffic during bootup. This part should be moved to switch and use
186 * the same code as ATM
187 */
188 {
189 int i;
190 u32 temp;
191
192 temp = IFX_REG_R32(SW_P2_CTL);
193
194 IFX_REG_W32(0x40020000, SW_P2_CTL);
195 for (i = 0; i < 200; i++)
196 udelay(2000);
197
198 IFX_REG_W32(0x00007028, DM_RXCFG);
199 IFX_REG_W32(0x00007028, DS_RXCFG);
200
201 IFX_REG_W32(0x00001100, DM_RXDB);
202 IFX_REG_W32(0x00001100, DS_RXDB);
203
204 IFX_REG_W32(0x00001600, DM_RXCB);
205 IFX_REG_W32(0x00001600, DS_RXCB);
206
207 /*
208 * For dynamic, must reset these counters,
209 * For once initialization, don't need to reset these counters
210 */
211 IFX_REG_W32(0x0, DM_RXPGCNT);
212 IFX_REG_W32(0x0, DS_RXPGCNT);
213 IFX_REG_W32(0x0, DM_RXPKTCNT);
214
215 IFX_REG_W32_MASK(0, 0x80000000, DM_RXCFG);
216 IFX_REG_W32_MASK(0, 0x8000, DS_RXCFG);
217
218 udelay(2000);
219 IFX_REG_W32(temp, SW_P2_CTL);
220 udelay(2000);
221 }
222 }
223
224 static inline void clear_share_buffer(void)
225 {
226 volatile u32 *p = SB_RAM0_ADDR(0);
227 unsigned int i;
228
229 for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ )
230 IFX_REG_W32(0, p++);
231 }
232
233 /*
234 * Description:
235 * Download PPE firmware binary code.
236 * Input:
237 * src --- u32 *, binary code buffer
238 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
239 * Output:
240 * int --- 0: Success
241 * else: Error Code
242 */
243 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
244 {
245 volatile u32 *dest;
246
247 if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
248 || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
249 return -1;
250
251 if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
252 IFX_REG_W32(0x00, CDM_CFG);
253 else
254 IFX_REG_W32(0x04, CDM_CFG);
255
256 /* copy code */
257 dest = CDM_CODE_MEMORY(0, 0);
258 while ( code_dword_len-- > 0 )
259 IFX_REG_W32(*code_src++, dest++);
260
261 /* copy data */
262 dest = CDM_DATA_MEMORY(0, 0);
263 while ( data_dword_len-- > 0 )
264 IFX_REG_W32(*data_src++, dest++);
265
266 return 0;
267 }
268
269
270
271 /*
272 * ####################################
273 * Global Function
274 * ####################################
275 */
276
277 void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
278 {
279 ASSERT(major != NULL, "pointer is NULL");
280 ASSERT(minor != NULL, "pointer is NULL");
281
282 *major = FW_VER_ID->major;
283 *minor = FW_VER_ID->minor;
284 }
285
286 void ifx_ptm_init_chip(void)
287 {
288 init_pmu();
289
290 reset_ppe();
291
292 init_ema();
293
294 init_mailbox();
295
296 init_atm_tc();
297
298 clear_share_buffer();
299 }
300
301 void ifx_ptm_uninit_chip(void)
302 {
303 uninit_pmu();
304 }
305
306 /*
307 * Description:
308 * Initialize and start up PP32.
309 * Input:
310 * none
311 * Output:
312 * int --- 0: Success
313 * else: Error Code
314 */
315 int ifx_pp32_start(int pp32)
316 {
317 int ret;
318
319 /* download firmware */
320 ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
321 if ( ret != 0 )
322 return ret;
323
324 /* run PP32 */
325 IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
326
327 /* idle for a while to let PP32 init itself */
328 udelay(10);
329
330 return 0;
331 }
332
333 /*
334 * Description:
335 * Halt PP32.
336 * Input:
337 * none
338 * Output:
339 * none
340 */
341 void ifx_pp32_stop(int pp32)
342 {
343 /* halt PP32 */
344 IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
345 }
346
347 int ifx_ptm_proc_read_regs(char *page, char **start, off_t off, int count, int *eof, void *data)
348 {
349 int len = 0;
350
351 len += sprintf(page + off + len, "EMA:\n");
352 len += sprintf(page + off + len, " SB_MST_PRI0 - 0x%08X, SB_MST_PRI1 - 0x%08X\n", IFX_REG_R32(SB_MST_PRI0), IFX_REG_R32(SB_MST_PRI1));
353 len += sprintf(page + off + len, " EMA_CMDCFG - 0x%08X, EMA_DATACFG - 0x%08X\n", IFX_REG_R32(EMA_CMDCFG), IFX_REG_R32(EMA_DATACFG));
354 len += sprintf(page + off + len, " EMA_IER - 0x%08X, EMA_CFG - 0x%08X\n", IFX_REG_R32(EMA_IER), IFX_REG_R32(EMA_CFG));
355
356 len += sprintf(page + off + len, "Mailbox:\n");
357 len += sprintf(page + off + len, " MBOX_IGU1_IER - 0x%08X, MBOX_IGU1_ISR - 0x%08X\n", IFX_REG_R32(MBOX_IGU1_IER), IFX_REG_R32(MBOX_IGU1_ISR));
358 len += sprintf(page + off + len, " MBOX_IGU3_IER - 0x%08X, MBOX_IGU3_ISR - 0x%08X\n", IFX_REG_R32(MBOX_IGU3_IER), IFX_REG_R32(MBOX_IGU3_ISR));
359
360 len += sprintf(page + off + len, "TC:\n");
361 len += sprintf(page + off + len, " RFBI_CFG - 0x%08X\n", IFX_REG_R32(RFBI_CFG));
362 len += sprintf(page + off + len, " SFSM_DBA0 - 0x%08X, SFSM_CBA0 - 0x%08X, SFSM_CFG0 - 0x%08X\n", IFX_REG_R32(SFSM_DBA0), IFX_REG_R32(SFSM_CBA0), IFX_REG_R32(SFSM_CFG0));
363 len += sprintf(page + off + len, " SFSM_DBA1 - 0x%08X, SFSM_CBA1 - 0x%08X, SFSM_CFG1 - 0x%08X\n", IFX_REG_R32(SFSM_DBA1), IFX_REG_R32(SFSM_CBA1), IFX_REG_R32(SFSM_CFG1));
364 len += sprintf(page + off + len, " FFSM_DBA0 - 0x%08X, FFSM_CFG0 - 0x%08X, IDLE_HEAD - 0x%08X\n", IFX_REG_R32(FFSM_DBA0), IFX_REG_R32(FFSM_CFG0), IFX_REG_R32(FFSM_IDLE_HEAD_BC0));
365 len += sprintf(page + off + len, " FFSM_DBA1 - 0x%08X, FFSM_CFG1 - 0x%08X, IDLE_HEAD - 0x%08X\n", IFX_REG_R32(FFSM_DBA1), IFX_REG_R32(FFSM_CFG1), IFX_REG_R32(FFSM_IDLE_HEAD_BC1));
366
367 len += sprintf(page + off + len, "DPlus:\n");
368 len += sprintf(page + off + len, " DM_RXDB - 0x%08X, DM_RXCB - 0x%08X, DM_RXCFG - 0x%08X\n", IFX_REG_R32(DM_RXDB), IFX_REG_R32(DM_RXCB), IFX_REG_R32(DM_RXCFG));
369 len += sprintf(page + off + len, " DM_RXPGCNT - 0x%08X, DM_RXPKTCNT - 0x%08X\n", IFX_REG_R32(DM_RXPGCNT), IFX_REG_R32(DM_RXPKTCNT));
370 len += sprintf(page + off + len, " DS_RXDB - 0x%08X, DS_RXCB - 0x%08X, DS_RXCFG - 0x%08X\n", IFX_REG_R32(DS_RXDB), IFX_REG_R32(DS_RXCB), IFX_REG_R32(DS_RXCFG));
371 len += sprintf(page + off + len, " DS_RXPGCNT - 0x%08X\n", IFX_REG_R32(DS_RXPGCNT));
372
373 *eof = 1;
374
375 return len;
376 }