package/kernel/mac80211/patches/302-ath10k-Delay-device-access-after-cold-reset.patch

   1 From: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
   2 Date: Fri, 3 Jul 2015 11:45:42 +0530
   3 Subject: [PATCH] ath10k: Delay device access after cold reset
   4
   5 It is observed that during cold reset pcie access right
   6 after a write operation to SOC_GLOBAL_RESET_ADDRESS causes
   7 Data Bus Error and system hard lockup. The reason
   8 for bus error is that pcie needs some time to get
   9 back to stable state for any transaction during cold reset. Add
  10 delay of 20 msecs after write of SOC_GLOBAL_RESET_ADDRESS
  11 to fix this issue.
  12
  13 Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qti.qualcomm.com>
  14 ---
  15
  16 --- a/drivers/net/wireless/ath/ath10k/pci.c
  17 +++ b/drivers/net/wireless/ath/ath10k/pci.c
  18 @@ -2761,7 +2761,6 @@ static int ath10k_pci_wait_for_target_in
  19
  20  static int ath10k_pci_cold_reset(struct ath10k *ar)
  21  {
  22 -       int i;
  23         u32 val;
  24
  25         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset\n");
  26 @@ -2777,23 +2776,18 @@ static int ath10k_pci_cold_reset(struct
  27         val |= 1;
  28         ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
  29
  30 -       for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
  31 -               if (ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
  32 -                                         RTC_STATE_COLD_RESET_MASK)
  33 -                       break;
  34 -               msleep(1);
  35 -       }
  36 +       /* After writing into SOC_GLOBAL_RESET to put device into
  37 +        * reset and pulling out of reset pcie may not be stable
  38 +        * for any immediate pcie register access and cause bus error,
  39 +        * add delay before any pcie access request to fix this issue.
  40 +        */
  41 +       msleep(20);
  42
  43         /* Pull Target, including PCIe, out of RESET. */
  44         val &= ~1;
  45         ath10k_pci_reg_write32(ar, SOC_GLOBAL_RESET_ADDRESS, val);
  46
  47 -       for (i = 0; i < ATH_PCI_RESET_WAIT_MAX; i++) {
  48 -               if (!(ath10k_pci_reg_read32(ar, RTC_STATE_ADDRESS) &
  49 -                                           RTC_STATE_COLD_RESET_MASK))
  50 -                       break;
  51 -               msleep(1);
  52 -       }
  53 +       msleep(20);
  54
  55         ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cold reset complete\n");
  56