package/kernel/mac80211/patches/344-0011-brcmfmac-remove-pcie-gen1-support.patch

   1 From: Hante Meuleman <meuleman@broadcom.com>
   2 Date: Wed, 17 Feb 2016 11:27:00 +0100
   3 Subject: [PATCH] brcmfmac: remove pcie gen1 support
   4
   5 The PCIE bus driver supports older gen1 (v1) chips, but there is no
   6 actual device which is using this older pcie core which is supported
   7 by brcmfmac. Remove all gen1 related code.
   8
   9 Reviewed-by: Arend Van Spriel <arend@broadcom.com>
  10 Reviewed-by: Franky (Zhenhui) Lin <frankyl@broadcom.com>
  11 Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com>
  12 Signed-off-by: Hante Meuleman <meuleman@broadcom.com>
  13 Signed-off-by: Arend van Spriel <arend@broadcom.com>
  14 Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
  15 ---
  16
  17 --- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
  18 +++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c
  19 @@ -100,9 +100,6 @@ static struct brcmf_firmware_mapping brc
  20  #define BRCMF_PCIE_PCIE2REG_CONFIGDATA         0x124
  21  #define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX                0x140
  22
  23 -#define BRCMF_PCIE_GENREV1                     1
  24 -#define BRCMF_PCIE_GENREV2                     2
  25 -
  26  #define BRCMF_PCIE2_INTA                       0x01
  27  #define BRCMF_PCIE2_INTB                       0x02
  28
  29 @@ -257,9 +254,7 @@ struct brcmf_pciedev_info {
  30         u32 ram_size;
  31         struct brcmf_chip *ci;
  32         u32 coreid;
  33 -       u32 generic_corerev;
  34         struct brcmf_pcie_shared_info shared;
  35 -       void (*ringbell)(struct brcmf_pciedev_info *devinfo);
  36         wait_queue_head_t mbdata_resp_wait;
  37         bool mbdata_completed;
  38         bool irq_allocated;
  39 @@ -746,68 +741,22 @@ static void brcmf_pcie_bus_console_read(
  40  }
  41
  42
  43 -static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
  44 -{
  45 -       u32 reg_value;
  46 -
  47 -       brcmf_dbg(PCIE, "RING !\n");
  48 -       reg_value = brcmf_pcie_read_reg32(devinfo,
  49 -                                         BRCMF_PCIE_PCIE2REG_MAILBOXINT);
  50 -       reg_value |= BRCMF_PCIE2_INTB;
  51 -       brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
  52 -                              reg_value);
  53 -}
  54 -
  55 -
  56 -static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
  57 -{
  58 -       brcmf_dbg(PCIE, "RING !\n");
  59 -       /* Any arbitrary value will do, lets use 1 */
  60 -       brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
  61 -}
  62 -
  63 -
  64  static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
  65  {
  66 -       if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
  67 -               pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
  68 -                                      0);
  69 -       else
  70 -               brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
  71 -                                      0);
  72 +       brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
  73  }
  74
  75
  76  static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
  77  {
  78 -       if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
  79 -               pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
  80 -                                      BRCMF_PCIE_INT_DEF);
  81 -       else
  82 -               brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
  83 -                                      BRCMF_PCIE_MB_INT_D2H_DB |
  84 -                                      BRCMF_PCIE_MB_INT_FN0_0 |
  85 -                                      BRCMF_PCIE_MB_INT_FN0_1);
  86 +       brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
  87 +                              BRCMF_PCIE_MB_INT_D2H_DB |
  88 +                              BRCMF_PCIE_MB_INT_FN0_0 |
  89 +                              BRCMF_PCIE_MB_INT_FN0_1);
  90  }
  91
  92
  93 -static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
  94 -{
  95 -       struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
  96 -       u32 status;
  97 -
  98 -       status = 0;
  99 -       pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 100 -       if (status) {
 101 -               brcmf_pcie_intr_disable(devinfo);
 102 -               brcmf_dbg(PCIE, "Enter\n");
 103 -               return IRQ_WAKE_THREAD;
 104 -       }
 105 -       return IRQ_NONE;
 106 -}
 107 -
 108 -
 109 -static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
 110 +static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
 111  {
 112         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 113
 114 @@ -820,29 +769,7 @@ static irqreturn_t brcmf_pcie_quick_chec
 115  }
 116
 117
 118 -static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
 119 -{
 120 -       struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 121 -       const struct pci_dev *pdev = devinfo->pdev;
 122 -       u32 status;
 123 -
 124 -       devinfo->in_irq = true;
 125 -       status = 0;
 126 -       pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 127 -       brcmf_dbg(PCIE, "Enter %x\n", status);
 128 -       if (status) {
 129 -               pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 130 -               if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 131 -                       brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
 132 -       }
 133 -       if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 134 -               brcmf_pcie_intr_enable(devinfo);
 135 -       devinfo->in_irq = false;
 136 -       return IRQ_HANDLED;
 137 -}
 138 -
 139 -
 140 -static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
 141 +static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
 142  {
 143         struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 144         u32 status;
 145 @@ -879,28 +806,14 @@ static int brcmf_pcie_request_irq(struct
 146         brcmf_pcie_intr_disable(devinfo);
 147
 148         brcmf_dbg(PCIE, "Enter\n");
 149 -       /* is it a v1 or v2 implementation */
 150 +
 151         pci_enable_msi(pdev);
 152 -       if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 153 -               if (request_threaded_irq(pdev->irq,
 154 -                                        brcmf_pcie_quick_check_isr_v1,
 155 -                                        brcmf_pcie_isr_thread_v1,
 156 -                                        IRQF_SHARED, "brcmf_pcie_intr",
 157 -                                        devinfo)) {
 158 -                       pci_disable_msi(pdev);
 159 -                       brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 160 -                       return -EIO;
 161 -               }
 162 -       } else {
 163 -               if (request_threaded_irq(pdev->irq,
 164 -                                        brcmf_pcie_quick_check_isr_v2,
 165 -                                        brcmf_pcie_isr_thread_v2,
 166 -                                        IRQF_SHARED, "brcmf_pcie_intr",
 167 -                                        devinfo)) {
 168 -                       pci_disable_msi(pdev);
 169 -                       brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 170 -                       return -EIO;
 171 -               }
 172 +       if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
 173 +                                brcmf_pcie_isr_thread, IRQF_SHARED,
 174 +                                "brcmf_pcie_intr", devinfo)) {
 175 +               pci_disable_msi(pdev);
 176 +               brcmf_err("Failed to request IRQ %d\n", pdev->irq);
 177 +               return -EIO;
 178         }
 179         devinfo->irq_allocated = true;
 180         return 0;
 181 @@ -931,16 +844,9 @@ static void brcmf_pcie_release_irq(struc
 182         if (devinfo->in_irq)
 183                 brcmf_err("Still in IRQ (processing) !!!\n");
 184
 185 -       if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
 186 -               status = 0;
 187 -               pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
 188 -               pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
 189 -       } else {
 190 -               status = brcmf_pcie_read_reg32(devinfo,
 191 -                                              BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 192 -               brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 193 -                                      status);
 194 -       }
 195 +       status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
 196 +       brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
 197 +
 198         devinfo->irq_allocated = false;
 199  }
 200
 201 @@ -989,7 +895,9 @@ static int brcmf_pcie_ring_mb_ring_bell(
 202         if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
 203                 return -EIO;
 204
 205 -       devinfo->ringbell(devinfo);
 206 +       brcmf_dbg(PCIE, "RING !\n");
 207 +       /* Any arbitrary value will do, lets use 1 */
 208 +       brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
 209
 210         return 0;
 211  }
 212 @@ -1503,9 +1411,6 @@ static int brcmf_pcie_download_fw_nvram(
 213         u32 address;
 214         u32 resetintr;
 215
 216 -       devinfo->ringbell = brcmf_pcie_ringbell_v2;
 217 -       devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
 218 -
 219         brcmf_dbg(PCIE, "Halt ARM.\n");
 220         err = brcmf_pcie_enter_download_state(devinfo);
 221         if (err)