lantiq: Tune the XWAY subtarget cflags
[openwrt/staging/yousong.git] / package / platform / lantiq / ltq-adsl-mei / src / ifxmips_mei_interface.h
1 /******************************************************************************
2
3 Copyright (c) 2009
4 Infineon Technologies AG
5 Am Campeon 1-12; 81726 Munich, Germany
6
7 For licensing information, see the file 'LICENSE' in the root folder of
8 this software module.
9
10 ******************************************************************************/
11
12 #ifndef IFXMIPS_MEI_H
13 #define IFXMIPS_MEI_H
14
15 //#define CONFIG_AMAZON_SE 1
16 //#define CONFIG_DANUBE 1
17 //#define CONFIG_AR9 1
18
19 #if !defined(CONFIG_DANUBE) && !defined(CONFIG_AMAZON_SE) && !defined(CONFIG_AR9) && !defined(CONFIG_VR9)
20 #error Platform undefined!!!
21 #endif
22
23 #ifdef IFX_MEI_BSP
24 /** This is the character datatype. */
25 typedef char DSL_char_t;
26 /** This is the unsigned 8-bit datatype. */
27 typedef unsigned char DSL_uint8_t;
28 /** This is the signed 8-bit datatype. */
29 typedef signed char DSL_int8_t;
30 /** This is the unsigned 16-bit datatype. */
31 typedef unsigned short DSL_uint16_t;
32 /** This is the signed 16-bit datatype. */
33 typedef signed short DSL_int16_t;
34 /** This is the unsigned 32-bit datatype. */
35 typedef unsigned long DSL_uint32_t;
36 /** This is the signed 32-bit datatype. */
37 typedef signed long DSL_int32_t;
38 /** This is the float datatype. */
39 typedef float DSL_float_t;
40 /** This is the void datatype. */
41 typedef void DSL_void_t;
42 /** integer type, width is depending on processor arch */
43 typedef int DSL_int_t;
44 /** unsigned integer type, width is depending on processor arch */
45 typedef unsigned int DSL_uint_t;
46 typedef struct file DSL_DRV_file_t;
47 typedef struct inode DSL_DRV_inode_t;
48
49 /**
50 * Defines all possible CMV groups
51 * */
52 typedef enum {
53 DSL_CMV_GROUP_CNTL = 1,
54 DSL_CMV_GROUP_STAT = 2,
55 DSL_CMV_GROUP_INFO = 3,
56 DSL_CMV_GROUP_TEST = 4,
57 DSL_CMV_GROUP_OPTN = 5,
58 DSL_CMV_GROUP_RATE = 6,
59 DSL_CMV_GROUP_PLAM = 7,
60 DSL_CMV_GROUP_CNFG = 8
61 } DSL_CmvGroup_t;
62 /**
63 * Defines all opcode types
64 * */
65 typedef enum {
66 H2D_CMV_READ = 0x00,
67 H2D_CMV_WRITE = 0x04,
68 H2D_CMV_INDICATE_REPLY = 0x10,
69 H2D_ERROR_OPCODE_UNKNOWN =0x20,
70 H2D_ERROR_CMV_UNKNOWN =0x30,
71
72 D2H_CMV_READ_REPLY =0x01,
73 D2H_CMV_WRITE_REPLY = 0x05,
74 D2H_CMV_INDICATE = 0x11,
75 D2H_ERROR_OPCODE_UNKNOWN = 0x21,
76 D2H_ERROR_CMV_UNKNOWN = 0x31,
77 D2H_ERROR_CMV_READ_NOT_AVAILABLE = 0x41,
78 D2H_ERROR_CMV_WRITE_ONLY = 0x51,
79 D2H_ERROR_CMV_READ_ONLY = 0x61,
80
81 H2D_DEBUG_READ_DM = 0x02,
82 H2D_DEBUG_READ_PM = 0x06,
83 H2D_DEBUG_WRITE_DM = 0x0a,
84 H2D_DEBUG_WRITE_PM = 0x0e,
85
86 D2H_DEBUG_READ_DM_REPLY = 0x03,
87 D2H_DEBUG_READ_FM_REPLY = 0x07,
88 D2H_DEBUG_WRITE_DM_REPLY = 0x0b,
89 D2H_DEBUG_WRITE_FM_REPLY = 0x0f,
90 D2H_ERROR_ADDR_UNKNOWN = 0x33,
91
92 D2H_AUTONOMOUS_MODEM_READY_MSG = 0xf1
93 } DSL_CmvOpcode_t;
94
95 /* mutex macros */
96 #define MEI_MUTEX_INIT(id,flag) \
97 sema_init(&id,flag)
98 #define MEI_MUTEX_LOCK(id) \
99 down_interruptible(&id)
100 #define MEI_MUTEX_UNLOCK(id) \
101 up(&id)
102 #define MEI_WAIT(ms) \
103 {\
104 set_current_state(TASK_INTERRUPTIBLE);\
105 schedule_timeout(ms);\
106 }
107 #define MEI_INIT_WAKELIST(name,queue) \
108 init_waitqueue_head(&queue)
109
110 /* wait for an event, timeout is measured in ms */
111 #define MEI_WAIT_EVENT_TIMEOUT(ev,timeout)\
112 interruptible_sleep_on_timeout(&ev,timeout * HZ / 1000)
113 #define MEI_WAKEUP_EVENT(ev)\
114 wake_up_interruptible(&ev)
115 #endif /* IFX_MEI_BSP */
116
117 /*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/
118 #define ME_DX_DATA (0x0000)
119 #define ME_VERSION (0x0004)
120 #define ME_ARC_GP_STAT (0x0008)
121 #define ME_DX_STAT (0x000C)
122 #define ME_DX_AD (0x0010)
123 #define ME_DX_MWS (0x0014)
124 #define ME_ME2ARC_INT (0x0018)
125 #define ME_ARC2ME_STAT (0x001C)
126 #define ME_ARC2ME_MASK (0x0020)
127 #define ME_DBG_WR_AD (0x0024)
128 #define ME_DBG_RD_AD (0x0028)
129 #define ME_DBG_DATA (0x002C)
130 #define ME_DBG_DECODE (0x0030)
131 #define ME_CONFIG (0x0034)
132 #define ME_RST_CTRL (0x0038)
133 #define ME_DBG_MASTER (0x003C)
134 #define ME_CLK_CTRL (0x0040)
135 #define ME_BIST_CTRL (0x0044)
136 #define ME_BIST_STAT (0x0048)
137 #define ME_XDATA_BASE_SH (0x004c)
138 #define ME_XDATA_BASE (0x0050)
139 #define ME_XMEM_BAR_BASE (0x0054)
140 #define ME_XMEM_BAR0 (0x0054)
141 #define ME_XMEM_BAR1 (0x0058)
142 #define ME_XMEM_BAR2 (0x005C)
143 #define ME_XMEM_BAR3 (0x0060)
144 #define ME_XMEM_BAR4 (0x0064)
145 #define ME_XMEM_BAR5 (0x0068)
146 #define ME_XMEM_BAR6 (0x006C)
147 #define ME_XMEM_BAR7 (0x0070)
148 #define ME_XMEM_BAR8 (0x0074)
149 #define ME_XMEM_BAR9 (0x0078)
150 #define ME_XMEM_BAR10 (0x007C)
151 #define ME_XMEM_BAR11 (0x0080)
152 #define ME_XMEM_BAR12 (0x0084)
153 #define ME_XMEM_BAR13 (0x0088)
154 #define ME_XMEM_BAR14 (0x008C)
155 #define ME_XMEM_BAR15 (0x0090)
156 #define ME_XMEM_BAR16 (0x0094)
157
158 #define WHILE_DELAY 20000
159 /*
160 ** Define where in ME Processor's memory map the Stratify chip lives
161 */
162
163 #define MAXSWAPSIZE (8 * 1024) //8k *(32bits)
164
165 // Mailboxes
166 #define MSG_LENGTH 16 // x16 bits
167 #define YES_REPLY 1
168 #define NO_REPLY 0
169
170 #define CMV_TIMEOUT 1000 //jiffies
171
172 // Block size per BAR
173 #define SDRAM_SEGMENT_SIZE (64*1024)
174 // Number of Bar registers
175 #define MAX_BAR_REGISTERS (17)
176
177 #define XDATA_REGISTER (15)
178
179 // ARC register addresss
180 #define ARC_STATUS 0x0
181 #define ARC_LP_START 0x2
182 #define ARC_LP_END 0x3
183 #define ARC_DEBUG 0x5
184 #define ARC_INT_MASK 0x10A
185
186 #define IRAM0_BASE (0x00000)
187 #define IRAM1_BASE (0x04000)
188 #if defined(CONFIG_DANUBE)
189 #define BRAM_BASE (0x0A000)
190 #elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
191 #define BRAM_BASE (0x08000)
192 #endif
193 #define XRAM_BASE (0x18000)
194 #define YRAM_BASE (0x1A000)
195 #define EXT_MEM_BASE (0x80000)
196 #define ARC_GPIO_CTRL (0xC030)
197 #define ARC_GPIO_DATA (0xC034)
198
199 #define IRAM0_SIZE (16*1024)
200 #define IRAM1_SIZE (16*1024)
201 #define BRAM_SIZE (12*1024)
202 #define XRAM_SIZE (8*1024)
203 #define YRAM_SIZE (8*1024)
204 #define EXT_MEM_SIZE (1536*1024)
205
206 #define ADSL_BASE (0x20000)
207 #define CRI_BASE (ADSL_BASE + 0x11F00)
208 #define CRI_CCR0 (CRI_BASE + 0x00)
209 #define CRI_RST (CRI_BASE + 0x04*4)
210 #define ADSL_DILV_BASE (ADSL_BASE+0x20000)
211
212 //
213 #define IRAM0_ADDR_BIT_MASK 0xFFF
214 #define IRAM1_ADDR_BIT_MASK 0xFFF
215 #define BRAM_ADDR_BIT_MASK 0xFFF
216 #define RX_DILV_ADDR_BIT_MASK 0x1FFF
217
218 /*** Bit definitions ***/
219 #define ARC_AUX_HALT (1 << 25)
220 #define ARC_DEBUG_HALT (1 << 1)
221 #define FALSE 0
222 #define TRUE 1
223 #define BIT0 (1<<0)
224 #define BIT1 (1<<1)
225 #define BIT2 (1<<2)
226 #define BIT3 (1<<3)
227 #define BIT4 (1<<4)
228 #define BIT5 (1<<5)
229 #define BIT6 (1<<6)
230 #define BIT7 (1<<7)
231 #define BIT8 (1<<8)
232 #define BIT9 (1<<9)
233 #define BIT10 (1<<10)
234 #define BIT11 (1<<11)
235 #define BIT12 (1<<12)
236 #define BIT13 (1<<13)
237 #define BIT14 (1<<14)
238 #define BIT15 (1<<15)
239 #define BIT16 (1<<16)
240 #define BIT17 (1<<17)
241 #define BIT18 (1<<18)
242 #define BIT19 (1<<19)
243 #define BIT20 (1<<20)
244 #define BIT21 (1<<21)
245 #define BIT22 (1<<22)
246 #define BIT23 (1<<23)
247 #define BIT24 (1<<24)
248 #define BIT25 (1<<25)
249 #define BIT26 (1<<26)
250 #define BIT27 (1<<27)
251 #define BIT28 (1<<28)
252 #define BIT29 (1<<29)
253 #define BIT30 (1<<30)
254 #define BIT31 (1<<31)
255
256 // CRI_CCR0 Register definitions
257 #define CLK_2M_MODE_ENABLE BIT6
258 #define ACL_CLK_MODE_ENABLE BIT4
259 #define FDF_CLK_MODE_ENABLE BIT2
260 #define STM_CLK_MODE_ENABLE BIT0
261
262 // CRI_RST Register definitions
263 #define FDF_SRST BIT3
264 #define MTE_SRST BIT2
265 #define FCI_SRST BIT1
266 #define AAI_SRST BIT0
267
268 // MEI_TO_ARC_INTERRUPT Register definitions
269 #define MEI_TO_ARC_INT1 BIT3
270 #define MEI_TO_ARC_INT0 BIT2
271 #define MEI_TO_ARC_CS_DONE BIT1 //need to check
272 #define MEI_TO_ARC_MSGAV BIT0
273
274 // ARC_TO_MEI_INTERRUPT Register definitions
275 #define ARC_TO_MEI_INT1 BIT8
276 #define ARC_TO_MEI_INT0 BIT7
277 #define ARC_TO_MEI_CS_REQ BIT6
278 #define ARC_TO_MEI_DBG_DONE BIT5
279 #define ARC_TO_MEI_MSGACK BIT4
280 #define ARC_TO_MEI_NO_ACCESS BIT3
281 #define ARC_TO_MEI_CHECK_AAITX BIT2
282 #define ARC_TO_MEI_CHECK_AAIRX BIT1
283 #define ARC_TO_MEI_MSGAV BIT0
284
285 // ARC_TO_MEI_INTERRUPT_MASK Register definitions
286 #define GP_INT1_EN BIT8
287 #define GP_INT0_EN BIT7
288 #define CS_REQ_EN BIT6
289 #define DBG_DONE_EN BIT5
290 #define MSGACK_EN BIT4
291 #define NO_ACC_EN BIT3
292 #define AAITX_EN BIT2
293 #define AAIRX_EN BIT1
294 #define MSGAV_EN BIT0
295
296 #define MEI_SOFT_RESET BIT0
297
298 #define HOST_MSTR BIT0
299
300 #define JTAG_MASTER_MODE 0x0
301 #define MEI_MASTER_MODE HOST_MSTR
302
303 // MEI_DEBUG_DECODE Register definitions
304 #define MEI_DEBUG_DEC_MASK (0x3)
305 #define MEI_DEBUG_DEC_AUX_MASK (0x0)
306 #define ME_DBG_DECODE_DMP1_MASK (0x1)
307 #define MEI_DEBUG_DEC_DMP2_MASK (0x2)
308 #define MEI_DEBUG_DEC_CORE_MASK (0x3)
309
310 #define AUX_STATUS (0x0)
311 #define AUX_ARC_GPIO_CTRL (0x10C)
312 #define AUX_ARC_GPIO_DATA (0x10D)
313 // ARC_TO_MEI_MAILBOX[11] is a special location used to indicate
314 // page swap requests.
315 #if defined(CONFIG_DANUBE)
316 #define OMBOX_BASE 0xDF80
317 #define ARC_TO_MEI_MAILBOX 0xDFA0
318 #define IMBOX_BASE 0xDFC0
319 #define MEI_TO_ARC_MAILBOX 0xDFD0
320 #elif defined(CONFIG_AMAZON_SE) || defined(CONFIG_AR9) || defined(CONFIG_VR9)
321 #define OMBOX_BASE 0xAF80
322 #define ARC_TO_MEI_MAILBOX 0xAFA0
323 #define IMBOX_BASE 0xAFC0
324 #define MEI_TO_ARC_MAILBOX 0xAFD0
325 #endif
326
327 #define MEI_TO_ARC_MAILBOXR (MEI_TO_ARC_MAILBOX + 0x2C)
328 #define ARC_MEI_MAILBOXR (ARC_TO_MEI_MAILBOX + 0x2C)
329 #define OMBOX1 (OMBOX_BASE+0x4)
330
331 // Codeswap request messages are indicated by setting BIT31
332 #define OMB_CODESWAP_MESSAGE_MSG_TYPE_MASK (0x80000000)
333
334 // Clear Eoc messages received are indicated by setting BIT17
335 #define OMB_CLEAREOC_INTERRUPT_CODE (0x00020000)
336 #define OMB_REBOOT_INTERRUPT_CODE (1 << 18)
337
338 /*
339 ** Swap page header
340 */
341 // Page must be loaded at boot time if size field has BIT31 set
342 #define BOOT_FLAG (BIT31)
343 #define BOOT_FLAG_MASK ~BOOT_FLAG
344
345 #define FREE_RELOAD 1
346 #define FREE_SHOWTIME 2
347 #define FREE_ALL 3
348
349 // marcos
350 #define IFX_MEI_WRITE_REGISTER_L(data,addr) *((volatile u32*)(addr)) = (u32)(data)
351 #define IFX_MEI_READ_REGISTER_L(addr) (*((volatile u32*)(addr)))
352 #define SET_BIT(reg, mask) reg |= (mask)
353 #define CLEAR_BIT(reg, mask) reg &= (~mask)
354 #define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask)
355 //#define SET_BITS(reg, mask) SET_BIT(reg, mask)
356 #define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);}
357
358 #define ALIGN_SIZE ( 1L<<10 ) //1K size align
359 #define MEM_ALIGN(addr) (((addr) + ALIGN_SIZE - 1) & ~ (ALIGN_SIZE -1) )
360
361 // swap marco
362 #define MEI_HALF_WORD_SWAP(data) {data = ((data & 0xffff)<<16) + ((data & 0xffff0000)>>16);}
363 #define MEI_BYTE_SWAP(data) {data = ((data & 0xff)<<24) + ((data & 0xff00)<<8)+ ((data & 0xff0000)>>8)+ ((data & 0xff000000)>>24);}
364
365
366 #ifdef CONFIG_PROC_FS
367 typedef struct reg_entry
368 {
369 int *flag;
370 char name[30]; /* big enough to hold names */
371 char description[100]; /* big enough to hold description */
372 unsigned short low_ino;
373 } reg_entry_t;
374 #endif
375 // Swap page header describes size in 32-bit words, load location, and image offset
376 // for program and/or data segments
377 typedef struct _arc_swp_page_hdr {
378 u32 p_offset; //Offset bytes of progseg from beginning of image
379 u32 p_dest; //Destination addr of progseg on processor
380 u32 p_size; //Size in 32-bitwords of program segment
381 u32 d_offset; //Offset bytes of dataseg from beginning of image
382 u32 d_dest; //Destination addr of dataseg on processor
383 u32 d_size; //Size in 32-bitwords of data segment
384 } ARC_SWP_PAGE_HDR;
385
386 /*
387 ** Swap image header
388 */
389 #define GET_PROG 0 // Flag used for program mem segment
390 #define GET_DATA 1 // Flag used for data mem segment
391
392 // Image header contains size of image, checksum for image, and count of
393 // page headers. Following that are 'count' page headers followed by
394 // the code and/or data segments to be loaded
395 typedef struct _arc_img_hdr {
396 u32 size; // Size of binary image in bytes
397 u32 checksum; // Checksum for image
398 u32 count; // Count of swp pages in image
399 ARC_SWP_PAGE_HDR page[1]; // Should be "count" pages - '1' to make compiler happy
400 } ARC_IMG_HDR;
401
402 typedef struct smmu_mem_info {
403 int type;
404 int boot;
405 unsigned long nCopy;
406 unsigned long size;
407 unsigned char *address;
408 unsigned char *org_address;
409 } smmu_mem_info_t;
410
411 #ifdef __KERNEL__
412 typedef struct ifx_mei_device_private {
413 int modem_ready;
414 int arcmsgav;
415 int cmv_reply;
416 int cmv_waiting;
417 // Mei to ARC CMV count, reply count, ARC Indicator count
418 int modem_ready_cnt;
419 int cmv_count;
420 int reply_count;
421 unsigned long image_size;
422 int nBar;
423 u16 Recent_indicator[MSG_LENGTH];
424
425 u16 CMV_RxMsg[MSG_LENGTH] __attribute__ ((aligned (4)));
426
427 smmu_mem_info_t adsl_mem_info[MAX_BAR_REGISTERS];
428 ARC_IMG_HDR *img_hdr;
429 // to wait for arc cmv reply, sleep on wait_queue_arcmsgav;
430 wait_queue_head_t wait_queue_arcmsgav;
431 wait_queue_head_t wait_queue_modemready;
432 struct semaphore mei_cmv_sema;
433 } ifx_mei_device_private_t;
434 #endif
435 typedef struct winhost_message {
436 union {
437 u16 RxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
438 u16 TxMessage[MSG_LENGTH] __attribute__ ((aligned (4)));
439 } msg;
440 } DSL_DEV_WinHost_Message_t;
441 /********************************************************************************************************
442 * DSL CPE API Driver Stack Interface Definitions
443 * *****************************************************************************************************/
444 /** IOCTL codes for bsp driver */
445 #define DSL_IOC_MEI_BSP_MAGIC 's'
446
447 #define DSL_FIO_BSP_DSL_START _IO (DSL_IOC_MEI_BSP_MAGIC, 0)
448 #define DSL_FIO_BSP_RUN _IO (DSL_IOC_MEI_BSP_MAGIC, 1)
449 #define DSL_FIO_BSP_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 2)
450 #define DSL_FIO_BSP_RESET _IO (DSL_IOC_MEI_BSP_MAGIC, 3)
451 #define DSL_FIO_BSP_REBOOT _IO (DSL_IOC_MEI_BSP_MAGIC, 4)
452 #define DSL_FIO_BSP_HALT _IO (DSL_IOC_MEI_BSP_MAGIC, 5)
453 #define DSL_FIO_BSP_BOOTDOWNLOAD _IO (DSL_IOC_MEI_BSP_MAGIC, 6)
454 #define DSL_FIO_BSP_JTAG_ENABLE _IO (DSL_IOC_MEI_BSP_MAGIC, 7)
455 #define DSL_FIO_FREE_RESOURCE _IO (DSL_IOC_MEI_BSP_MAGIC, 8)
456 #define DSL_FIO_ARC_MUX_TEST _IO (DSL_IOC_MEI_BSP_MAGIC, 9)
457 #define DSL_FIO_BSP_REMOTE _IOW (DSL_IOC_MEI_BSP_MAGIC, 10, u32)
458 #define DSL_FIO_BSP_GET_BASE_ADDRESS _IOR (DSL_IOC_MEI_BSP_MAGIC, 11, u32)
459 #define DSL_FIO_BSP_IS_MODEM_READY _IOR (DSL_IOC_MEI_BSP_MAGIC, 12, u32)
460 #define DSL_FIO_BSP_GET_VERSION _IOR (DSL_IOC_MEI_BSP_MAGIC, 13, DSL_DEV_Version_t)
461 #define DSL_FIO_BSP_CMV_WINHOST _IOWR(DSL_IOC_MEI_BSP_MAGIC, 14, DSL_DEV_WinHost_Message_t)
462 #define DSL_FIO_BSP_CMV_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 15, DSL_DEV_MeiReg_t)
463 #define DSL_FIO_BSP_CMV_WRITE _IOW (DSL_IOC_MEI_BSP_MAGIC, 16, DSL_DEV_MeiReg_t)
464 #define DSL_FIO_BSP_DEBUG_READ _IOWR(DSL_IOC_MEI_BSP_MAGIC, 17, DSL_DEV_MeiDebug_t)
465 #define DSL_FIO_BSP_DEBUG_WRITE _IOWR(DSL_IOC_MEI_BSP_MAGIC, 18, DSL_DEV_MeiDebug_t)
466 #define DSL_FIO_BSP_GET_CHIP_INFO _IOR (DSL_IOC_MEI_BSP_MAGIC, 19, DSL_DEV_HwVersion_t)
467
468 #define DSL_DEV_MEIDEBUG_BUFFER_SIZES 512
469
470 typedef struct DSL_DEV_MeiDebug
471 {
472 DSL_uint32_t iAddress;
473 DSL_uint32_t iCount;
474 DSL_uint32_t buffer[DSL_DEV_MEIDEBUG_BUFFER_SIZES];
475 } DSL_DEV_MeiDebug_t; /* meidebug */
476
477 /**
478 * Structure is used for debug access only.
479 * Refer to configure option INCLUDE_ADSL_WINHOST_DEBUG */
480 typedef struct struct_meireg
481 {
482 /*
483 * Specifies that address for debug access */
484 unsigned long iAddress;
485 /*
486 * Specifies the pointer to the data that has to be written or returns a
487 * pointer to the data that has been read out*/
488 unsigned long iData;
489 } DSL_DEV_MeiReg_t; /* meireg */
490
491 typedef struct DSL_DEV_Device
492 {
493 DSL_int_t nInUse; /* modem state, update by bsp driver, */
494 DSL_void_t *pPriv;
495 DSL_uint32_t base_address; /* mei base address */
496 DSL_int_t nIrq[2]; /* irq number */
497 #define IFX_DFEIR 0
498 #define IFX_DYING_GASP 1
499 DSL_DEV_MeiDebug_t lop_debugwr; /* dying gasp */
500 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0))
501 struct module *owner;
502 #endif
503 } DSL_DEV_Device_t; /* ifx_adsl_device_t */
504
505 #define DSL_DEV_PRIVATE(dev) ((ifx_mei_device_private_t*)(dev->pPriv))
506
507 typedef struct DSL_DEV_Version /* ifx_adsl_bsp_version */
508 {
509 unsigned long major;
510 unsigned long minor;
511 unsigned long revision;
512 } DSL_DEV_Version_t; /* ifx_adsl_bsp_version_t */
513
514 typedef struct DSL_DEV_ChipInfo
515 {
516 unsigned long major;
517 unsigned long minor;
518 } DSL_DEV_HwVersion_t;
519
520 typedef struct
521 {
522 DSL_uint8_t dummy;
523 } DSL_DEV_DeviceConfig_t;
524
525 /** error code definitions */
526 typedef enum DSL_DEV_MeiError
527 {
528 DSL_DEV_MEI_ERR_SUCCESS = 0,
529 DSL_DEV_MEI_ERR_FAILURE = -1,
530 DSL_DEV_MEI_ERR_MAILBOX_FULL = -2,
531 DSL_DEV_MEI_ERR_MAILBOX_EMPTY = -3,
532 DSL_DEV_MEI_ERR_MAILBOX_TIMEOUT = -4
533 } DSL_DEV_MeiError_t; /* MEI_ERROR */
534
535 typedef enum {
536 DSL_BSP_MEMORY_READ=0,
537 DSL_BSP_MEMORY_WRITE,
538 } DSL_BSP_MemoryAccessType_t; /* ifx_adsl_memory_access_type_t */
539
540 typedef enum
541 {
542 DSL_LED_LINK_ID=0,
543 DSL_LED_DATA_ID
544 } DSL_DEV_LedId_t; /* ifx_adsl_led_id_t */
545
546 typedef enum
547 {
548 DSL_LED_LINK_TYPE=0,
549 DSL_LED_DATA_TYPE
550 } DSL_DEV_LedType_t; /* ifx_adsl_led_type_t */
551
552 typedef enum
553 {
554 DSL_LED_HD_CPU=0,
555 DSL_LED_HD_FW
556 } DSL_DEV_LedHandler_t; /* ifx_adsl_led_handler_t */
557
558 typedef enum {
559 DSL_LED_ON=0,
560 DSL_LED_OFF,
561 DSL_LED_FLASH,
562 } DSL_DEV_LedMode_t; /* ifx_adsl_led_mode_t */
563
564 typedef enum {
565 DSL_CPU_HALT=0,
566 DSL_CPU_RUN,
567 DSL_CPU_RESET,
568 } DSL_DEV_CpuMode_t; /* ifx_adsl_cpu_mode_t */
569
570 #if 0
571 typedef enum {
572 DSL_BSP_EVENT_DYING_GASP = 0,
573 DSL_BSP_EVENT_CEOC_IRQ,
574 } DSL_BSP_Event_id_t; /* ifx_adsl_event_id_t */
575
576 typedef union DSL_BSP_CB_Param
577 {
578 DSL_uint32_t nIrqMessage;
579 } DSL_BSP_CB_Param_t; /* ifx_adsl_cbparam_t */
580
581 typedef struct DSL_BSP_CB_Event
582 {
583 DSL_BSP_Event_id_t nID;
584 DSL_DEV_Device_t *pDev;
585 DSL_BSP_CB_Param_t *pParam;
586 } DSL_BSP_CB_Event_t; /* ifx_adsl_cb_event_t */
587 #endif
588
589 /* external functions (from the BSP Driver) */
590 extern DSL_DEV_Device_t* DSL_BSP_DriverHandleGet(int, int);
591 extern DSL_int_t DSL_BSP_DriverHandleDelete(DSL_DEV_Device_t *);
592 extern DSL_DEV_MeiError_t DSL_BSP_FWDownload(DSL_DEV_Device_t *, const DSL_char_t *, DSL_uint32_t, DSL_int32_t *, DSL_int32_t *);
593 extern int DSL_BSP_KernelIoctls(DSL_DEV_Device_t *, unsigned int, unsigned long);
594 extern DSL_DEV_MeiError_t DSL_BSP_SendCMV(DSL_DEV_Device_t *, DSL_uint16_t *, DSL_int_t, DSL_uint16_t *);
595 extern DSL_DEV_MeiError_t DSL_BSP_AdslLedInit(DSL_DEV_Device_t *, DSL_DEV_LedId_t, DSL_DEV_LedType_t, DSL_DEV_LedHandler_t);
596 extern DSL_DEV_MeiError_t DSL_BSP_Showtime(DSL_DEV_Device_t *, DSL_uint32_t, DSL_uint32_t);
597 extern int DSL_BSP_ATMLedCBRegister( int (*ifx_adsl_ledcallback)(void));
598 extern DSL_DEV_MeiError_t DSL_BSP_MemoryDebugAccess(DSL_DEV_Device_t *, DSL_BSP_MemoryAccessType_t, DSL_uint32_t, DSL_uint32_t *, DSL_uint32_t);
599 extern volatile DSL_DEV_Device_t *adsl_dev;
600
601 /**
602 * Dummy structure by now to show mechanism of extended data that will be
603 * provided within event callback itself.
604 * */
605 typedef struct
606 {
607 /**
608 * Dummy value */
609 DSL_uint32_t nDummy1;
610 } DSL_BSP_CB_Event1DataDummy_t;
611
612 /**
613 * Dummy structure by now to show mechanism of extended data that will be
614 * provided within event callback itself.
615 * */
616 typedef struct
617 {
618 /**
619 * Dummy value */
620 DSL_uint32_t nDummy2;
621 } DSL_BSP_CB_Event2DataDummy_t;
622
623 /**
624 * encapsulate all data structures that are necessary for status event
625 * callbacks.
626 * */
627 typedef union
628 {
629 DSL_BSP_CB_Event1DataDummy_t dataEvent1;
630 DSL_BSP_CB_Event2DataDummy_t dataEvent2;
631 } DSL_BSP_CB_DATA_Union_t;
632
633
634 typedef enum
635 {
636 /**
637 * Informs the upper layer driver (DSL CPE API) about a reboot request from the
638 * firmware.
639 * \note This event does NOT include any additional data.
640 * More detailed information upon reboot reason has to be requested from
641 * upper layer software via CMV (INFO 109) if necessary. */
642 DSL_BSP_CB_FIRST = 0,
643 DSL_BSP_CB_DYING_GASP,
644 DSL_BSP_CB_CEOC_IRQ,
645 DSL_BSP_CB_FIRMWARE_REBOOT,
646 /**
647 * Delimiter only */
648 DSL_BSP_CB_LAST
649 } DSL_BSP_CB_Type_t;
650
651 /**
652 * Specifies the common event type that has to be used for registering and
653 * signalling of interrupts/autonomous status events from MEI BSP Driver.
654 *
655 * \param pDev
656 * Context pointer from MEI BSP Driver.
657 *
658 * \param IFX_ADSL_BSP_CallbackType_t
659 * Specifies the event callback type (reason of callback). Regrading to the
660 * setting of this value the data which is included in the following union
661 * might have different meanings.
662 * Please refer to the description of the union to get information about the
663 * meaning of the included data.
664 *
665 * \param pData
666 * Data according to \ref DSL_BSP_CB_DATA_Union_t.
667 * If this pointer is NULL there is no additional data available.
668 *
669 * \return depending on event
670 */
671 typedef int (*DSL_BSP_EventCallback_t)
672 (
673 DSL_DEV_Device_t *pDev,
674 DSL_BSP_CB_Type_t nCallbackType,
675 DSL_BSP_CB_DATA_Union_t *pData
676 );
677
678 typedef struct {
679 DSL_BSP_EventCallback_t function;
680 DSL_BSP_CB_Type_t event;
681 DSL_BSP_CB_DATA_Union_t *pData;
682 } DSL_BSP_EventCallBack_t;
683
684 extern int DSL_BSP_EventCBRegister(DSL_BSP_EventCallBack_t *);
685 extern int DSL_BSP_EventCBUnregister(DSL_BSP_EventCallBack_t *);
686
687 /** Modem states */
688 #define DSL_DEV_STAT_InitState 0x0000
689 #define DSL_DEV_STAT_ReadyState 0x0001
690 #define DSL_DEV_STAT_FailState 0x0002
691 #define DSL_DEV_STAT_IdleState 0x0003
692 #define DSL_DEV_STAT_QuietState 0x0004
693 #define DSL_DEV_STAT_GhsState 0x0005
694 #define DSL_DEV_STAT_FullInitState 0x0006
695 #define DSL_DEV_STAT_ShowTimeState 0x0007
696 #define DSL_DEV_STAT_FastRetrainState 0x0008
697 #define DSL_DEV_STAT_LoopDiagMode 0x0009
698 #define DSL_DEV_STAT_ShortInit 0x000A /* Bis short initialization */
699
700 #define DSL_DEV_STAT_CODESWAP_COMPLETE 0x0002
701
702 #endif //IFXMIPS_MEI_H