kernel: update phy drivers for 4.9
[openwrt/staging/yousong.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
37
38 #include "ar8216.h"
39
40 extern const struct ar8xxx_chip ar8327_chip;
41 extern const struct ar8xxx_chip ar8337_chip;
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 #define MIB_DESC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 }
51
52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
90 };
91
92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
132 };
133
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
135 static LIST_HEAD(ar8xxx_dev_list);
136
137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
138 static int
139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
140 {
141 unsigned int sleep_msecs = 20;
142 int ret, elapsed, i;
143
144 for (elapsed = sleep_msecs; elapsed <= 600;
145 elapsed += sleep_msecs) {
146 msleep(sleep_msecs);
147 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
148 ret = mdiobus_read(bus, i, MII_BMCR);
149 if (ret < 0)
150 return ret;
151 if (ret & BMCR_RESET)
152 break;
153 if (i == AR8XXX_NUM_PHYS - 1) {
154 usleep_range(1000, 2000);
155 return 0;
156 }
157 }
158 }
159 return -ETIMEDOUT;
160 }
161
162 static int
163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
164 {
165 int ret;
166
167 if (phydev->autoneg != AUTONEG_ENABLE)
168 return 0;
169 /*
170 * BMCR_ANENABLE might have been cleared
171 * by phy_init_hw in certain kernel versions
172 * therefore check for it
173 */
174 ret = phy_read(phydev, MII_BMCR);
175 if (ret < 0)
176 return ret;
177 if (ret & BMCR_ANENABLE)
178 return 0;
179
180 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
181 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
182 return phy_write(phydev, MII_BMCR, ret);
183 }
184
185 void
186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
187 {
188 int i;
189 struct mii_bus *bus;
190
191 bus = priv->mii_bus;
192 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
193 if (priv->chip->phy_fixup)
194 priv->chip->phy_fixup(priv, i);
195
196 /* initialize the port itself */
197 mdiobus_write(bus, i, MII_ADVERTISE,
198 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
199 if (ar8xxx_has_gige(priv))
200 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
201 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
202 }
203
204 ar8xxx_phy_poll_reset(bus);
205 }
206
207 u32
208 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
209 {
210 struct mii_bus *bus = priv->mii_bus;
211 u16 lo, hi;
212
213 lo = bus->read(bus, phy_id, regnum);
214 hi = bus->read(bus, phy_id, regnum + 1);
215
216 return (hi << 16) | lo;
217 }
218
219 void
220 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
221 {
222 struct mii_bus *bus = priv->mii_bus;
223 u16 lo, hi;
224
225 lo = val & 0xffff;
226 hi = (u16) (val >> 16);
227
228 if (priv->chip->mii_lo_first)
229 {
230 bus->write(bus, phy_id, regnum, lo);
231 bus->write(bus, phy_id, regnum + 1, hi);
232 } else {
233 bus->write(bus, phy_id, regnum + 1, hi);
234 bus->write(bus, phy_id, regnum, lo);
235 }
236 }
237
238 u32
239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
240 {
241 struct mii_bus *bus = priv->mii_bus;
242 u16 r1, r2, page;
243 u32 val;
244
245 split_addr((u32) reg, &r1, &r2, &page);
246
247 mutex_lock(&bus->mdio_lock);
248
249 bus->write(bus, 0x18, 0, page);
250 wait_for_page_switch();
251 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
252
253 mutex_unlock(&bus->mdio_lock);
254
255 return val;
256 }
257
258 void
259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
260 {
261 struct mii_bus *bus = priv->mii_bus;
262 u16 r1, r2, page;
263
264 split_addr((u32) reg, &r1, &r2, &page);
265
266 mutex_lock(&bus->mdio_lock);
267
268 bus->write(bus, 0x18, 0, page);
269 wait_for_page_switch();
270 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
271
272 mutex_unlock(&bus->mdio_lock);
273 }
274
275 u32
276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
277 {
278 struct mii_bus *bus = priv->mii_bus;
279 u16 r1, r2, page;
280 u32 ret;
281
282 split_addr((u32) reg, &r1, &r2, &page);
283
284 mutex_lock(&bus->mdio_lock);
285
286 bus->write(bus, 0x18, 0, page);
287 wait_for_page_switch();
288
289 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
290 ret &= ~mask;
291 ret |= val;
292 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
293
294 mutex_unlock(&bus->mdio_lock);
295
296 return ret;
297 }
298
299 void
300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
301 u16 dbg_addr, u16 dbg_data)
302 {
303 struct mii_bus *bus = priv->mii_bus;
304
305 mutex_lock(&bus->mdio_lock);
306 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
307 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
308 mutex_unlock(&bus->mdio_lock);
309 }
310
311 static inline void
312 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
313 {
314 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
315 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
316 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
317 }
318
319 void
320 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
321 {
322 struct mii_bus *bus = priv->mii_bus;
323
324 mutex_lock(&bus->mdio_lock);
325 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
326 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
327 mutex_unlock(&bus->mdio_lock);
328 }
329
330 u16
331 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
332 {
333 struct mii_bus *bus = priv->mii_bus;
334 u16 data;
335
336 mutex_lock(&bus->mdio_lock);
337 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
338 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
339 mutex_unlock(&bus->mdio_lock);
340
341 return data;
342 }
343
344 static int
345 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
346 unsigned timeout)
347 {
348 int i;
349
350 for (i = 0; i < timeout; i++) {
351 u32 t;
352
353 t = ar8xxx_read(priv, reg);
354 if ((t & mask) == val)
355 return 0;
356
357 usleep_range(1000, 2000);
358 }
359
360 return -ETIMEDOUT;
361 }
362
363 static int
364 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
365 {
366 unsigned mib_func = priv->chip->mib_func;
367 int ret;
368
369 lockdep_assert_held(&priv->mib_lock);
370
371 /* Capture the hardware statistics for all ports */
372 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
373
374 /* Wait for the capturing to complete. */
375 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
376 if (ret)
377 goto out;
378
379 ret = 0;
380
381 out:
382 return ret;
383 }
384
385 static int
386 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
387 {
388 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
389 }
390
391 static int
392 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
393 {
394 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
395 }
396
397 static void
398 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
399 {
400 unsigned int base;
401 u64 *mib_stats;
402 int i;
403
404 WARN_ON(port >= priv->dev.ports);
405
406 lockdep_assert_held(&priv->mib_lock);
407
408 base = priv->chip->reg_port_stats_start +
409 priv->chip->reg_port_stats_length * port;
410
411 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
412 for (i = 0; i < priv->chip->num_mibs; i++) {
413 const struct ar8xxx_mib_desc *mib;
414 u64 t;
415
416 mib = &priv->chip->mib_decs[i];
417 t = ar8xxx_read(priv, base + mib->offset);
418 if (mib->size == 2) {
419 u64 hi;
420
421 hi = ar8xxx_read(priv, base + mib->offset + 4);
422 t |= hi << 32;
423 }
424
425 if (flush)
426 mib_stats[i] = 0;
427 else
428 mib_stats[i] += t;
429 }
430 }
431
432 static void
433 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
434 struct switch_port_link *link)
435 {
436 u32 status;
437 u32 speed;
438
439 memset(link, '\0', sizeof(*link));
440
441 status = priv->chip->read_port_status(priv, port);
442
443 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
444 if (link->aneg) {
445 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
446 } else {
447 link->link = true;
448
449 if (priv->get_port_link) {
450 int err;
451
452 err = priv->get_port_link(port);
453 if (err >= 0)
454 link->link = !!err;
455 }
456 }
457
458 if (!link->link)
459 return;
460
461 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
462 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
463 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
464
465 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
466 link->eee = priv->chip->read_port_eee_status(priv, port);
467
468 speed = (status & AR8216_PORT_STATUS_SPEED) >>
469 AR8216_PORT_STATUS_SPEED_S;
470
471 switch (speed) {
472 case AR8216_PORT_SPEED_10M:
473 link->speed = SWITCH_PORT_SPEED_10;
474 break;
475 case AR8216_PORT_SPEED_100M:
476 link->speed = SWITCH_PORT_SPEED_100;
477 break;
478 case AR8216_PORT_SPEED_1000M:
479 link->speed = SWITCH_PORT_SPEED_1000;
480 break;
481 default:
482 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
483 break;
484 }
485 }
486
487 static struct sk_buff *
488 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
489 {
490 struct ar8xxx_priv *priv = dev->phy_ptr;
491 unsigned char *buf;
492
493 if (unlikely(!priv))
494 goto error;
495
496 if (!priv->vlan)
497 goto send;
498
499 if (unlikely(skb_headroom(skb) < 2)) {
500 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
501 goto error;
502 }
503
504 buf = skb_push(skb, 2);
505 buf[0] = 0x10;
506 buf[1] = 0x80;
507
508 send:
509 return skb;
510
511 error:
512 dev_kfree_skb_any(skb);
513 return NULL;
514 }
515
516 static void
517 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
518 {
519 struct ar8xxx_priv *priv;
520 unsigned char *buf;
521 int port, vlan;
522
523 priv = dev->phy_ptr;
524 if (!priv)
525 return;
526
527 /* don't strip the header if vlan mode is disabled */
528 if (!priv->vlan)
529 return;
530
531 /* strip header, get vlan id */
532 buf = skb->data;
533 skb_pull(skb, 2);
534
535 /* check for vlan header presence */
536 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
537 return;
538
539 port = buf[0] & 0x7;
540
541 /* no need to fix up packets coming from a tagged source */
542 if (priv->vlan_tagged & (1 << port))
543 return;
544
545 /* lookup port vid from local table, the switch passes an invalid vlan id */
546 vlan = priv->vlan_id[priv->pvid[port]];
547
548 buf[14 + 2] &= 0xf0;
549 buf[14 + 2] |= vlan >> 8;
550 buf[15 + 2] = vlan & 0xff;
551 }
552
553 int
554 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
555 {
556 int timeout = 20;
557 u32 t = 0;
558
559 while (1) {
560 t = ar8xxx_read(priv, reg);
561 if ((t & mask) == val)
562 return 0;
563
564 if (timeout-- <= 0)
565 break;
566
567 udelay(10);
568 }
569
570 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
571 (unsigned int) reg, t, mask, val);
572 return -ETIMEDOUT;
573 }
574
575 static void
576 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
577 {
578 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
579 return;
580 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
581 val &= AR8216_VTUDATA_MEMBER;
582 val |= AR8216_VTUDATA_VALID;
583 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
584 }
585 op |= AR8216_VTU_ACTIVE;
586 ar8xxx_write(priv, AR8216_REG_VTU, op);
587 }
588
589 static void
590 ar8216_vtu_flush(struct ar8xxx_priv *priv)
591 {
592 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
593 }
594
595 static void
596 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
597 {
598 u32 op;
599
600 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
601 ar8216_vtu_op(priv, op, port_mask);
602 }
603
604 static int
605 ar8216_atu_flush(struct ar8xxx_priv *priv)
606 {
607 int ret;
608
609 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
610 if (!ret)
611 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
612 AR8216_ATU_ACTIVE);
613
614 return ret;
615 }
616
617 static int
618 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
619 {
620 u32 t;
621 int ret;
622
623 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
624 if (!ret) {
625 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
626 t |= AR8216_ATU_ACTIVE;
627 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
628 }
629
630 return ret;
631 }
632
633 static u32
634 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
635 {
636 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
637 }
638
639 static void
640 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
641 {
642 u32 header;
643 u32 egress, ingress;
644 u32 pvid;
645
646 if (priv->vlan) {
647 pvid = priv->vlan_id[priv->pvid[port]];
648 if (priv->vlan_tagged & (1 << port))
649 egress = AR8216_OUT_ADD_VLAN;
650 else
651 egress = AR8216_OUT_STRIP_VLAN;
652 ingress = AR8216_IN_SECURE;
653 } else {
654 pvid = port;
655 egress = AR8216_OUT_KEEP;
656 ingress = AR8216_IN_PORT_ONLY;
657 }
658
659 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
660 header = AR8216_PORT_CTRL_HEADER;
661 else
662 header = 0;
663
664 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
665 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
666 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
667 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
668 AR8216_PORT_CTRL_LEARN | header |
669 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
670 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
671
672 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
673 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
674 AR8216_PORT_VLAN_DEFAULT_ID,
675 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
676 (ingress << AR8216_PORT_VLAN_MODE_S) |
677 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
678 }
679
680 static int
681 ar8216_hw_init(struct ar8xxx_priv *priv)
682 {
683 if (priv->initialized)
684 return 0;
685
686 ar8xxx_phy_init(priv);
687
688 priv->initialized = true;
689 return 0;
690 }
691
692 static void
693 ar8216_init_globals(struct ar8xxx_priv *priv)
694 {
695 /* standard atheros magic */
696 ar8xxx_write(priv, 0x38, 0xc000050e);
697
698 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
699 AR8216_GCTRL_MTU, 1518 + 8 + 2);
700 }
701
702 static void
703 ar8216_init_port(struct ar8xxx_priv *priv, int port)
704 {
705 /* Enable port learning and tx */
706 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
707 AR8216_PORT_CTRL_LEARN |
708 (4 << AR8216_PORT_CTRL_STATE_S));
709
710 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
711
712 if (port == AR8216_PORT_CPU) {
713 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
714 AR8216_PORT_STATUS_LINK_UP |
715 (ar8xxx_has_gige(priv) ?
716 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
717 AR8216_PORT_STATUS_TXMAC |
718 AR8216_PORT_STATUS_RXMAC |
719 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
720 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
721 AR8216_PORT_STATUS_DUPLEX);
722 } else {
723 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
724 AR8216_PORT_STATUS_LINK_AUTO);
725 }
726 }
727
728 static void
729 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
730 {
731 int timeout = 20;
732
733 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout)
734 udelay(10);
735
736 if (!timeout)
737 pr_err("ar8216: timeout waiting for atu to become ready\n");
738 }
739
740 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
741 struct arl_entry *a, u32 *status, enum arl_op op)
742 {
743 struct mii_bus *bus = priv->mii_bus;
744 u16 r2, page;
745 u16 r1_func0, r1_func1, r1_func2;
746 u32 t, val0, val1, val2;
747 int i;
748
749 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
750 r2 |= 0x10;
751
752 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
753 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
754
755 switch (op) {
756 case AR8XXX_ARL_INITIALIZE:
757 /* all ATU registers are on the same page
758 * therefore set page only once
759 */
760 bus->write(bus, 0x18, 0, page);
761 wait_for_page_switch();
762
763 ar8216_wait_atu_ready(priv, r2, r1_func0);
764
765 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
766 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
767 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
768 break;
769 case AR8XXX_ARL_GET_NEXT:
770 t = ar8xxx_mii_read32(priv, r2, r1_func0);
771 t |= AR8216_ATU_ACTIVE;
772 ar8xxx_mii_write32(priv, r2, r1_func0, t);
773 ar8216_wait_atu_ready(priv, r2, r1_func0);
774
775 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
776 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
777 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
778
779 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
780 if (!*status)
781 break;
782
783 i = 0;
784 t = AR8216_ATU_PORT0;
785 while (!(val2 & t) && ++i < priv->dev.ports)
786 t <<= 1;
787
788 a->port = i;
789 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
790 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
791 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
792 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
793 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
794 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
795 break;
796 }
797 }
798
799 static void
800 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
801 {
802 u32 egress, ingress;
803 u32 pvid;
804
805 if (priv->vlan) {
806 pvid = priv->vlan_id[priv->pvid[port]];
807 if (priv->vlan_tagged & (1 << port))
808 egress = AR8216_OUT_ADD_VLAN;
809 else
810 egress = AR8216_OUT_STRIP_VLAN;
811 ingress = AR8216_IN_SECURE;
812 } else {
813 pvid = port;
814 egress = AR8216_OUT_KEEP;
815 ingress = AR8216_IN_PORT_ONLY;
816 }
817
818 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
819 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
820 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
821 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
822 AR8216_PORT_CTRL_LEARN |
823 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
824 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
825
826 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
827 AR8236_PORT_VLAN_DEFAULT_ID,
828 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
829
830 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
831 AR8236_PORT_VLAN2_VLAN_MODE |
832 AR8236_PORT_VLAN2_MEMBER,
833 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
834 (members << AR8236_PORT_VLAN2_MEMBER_S));
835 }
836
837 static void
838 ar8236_init_globals(struct ar8xxx_priv *priv)
839 {
840 /* enable jumbo frames */
841 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
842 AR8316_GCTRL_MTU, 9018 + 8 + 2);
843
844 /* enable cpu port to receive arp frames */
845 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
846 AR8236_ATU_CTRL_RES);
847
848 /* enable cpu port to receive multicast and broadcast frames */
849 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
850 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
851
852 /* Enable MIB counters */
853 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
854 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
855 AR8236_MIB_EN);
856 }
857
858 static int
859 ar8316_hw_init(struct ar8xxx_priv *priv)
860 {
861 u32 val, newval;
862
863 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
864
865 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
866 if (priv->port4_phy) {
867 /* value taken from Ubiquiti RouterStation Pro */
868 newval = 0x81461bea;
869 pr_info("ar8316: Using port 4 as PHY\n");
870 } else {
871 newval = 0x01261be2;
872 pr_info("ar8316: Using port 4 as switch port\n");
873 }
874 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
875 /* value taken from AVM Fritz!Box 7390 sources */
876 newval = 0x010e5b71;
877 } else {
878 /* no known value for phy interface */
879 pr_err("ar8316: unsupported mii mode: %d.\n",
880 priv->phy->interface);
881 return -EINVAL;
882 }
883
884 if (val == newval)
885 goto out;
886
887 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
888
889 if (priv->port4_phy &&
890 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
891 /* work around for phy4 rgmii mode */
892 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
893 /* rx delay */
894 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
895 /* tx delay */
896 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
897 msleep(1000);
898 }
899
900 ar8xxx_phy_init(priv);
901
902 out:
903 priv->initialized = true;
904 return 0;
905 }
906
907 static void
908 ar8316_init_globals(struct ar8xxx_priv *priv)
909 {
910 /* standard atheros magic */
911 ar8xxx_write(priv, 0x38, 0xc000050e);
912
913 /* enable cpu port to receive multicast and broadcast frames */
914 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
915
916 /* enable jumbo frames */
917 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
918 AR8316_GCTRL_MTU, 9018 + 8 + 2);
919
920 /* Enable MIB counters */
921 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
922 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
923 AR8236_MIB_EN);
924 }
925
926 int
927 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
928 struct switch_val *val)
929 {
930 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
931 priv->vlan = !!val->value.i;
932 return 0;
933 }
934
935 int
936 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
937 struct switch_val *val)
938 {
939 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
940 val->value.i = priv->vlan;
941 return 0;
942 }
943
944
945 int
946 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
947 {
948 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
949
950 /* make sure no invalid PVIDs get set */
951
952 if (vlan < 0 || vlan >= dev->vlans ||
953 port < 0 || port >= AR8X16_MAX_PORTS)
954 return -EINVAL;
955
956 priv->pvid[port] = vlan;
957 return 0;
958 }
959
960 int
961 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
962 {
963 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
964
965 if (port < 0 || port >= AR8X16_MAX_PORTS)
966 return -EINVAL;
967
968 *vlan = priv->pvid[port];
969 return 0;
970 }
971
972 static int
973 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
974 struct switch_val *val)
975 {
976 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
977
978 if (val->port_vlan >= AR8X16_MAX_VLANS)
979 return -EINVAL;
980
981 priv->vlan_id[val->port_vlan] = val->value.i;
982 return 0;
983 }
984
985 static int
986 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
987 struct switch_val *val)
988 {
989 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
990 val->value.i = priv->vlan_id[val->port_vlan];
991 return 0;
992 }
993
994 int
995 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
996 struct switch_port_link *link)
997 {
998 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
999
1000 ar8216_read_port_link(priv, port, link);
1001 return 0;
1002 }
1003
1004 static int
1005 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1006 {
1007 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1008 u8 ports;
1009 int i;
1010
1011 if (val->port_vlan >= AR8X16_MAX_VLANS)
1012 return -EINVAL;
1013
1014 ports = priv->vlan_table[val->port_vlan];
1015 val->len = 0;
1016 for (i = 0; i < dev->ports; i++) {
1017 struct switch_port *p;
1018
1019 if (!(ports & (1 << i)))
1020 continue;
1021
1022 p = &val->value.ports[val->len++];
1023 p->id = i;
1024 if (priv->vlan_tagged & (1 << i))
1025 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1026 else
1027 p->flags = 0;
1028 }
1029 return 0;
1030 }
1031
1032 static int
1033 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1034 {
1035 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1036 u8 *vt = &priv->vlan_table[val->port_vlan];
1037 int i, j;
1038
1039 *vt = 0;
1040 for (i = 0; i < val->len; i++) {
1041 struct switch_port *p = &val->value.ports[i];
1042
1043 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1044 priv->vlan_tagged |= (1 << p->id);
1045 } else {
1046 priv->vlan_tagged &= ~(1 << p->id);
1047 priv->pvid[p->id] = val->port_vlan;
1048
1049 /* make sure that an untagged port does not
1050 * appear in other vlans */
1051 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1052 if (j == val->port_vlan)
1053 continue;
1054 priv->vlan_table[j] &= ~(1 << p->id);
1055 }
1056 }
1057
1058 *vt |= 1 << p->id;
1059 }
1060 return 0;
1061 }
1062
1063 static void
1064 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1065 {
1066 int port;
1067
1068 /* reset all mirror registers */
1069 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1070 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1071 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1072 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1073 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1074 AR8216_PORT_CTRL_MIRROR_RX);
1075
1076 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1077 AR8216_PORT_CTRL_MIRROR_TX);
1078 }
1079
1080 /* now enable mirroring if necessary */
1081 if (priv->source_port >= AR8216_NUM_PORTS ||
1082 priv->monitor_port >= AR8216_NUM_PORTS ||
1083 priv->source_port == priv->monitor_port) {
1084 return;
1085 }
1086
1087 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1088 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1089 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1090
1091 if (priv->mirror_rx)
1092 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1093 AR8216_PORT_CTRL_MIRROR_RX);
1094
1095 if (priv->mirror_tx)
1096 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1097 AR8216_PORT_CTRL_MIRROR_TX);
1098 }
1099
1100 static inline u32
1101 ar8xxx_age_time_val(int age_time)
1102 {
1103 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1104 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1105 }
1106
1107 static inline void
1108 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1109 {
1110 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1111 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1112 }
1113
1114 int
1115 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1116 {
1117 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1118 const struct ar8xxx_chip *chip = priv->chip;
1119 u8 portmask[AR8X16_MAX_PORTS];
1120 int i, j;
1121
1122 mutex_lock(&priv->reg_mutex);
1123 /* flush all vlan translation unit entries */
1124 priv->chip->vtu_flush(priv);
1125
1126 memset(portmask, 0, sizeof(portmask));
1127 if (!priv->init) {
1128 /* calculate the port destination masks and load vlans
1129 * into the vlan translation unit */
1130 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1131 u8 vp = priv->vlan_table[j];
1132
1133 if (!vp)
1134 continue;
1135
1136 for (i = 0; i < dev->ports; i++) {
1137 u8 mask = (1 << i);
1138 if (vp & mask)
1139 portmask[i] |= vp & ~mask;
1140 }
1141
1142 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1143 priv->vlan_table[j]);
1144 }
1145 } else {
1146 /* vlan disabled:
1147 * isolate all ports, but connect them to the cpu port */
1148 for (i = 0; i < dev->ports; i++) {
1149 if (i == AR8216_PORT_CPU)
1150 continue;
1151
1152 portmask[i] = 1 << AR8216_PORT_CPU;
1153 portmask[AR8216_PORT_CPU] |= (1 << i);
1154 }
1155 }
1156
1157 /* update the port destination mask registers and tag settings */
1158 for (i = 0; i < dev->ports; i++) {
1159 chip->setup_port(priv, i, portmask[i]);
1160 }
1161
1162 chip->set_mirror_regs(priv);
1163
1164 /* set age time */
1165 if (chip->reg_arl_ctrl)
1166 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1167
1168 mutex_unlock(&priv->reg_mutex);
1169 return 0;
1170 }
1171
1172 int
1173 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1174 {
1175 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1176 const struct ar8xxx_chip *chip = priv->chip;
1177 int i;
1178
1179 mutex_lock(&priv->reg_mutex);
1180 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1181 offsetof(struct ar8xxx_priv, vlan));
1182
1183 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1184 priv->vlan_id[i] = i;
1185
1186 /* Configure all ports */
1187 for (i = 0; i < dev->ports; i++)
1188 chip->init_port(priv, i);
1189
1190 priv->mirror_rx = false;
1191 priv->mirror_tx = false;
1192 priv->source_port = 0;
1193 priv->monitor_port = 0;
1194 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1195
1196 chip->init_globals(priv);
1197
1198 mutex_unlock(&priv->reg_mutex);
1199
1200 return chip->sw_hw_apply(dev);
1201 }
1202
1203 int
1204 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1205 const struct switch_attr *attr,
1206 struct switch_val *val)
1207 {
1208 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1209 unsigned int len;
1210 int ret;
1211
1212 if (!ar8xxx_has_mib_counters(priv))
1213 return -EOPNOTSUPP;
1214
1215 mutex_lock(&priv->mib_lock);
1216
1217 len = priv->dev.ports * priv->chip->num_mibs *
1218 sizeof(*priv->mib_stats);
1219 memset(priv->mib_stats, '\0', len);
1220 ret = ar8xxx_mib_flush(priv);
1221 if (ret)
1222 goto unlock;
1223
1224 ret = 0;
1225
1226 unlock:
1227 mutex_unlock(&priv->mib_lock);
1228 return ret;
1229 }
1230
1231 int
1232 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1233 const struct switch_attr *attr,
1234 struct switch_val *val)
1235 {
1236 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1237
1238 mutex_lock(&priv->reg_mutex);
1239 priv->mirror_rx = !!val->value.i;
1240 priv->chip->set_mirror_regs(priv);
1241 mutex_unlock(&priv->reg_mutex);
1242
1243 return 0;
1244 }
1245
1246 int
1247 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1248 const struct switch_attr *attr,
1249 struct switch_val *val)
1250 {
1251 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1252 val->value.i = priv->mirror_rx;
1253 return 0;
1254 }
1255
1256 int
1257 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1258 const struct switch_attr *attr,
1259 struct switch_val *val)
1260 {
1261 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1262
1263 mutex_lock(&priv->reg_mutex);
1264 priv->mirror_tx = !!val->value.i;
1265 priv->chip->set_mirror_regs(priv);
1266 mutex_unlock(&priv->reg_mutex);
1267
1268 return 0;
1269 }
1270
1271 int
1272 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1273 const struct switch_attr *attr,
1274 struct switch_val *val)
1275 {
1276 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1277 val->value.i = priv->mirror_tx;
1278 return 0;
1279 }
1280
1281 int
1282 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1283 const struct switch_attr *attr,
1284 struct switch_val *val)
1285 {
1286 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1287
1288 mutex_lock(&priv->reg_mutex);
1289 priv->monitor_port = val->value.i;
1290 priv->chip->set_mirror_regs(priv);
1291 mutex_unlock(&priv->reg_mutex);
1292
1293 return 0;
1294 }
1295
1296 int
1297 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1298 const struct switch_attr *attr,
1299 struct switch_val *val)
1300 {
1301 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1302 val->value.i = priv->monitor_port;
1303 return 0;
1304 }
1305
1306 int
1307 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1308 const struct switch_attr *attr,
1309 struct switch_val *val)
1310 {
1311 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1312
1313 mutex_lock(&priv->reg_mutex);
1314 priv->source_port = val->value.i;
1315 priv->chip->set_mirror_regs(priv);
1316 mutex_unlock(&priv->reg_mutex);
1317
1318 return 0;
1319 }
1320
1321 int
1322 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1323 const struct switch_attr *attr,
1324 struct switch_val *val)
1325 {
1326 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1327 val->value.i = priv->source_port;
1328 return 0;
1329 }
1330
1331 int
1332 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1333 const struct switch_attr *attr,
1334 struct switch_val *val)
1335 {
1336 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1337 int port;
1338 int ret;
1339
1340 if (!ar8xxx_has_mib_counters(priv))
1341 return -EOPNOTSUPP;
1342
1343 port = val->port_vlan;
1344 if (port >= dev->ports)
1345 return -EINVAL;
1346
1347 mutex_lock(&priv->mib_lock);
1348 ret = ar8xxx_mib_capture(priv);
1349 if (ret)
1350 goto unlock;
1351
1352 ar8xxx_mib_fetch_port_stat(priv, port, true);
1353
1354 ret = 0;
1355
1356 unlock:
1357 mutex_unlock(&priv->mib_lock);
1358 return ret;
1359 }
1360
1361 static void
1362 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1363 {
1364 unsigned long b;
1365 const char *unit;
1366
1367 if (byte >= 0x40000000) { /* 1 GiB */
1368 b = byte * 10 / 0x40000000;
1369 unit = "GiB";
1370 } else if (byte >= 0x100000) { /* 1 MiB */
1371 b = byte * 10 / 0x100000;
1372 unit = "MiB";
1373 } else if (byte >= 0x400) { /* 1 KiB */
1374 b = byte * 10 / 0x400;
1375 unit = "KiB";
1376 } else {
1377 b = byte;
1378 unit = "Byte";
1379 }
1380 if (strcmp(unit, "Byte"))
1381 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1382 else
1383 snprintf(buf, len, "%lu %s", b, unit);
1384 }
1385
1386 int
1387 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1388 const struct switch_attr *attr,
1389 struct switch_val *val)
1390 {
1391 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1392 const struct ar8xxx_chip *chip = priv->chip;
1393 u64 *mib_stats, mib_data;
1394 unsigned int port;
1395 int ret;
1396 char *buf = priv->buf;
1397 char buf1[64];
1398 const char *mib_name;
1399 int i, len = 0;
1400 bool mib_stats_empty = true;
1401
1402 if (!ar8xxx_has_mib_counters(priv))
1403 return -EOPNOTSUPP;
1404
1405 port = val->port_vlan;
1406 if (port >= dev->ports)
1407 return -EINVAL;
1408
1409 mutex_lock(&priv->mib_lock);
1410 ret = ar8xxx_mib_capture(priv);
1411 if (ret)
1412 goto unlock;
1413
1414 ar8xxx_mib_fetch_port_stat(priv, port, false);
1415
1416 len += snprintf(buf + len, sizeof(priv->buf) - len,
1417 "MIB counters\n");
1418
1419 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1420 for (i = 0; i < chip->num_mibs; i++) {
1421 mib_name = chip->mib_decs[i].name;
1422 mib_data = mib_stats[i];
1423 len += snprintf(buf + len, sizeof(priv->buf) - len,
1424 "%-12s: %llu\n", mib_name, mib_data);
1425 if ((!strcmp(mib_name, "TxByte") ||
1426 !strcmp(mib_name, "RxGoodByte")) &&
1427 mib_data >= 1024) {
1428 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1429 --len; /* discard newline at the end of buf */
1430 len += snprintf(buf + len, sizeof(priv->buf) - len,
1431 " (%s)\n", buf1);
1432 }
1433 if (mib_stats_empty && mib_data)
1434 mib_stats_empty = false;
1435 }
1436
1437 if (mib_stats_empty)
1438 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1439
1440 val->value.s = buf;
1441 val->len = len;
1442
1443 ret = 0;
1444
1445 unlock:
1446 mutex_unlock(&priv->mib_lock);
1447 return ret;
1448 }
1449
1450 int
1451 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1452 struct switch_val *val)
1453 {
1454 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1455 int age_time = val->value.i;
1456 u32 age_time_val;
1457
1458 if (age_time < 0)
1459 return -EINVAL;
1460
1461 age_time_val = ar8xxx_age_time_val(age_time);
1462 if (age_time_val == 0 || age_time_val > 0xffff)
1463 return -EINVAL;
1464
1465 priv->arl_age_time = age_time;
1466 return 0;
1467 }
1468
1469 int
1470 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1471 struct switch_val *val)
1472 {
1473 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1474 val->value.i = priv->arl_age_time;
1475 return 0;
1476 }
1477
1478 int
1479 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1480 const struct switch_attr *attr,
1481 struct switch_val *val)
1482 {
1483 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1484 struct mii_bus *bus = priv->mii_bus;
1485 const struct ar8xxx_chip *chip = priv->chip;
1486 char *buf = priv->arl_buf;
1487 int i, j, k, len = 0;
1488 struct arl_entry *a, *a1;
1489 u32 status;
1490
1491 if (!chip->get_arl_entry)
1492 return -EOPNOTSUPP;
1493
1494 mutex_lock(&priv->reg_mutex);
1495 mutex_lock(&bus->mdio_lock);
1496
1497 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1498
1499 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1500 a = &priv->arl_table[i];
1501 duplicate:
1502 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1503
1504 if (!status)
1505 break;
1506
1507 /* avoid duplicates
1508 * ARL table can include multiple valid entries
1509 * per MAC, just with differing status codes
1510 */
1511 for (j = 0; j < i; ++j) {
1512 a1 = &priv->arl_table[j];
1513 if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1514 goto duplicate;
1515 }
1516 }
1517
1518 mutex_unlock(&bus->mdio_lock);
1519
1520 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1521 "address resolution table\n");
1522
1523 if (i == AR8XXX_NUM_ARL_RECORDS)
1524 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1525 "Too many entries found, displaying the first %d only!\n",
1526 AR8XXX_NUM_ARL_RECORDS);
1527
1528 for (j = 0; j < priv->dev.ports; ++j) {
1529 for (k = 0; k < i; ++k) {
1530 a = &priv->arl_table[k];
1531 if (a->port != j)
1532 continue;
1533 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1534 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1535 j,
1536 a->mac[5], a->mac[4], a->mac[3],
1537 a->mac[2], a->mac[1], a->mac[0]);
1538 }
1539 }
1540
1541 val->value.s = buf;
1542 val->len = len;
1543
1544 mutex_unlock(&priv->reg_mutex);
1545
1546 return 0;
1547 }
1548
1549 int
1550 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1551 const struct switch_attr *attr,
1552 struct switch_val *val)
1553 {
1554 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1555 int ret;
1556
1557 mutex_lock(&priv->reg_mutex);
1558 ret = priv->chip->atu_flush(priv);
1559 mutex_unlock(&priv->reg_mutex);
1560
1561 return ret;
1562 }
1563
1564 int
1565 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1566 const struct switch_attr *attr,
1567 struct switch_val *val)
1568 {
1569 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1570 int port, ret;
1571
1572 port = val->port_vlan;
1573 if (port >= dev->ports)
1574 return -EINVAL;
1575
1576 mutex_lock(&priv->reg_mutex);
1577 ret = priv->chip->atu_flush_port(priv, port);
1578 mutex_unlock(&priv->reg_mutex);
1579
1580 return ret;
1581 }
1582
1583 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1584 {
1585 .type = SWITCH_TYPE_INT,
1586 .name = "enable_vlan",
1587 .description = "Enable VLAN mode",
1588 .set = ar8xxx_sw_set_vlan,
1589 .get = ar8xxx_sw_get_vlan,
1590 .max = 1
1591 },
1592 {
1593 .type = SWITCH_TYPE_NOVAL,
1594 .name = "reset_mibs",
1595 .description = "Reset all MIB counters",
1596 .set = ar8xxx_sw_set_reset_mibs,
1597 },
1598 {
1599 .type = SWITCH_TYPE_INT,
1600 .name = "enable_mirror_rx",
1601 .description = "Enable mirroring of RX packets",
1602 .set = ar8xxx_sw_set_mirror_rx_enable,
1603 .get = ar8xxx_sw_get_mirror_rx_enable,
1604 .max = 1
1605 },
1606 {
1607 .type = SWITCH_TYPE_INT,
1608 .name = "enable_mirror_tx",
1609 .description = "Enable mirroring of TX packets",
1610 .set = ar8xxx_sw_set_mirror_tx_enable,
1611 .get = ar8xxx_sw_get_mirror_tx_enable,
1612 .max = 1
1613 },
1614 {
1615 .type = SWITCH_TYPE_INT,
1616 .name = "mirror_monitor_port",
1617 .description = "Mirror monitor port",
1618 .set = ar8xxx_sw_set_mirror_monitor_port,
1619 .get = ar8xxx_sw_get_mirror_monitor_port,
1620 .max = AR8216_NUM_PORTS - 1
1621 },
1622 {
1623 .type = SWITCH_TYPE_INT,
1624 .name = "mirror_source_port",
1625 .description = "Mirror source port",
1626 .set = ar8xxx_sw_set_mirror_source_port,
1627 .get = ar8xxx_sw_get_mirror_source_port,
1628 .max = AR8216_NUM_PORTS - 1
1629 },
1630 {
1631 .type = SWITCH_TYPE_STRING,
1632 .name = "arl_table",
1633 .description = "Get ARL table",
1634 .set = NULL,
1635 .get = ar8xxx_sw_get_arl_table,
1636 },
1637 {
1638 .type = SWITCH_TYPE_NOVAL,
1639 .name = "flush_arl_table",
1640 .description = "Flush ARL table",
1641 .set = ar8xxx_sw_set_flush_arl_table,
1642 },
1643 };
1644
1645 const struct switch_attr ar8xxx_sw_attr_port[] = {
1646 {
1647 .type = SWITCH_TYPE_NOVAL,
1648 .name = "reset_mib",
1649 .description = "Reset single port MIB counters",
1650 .set = ar8xxx_sw_set_port_reset_mib,
1651 },
1652 {
1653 .type = SWITCH_TYPE_STRING,
1654 .name = "mib",
1655 .description = "Get port's MIB counters",
1656 .set = NULL,
1657 .get = ar8xxx_sw_get_port_mib,
1658 },
1659 {
1660 .type = SWITCH_TYPE_NOVAL,
1661 .name = "flush_arl_table",
1662 .description = "Flush port's ARL table entries",
1663 .set = ar8xxx_sw_set_flush_port_arl_table,
1664 },
1665 };
1666
1667 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1668 {
1669 .type = SWITCH_TYPE_INT,
1670 .name = "vid",
1671 .description = "VLAN ID (0-4094)",
1672 .set = ar8xxx_sw_set_vid,
1673 .get = ar8xxx_sw_get_vid,
1674 .max = 4094,
1675 },
1676 };
1677
1678 static const struct switch_dev_ops ar8xxx_sw_ops = {
1679 .attr_global = {
1680 .attr = ar8xxx_sw_attr_globals,
1681 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1682 },
1683 .attr_port = {
1684 .attr = ar8xxx_sw_attr_port,
1685 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1686 },
1687 .attr_vlan = {
1688 .attr = ar8xxx_sw_attr_vlan,
1689 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1690 },
1691 .get_port_pvid = ar8xxx_sw_get_pvid,
1692 .set_port_pvid = ar8xxx_sw_set_pvid,
1693 .get_vlan_ports = ar8xxx_sw_get_ports,
1694 .set_vlan_ports = ar8xxx_sw_set_ports,
1695 .apply_config = ar8xxx_sw_hw_apply,
1696 .reset_switch = ar8xxx_sw_reset_switch,
1697 .get_port_link = ar8xxx_sw_get_port_link,
1698 };
1699
1700 static const struct ar8xxx_chip ar8216_chip = {
1701 .caps = AR8XXX_CAP_MIB_COUNTERS,
1702
1703 .reg_port_stats_start = 0x19000,
1704 .reg_port_stats_length = 0xa0,
1705 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1706
1707 .name = "Atheros AR8216",
1708 .ports = AR8216_NUM_PORTS,
1709 .vlans = AR8216_NUM_VLANS,
1710 .swops = &ar8xxx_sw_ops,
1711
1712 .hw_init = ar8216_hw_init,
1713 .init_globals = ar8216_init_globals,
1714 .init_port = ar8216_init_port,
1715 .setup_port = ar8216_setup_port,
1716 .read_port_status = ar8216_read_port_status,
1717 .atu_flush = ar8216_atu_flush,
1718 .atu_flush_port = ar8216_atu_flush_port,
1719 .vtu_flush = ar8216_vtu_flush,
1720 .vtu_load_vlan = ar8216_vtu_load_vlan,
1721 .set_mirror_regs = ar8216_set_mirror_regs,
1722 .get_arl_entry = ar8216_get_arl_entry,
1723 .sw_hw_apply = ar8xxx_sw_hw_apply,
1724
1725 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1726 .mib_decs = ar8216_mibs,
1727 .mib_func = AR8216_REG_MIB_FUNC
1728 };
1729
1730 static const struct ar8xxx_chip ar8236_chip = {
1731 .caps = AR8XXX_CAP_MIB_COUNTERS,
1732
1733 .reg_port_stats_start = 0x20000,
1734 .reg_port_stats_length = 0x100,
1735 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1736
1737 .name = "Atheros AR8236",
1738 .ports = AR8216_NUM_PORTS,
1739 .vlans = AR8216_NUM_VLANS,
1740 .swops = &ar8xxx_sw_ops,
1741
1742 .hw_init = ar8216_hw_init,
1743 .init_globals = ar8236_init_globals,
1744 .init_port = ar8216_init_port,
1745 .setup_port = ar8236_setup_port,
1746 .read_port_status = ar8216_read_port_status,
1747 .atu_flush = ar8216_atu_flush,
1748 .atu_flush_port = ar8216_atu_flush_port,
1749 .vtu_flush = ar8216_vtu_flush,
1750 .vtu_load_vlan = ar8216_vtu_load_vlan,
1751 .set_mirror_regs = ar8216_set_mirror_regs,
1752 .get_arl_entry = ar8216_get_arl_entry,
1753 .sw_hw_apply = ar8xxx_sw_hw_apply,
1754
1755 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1756 .mib_decs = ar8236_mibs,
1757 .mib_func = AR8216_REG_MIB_FUNC
1758 };
1759
1760 static const struct ar8xxx_chip ar8316_chip = {
1761 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1762
1763 .reg_port_stats_start = 0x20000,
1764 .reg_port_stats_length = 0x100,
1765 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
1766
1767 .name = "Atheros AR8316",
1768 .ports = AR8216_NUM_PORTS,
1769 .vlans = AR8X16_MAX_VLANS,
1770 .swops = &ar8xxx_sw_ops,
1771
1772 .hw_init = ar8316_hw_init,
1773 .init_globals = ar8316_init_globals,
1774 .init_port = ar8216_init_port,
1775 .setup_port = ar8216_setup_port,
1776 .read_port_status = ar8216_read_port_status,
1777 .atu_flush = ar8216_atu_flush,
1778 .atu_flush_port = ar8216_atu_flush_port,
1779 .vtu_flush = ar8216_vtu_flush,
1780 .vtu_load_vlan = ar8216_vtu_load_vlan,
1781 .set_mirror_regs = ar8216_set_mirror_regs,
1782 .get_arl_entry = ar8216_get_arl_entry,
1783 .sw_hw_apply = ar8xxx_sw_hw_apply,
1784
1785 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1786 .mib_decs = ar8236_mibs,
1787 .mib_func = AR8216_REG_MIB_FUNC
1788 };
1789
1790 static int
1791 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1792 {
1793 u32 val;
1794 u16 id;
1795 int i;
1796
1797 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1798 if (val == ~0)
1799 return -ENODEV;
1800
1801 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1802 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1803 u16 t;
1804
1805 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1806 if (val == ~0)
1807 return -ENODEV;
1808
1809 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1810 if (t != id)
1811 return -ENODEV;
1812 }
1813
1814 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1815 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1816
1817 switch (priv->chip_ver) {
1818 case AR8XXX_VER_AR8216:
1819 priv->chip = &ar8216_chip;
1820 break;
1821 case AR8XXX_VER_AR8236:
1822 priv->chip = &ar8236_chip;
1823 break;
1824 case AR8XXX_VER_AR8316:
1825 priv->chip = &ar8316_chip;
1826 break;
1827 case AR8XXX_VER_AR8327:
1828 priv->chip = &ar8327_chip;
1829 break;
1830 case AR8XXX_VER_AR8337:
1831 priv->chip = &ar8337_chip;
1832 break;
1833 default:
1834 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1835 priv->chip_ver, priv->chip_rev);
1836
1837 return -ENODEV;
1838 }
1839
1840 return 0;
1841 }
1842
1843 static void
1844 ar8xxx_mib_work_func(struct work_struct *work)
1845 {
1846 struct ar8xxx_priv *priv;
1847 int err;
1848
1849 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1850
1851 mutex_lock(&priv->mib_lock);
1852
1853 err = ar8xxx_mib_capture(priv);
1854 if (err)
1855 goto next_port;
1856
1857 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1858
1859 next_port:
1860 priv->mib_next_port++;
1861 if (priv->mib_next_port >= priv->dev.ports)
1862 priv->mib_next_port = 0;
1863
1864 mutex_unlock(&priv->mib_lock);
1865 schedule_delayed_work(&priv->mib_work,
1866 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1867 }
1868
1869 static int
1870 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1871 {
1872 unsigned int len;
1873
1874 if (!ar8xxx_has_mib_counters(priv))
1875 return 0;
1876
1877 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1878
1879 len = priv->dev.ports * priv->chip->num_mibs *
1880 sizeof(*priv->mib_stats);
1881 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1882
1883 if (!priv->mib_stats)
1884 return -ENOMEM;
1885
1886 return 0;
1887 }
1888
1889 static void
1890 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1891 {
1892 if (!ar8xxx_has_mib_counters(priv))
1893 return;
1894
1895 schedule_delayed_work(&priv->mib_work,
1896 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1897 }
1898
1899 static void
1900 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1901 {
1902 if (!ar8xxx_has_mib_counters(priv))
1903 return;
1904
1905 cancel_delayed_work_sync(&priv->mib_work);
1906 }
1907
1908 static struct ar8xxx_priv *
1909 ar8xxx_create(void)
1910 {
1911 struct ar8xxx_priv *priv;
1912
1913 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1914 if (priv == NULL)
1915 return NULL;
1916
1917 mutex_init(&priv->reg_mutex);
1918 mutex_init(&priv->mib_lock);
1919 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1920
1921 return priv;
1922 }
1923
1924 static void
1925 ar8xxx_free(struct ar8xxx_priv *priv)
1926 {
1927 if (priv->chip && priv->chip->cleanup)
1928 priv->chip->cleanup(priv);
1929
1930 kfree(priv->chip_data);
1931 kfree(priv->mib_stats);
1932 kfree(priv);
1933 }
1934
1935 static int
1936 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1937 {
1938 const struct ar8xxx_chip *chip;
1939 struct switch_dev *swdev;
1940 int ret;
1941
1942 ret = ar8xxx_id_chip(priv);
1943 if (ret)
1944 return ret;
1945
1946 chip = priv->chip;
1947
1948 swdev = &priv->dev;
1949 swdev->cpu_port = AR8216_PORT_CPU;
1950 swdev->name = chip->name;
1951 swdev->vlans = chip->vlans;
1952 swdev->ports = chip->ports;
1953 swdev->ops = chip->swops;
1954
1955 ret = ar8xxx_mib_init(priv);
1956 if (ret)
1957 return ret;
1958
1959 return 0;
1960 }
1961
1962 static int
1963 ar8xxx_start(struct ar8xxx_priv *priv)
1964 {
1965 int ret;
1966
1967 priv->init = true;
1968
1969 ret = priv->chip->hw_init(priv);
1970 if (ret)
1971 return ret;
1972
1973 ret = ar8xxx_sw_reset_switch(&priv->dev);
1974 if (ret)
1975 return ret;
1976
1977 priv->init = false;
1978
1979 ar8xxx_mib_start(priv);
1980
1981 return 0;
1982 }
1983
1984 static int
1985 ar8xxx_phy_config_init(struct phy_device *phydev)
1986 {
1987 struct ar8xxx_priv *priv = phydev->priv;
1988 struct net_device *dev = phydev->attached_dev;
1989 int ret;
1990
1991 if (WARN_ON(!priv))
1992 return -ENODEV;
1993
1994 if (priv->chip->config_at_probe)
1995 return ar8xxx_phy_check_aneg(phydev);
1996
1997 priv->phy = phydev;
1998
1999 if (phydev->mdio.addr != 0) {
2000 if (chip_is_ar8316(priv)) {
2001 /* switch device has been initialized, reinit */
2002 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2003 priv->initialized = false;
2004 priv->port4_phy = true;
2005 ar8316_hw_init(priv);
2006 return 0;
2007 }
2008
2009 return 0;
2010 }
2011
2012 ret = ar8xxx_start(priv);
2013 if (ret)
2014 return ret;
2015
2016 /* VID fixup only needed on ar8216 */
2017 if (chip_is_ar8216(priv)) {
2018 dev->phy_ptr = priv;
2019 dev->priv_flags |= IFF_NO_IP_ALIGN;
2020 dev->eth_mangle_rx = ar8216_mangle_rx;
2021 dev->eth_mangle_tx = ar8216_mangle_tx;
2022 }
2023
2024 return 0;
2025 }
2026
2027 static bool
2028 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2029 {
2030 bool link_new, changed = false;
2031 u32 status;
2032 int i;
2033
2034 mutex_lock(&priv->reg_mutex);
2035
2036 for (i = 0; i < priv->dev.ports; i++) {
2037 status = priv->chip->read_port_status(priv, i);
2038 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2039 if (link_new == priv->link_up[i])
2040 continue;
2041
2042 priv->link_up[i] = link_new;
2043 changed = true;
2044 /* flush ARL entries for this port if it went down*/
2045 if (!link_new)
2046 priv->chip->atu_flush_port(priv, i);
2047 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2048 i, link_new ? "up" : "down");
2049 }
2050
2051 mutex_unlock(&priv->reg_mutex);
2052
2053 return changed;
2054 }
2055
2056 static int
2057 ar8xxx_phy_read_status(struct phy_device *phydev)
2058 {
2059 struct ar8xxx_priv *priv = phydev->priv;
2060 struct switch_port_link link;
2061
2062 /* check for switch port link changes */
2063 if (phydev->state == PHY_CHANGELINK)
2064 ar8xxx_check_link_states(priv);
2065
2066 if (phydev->mdio.addr != 0)
2067 return genphy_read_status(phydev);
2068
2069 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2070 phydev->link = !!link.link;
2071 if (!phydev->link)
2072 return 0;
2073
2074 switch (link.speed) {
2075 case SWITCH_PORT_SPEED_10:
2076 phydev->speed = SPEED_10;
2077 break;
2078 case SWITCH_PORT_SPEED_100:
2079 phydev->speed = SPEED_100;
2080 break;
2081 case SWITCH_PORT_SPEED_1000:
2082 phydev->speed = SPEED_1000;
2083 break;
2084 default:
2085 phydev->speed = 0;
2086 }
2087 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2088
2089 phydev->state = PHY_RUNNING;
2090 netif_carrier_on(phydev->attached_dev);
2091 phydev->adjust_link(phydev->attached_dev);
2092
2093 return 0;
2094 }
2095
2096 static int
2097 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2098 {
2099 if (phydev->mdio.addr == 0)
2100 return 0;
2101
2102 return genphy_config_aneg(phydev);
2103 }
2104
2105 static const u32 ar8xxx_phy_ids[] = {
2106 0x004dd033,
2107 0x004dd034, /* AR8327 */
2108 0x004dd036, /* AR8337 */
2109 0x004dd041,
2110 0x004dd042,
2111 0x004dd043, /* AR8236 */
2112 };
2113
2114 static bool
2115 ar8xxx_phy_match(u32 phy_id)
2116 {
2117 int i;
2118
2119 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2120 if (phy_id == ar8xxx_phy_ids[i])
2121 return true;
2122
2123 return false;
2124 }
2125
2126 static bool
2127 ar8xxx_is_possible(struct mii_bus *bus)
2128 {
2129 unsigned int i, found_phys = 0;
2130
2131 for (i = 0; i < 5; i++) {
2132 u32 phy_id;
2133
2134 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2135 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2136 if (ar8xxx_phy_match(phy_id)) {
2137 found_phys++;
2138 } else if (phy_id) {
2139 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2140 dev_name(&bus->dev), i, phy_id);
2141 }
2142 }
2143 return !!found_phys;
2144 }
2145
2146 static int
2147 ar8xxx_phy_probe(struct phy_device *phydev)
2148 {
2149 struct ar8xxx_priv *priv;
2150 struct switch_dev *swdev;
2151 int ret;
2152
2153 /* skip PHYs at unused adresses */
2154 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 4)
2155 return -ENODEV;
2156
2157 if (!ar8xxx_is_possible(phydev->mdio.bus))
2158 return -ENODEV;
2159
2160 mutex_lock(&ar8xxx_dev_list_lock);
2161 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2162 if (priv->mii_bus == phydev->mdio.bus)
2163 goto found;
2164
2165 priv = ar8xxx_create();
2166 if (priv == NULL) {
2167 ret = -ENOMEM;
2168 goto unlock;
2169 }
2170
2171 priv->mii_bus = phydev->mdio.bus;
2172
2173 ret = ar8xxx_probe_switch(priv);
2174 if (ret)
2175 goto free_priv;
2176
2177 swdev = &priv->dev;
2178 swdev->alias = dev_name(&priv->mii_bus->dev);
2179 ret = register_switch(swdev, NULL);
2180 if (ret)
2181 goto free_priv;
2182
2183 pr_info("%s: %s rev. %u switch registered on %s\n",
2184 swdev->devname, swdev->name, priv->chip_rev,
2185 dev_name(&priv->mii_bus->dev));
2186
2187 list_add(&priv->list, &ar8xxx_dev_list);
2188
2189 found:
2190 priv->use_count++;
2191
2192 if (phydev->mdio.addr == 0) {
2193 if (ar8xxx_has_gige(priv)) {
2194 phydev->supported = SUPPORTED_1000baseT_Full;
2195 phydev->advertising = ADVERTISED_1000baseT_Full;
2196 } else {
2197 phydev->supported = SUPPORTED_100baseT_Full;
2198 phydev->advertising = ADVERTISED_100baseT_Full;
2199 }
2200
2201 if (priv->chip->config_at_probe) {
2202 priv->phy = phydev;
2203
2204 ret = ar8xxx_start(priv);
2205 if (ret)
2206 goto err_unregister_switch;
2207 }
2208 } else {
2209 if (ar8xxx_has_gige(priv)) {
2210 phydev->supported |= SUPPORTED_1000baseT_Full;
2211 phydev->advertising |= ADVERTISED_1000baseT_Full;
2212 }
2213 }
2214
2215 phydev->priv = priv;
2216
2217 mutex_unlock(&ar8xxx_dev_list_lock);
2218
2219 return 0;
2220
2221 err_unregister_switch:
2222 if (--priv->use_count)
2223 goto unlock;
2224
2225 unregister_switch(&priv->dev);
2226
2227 free_priv:
2228 ar8xxx_free(priv);
2229 unlock:
2230 mutex_unlock(&ar8xxx_dev_list_lock);
2231 return ret;
2232 }
2233
2234 static void
2235 ar8xxx_phy_detach(struct phy_device *phydev)
2236 {
2237 struct net_device *dev = phydev->attached_dev;
2238
2239 if (!dev)
2240 return;
2241
2242 dev->phy_ptr = NULL;
2243 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2244 dev->eth_mangle_rx = NULL;
2245 dev->eth_mangle_tx = NULL;
2246 }
2247
2248 static void
2249 ar8xxx_phy_remove(struct phy_device *phydev)
2250 {
2251 struct ar8xxx_priv *priv = phydev->priv;
2252
2253 if (WARN_ON(!priv))
2254 return;
2255
2256 phydev->priv = NULL;
2257
2258 mutex_lock(&ar8xxx_dev_list_lock);
2259
2260 if (--priv->use_count > 0) {
2261 mutex_unlock(&ar8xxx_dev_list_lock);
2262 return;
2263 }
2264
2265 list_del(&priv->list);
2266 mutex_unlock(&ar8xxx_dev_list_lock);
2267
2268 unregister_switch(&priv->dev);
2269 ar8xxx_mib_stop(priv);
2270 ar8xxx_free(priv);
2271 }
2272
2273 static int
2274 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2275 {
2276 /* we don't need an extra reset */
2277 return 0;
2278 }
2279
2280 static struct phy_driver ar8xxx_phy_driver[] = {
2281 {
2282 .phy_id = 0x004d0000,
2283 .name = "Atheros AR8216/AR8236/AR8316",
2284 .phy_id_mask = 0xffff0000,
2285 .features = PHY_BASIC_FEATURES,
2286 .probe = ar8xxx_phy_probe,
2287 .remove = ar8xxx_phy_remove,
2288 .detach = ar8xxx_phy_detach,
2289 .config_init = ar8xxx_phy_config_init,
2290 .config_aneg = ar8xxx_phy_config_aneg,
2291 .read_status = ar8xxx_phy_read_status,
2292 .soft_reset = ar8xxx_phy_soft_reset,
2293 }
2294 };
2295
2296 module_phy_driver(ar8xxx_phy_driver);
2297 MODULE_LICENSE("GPL");