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[openwrt/staging/yousong.git] / target / linux / generic / patches-3.8 / 020-ssb_update.patch
1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -136,10 +136,15 @@ config SSB_DRIVER_MIPS
4
5 If unsure, say N
6
7 +config SSB_SFLASH
8 + bool "SSB serial flash support"
9 + depends on SSB_DRIVER_MIPS
10 + default y
11 +
12 # Assumption: We are on embedded, if we compile the MIPS core.
13 config SSB_EMBEDDED
14 bool
15 - depends on SSB_DRIVER_MIPS
16 + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
17 default y
18
19 config SSB_DRIVER_EXTIF
20 --- a/drivers/ssb/Makefile
21 +++ b/drivers/ssb/Makefile
22 @@ -11,6 +11,7 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
23 # built-in drivers
24 ssb-y += driver_chipcommon.o
25 ssb-y += driver_chipcommon_pmu.o
26 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
27 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
28 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
29 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
30 --- a/drivers/ssb/driver_chipcommon.c
31 +++ b/drivers/ssb/driver_chipcommon.c
32 @@ -354,7 +354,7 @@ void ssb_chipcommon_init(struct ssb_chip
33
34 if (cc->dev->id.revision >= 11)
35 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
36 - ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
37 + ssb_dbg("chipcommon status is 0x%x\n", cc->status);
38
39 if (cc->dev->id.revision >= 20) {
40 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
41 --- a/drivers/ssb/driver_chipcommon_pmu.c
42 +++ b/drivers/ssb/driver_chipcommon_pmu.c
43 @@ -110,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
44 return;
45 }
46
47 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
48 - (crystalfreq / 1000), (crystalfreq % 1000));
49 + ssb_info("Programming PLL to %u.%03u MHz\n",
50 + crystalfreq / 1000, crystalfreq % 1000);
51
52 /* First turn the PLL off. */
53 switch (bus->chip_id) {
54 @@ -138,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
55 }
56 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
57 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
58 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
59 + ssb_emerg("Failed to turn the PLL off!\n");
60
61 /* Set PDIV in PLL control 0. */
62 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
63 @@ -249,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
64 return;
65 }
66
67 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
68 - (crystalfreq / 1000), (crystalfreq % 1000));
69 + ssb_info("Programming PLL to %u.%03u MHz\n",
70 + crystalfreq / 1000, crystalfreq % 1000);
71
72 /* First turn the PLL off. */
73 switch (bus->chip_id) {
74 @@ -275,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
75 }
76 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
77 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
78 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
79 + ssb_emerg("Failed to turn the PLL off!\n");
80
81 /* Set p1div and p2div. */
82 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
83 @@ -349,9 +349,8 @@ static void ssb_pmu_pll_init(struct ssb_
84 case 43222:
85 break;
86 default:
87 - ssb_printk(KERN_ERR PFX
88 - "ERROR: PLL init unknown for device %04X\n",
89 - bus->chip_id);
90 + ssb_err("ERROR: PLL init unknown for device %04X\n",
91 + bus->chip_id);
92 }
93 }
94
95 @@ -472,9 +471,8 @@ static void ssb_pmu_resources_init(struc
96 max_msk = 0xFFFFF;
97 break;
98 default:
99 - ssb_printk(KERN_ERR PFX
100 - "ERROR: PMU resource config unknown for device %04X\n",
101 - bus->chip_id);
102 + ssb_err("ERROR: PMU resource config unknown for device %04X\n",
103 + bus->chip_id);
104 }
105
106 if (updown_tab) {
107 @@ -526,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
108 pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
109 cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
110
111 - ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
112 - cc->pmu.rev, pmucap);
113 + ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
114 + cc->pmu.rev, pmucap);
115
116 if (cc->pmu.rev == 1)
117 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
118 @@ -638,9 +636,8 @@ u32 ssb_pmu_get_alp_clock(struct ssb_chi
119 case 0x5354:
120 ssb_pmu_get_alp_clock_clk0(cc);
121 default:
122 - ssb_printk(KERN_ERR PFX
123 - "ERROR: PMU alp clock unknown for device %04X\n",
124 - bus->chip_id);
125 + ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
126 + bus->chip_id);
127 return 0;
128 }
129 }
130 @@ -654,9 +651,8 @@ u32 ssb_pmu_get_cpu_clock(struct ssb_chi
131 /* 5354 chip uses a non programmable PLL of frequency 240MHz */
132 return 240000000;
133 default:
134 - ssb_printk(KERN_ERR PFX
135 - "ERROR: PMU cpu clock unknown for device %04X\n",
136 - bus->chip_id);
137 + ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
138 + bus->chip_id);
139 return 0;
140 }
141 }
142 @@ -669,9 +665,8 @@ u32 ssb_pmu_get_controlclock(struct ssb_
143 case 0x5354:
144 return 120000000;
145 default:
146 - ssb_printk(KERN_ERR PFX
147 - "ERROR: PMU controlclock unknown for device %04X\n",
148 - bus->chip_id);
149 + ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
150 + bus->chip_id);
151 return 0;
152 }
153 }
154 @@ -692,8 +687,23 @@ void ssb_pmu_spuravoid_pllupdate(struct
155 pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
156 break;
157 case 43222:
158 - /* TODO: BCM43222 requires updating PLLs too */
159 - return;
160 + if (spuravoid == 1) {
161 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
162 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
163 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
164 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
165 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
166 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
167 + } else {
168 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
169 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
170 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
171 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
172 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
173 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
174 + }
175 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
176 + break;
177 default:
178 ssb_printk(KERN_ERR PFX
179 "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
180 --- /dev/null
181 +++ b/drivers/ssb/driver_chipcommon_sflash.c
182 @@ -0,0 +1,164 @@
183 +/*
184 + * Sonics Silicon Backplane
185 + * ChipCommon serial flash interface
186 + *
187 + * Licensed under the GNU/GPL. See COPYING for details.
188 + */
189 +
190 +#include <linux/ssb/ssb.h>
191 +
192 +#include "ssb_private.h"
193 +
194 +static struct resource ssb_sflash_resource = {
195 + .name = "ssb_sflash",
196 + .start = SSB_FLASH2,
197 + .end = 0,
198 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
199 +};
200 +
201 +struct platform_device ssb_sflash_dev = {
202 + .name = "ssb_sflash",
203 + .resource = &ssb_sflash_resource,
204 + .num_resources = 1,
205 +};
206 +
207 +struct ssb_sflash_tbl_e {
208 + char *name;
209 + u32 id;
210 + u32 blocksize;
211 + u16 numblocks;
212 +};
213 +
214 +static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
215 + { "M25P20", 0x11, 0x10000, 4, },
216 + { "M25P40", 0x12, 0x10000, 8, },
217 +
218 + { "M25P16", 0x14, 0x10000, 32, },
219 + { "M25P32", 0x15, 0x10000, 64, },
220 + { "M25P64", 0x16, 0x10000, 128, },
221 + { "M25FL128", 0x17, 0x10000, 256, },
222 + { 0 },
223 +};
224 +
225 +static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
226 + { "SST25WF512", 1, 0x1000, 16, },
227 + { "SST25VF512", 0x48, 0x1000, 16, },
228 + { "SST25WF010", 2, 0x1000, 32, },
229 + { "SST25VF010", 0x49, 0x1000, 32, },
230 + { "SST25WF020", 3, 0x1000, 64, },
231 + { "SST25VF020", 0x43, 0x1000, 64, },
232 + { "SST25WF040", 4, 0x1000, 128, },
233 + { "SST25VF040", 0x44, 0x1000, 128, },
234 + { "SST25VF040B", 0x8d, 0x1000, 128, },
235 + { "SST25WF080", 5, 0x1000, 256, },
236 + { "SST25VF080B", 0x8e, 0x1000, 256, },
237 + { "SST25VF016", 0x41, 0x1000, 512, },
238 + { "SST25VF032", 0x4a, 0x1000, 1024, },
239 + { "SST25VF064", 0x4b, 0x1000, 2048, },
240 + { 0 },
241 +};
242 +
243 +static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
244 + { "AT45DB011", 0xc, 256, 512, },
245 + { "AT45DB021", 0x14, 256, 1024, },
246 + { "AT45DB041", 0x1c, 256, 2048, },
247 + { "AT45DB081", 0x24, 256, 4096, },
248 + { "AT45DB161", 0x2c, 512, 4096, },
249 + { "AT45DB321", 0x34, 512, 8192, },
250 + { "AT45DB642", 0x3c, 1024, 8192, },
251 + { 0 },
252 +};
253 +
254 +static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
255 +{
256 + int i;
257 + chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
258 + SSB_CHIPCO_FLASHCTL_START | opcode);
259 + for (i = 0; i < 1000; i++) {
260 + if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
261 + SSB_CHIPCO_FLASHCTL_BUSY))
262 + return;
263 + cpu_relax();
264 + }
265 + pr_err("SFLASH control command failed (timeout)!\n");
266 +}
267 +
268 +/* Initialize serial flash access */
269 +int ssb_sflash_init(struct ssb_chipcommon *cc)
270 +{
271 + struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
272 + const struct ssb_sflash_tbl_e *e;
273 + u32 id, id2;
274 +
275 + switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
276 + case SSB_CHIPCO_FLASHT_STSER:
277 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
278 +
279 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
280 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
281 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
282 +
283 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
284 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
285 + id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
286 +
287 + switch (id) {
288 + case 0xbf:
289 + for (e = ssb_sflash_sst_tbl; e->name; e++) {
290 + if (e->id == id2)
291 + break;
292 + }
293 + break;
294 + case 0x13:
295 + return -ENOTSUPP;
296 + default:
297 + for (e = ssb_sflash_st_tbl; e->name; e++) {
298 + if (e->id == id)
299 + break;
300 + }
301 + break;
302 + }
303 + if (!e->name) {
304 + pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
305 + id, id2);
306 + return -ENOTSUPP;
307 + }
308 +
309 + break;
310 + case SSB_CHIPCO_FLASHT_ATSER:
311 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
312 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
313 +
314 + for (e = ssb_sflash_at_tbl; e->name; e++) {
315 + if (e->id == id)
316 + break;
317 + }
318 + if (!e->name) {
319 + pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
320 + id);
321 + return -ENOTSUPP;
322 + }
323 +
324 + break;
325 + default:
326 + pr_err("Unsupported flash type\n");
327 + return -ENOTSUPP;
328 + }
329 +
330 + sflash->window = SSB_FLASH2;
331 + sflash->blocksize = e->blocksize;
332 + sflash->numblocks = e->numblocks;
333 + sflash->size = sflash->blocksize * sflash->numblocks;
334 + sflash->present = true;
335 +
336 + pr_info("Found %s serial flash (size: %dKiB, blocksize: 0x%X, blocks: %d)\n",
337 + e->name, sflash->size / 1024, e->blocksize, e->numblocks);
338 +
339 + /* Prepare platform device, but don't register it yet. It's too early,
340 + * malloc (required by device_private_init) is not available yet. */
341 + ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
342 + sflash->size;
343 + ssb_sflash_dev.dev.platform_data = sflash;
344 +
345 + return 0;
346 +}
347 --- a/drivers/ssb/driver_gpio.c
348 +++ b/drivers/ssb/driver_gpio.c
349 @@ -74,6 +74,16 @@ static void ssb_gpio_chipco_free(struct
350 ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
351 }
352
353 +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
354 +{
355 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
356 +
357 + if (bus->bustype == SSB_BUSTYPE_SSB)
358 + return ssb_mips_irq(bus->chipco.dev) + 2;
359 + else
360 + return -EINVAL;
361 +}
362 +
363 static int ssb_gpio_chipco_init(struct ssb_bus *bus)
364 {
365 struct gpio_chip *chip = &bus->gpio;
366 @@ -86,6 +96,7 @@ static int ssb_gpio_chipco_init(struct s
367 chip->set = ssb_gpio_chipco_set_value;
368 chip->direction_input = ssb_gpio_chipco_direction_input;
369 chip->direction_output = ssb_gpio_chipco_direction_output;
370 + chip->to_irq = ssb_gpio_chipco_to_irq;
371 chip->ngpio = 16;
372 /* There is just one SoC in one device and its GPIO addresses should be
373 * deterministic to address them more easily. The other buses could get
374 @@ -134,6 +145,16 @@ static int ssb_gpio_extif_direction_outp
375 return 0;
376 }
377
378 +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
379 +{
380 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
381 +
382 + if (bus->bustype == SSB_BUSTYPE_SSB)
383 + return ssb_mips_irq(bus->extif.dev) + 2;
384 + else
385 + return -EINVAL;
386 +}
387 +
388 static int ssb_gpio_extif_init(struct ssb_bus *bus)
389 {
390 struct gpio_chip *chip = &bus->gpio;
391 @@ -144,6 +165,7 @@ static int ssb_gpio_extif_init(struct ss
392 chip->set = ssb_gpio_extif_set_value;
393 chip->direction_input = ssb_gpio_extif_direction_input;
394 chip->direction_output = ssb_gpio_extif_direction_output;
395 + chip->to_irq = ssb_gpio_extif_to_irq;
396 chip->ngpio = 5;
397 /* There is just one SoC in one device and its GPIO addresses should be
398 * deterministic to address them more easily. The other buses could get
399 --- a/drivers/ssb/driver_mipscore.c
400 +++ b/drivers/ssb/driver_mipscore.c
401 @@ -10,6 +10,7 @@
402
403 #include <linux/ssb/ssb.h>
404
405 +#include <linux/mtd/physmap.h>
406 #include <linux/serial.h>
407 #include <linux/serial_core.h>
408 #include <linux/serial_reg.h>
409 @@ -17,6 +18,25 @@
410
411 #include "ssb_private.h"
412
413 +static const char *part_probes[] = { "bcm47xxpart", NULL };
414 +
415 +static struct physmap_flash_data ssb_pflash_data = {
416 + .part_probe_types = part_probes,
417 +};
418 +
419 +static struct resource ssb_pflash_resource = {
420 + .name = "ssb_pflash",
421 + .flags = IORESOURCE_MEM,
422 +};
423 +
424 +struct platform_device ssb_pflash_dev = {
425 + .name = "physmap-flash",
426 + .dev = {
427 + .platform_data = &ssb_pflash_data,
428 + },
429 + .resource = &ssb_pflash_resource,
430 + .num_resources = 1,
431 +};
432
433 static inline u32 mips_read32(struct ssb_mipscore *mcore,
434 u16 offset)
435 @@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d
436 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
437 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
438 }
439 - ssb_dprintk(KERN_INFO PFX
440 - "set_irq: core 0x%04x, irq %d => %d\n",
441 - dev->id.coreid, oldirq+2, irq+2);
442 + ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
443 + dev->id.coreid, oldirq+2, irq+2);
444 }
445
446 static void print_irq(struct ssb_device *dev, unsigned int irq)
447 {
448 - int i;
449 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
450 - ssb_dprintk(KERN_INFO PFX
451 - "core 0x%04x, irq :", dev->id.coreid);
452 - for (i = 0; i <= 6; i++) {
453 - ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
454 - }
455 - ssb_dprintk("\n");
456 + ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
457 + dev->id.coreid,
458 + irq_name[0], irq == 0 ? "*" : " ",
459 + irq_name[1], irq == 1 ? "*" : " ",
460 + irq_name[2], irq == 2 ? "*" : " ",
461 + irq_name[3], irq == 3 ? "*" : " ",
462 + irq_name[4], irq == 4 ? "*" : " ",
463 + irq_name[5], irq == 5 ? "*" : " ",
464 + irq_name[6], irq == 6 ? "*" : " ");
465 }
466
467 static void dump_irq(struct ssb_bus *bus)
468 @@ -189,34 +210,43 @@ static void ssb_mips_serial_init(struct
469 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
470 {
471 struct ssb_bus *bus = mcore->dev->bus;
472 + struct ssb_pflash *pflash = &mcore->pflash;
473
474 /* When there is no chipcommon on the bus there is 4MB flash */
475 if (!ssb_chipco_available(&bus->chipco)) {
476 - mcore->pflash.present = true;
477 - mcore->pflash.buswidth = 2;
478 - mcore->pflash.window = SSB_FLASH1;
479 - mcore->pflash.window_size = SSB_FLASH1_SZ;
480 - return;
481 + pflash->present = true;
482 + pflash->buswidth = 2;
483 + pflash->window = SSB_FLASH1;
484 + pflash->window_size = SSB_FLASH1_SZ;
485 + goto ssb_pflash;
486 }
487
488 /* There is ChipCommon, so use it to read info about flash */
489 switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
490 case SSB_CHIPCO_FLASHT_STSER:
491 case SSB_CHIPCO_FLASHT_ATSER:
492 - pr_err("Serial flash not supported\n");
493 + pr_debug("Found serial flash\n");
494 + ssb_sflash_init(&bus->chipco);
495 break;
496 case SSB_CHIPCO_FLASHT_PARA:
497 pr_debug("Found parallel flash\n");
498 - mcore->pflash.present = true;
499 - mcore->pflash.window = SSB_FLASH2;
500 - mcore->pflash.window_size = SSB_FLASH2_SZ;
501 + pflash->present = true;
502 + pflash->window = SSB_FLASH2;
503 + pflash->window_size = SSB_FLASH2_SZ;
504 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
505 & SSB_CHIPCO_CFG_DS16) == 0)
506 - mcore->pflash.buswidth = 1;
507 + pflash->buswidth = 1;
508 else
509 - mcore->pflash.buswidth = 2;
510 + pflash->buswidth = 2;
511 break;
512 }
513 +
514 +ssb_pflash:
515 + if (pflash->present) {
516 + ssb_pflash_data.width = pflash->buswidth;
517 + ssb_pflash_resource.start = pflash->window;
518 + ssb_pflash_resource.end = pflash->window + pflash->window_size;
519 + }
520 }
521
522 u32 ssb_cpu_clock(struct ssb_mipscore *mcore)
523 @@ -257,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco
524 if (!mcore->dev)
525 return; /* We don't have a MIPS core */
526
527 - ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
528 + ssb_dbg("Initializing MIPS core...\n");
529
530 bus = mcore->dev->bus;
531 hz = ssb_clockspeed(bus);
532 @@ -305,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco
533 break;
534 }
535 }
536 - ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
537 + ssb_dbg("after irq reconfiguration\n");
538 dump_irq(bus);
539
540 ssb_mips_serial_init(mcore);
541 --- a/drivers/ssb/driver_pcicore.c
542 +++ b/drivers/ssb/driver_pcicore.c
543 @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
544 return -ENODEV;
545 }
546
547 - ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
548 - pci_name(d));
549 + ssb_info("PCI: Fixing up device %s\n", pci_name(d));
550
551 /* Fix up interrupt lines */
552 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
553 @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
554 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
555 return;
556
557 - ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
558 + ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
559
560 /* Enable PCI bridge bus mastering and memory space */
561 pci_set_master(dev);
562 if (pcibios_enable_device(dev, ~0) < 0) {
563 - ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
564 + ssb_err("PCI: SSB bridge enable failed\n");
565 return;
566 }
567
568 @@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
569
570 /* Make sure our latency is high enough to handle the devices behind us */
571 lat = 168;
572 - ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
573 - pci_name(dev), lat);
574 + ssb_info("PCI: Fixing latency timer of device %s to %u\n",
575 + pci_name(dev), lat);
576 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
577 }
578 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
579 @@ -323,7 +322,7 @@ static void ssb_pcicore_init_hostmode(st
580 return;
581 extpci_core = pc;
582
583 - ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
584 + ssb_dbg("PCIcore in host mode found\n");
585 /* Reset devices on the external PCI bus */
586 val = SSB_PCICORE_CTL_RST_OE;
587 val |= SSB_PCICORE_CTL_CLK_OE;
588 @@ -338,7 +337,7 @@ static void ssb_pcicore_init_hostmode(st
589 udelay(1); /* Assertion time demanded by the PCI standard */
590
591 if (pc->dev->bus->has_cardbus_slot) {
592 - ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
593 + ssb_dbg("CardBus slot detected\n");
594 pc->cardbusmode = 1;
595 /* GPIO 1 resets the bridge */
596 ssb_gpio_out(pc->dev->bus, 1, 1);
597 --- a/drivers/ssb/embedded.c
598 +++ b/drivers/ssb/embedded.c
599 @@ -57,9 +57,8 @@ int ssb_watchdog_register(struct ssb_bus
600 bus->busnumber, &wdt,
601 sizeof(wdt));
602 if (IS_ERR(pdev)) {
603 - ssb_dprintk(KERN_INFO PFX
604 - "can not register watchdog device, err: %li\n",
605 - PTR_ERR(pdev));
606 + ssb_dbg("can not register watchdog device, err: %li\n",
607 + PTR_ERR(pdev));
608 return PTR_ERR(pdev);
609 }
610
611 --- a/drivers/ssb/main.c
612 +++ b/drivers/ssb/main.c
613 @@ -275,8 +275,8 @@ int ssb_devices_thaw(struct ssb_freeze_c
614
615 err = sdrv->probe(sdev, &sdev->id);
616 if (err) {
617 - ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
618 - dev_name(sdev->dev));
619 + ssb_err("Failed to thaw device %s\n",
620 + dev_name(sdev->dev));
621 result = err;
622 }
623 ssb_device_put(sdev);
624 @@ -447,10 +447,9 @@ void ssb_bus_unregister(struct ssb_bus *
625
626 err = ssb_gpio_unregister(bus);
627 if (err == -EBUSY)
628 - ssb_dprintk(KERN_ERR PFX "Some GPIOs are still in use.\n");
629 + ssb_dbg("Some GPIOs are still in use\n");
630 else if (err)
631 - ssb_dprintk(KERN_ERR PFX
632 - "Can not unregister GPIO driver: %i\n", err);
633 + ssb_dbg("Can not unregister GPIO driver: %i\n", err);
634
635 ssb_buses_lock();
636 ssb_devices_unregister(bus);
637 @@ -497,8 +496,7 @@ static int ssb_devices_register(struct s
638
639 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
640 if (!devwrap) {
641 - ssb_printk(KERN_ERR PFX
642 - "Could not allocate device\n");
643 + ssb_err("Could not allocate device\n");
644 err = -ENOMEM;
645 goto error;
646 }
647 @@ -537,9 +535,7 @@ static int ssb_devices_register(struct s
648 sdev->dev = dev;
649 err = device_register(dev);
650 if (err) {
651 - ssb_printk(KERN_ERR PFX
652 - "Could not register %s\n",
653 - dev_name(dev));
654 + ssb_err("Could not register %s\n", dev_name(dev));
655 /* Set dev to NULL to not unregister
656 * dev on error unwinding. */
657 sdev->dev = NULL;
658 @@ -549,6 +545,22 @@ static int ssb_devices_register(struct s
659 dev_idx++;
660 }
661
662 +#ifdef CONFIG_SSB_DRIVER_MIPS
663 + if (bus->mipscore.pflash.present) {
664 + err = platform_device_register(&ssb_pflash_dev);
665 + if (err)
666 + pr_err("Error registering parallel flash\n");
667 + }
668 +#endif
669 +
670 +#ifdef CONFIG_SSB_SFLASH
671 + if (bus->mipscore.sflash.present) {
672 + err = platform_device_register(&ssb_sflash_dev);
673 + if (err)
674 + pr_err("Error registering serial flash\n");
675 + }
676 +#endif
677 +
678 return 0;
679 error:
680 /* Unwind the already registered devices. */
681 @@ -817,10 +829,9 @@ static int ssb_bus_register(struct ssb_b
682 ssb_mipscore_init(&bus->mipscore);
683 err = ssb_gpio_init(bus);
684 if (err == -ENOTSUPP)
685 - ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
686 + ssb_dbg("GPIO driver not activated\n");
687 else if (err)
688 - ssb_dprintk(KERN_ERR PFX
689 - "Error registering GPIO driver: %i\n", err);
690 + ssb_dbg("Error registering GPIO driver: %i\n", err);
691 err = ssb_fetch_invariants(bus, get_invariants);
692 if (err) {
693 ssb_bus_may_powerdown(bus);
694 @@ -870,11 +881,11 @@ int ssb_bus_pcibus_register(struct ssb_b
695
696 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
697 if (!err) {
698 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
699 - "PCI device %s\n", dev_name(&host_pci->dev));
700 + ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
701 + dev_name(&host_pci->dev));
702 } else {
703 - ssb_printk(KERN_ERR PFX "Failed to register PCI version"
704 - " of SSB with error %d\n", err);
705 + ssb_err("Failed to register PCI version of SSB with error %d\n",
706 + err);
707 }
708
709 return err;
710 @@ -895,8 +906,8 @@ int ssb_bus_pcmciabus_register(struct ss
711
712 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
713 if (!err) {
714 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
715 - "PCMCIA device %s\n", pcmcia_dev->devname);
716 + ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
717 + pcmcia_dev->devname);
718 }
719
720 return err;
721 @@ -917,8 +928,8 @@ int ssb_bus_sdiobus_register(struct ssb_
722
723 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
724 if (!err) {
725 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
726 - "SDIO device %s\n", sdio_func_id(func));
727 + ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
728 + sdio_func_id(func));
729 }
730
731 return err;
732 @@ -936,8 +947,8 @@ int ssb_bus_ssbbus_register(struct ssb_b
733
734 err = ssb_bus_register(bus, get_invariants, baseaddr);
735 if (!err) {
736 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
737 - "address 0x%08lX\n", baseaddr);
738 + ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
739 + baseaddr);
740 }
741
742 return err;
743 @@ -1331,7 +1342,7 @@ out:
744 #endif
745 return err;
746 error:
747 - ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
748 + ssb_err("Bus powerdown failed\n");
749 goto out;
750 }
751 EXPORT_SYMBOL(ssb_bus_may_powerdown);
752 @@ -1354,7 +1365,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
753
754 return 0;
755 error:
756 - ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
757 + ssb_err("Bus powerup failed\n");
758 return err;
759 }
760 EXPORT_SYMBOL(ssb_bus_powerup);
761 @@ -1462,15 +1473,13 @@ static int __init ssb_modinit(void)
762
763 err = b43_pci_ssb_bridge_init();
764 if (err) {
765 - ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
766 - "initialization failed\n");
767 + ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
768 /* don't fail SSB init because of this */
769 err = 0;
770 }
771 err = ssb_gige_init();
772 if (err) {
773 - ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
774 - "driver initialization failed\n");
775 + ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
776 /* don't fail SSB init because of this */
777 err = 0;
778 }
779 --- a/drivers/ssb/pci.c
780 +++ b/drivers/ssb/pci.c
781 @@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
782 }
783 return 0;
784 error:
785 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
786 + ssb_err("Failed to switch to core %u\n", coreidx);
787 return -ENODEV;
788 }
789
790 @@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
791 unsigned long flags;
792
793 #if SSB_VERBOSE_PCICORESWITCH_DEBUG
794 - ssb_printk(KERN_INFO PFX
795 - "Switching to %s core, index %d\n",
796 - ssb_core_name(dev->id.coreid),
797 - dev->core_index);
798 + ssb_info("Switching to %s core, index %d\n",
799 + ssb_core_name(dev->id.coreid),
800 + dev->core_index);
801 #endif
802
803 spin_lock_irqsave(&bus->bar_lock, flags);
804 @@ -231,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
805 return t[crc ^ data];
806 }
807
808 +static void sprom_get_mac(char *mac, const u16 *in)
809 +{
810 + int i;
811 + for (i = 0; i < 3; i++) {
812 + *mac++ = in[i] >> 8;
813 + *mac++ = in[i];
814 + }
815 +}
816 +
817 static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
818 {
819 int word;
820 @@ -278,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
821 u32 spromctl;
822 u16 size = bus->sprom_size;
823
824 - ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
825 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
826 err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
827 if (err)
828 goto err_ctlreg;
829 @@ -286,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
830 err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
831 if (err)
832 goto err_ctlreg;
833 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
834 + ssb_notice("[ 0%%");
835 msleep(500);
836 for (i = 0; i < size; i++) {
837 if (i == size / 4)
838 - ssb_printk("25%%");
839 + ssb_cont("25%%");
840 else if (i == size / 2)
841 - ssb_printk("50%%");
842 + ssb_cont("50%%");
843 else if (i == (size * 3) / 4)
844 - ssb_printk("75%%");
845 + ssb_cont("75%%");
846 else if (i % 2)
847 - ssb_printk(".");
848 + ssb_cont(".");
849 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
850 mmiowb();
851 msleep(20);
852 @@ -309,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
853 if (err)
854 goto err_ctlreg;
855 msleep(500);
856 - ssb_printk("100%% ]\n");
857 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
858 + ssb_cont("100%% ]\n");
859 + ssb_notice("SPROM written\n");
860
861 return 0;
862 err_ctlreg:
863 - ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
864 + ssb_err("Could not access SPROM control register.\n");
865 return err;
866 }
867
868 @@ -339,10 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
869 return (s8)gain;
870 }
871
872 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
873 +{
874 + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
875 + SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
876 + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
877 + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
878 + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
879 + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
880 + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
881 + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
882 + SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
883 + SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
884 + SSB_SPROM2_MAXP_A_LO_SHIFT);
885 +}
886 +
887 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
888 {
889 - int i;
890 - u16 v;
891 u16 loc[3];
892
893 if (out->revision == 3) /* rev 3 moved MAC */
894 @@ -352,19 +373,10 @@ static void sprom_extract_r123(struct ss
895 loc[1] = SSB_SPROM1_ET0MAC;
896 loc[2] = SSB_SPROM1_ET1MAC;
897 }
898 - for (i = 0; i < 3; i++) {
899 - v = in[SPOFF(loc[0]) + i];
900 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
901 - }
902 + sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
903 if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
904 - for (i = 0; i < 3; i++) {
905 - v = in[SPOFF(loc[1]) + i];
906 - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
907 - }
908 - for (i = 0; i < 3; i++) {
909 - v = in[SPOFF(loc[2]) + i];
910 - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
911 - }
912 + sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
913 + sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
914 }
915 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
916 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
917 @@ -372,6 +384,7 @@ static void sprom_extract_r123(struct ss
918 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
919 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
920 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
921 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
922 if (out->revision == 1)
923 SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
924 SSB_SPROM1_BINF_CCODE_SHIFT);
925 @@ -398,8 +411,7 @@ static void sprom_extract_r123(struct ss
926 SSB_SPROM1_ITSSI_A_SHIFT);
927 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
928 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
929 - if (out->revision >= 2)
930 - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
931 +
932 SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
933 SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
934
935 @@ -410,6 +422,8 @@ static void sprom_extract_r123(struct ss
936 out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
937 SSB_SPROM1_AGAIN_A,
938 SSB_SPROM1_AGAIN_A_SHIFT);
939 + if (out->revision >= 2)
940 + sprom_extract_r23(out, in);
941 }
942
943 /* Revs 4 5 and 8 have partially shared layout */
944 @@ -454,23 +468,20 @@ static void sprom_extract_r458(struct ss
945
946 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
947 {
948 - int i;
949 - u16 v;
950 u16 il0mac_offset;
951
952 if (out->revision == 4)
953 il0mac_offset = SSB_SPROM4_IL0MAC;
954 else
955 il0mac_offset = SSB_SPROM5_IL0MAC;
956 - /* extract the MAC address */
957 - for (i = 0; i < 3; i++) {
958 - v = in[SPOFF(il0mac_offset) + i];
959 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
960 - }
961 +
962 + sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
963 +
964 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
965 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
966 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
967 SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
968 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
969 if (out->revision == 4) {
970 SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
971 SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
972 @@ -530,7 +541,7 @@ static void sprom_extract_r45(struct ssb
973 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
974 {
975 int i;
976 - u16 v, o;
977 + u16 o;
978 u16 pwr_info_offset[] = {
979 SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
980 SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
981 @@ -539,11 +550,10 @@ static void sprom_extract_r8(struct ssb_
982 ARRAY_SIZE(out->core_pwr_info));
983
984 /* extract the MAC address */
985 - for (i = 0; i < 3; i++) {
986 - v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
987 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
988 - }
989 + sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
990 +
991 SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
992 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
993 SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
994 SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
995 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
996 @@ -743,7 +753,7 @@ static int sprom_extract(struct ssb_bus
997 memset(out, 0, sizeof(*out));
998
999 out->revision = in[size - 1] & 0x00FF;
1000 - ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1001 + ssb_dbg("SPROM revision %d detected\n", out->revision);
1002 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1003 memset(out->et1mac, 0xFF, 6);
1004
1005 @@ -752,7 +762,7 @@ static int sprom_extract(struct ssb_bus
1006 * number stored in the SPROM.
1007 * Always extract r1. */
1008 out->revision = 1;
1009 - ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1010 + ssb_dbg("SPROM treated as revision %d\n", out->revision);
1011 }
1012
1013 switch (out->revision) {
1014 @@ -769,9 +779,8 @@ static int sprom_extract(struct ssb_bus
1015 sprom_extract_r8(out, in);
1016 break;
1017 default:
1018 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1019 - " revision %d detected. Will extract"
1020 - " v1\n", out->revision);
1021 + ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
1022 + out->revision);
1023 out->revision = 1;
1024 sprom_extract_r123(out, in);
1025 }
1026 @@ -791,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
1027 u16 *buf;
1028
1029 if (!ssb_is_sprom_available(bus)) {
1030 - ssb_printk(KERN_ERR PFX "No SPROM available!\n");
1031 + ssb_err("No SPROM available!\n");
1032 return -ENODEV;
1033 }
1034 if (bus->chipco.dev) { /* can be unavailable! */
1035 @@ -810,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
1036 } else {
1037 bus->sprom_offset = SSB_SPROM_BASE1;
1038 }
1039 - ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
1040 + ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
1041
1042 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
1043 if (!buf)
1044 @@ -835,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
1045 * available for this device in some other storage */
1046 err = ssb_fill_sprom_with_fallback(bus, sprom);
1047 if (err) {
1048 - ssb_printk(KERN_WARNING PFX "WARNING: Using"
1049 - " fallback SPROM failed (err %d)\n",
1050 - err);
1051 + ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
1052 + err);
1053 } else {
1054 - ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
1055 - " revision %d provided by"
1056 - " platform.\n", sprom->revision);
1057 + ssb_dbg("Using SPROM revision %d provided by platform\n",
1058 + sprom->revision);
1059 err = 0;
1060 goto out_free;
1061 }
1062 - ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
1063 - " SPROM CRC (corrupt SPROM)\n");
1064 + ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
1065 }
1066 }
1067 err = sprom_extract(bus, sprom, buf, bus->sprom_size);
1068 --- a/drivers/ssb/pcihost_wrapper.c
1069 +++ b/drivers/ssb/pcihost_wrapper.c
1070 @@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
1071 struct ssb_bus *ssb = pci_get_drvdata(dev);
1072 int err;
1073
1074 - pci_set_power_state(dev, 0);
1075 + pci_set_power_state(dev, PCI_D0);
1076 err = pci_enable_device(dev);
1077 if (err)
1078 return err;
1079 --- a/drivers/ssb/pcmcia.c
1080 +++ b/drivers/ssb/pcmcia.c
1081 @@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
1082
1083 return 0;
1084 error:
1085 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1086 + ssb_err("Failed to switch to core %u\n", coreidx);
1087 return err;
1088 }
1089
1090 @@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
1091 int err;
1092
1093 #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
1094 - ssb_printk(KERN_INFO PFX
1095 - "Switching to %s core, index %d\n",
1096 - ssb_core_name(dev->id.coreid),
1097 - dev->core_index);
1098 + ssb_info("Switching to %s core, index %d\n",
1099 + ssb_core_name(dev->id.coreid),
1100 + dev->core_index);
1101 #endif
1102
1103 err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
1104 @@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
1105
1106 return 0;
1107 error:
1108 - ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
1109 + ssb_err("Failed to switch pcmcia segment\n");
1110 return err;
1111 }
1112
1113 @@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
1114 bool failed = 0;
1115 size_t size = SSB_PCMCIA_SPROM_SIZE;
1116
1117 - ssb_printk(KERN_NOTICE PFX
1118 - "Writing SPROM. Do NOT turn off the power! "
1119 - "Please stand by...\n");
1120 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1121 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
1122 if (err) {
1123 - ssb_printk(KERN_NOTICE PFX
1124 - "Could not enable SPROM write access.\n");
1125 + ssb_notice("Could not enable SPROM write access\n");
1126 return -EBUSY;
1127 }
1128 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
1129 + ssb_notice("[ 0%%");
1130 msleep(500);
1131 for (i = 0; i < size; i++) {
1132 if (i == size / 4)
1133 - ssb_printk("25%%");
1134 + ssb_cont("25%%");
1135 else if (i == size / 2)
1136 - ssb_printk("50%%");
1137 + ssb_cont("50%%");
1138 else if (i == (size * 3) / 4)
1139 - ssb_printk("75%%");
1140 + ssb_cont("75%%");
1141 else if (i % 2)
1142 - ssb_printk(".");
1143 + ssb_cont(".");
1144 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
1145 if (err) {
1146 - ssb_printk(KERN_NOTICE PFX
1147 - "Failed to write to SPROM.\n");
1148 + ssb_notice("Failed to write to SPROM\n");
1149 failed = 1;
1150 break;
1151 }
1152 }
1153 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
1154 if (err) {
1155 - ssb_printk(KERN_NOTICE PFX
1156 - "Could not disable SPROM write access.\n");
1157 + ssb_notice("Could not disable SPROM write access\n");
1158 failed = 1;
1159 }
1160 msleep(500);
1161 if (!failed) {
1162 - ssb_printk("100%% ]\n");
1163 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1164 + ssb_cont("100%% ]\n");
1165 + ssb_notice("SPROM written\n");
1166 }
1167
1168 return failed ? -EBUSY : 0;
1169 @@ -700,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
1170 return -ENOSPC; /* continue with next entry */
1171
1172 error:
1173 - ssb_printk(KERN_ERR PFX
1174 + ssb_err(
1175 "PCMCIA: Failed to fetch device invariants: %s\n",
1176 error_description);
1177 return -ENODEV;
1178 @@ -722,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1179 res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
1180 ssb_pcmcia_get_mac, sprom);
1181 if (res != 0) {
1182 - ssb_printk(KERN_ERR PFX
1183 + ssb_err(
1184 "PCMCIA: Failed to fetch MAC address\n");
1185 return -ENODEV;
1186 }
1187 @@ -733,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
1188 if ((res == 0) || (res == -ENOSPC))
1189 return 0;
1190
1191 - ssb_printk(KERN_ERR PFX
1192 + ssb_err(
1193 "PCMCIA: Failed to fetch device invariants\n");
1194 return -ENODEV;
1195 }
1196 @@ -843,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
1197
1198 return 0;
1199 error:
1200 - ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
1201 + ssb_err("Failed to initialize PCMCIA host device\n");
1202 return err;
1203 }
1204 --- a/drivers/ssb/scan.c
1205 +++ b/drivers/ssb/scan.c
1206 @@ -125,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
1207 chipid_fallback = 0x4401;
1208 break;
1209 default:
1210 - ssb_printk(KERN_ERR PFX
1211 - "PCI-ID not in fallback list\n");
1212 + ssb_err("PCI-ID not in fallback list\n");
1213 }
1214
1215 return chipid_fallback;
1216 @@ -152,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
1217 case 0x4704:
1218 return 9;
1219 default:
1220 - ssb_printk(KERN_ERR PFX
1221 - "CHIPID not in nrcores fallback list\n");
1222 + ssb_err("CHIPID not in nrcores fallback list\n");
1223 }
1224
1225 return 1;
1226 @@ -320,15 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
1227 bus->chip_package = 0;
1228 }
1229 }
1230 - ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
1231 - "package 0x%02X\n", bus->chip_id, bus->chip_rev,
1232 - bus->chip_package);
1233 + ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1234 + bus->chip_id, bus->chip_rev, bus->chip_package);
1235 if (!bus->nr_devices)
1236 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1237 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1238 - ssb_printk(KERN_ERR PFX
1239 - "More than %d ssb cores found (%d)\n",
1240 - SSB_MAX_NR_CORES, bus->nr_devices);
1241 + ssb_err("More than %d ssb cores found (%d)\n",
1242 + SSB_MAX_NR_CORES, bus->nr_devices);
1243 goto err_unmap;
1244 }
1245 if (bus->bustype == SSB_BUSTYPE_SSB) {
1246 @@ -370,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1247 nr_80211_cores++;
1248 if (nr_80211_cores > 1) {
1249 if (!we_support_multiple_80211_cores(bus)) {
1250 - ssb_dprintk(KERN_INFO PFX "Ignoring additional "
1251 - "802.11 core\n");
1252 + ssb_dbg("Ignoring additional 802.11 core\n");
1253 continue;
1254 }
1255 }
1256 @@ -379,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1257 case SSB_DEV_EXTIF:
1258 #ifdef CONFIG_SSB_DRIVER_EXTIF
1259 if (bus->extif.dev) {
1260 - ssb_printk(KERN_WARNING PFX
1261 - "WARNING: Multiple EXTIFs found\n");
1262 + ssb_warn("WARNING: Multiple EXTIFs found\n");
1263 break;
1264 }
1265 bus->extif.dev = dev;
1266 @@ -388,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1267 break;
1268 case SSB_DEV_CHIPCOMMON:
1269 if (bus->chipco.dev) {
1270 - ssb_printk(KERN_WARNING PFX
1271 - "WARNING: Multiple ChipCommon found\n");
1272 + ssb_warn("WARNING: Multiple ChipCommon found\n");
1273 break;
1274 }
1275 bus->chipco.dev = dev;
1276 @@ -398,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1277 case SSB_DEV_MIPS_3302:
1278 #ifdef CONFIG_SSB_DRIVER_MIPS
1279 if (bus->mipscore.dev) {
1280 - ssb_printk(KERN_WARNING PFX
1281 - "WARNING: Multiple MIPS cores found\n");
1282 + ssb_warn("WARNING: Multiple MIPS cores found\n");
1283 break;
1284 }
1285 bus->mipscore.dev = dev;
1286 @@ -420,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1287 }
1288 }
1289 if (bus->pcicore.dev) {
1290 - ssb_printk(KERN_WARNING PFX
1291 - "WARNING: Multiple PCI(E) cores found\n");
1292 + ssb_warn("WARNING: Multiple PCI(E) cores found\n");
1293 break;
1294 }
1295 bus->pcicore.dev = dev;
1296 --- a/drivers/ssb/sprom.c
1297 +++ b/drivers/ssb/sprom.c
1298 @@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
1299 while (cnt < sprom_size_words) {
1300 memcpy(tmp, dump, 4);
1301 dump += 4;
1302 - err = strict_strtoul(tmp, 16, &parsed);
1303 + err = kstrtoul(tmp, 16, &parsed);
1304 if (err)
1305 return err;
1306 sprom[cnt++] = swab16((u16)parsed);
1307 @@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1308 goto out_kfree;
1309 err = ssb_devices_freeze(bus, &freeze);
1310 if (err) {
1311 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
1312 + ssb_err("SPROM write: Could not freeze all devices\n");
1313 goto out_unlock;
1314 }
1315 res = sprom_write(bus, sprom);
1316 err = ssb_devices_thaw(&freeze);
1317 if (err)
1318 - ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
1319 + ssb_err("SPROM write: Could not thaw all devices\n");
1320 out_unlock:
1321 mutex_unlock(&bus->sprom_mutex);
1322 out_kfree:
1323 --- a/drivers/ssb/ssb_private.h
1324 +++ b/drivers/ssb/ssb_private.h
1325 @@ -9,16 +9,27 @@
1326 #define PFX "ssb: "
1327
1328 #ifdef CONFIG_SSB_SILENT
1329 -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
1330 +# define ssb_printk(fmt, ...) \
1331 + do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
1332 #else
1333 -# define ssb_printk printk
1334 +# define ssb_printk(fmt, ...) \
1335 + printk(fmt, ##__VA_ARGS__)
1336 #endif /* CONFIG_SSB_SILENT */
1337
1338 +#define ssb_emerg(fmt, ...) ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
1339 +#define ssb_err(fmt, ...) ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
1340 +#define ssb_warn(fmt, ...) ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
1341 +#define ssb_notice(fmt, ...) ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
1342 +#define ssb_info(fmt, ...) ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
1343 +#define ssb_cont(fmt, ...) ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
1344 +
1345 /* dprintk: Debugging printk; vanishes for non-debug compilation */
1346 #ifdef CONFIG_SSB_DEBUG
1347 -# define ssb_dprintk(fmt, x...) ssb_printk(fmt , ##x)
1348 +# define ssb_dbg(fmt, ...) \
1349 + ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
1350 #else
1351 -# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0)
1352 +# define ssb_dbg(fmt, ...) \
1353 + do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
1354 #endif
1355
1356 #ifdef CONFIG_SSB_DEBUG
1357 @@ -217,6 +228,25 @@ extern u32 ssb_chipco_watchdog_timer_set
1358 u32 ticks);
1359 extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
1360
1361 +/* driver_chipcommon_sflash.c */
1362 +#ifdef CONFIG_SSB_SFLASH
1363 +int ssb_sflash_init(struct ssb_chipcommon *cc);
1364 +#else
1365 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
1366 +{
1367 + pr_err("Serial flash not supported\n");
1368 + return 0;
1369 +}
1370 +#endif /* CONFIG_SSB_SFLASH */
1371 +
1372 +#ifdef CONFIG_SSB_DRIVER_MIPS
1373 +extern struct platform_device ssb_pflash_dev;
1374 +#endif
1375 +
1376 +#ifdef CONFIG_SSB_SFLASH
1377 +extern struct platform_device ssb_sflash_dev;
1378 +#endif
1379 +
1380 #ifdef CONFIG_SSB_DRIVER_EXTIF
1381 extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
1382 extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
1383 --- a/include/linux/ssb/ssb.h
1384 +++ b/include/linux/ssb/ssb.h
1385 @@ -26,13 +26,14 @@ struct ssb_sprom_core_pwr_info {
1386
1387 struct ssb_sprom {
1388 u8 revision;
1389 - u8 il0mac[6]; /* MAC address for 802.11b/g */
1390 - u8 et0mac[6]; /* MAC address for Ethernet */
1391 - u8 et1mac[6]; /* MAC address for 802.11a */
1392 + u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */
1393 + u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */
1394 + u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */
1395 u8 et0phyaddr; /* MII address for enet0 */
1396 u8 et1phyaddr; /* MII address for enet1 */
1397 u8 et0mdcport; /* MDIO for enet0 */
1398 u8 et1mdcport; /* MDIO for enet1 */
1399 + u16 dev_id; /* Device ID overriding e.g. PCI ID */
1400 u16 board_rev; /* Board revision number from SPROM. */
1401 u16 board_num; /* Board number from SPROM. */
1402 u16 board_type; /* Board type from SPROM. */
1403 @@ -340,13 +341,61 @@ enum ssb_bustype {
1404 #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
1405 #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
1406 /* board_type */
1407 +#define SSB_BOARD_BCM94301CB 0x0406
1408 +#define SSB_BOARD_BCM94301MP 0x0407
1409 +#define SSB_BOARD_BU4309 0x040A
1410 +#define SSB_BOARD_BCM94309CB 0x040B
1411 +#define SSB_BOARD_BCM4309MP 0x040C
1412 +#define SSB_BOARD_BU4306 0x0416
1413 #define SSB_BOARD_BCM94306MP 0x0418
1414 #define SSB_BOARD_BCM4309G 0x0421
1415 #define SSB_BOARD_BCM4306CB 0x0417
1416 -#define SSB_BOARD_BCM4309MP 0x040C
1417 +#define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */
1418 +#define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */
1419 +#define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */
1420 +#define SSB_BOARD_BU4704SD 0x042E /* with sdram */
1421 +#define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */
1422 +#define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */
1423 +#define SSB_BOARD_BU4318 0x0447
1424 +#define SSB_BOARD_CB4318 0x0448
1425 +#define SSB_BOARD_MPG4318 0x0449
1426 #define SSB_BOARD_MP4318 0x044A
1427 -#define SSB_BOARD_BU4306 0x0416
1428 -#define SSB_BOARD_BU4309 0x040A
1429 +#define SSB_BOARD_SD4318 0x044B
1430 +#define SSB_BOARD_BCM94306P 0x044C /* with SiGe */
1431 +#define SSB_BOARD_BCM94303MP 0x044E
1432 +#define SSB_BOARD_BCM94306MPM 0x0450
1433 +#define SSB_BOARD_BCM94306MPL 0x0453
1434 +#define SSB_BOARD_PC4303 0x0454 /* pcmcia */
1435 +#define SSB_BOARD_BCM94306MPLNA 0x0457
1436 +#define SSB_BOARD_BCM94306MPH 0x045B
1437 +#define SSB_BOARD_BCM94306PCIV 0x045C
1438 +#define SSB_BOARD_BCM94318MPGH 0x0463
1439 +#define SSB_BOARD_BU4311 0x0464
1440 +#define SSB_BOARD_BCM94311MC 0x0465
1441 +#define SSB_BOARD_BCM94311MCAG 0x0466
1442 +/* 4321 boards */
1443 +#define SSB_BOARD_BU4321 0x046B
1444 +#define SSB_BOARD_BU4321E 0x047C
1445 +#define SSB_BOARD_MP4321 0x046C
1446 +#define SSB_BOARD_CB2_4321 0x046D
1447 +#define SSB_BOARD_CB2_4321_AG 0x0066
1448 +#define SSB_BOARD_MC4321 0x046E
1449 +/* 4325 boards */
1450 +#define SSB_BOARD_BCM94325DEVBU 0x0490
1451 +#define SSB_BOARD_BCM94325BGABU 0x0491
1452 +#define SSB_BOARD_BCM94325SDGWB 0x0492
1453 +#define SSB_BOARD_BCM94325SDGMDL 0x04AA
1454 +#define SSB_BOARD_BCM94325SDGMDL2 0x04C6
1455 +#define SSB_BOARD_BCM94325SDGMDL3 0x04C9
1456 +#define SSB_BOARD_BCM94325SDABGWBA 0x04E1
1457 +/* 4322 boards */
1458 +#define SSB_BOARD_BCM94322MC 0x04A4
1459 +#define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */
1460 +#define SSB_BOARD_BCM94322HM 0x04B0
1461 +#define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */
1462 +/* 4312 boards */
1463 +#define SSB_BOARD_BU4312 0x048A
1464 +#define SSB_BOARD_BCM4312MCGSG 0x04B5
1465 /* chip_package */
1466 #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
1467 #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
1468 --- a/include/linux/ssb/ssb_driver_gige.h
1469 +++ b/include/linux/ssb/ssb_driver_gige.h
1470 @@ -97,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
1471 return 0;
1472 }
1473
1474 -#ifdef CONFIG_BCM47XX
1475 -#include <asm/mach-bcm47xx/nvram.h>
1476 /* Get the device MAC address */
1477 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
1478 -{
1479 - char buf[20];
1480 - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
1481 - return;
1482 - nvram_parse_macaddr(buf, macaddr);
1483 -}
1484 -#else
1485 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
1486 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
1487 {
1488 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
1489 + if (!dev)
1490 + return -ENODEV;
1491 +
1492 + memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
1493 + return 0;
1494 }
1495 -#endif
1496
1497 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
1498 struct pci_dev *pdev);
1499 @@ -175,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
1500 {
1501 return 0;
1502 }
1503 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
1504 +{
1505 + return -ENODEV;
1506 +}
1507
1508 #endif /* CONFIG_SSB_DRIVER_GIGE */
1509 #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
1510 --- a/include/linux/ssb/ssb_driver_mips.h
1511 +++ b/include/linux/ssb/ssb_driver_mips.h
1512 @@ -20,6 +20,18 @@ struct ssb_pflash {
1513 u32 window_size;
1514 };
1515
1516 +#ifdef CONFIG_SSB_SFLASH
1517 +struct ssb_sflash {
1518 + bool present;
1519 + u32 window;
1520 + u32 blocksize;
1521 + u16 numblocks;
1522 + u32 size;
1523 +
1524 + void *priv;
1525 +};
1526 +#endif
1527 +
1528 struct ssb_mipscore {
1529 struct ssb_device *dev;
1530
1531 @@ -27,6 +39,9 @@ struct ssb_mipscore {
1532 struct ssb_serial_port serial_ports[4];
1533
1534 struct ssb_pflash pflash;
1535 +#ifdef CONFIG_SSB_SFLASH
1536 + struct ssb_sflash sflash;
1537 +#endif
1538 };
1539
1540 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
1541 @@ -45,6 +60,11 @@ void ssb_mipscore_init(struct ssb_mipsco
1542 {
1543 }
1544
1545 +static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
1546 +{
1547 + return 0;
1548 +}
1549 +
1550 #endif /* CONFIG_SSB_DRIVER_MIPS */
1551
1552 #endif /* LINUX_SSB_MIPSCORE_H_ */
1553 --- a/include/linux/ssb/ssb_regs.h
1554 +++ b/include/linux/ssb/ssb_regs.h
1555 @@ -172,6 +172,7 @@
1556 #define SSB_SPROMSIZE_WORDS_R4 220
1557 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
1558 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
1559 +#define SSB_SPROMSIZE_WORDS_R10 230
1560 #define SSB_SPROM_BASE1 0x1000
1561 #define SSB_SPROM_BASE31 0x0800
1562 #define SSB_SPROM_REVISION 0x007E
1563 @@ -289,11 +290,11 @@
1564 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
1565 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
1566 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
1567 -#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
1568 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
1569 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
1570 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
1571 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
1572 +#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
1573 +#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1574 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
1575 +#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1576 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
1577 #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
1578 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
1579 #define SSB_SPROM4_AGAIN0_SHIFT 0
1580 --- a/arch/mips/bcm47xx/sprom.c
1581 +++ b/arch/mips/bcm47xx/sprom.c
1582 @@ -168,6 +168,7 @@ static void nvram_read_alpha2(const char
1583 static void bcm47xx_fill_sprom_r1234589(struct ssb_sprom *sprom,
1584 const char *prefix, bool fallback)
1585 {
1586 + nvram_read_u16(prefix, NULL, "devid", &sprom->dev_id, 0, fallback);
1587 nvram_read_u8(prefix, NULL, "ledbh0", &sprom->gpio0, 0xff, fallback);
1588 nvram_read_u8(prefix, NULL, "ledbh1", &sprom->gpio1, 0xff, fallback);
1589 nvram_read_u8(prefix, NULL, "ledbh2", &sprom->gpio2, 0xff, fallback);
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