target/linux/imx6/files-4.1/drivers/net/phy/gw16083.h

   1 /*
   2  * drivers/net/phy/mv88e6176.h
   3  *
   4  * Driver for Marvell Switch
   5  *
   6  * Author: Tim Harvey
   7  *
   8  * Copyright (c) 2014 Tim Harvey <tharvey@gateworks.com>
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #ifndef _GW16083_H_
  18 #define _GW16083_H_
  19
  20 #define MII_MARVELL_PHY_PAGE            22
  21
  22 /*
  23  * I2C Addresses
  24  */
  25 #define GW16083_I2C_ADDR_SFP1           0x50
  26 #define GW16083_I2C_ADDR_SFP2           0x51
  27 #define GW16083_I2C_ADDR_EEPROM         0x52
  28 #define GW16083_I2C_ADDR_PCA9543        0x70
  29
  30 /*
  31  * MV88E1111 PHY Registers
  32  */
  33 enum {
  34         MII_M1111_PHY_CONTROL           = 0,
  35         MII_M1111_PHY_STATUS            = 1,
  36         MII_M1111_PHY_IDENT0            = 2,
  37         MII_M1111_PHY_IDENT1            = 3,
  38         MII_M1111_PHY_EXT_CR            = 20,
  39         MII_M1111_PHY_LED_CONTROL       = 24,
  40         MII_M1111_PHY_EXT_SR            = 27,
  41 };
  42
  43 #define MII_M1111_PHY_ID_MASK           0xfffffff0
  44 #define MII_M1111_PHY_ID                0x01410cc0
  45
  46 #define MII_M1111_PHY_CONTROL_RESET     (1 << 15)
  47 #define MII_M1111_PHY_LED_DIRECT        0x4100
  48 #define MII_M1111_PHY_LED_PULSE_STR     0x4111
  49 #define MII_M1111_PHY_LED_COMBINE       0x411c
  50 #define MII_M1111_RX_DELAY              0x80
  51 #define MII_M1111_TX_DELAY              0x2
  52
  53 /*
  54  * MV88E6176 Switch Registers
  55  */
  56
  57 /* PHY Addrs */
  58 #define MV_BASE         0x10
  59 #define MV_GLOBAL1      0x1b
  60 #define MV_GLOBAL2      0x1c
  61 #define MV_GLOBAL3      0x1d
  62
  63 /* Global2 Registers */
  64 enum {
  65         MV_SMI_PHY_COMMAND      = 0x18,
  66         MV_SMI_PHY_DATA         = 0x19,
  67         MV_SCRATCH_MISC         = 0x1A,
  68 };
  69
  70 /* Scratch And Misc Reg offsets */
  71 enum {
  72         MV_GPIO_MODE            = 0x60,
  73         MV_GPIO_DIR             = 0x62,
  74         MV_GPIO_DATA            = 0x64,
  75         MV_GPIO76_CNTL          = 0x6B,
  76         MV_GPIO54_CNTL          = 0x6A,
  77         MV_GPIO32_CNTL          = 0x69,
  78         MV_GPIO10_CNTL          = 0x68,
  79         MV_CONFIG0              = 0x70,
  80         MV_CONFIG1              = 0x71,
  81         MV_CONFIG2              = 0x72,
  82         MV_CONFIG3              = 0x73,
  83 };
  84
  85 /* PHY Registers */
  86 enum {
  87         MV_PHY_CONTROL      = 0x00,
  88         MV_PHY_STATUS       = 0x01,
  89         MV_PHY_IDENT0       = 0x02,
  90         MV_PHY_IDENT1       = 0x03,
  91         MV_PHY_ANEG         = 0x04,
  92         MV_PHY_LINK_ABILITY = 0x05,
  93         MV_PHY_ANEG_EXPAND  = 0x06,
  94         MV_PHY_XMIT_NEXTP   = 0x07,
  95         MV_PHY_LINK_NEXTP   = 0x08,
  96         MV_PHY_CONTROL1     = 0x10,
  97         MV_PHY_STATUS1      = 0x11,
  98         MV_PHY_INTR_EN      = 0x12,
  99 };
 100
 101 /* Port Registers */
 102 enum {
 103         MV_PORT_STATUS          = 0x00,
 104         MV_PORT_PHYS_CONTROL    = 0x01,
 105         MV_PORT_IDENT           = 0x03,
 106         MV_PORT_CONTROL         = 0x04,
 107         MV_PORT_VLANMAP         = 0x06,
 108         MV_PORT_ASSOC           = 0x0b,
 109         MV_PORT_RXCOUNT         = 0x10,
 110         MV_PORT_TXCOUNT         = 0x11,
 111 };
 112
 113 #define SMIBUSY         (1<<15)
 114 #define SMIMODE22       (1<<12)
 115 #define SMIOP_READ      (2<<10)
 116 #define SMIOP_WRITE     (1<<10)
 117 #define DEVADDR         5
 118 #define REGADDR         0
 119
 120 #define MV_IDENT_MASK           0x0000fff0
 121 #define MV_IDENT_VALUE          0x00001760
 122
 123 #endif /* _GW16083_H_ */