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[openwrt/staging/yousong.git] / target / linux / ipq806x / patches-4.4 / 179-clk-qcom-Add-support-for-RPM-Clocks.patch
1 !This is the adjusted version of patch that has been submitted to upstream and that, unfortunately, provides support for RPM clocks only for apq8064 board.
2
3 !TODO: make a patch that adds support for ipq806x along with apq8064 and not replaces it.
4
5 From patchwork Wed Nov 2 15:56:57 2016
6 Content-Type: text/plain; charset="utf-8"
7 MIME-Version: 1.0
8 Content-Transfer-Encoding: 7bit
9 Subject: [v9,2/3] clk: qcom: Add support for RPM Clocks
10 From: Georgi Djakov <georgi.djakov@linaro.org>
11 X-Patchwork-Id: 9409425
12 Message-Id: <20161102155658.32203-3-georgi.djakov@linaro.org>
13 To: sboyd@codeaurora.org, mturquette@baylibre.com
14 Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
15 robh+dt@kernel.org, mark.rutland@arm.com,
16 linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
17 georgi.djakov@linaro.org
18 Date: Wed, 2 Nov 2016 17:56:57 +0200
19
20 This adds initial support for clocks controlled by the Resource
21 Power Manager (RPM) processor on some Qualcomm SoCs, which use
22 the qcom_rpm driver to communicate with RPM.
23 Such platforms are ipq806x and msm8960.
24
25 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
26 ---
27 .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
28 drivers/clk/qcom/Kconfig | 13 +
29 drivers/clk/qcom/Makefile | 1 +
30 drivers/clk/qcom/clk-rpm.c | 489 +++++++++++++++++++++
31 include/dt-bindings/clock/qcom,rpmcc.h | 24 +
32 5 files changed, 528 insertions(+)
33 create mode 100644 drivers/clk/qcom/clk-rpm.c
34
35 --
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37 the body of a message to majordomo@vger.kernel.org
38 More majordomo info at http://vger.kernel.org/majordomo-info.html
39
40 --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
41 +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
42 @@ -11,6 +11,7 @@ Required properties :
43 compatible "qcom,rpmcc" should be also included.
44
45 "qcom,rpmcc-msm8916", "qcom,rpmcc"
46 + "qcom,rpmcc-ipq806x", "qcom,rpmcc"
47
48 - #clock-cells : shall contain 1
49
50 --- a/drivers/clk/qcom/Kconfig
51 +++ b/drivers/clk/qcom/Kconfig
52 @@ -12,6 +12,19 @@ config COMMON_CLK_QCOM
53 select REGMAP_MMIO
54 select RESET_CONTROLLER
55
56 +config QCOM_CLK_RPM
57 + tristate "RPM based Clock Controller"
58 + depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
59 + select QCOM_RPMCC
60 + help
61 + The RPM (Resource Power Manager) is a dedicated hardware engine for
62 + managing the shared SoC resources in order to keep the lowest power
63 + profile. It communicates with other hardware subsystems via shared
64 + memory and accepts clock requests, aggregates the requests and turns
65 + the clocks on/off or scales them on demand.
66 + Say Y if you want to support the clocks exposed by the RPM on
67 + platforms such as ipq806x, msm8660, msm8960 etc.
68 +
69 config QCOM_CLK_SMD_RPM
70 tristate "RPM over SMD based Clock Controller"
71 depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
72 --- a/drivers/clk/qcom/Makefile
73 +++ b/drivers/clk/qcom/Makefile
74 @@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8
75 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
76 obj-$(CONFIG_KRAITCC) += krait-cc.o
77 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
78 +obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
79 --- /dev/null
80 +++ b/drivers/clk/qcom/clk-rpm.c
81 @@ -0,0 +1,486 @@
82 +/*
83 + * Copyright (c) 2016, Linaro Limited
84 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
85 + *
86 + * This software is licensed under the terms of the GNU General Public
87 + * License version 2, as published by the Free Software Foundation, and
88 + * may be copied, distributed, and modified under those terms.
89 + *
90 + * This program is distributed in the hope that it will be useful,
91 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
92 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
93 + * GNU General Public License for more details.
94 + */
95 +
96 +#include <linux/clk-provider.h>
97 +#include <linux/err.h>
98 +#include <linux/export.h>
99 +#include <linux/init.h>
100 +#include <linux/kernel.h>
101 +#include <linux/module.h>
102 +#include <linux/mutex.h>
103 +#include <linux/mfd/qcom_rpm.h>
104 +#include <linux/of.h>
105 +#include <linux/of_device.h>
106 +#include <linux/platform_device.h>
107 +
108 +#include <dt-bindings/mfd/qcom-rpm.h>
109 +#include <dt-bindings/clock/qcom,rpmcc.h>
110 +
111 +#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
112 +#define QCOM_RPM_SCALING_ENABLE_ID 0x2
113 +
114 +#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
115 + static struct clk_rpm _platform##_##_active; \
116 + static struct clk_rpm _platform##_##_name = { \
117 + .rpm_clk_id = (r_id), \
118 + .peer = &_platform##_##_active, \
119 + .rate = INT_MAX, \
120 + .hw.init = &(struct clk_init_data){ \
121 + .ops = &clk_rpm_ops, \
122 + .name = #_name, \
123 + .parent_names = (const char *[]){ "pxo_board" }, \
124 + .num_parents = 1, \
125 + }, \
126 + }; \
127 + static struct clk_rpm _platform##_##_active = { \
128 + .rpm_clk_id = (r_id), \
129 + .peer = &_platform##_##_name, \
130 + .active_only = true, \
131 + .rate = INT_MAX, \
132 + .hw.init = &(struct clk_init_data){ \
133 + .ops = &clk_rpm_ops, \
134 + .name = #_active, \
135 + .parent_names = (const char *[]){ "pxo_board" }, \
136 + .num_parents = 1, \
137 + }, \
138 + }
139 +
140 +#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
141 + static struct clk_rpm _platform##_##_active; \
142 + static struct clk_rpm _platform##_##_name = { \
143 + .rpm_clk_id = (r_id), \
144 + .active_only = true, \
145 + .peer = &_platform##_##_active, \
146 + .rate = (r), \
147 + .branch = true, \
148 + .hw.init = &(struct clk_init_data){ \
149 + .ops = &clk_rpm_branch_ops, \
150 + .name = #_name, \
151 + .parent_names = (const char *[]){ "pxo_board" }, \
152 + .num_parents = 1, \
153 + }, \
154 + }; \
155 + static struct clk_rpm _platform##_##_active = { \
156 + .rpm_clk_id = (r_id), \
157 + .peer = &_platform##_##_name, \
158 + .rate = (r), \
159 + .branch = true, \
160 + .hw.init = &(struct clk_init_data){ \
161 + .ops = &clk_rpm_branch_ops, \
162 + .name = #_active, \
163 + .parent_names = (const char *[]){ "pxo_board" }, \
164 + .num_parents = 1, \
165 + }, \
166 + }
167 +
168 +#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
169 + static struct clk_rpm _platform##_##_active; \
170 + static struct clk_rpm _platform##_##_name = { \
171 + .rpm_clk_id = (r_id), \
172 + .peer = &_platform##_##_active, \
173 + .rate = (r), \
174 + .branch = true, \
175 + .hw.init = &(struct clk_init_data){ \
176 + .ops = &clk_rpm_branch_ops, \
177 + .name = #_name, \
178 + .parent_names = (const char *[]){ "cxo_board" }, \
179 + .num_parents = 1, \
180 + }, \
181 + }; \
182 + static struct clk_rpm _platform##_##_active = { \
183 + .rpm_clk_id = (r_id), \
184 + .active_only = true, \
185 + .peer = &_platform##_##_name, \
186 + .rate = (r), \
187 + .branch = true, \
188 + .hw.init = &(struct clk_init_data){ \
189 + .ops = &clk_rpm_branch_ops, \
190 + .name = #_active, \
191 + .parent_names = (const char *[]){ "cxo_board" }, \
192 + .num_parents = 1, \
193 + }, \
194 + }
195 +
196 +#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
197 +
198 +struct clk_rpm {
199 + const int rpm_clk_id;
200 + const bool active_only;
201 + unsigned long rate;
202 + bool enabled;
203 + bool branch;
204 + struct clk_rpm *peer;
205 + struct clk_hw hw;
206 + struct qcom_rpm *rpm;
207 +};
208 +
209 +struct rpm_cc {
210 + struct qcom_rpm *rpm;
211 + struct clk_hw_onecell_data data;
212 + struct clk_hw *hws[];
213 +};
214 +
215 +struct rpm_clk_desc {
216 + struct clk_rpm **clks;
217 + size_t num_clks;
218 +};
219 +
220 +static DEFINE_MUTEX(rpm_clk_lock);
221 +
222 +static int clk_rpm_handoff(struct clk_rpm *r)
223 +{
224 + int ret;
225 + u32 value = INT_MAX;
226 +
227 + ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
228 + r->rpm_clk_id, &value, 1);
229 + if (ret)
230 + return ret;
231 + ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
232 + r->rpm_clk_id, &value, 1);
233 + if (ret)
234 + return ret;
235 +
236 + return 0;
237 +}
238 +
239 +static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
240 +{
241 + u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
242 +
243 + return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
244 + r->rpm_clk_id, &value, 1);
245 +}
246 +
247 +static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
248 +{
249 + u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
250 +
251 + return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
252 + r->rpm_clk_id, &value, 1);
253 +}
254 +
255 +static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
256 + unsigned long *active, unsigned long *sleep)
257 +{
258 + *active = rate;
259 +
260 + /*
261 + * Active-only clocks don't care what the rate is during sleep. So,
262 + * they vote for zero.
263 + */
264 + if (r->active_only)
265 + *sleep = 0;
266 + else
267 + *sleep = *active;
268 +}
269 +
270 +static int clk_rpm_prepare(struct clk_hw *hw)
271 +{
272 + struct clk_rpm *r = to_clk_rpm(hw);
273 + struct clk_rpm *peer = r->peer;
274 + unsigned long this_rate = 0, this_sleep_rate = 0;
275 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
276 + unsigned long active_rate, sleep_rate;
277 + int ret = 0;
278 +
279 + mutex_lock(&rpm_clk_lock);
280 +
281 + /* Don't send requests to the RPM if the rate has not been set. */
282 + if (!r->rate)
283 + goto out;
284 +
285 + to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
286 +
287 + /* Take peer clock's rate into account only if it's enabled. */
288 + if (peer->enabled)
289 + to_active_sleep(peer, peer->rate,
290 + &peer_rate, &peer_sleep_rate);
291 +
292 + active_rate = max(this_rate, peer_rate);
293 +
294 + if (r->branch)
295 + active_rate = !!active_rate;
296 +
297 + ret = clk_rpm_set_rate_active(r, active_rate);
298 + if (ret)
299 + goto out;
300 +
301 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
302 + if (r->branch)
303 + sleep_rate = !!sleep_rate;
304 +
305 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
306 + if (ret)
307 + /* Undo the active set vote and restore it */
308 + ret = clk_rpm_set_rate_active(r, peer_rate);
309 +
310 +out:
311 + if (!ret)
312 + r->enabled = true;
313 +
314 + mutex_unlock(&rpm_clk_lock);
315 +
316 + return ret;
317 +}
318 +
319 +static void clk_rpm_unprepare(struct clk_hw *hw)
320 +{
321 + struct clk_rpm *r = to_clk_rpm(hw);
322 + struct clk_rpm *peer = r->peer;
323 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
324 + unsigned long active_rate, sleep_rate;
325 + int ret;
326 +
327 + mutex_lock(&rpm_clk_lock);
328 +
329 + if (!r->rate)
330 + goto out;
331 +
332 + /* Take peer clock's rate into account only if it's enabled. */
333 + if (peer->enabled)
334 + to_active_sleep(peer, peer->rate, &peer_rate,
335 + &peer_sleep_rate);
336 +
337 + active_rate = r->branch ? !!peer_rate : peer_rate;
338 + ret = clk_rpm_set_rate_active(r, active_rate);
339 + if (ret)
340 + goto out;
341 +
342 + sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
343 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
344 + if (ret)
345 + goto out;
346 +
347 + r->enabled = false;
348 +
349 +out:
350 + mutex_unlock(&rpm_clk_lock);
351 +}
352 +
353 +static int clk_rpm_set_rate(struct clk_hw *hw,
354 + unsigned long rate, unsigned long parent_rate)
355 +{
356 + struct clk_rpm *r = to_clk_rpm(hw);
357 + struct clk_rpm *peer = r->peer;
358 + unsigned long active_rate, sleep_rate;
359 + unsigned long this_rate = 0, this_sleep_rate = 0;
360 + unsigned long peer_rate = 0, peer_sleep_rate = 0;
361 + int ret = 0;
362 +
363 + mutex_lock(&rpm_clk_lock);
364 +
365 + if (!r->enabled)
366 + goto out;
367 +
368 + to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
369 +
370 + /* Take peer clock's rate into account only if it's enabled. */
371 + if (peer->enabled)
372 + to_active_sleep(peer, peer->rate,
373 + &peer_rate, &peer_sleep_rate);
374 +
375 + active_rate = max(this_rate, peer_rate);
376 + ret = clk_rpm_set_rate_active(r, active_rate);
377 + if (ret)
378 + goto out;
379 +
380 + sleep_rate = max(this_sleep_rate, peer_sleep_rate);
381 + ret = clk_rpm_set_rate_sleep(r, sleep_rate);
382 + if (ret)
383 + goto out;
384 +
385 + r->rate = rate;
386 +
387 +out:
388 + mutex_unlock(&rpm_clk_lock);
389 +
390 + return ret;
391 +}
392 +
393 +static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
394 + unsigned long *parent_rate)
395 +{
396 + /*
397 + * RPM handles rate rounding and we don't have a way to
398 + * know what the rate will be, so just return whatever
399 + * rate is requested.
400 + */
401 + return rate;
402 +}
403 +
404 +static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
405 + unsigned long parent_rate)
406 +{
407 + struct clk_rpm *r = to_clk_rpm(hw);
408 +
409 + /*
410 + * RPM handles rate rounding and we don't have a way to
411 + * know what the rate will be, so just return whatever
412 + * rate was set.
413 + */
414 + return r->rate;
415 +}
416 +
417 +static const struct clk_ops clk_rpm_ops = {
418 + .prepare = clk_rpm_prepare,
419 + .unprepare = clk_rpm_unprepare,
420 + .set_rate = clk_rpm_set_rate,
421 + .round_rate = clk_rpm_round_rate,
422 + .recalc_rate = clk_rpm_recalc_rate,
423 +};
424 +
425 +static const struct clk_ops clk_rpm_branch_ops = {
426 + .prepare = clk_rpm_prepare,
427 + .unprepare = clk_rpm_unprepare,
428 + .round_rate = clk_rpm_round_rate,
429 + .recalc_rate = clk_rpm_recalc_rate,
430 +};
431 +
432 +/* ipq806x */
433 +DEFINE_CLK_RPM(ipq806x, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
434 +DEFINE_CLK_RPM(ipq806x, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
435 +DEFINE_CLK_RPM(ipq806x, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
436 +DEFINE_CLK_RPM(ipq806x, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
437 +DEFINE_CLK_RPM(ipq806x, nss_fabric_0_clk, nss_fabric_0_a_clk, QCOM_RPM_NSS_FABRIC_0_CLK);
438 +DEFINE_CLK_RPM(ipq806x, nss_fabric_1_clk, nss_fabric_1_a_clk, QCOM_RPM_NSS_FABRIC_1_CLK);
439 +DEFINE_CLK_RPM(ipq806x, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
440 +DEFINE_CLK_RPM(ipq806x, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
441 +
442 +static struct clk_rpm *ipq806x_clks[] = {
443 + [RPM_APPS_FABRIC_CLK] = &ipq806x_afab_clk,
444 + [RPM_APPS_FABRIC_A_CLK] = &ipq806x_afab_a_clk,
445 + [RPM_CFPB_CLK] = &ipq806x_cfpb_clk,
446 + [RPM_CFPB_A_CLK] = &ipq806x_cfpb_a_clk,
447 + [RPM_DAYTONA_FABRIC_CLK] = &ipq806x_daytona_clk,
448 + [RPM_DAYTONA_FABRIC_A_CLK] = &ipq806x_daytona_a_clk,
449 + [RPM_EBI1_CLK] = &ipq806x_ebi1_clk,
450 + [RPM_EBI1_A_CLK] = &ipq806x_ebi1_a_clk,
451 + [RPM_NSS_FABRIC_0_CLK] = &ipq806x_nss_fabric_0_clk,
452 + [RPM_NSS_FABRIC_0_A_CLK] = &ipq806x_nss_fabric_0_a_clk,
453 + [RPM_NSS_FABRIC_1_CLK] = &ipq806x_nss_fabric_1_clk,
454 + [RPM_NSS_FABRIC_1_A_CLK] = &ipq806x_nss_fabric_1_a_clk,
455 + [RPM_SYS_FABRIC_CLK] = &ipq806x_sfab_clk,
456 + [RPM_SYS_FABRIC_A_CLK] = &ipq806x_sfab_a_clk,
457 + [RPM_SFPB_CLK] = &ipq806x_sfpb_clk,
458 + [RPM_SFPB_A_CLK] = &ipq806x_sfpb_a_clk,
459 +};
460 +
461 +static const struct rpm_clk_desc rpm_clk_ipq806x = {
462 + .clks = ipq806x_clks,
463 + .num_clks = ARRAY_SIZE(ipq806x_clks),
464 +};
465 +
466 +static const struct of_device_id rpm_clk_match_table[] = {
467 + { .compatible = "qcom,rpmcc-ipq806x", .data = &rpm_clk_ipq806x },
468 + { }
469 +};
470 +MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
471 +
472 +static int rpm_clk_probe(struct platform_device *pdev)
473 +{
474 + struct clk_hw **hws;
475 + struct rpm_cc *rcc;
476 + struct clk_hw_onecell_data *data;
477 + int ret;
478 + size_t num_clks, i;
479 + struct qcom_rpm *rpm;
480 + struct clk_rpm **rpm_clks;
481 + const struct rpm_clk_desc *desc;
482 +
483 + rpm = dev_get_drvdata(pdev->dev.parent);
484 + if (!rpm) {
485 + dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
486 + return -ENODEV;
487 + }
488 +
489 + desc = of_device_get_match_data(&pdev->dev);
490 + if (!desc)
491 + return -EINVAL;
492 +
493 + rpm_clks = desc->clks;
494 + num_clks = desc->num_clks;
495 +
496 + rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
497 + GFP_KERNEL);
498 + if (!rcc)
499 + return -ENOMEM;
500 +
501 + hws = rcc->hws;
502 + data = &rcc->data;
503 + data->num = num_clks;
504 +
505 + for (i = 0; i < num_clks; i++) {
506 + if (!rpm_clks[i])
507 + continue;
508 +
509 + rpm_clks[i]->rpm = rpm;
510 +
511 + ret = clk_rpm_handoff(rpm_clks[i]);
512 + if (ret)
513 + goto err;
514 + }
515 +
516 + for (i = 0; i < num_clks; i++) {
517 + if (!rpm_clks[i]) {
518 + data->hws[i] = ERR_PTR(-ENOENT);
519 + continue;
520 + }
521 +
522 + ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
523 + if (ret)
524 + goto err;
525 + }
526 +
527 + ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
528 + data);
529 + if (ret)
530 + goto err;
531 +
532 + return 0;
533 +err:
534 + dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
535 + return ret;
536 +}
537 +
538 +static int rpm_clk_remove(struct platform_device *pdev)
539 +{
540 + of_clk_del_provider(pdev->dev.of_node);
541 + return 0;
542 +}
543 +
544 +static struct platform_driver rpm_clk_driver = {
545 + .driver = {
546 + .name = "qcom-clk-rpm",
547 + .of_match_table = rpm_clk_match_table,
548 + },
549 + .probe = rpm_clk_probe,
550 + .remove = rpm_clk_remove,
551 +};
552 +
553 +static int __init rpm_clk_init(void)
554 +{
555 + return platform_driver_register(&rpm_clk_driver);
556 +}
557 +core_initcall(rpm_clk_init);
558 +
559 +static void __exit rpm_clk_exit(void)
560 +{
561 + platform_driver_unregister(&rpm_clk_driver);
562 +}
563 +module_exit(rpm_clk_exit);
564 +
565 +MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
566 +MODULE_LICENSE("GPL v2");
567 +MODULE_ALIAS("platform:qcom-clk-rpm");
568 --- a/include/dt-bindings/clock/qcom,rpmcc.h
569 +++ b/include/dt-bindings/clock/qcom,rpmcc.h
570 @@ -14,6 +14,28 @@
571 #ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
572 #define _DT_BINDINGS_CLK_MSM_RPMCC_H
573
574 +/* ipq806x */
575 +#define RPM_PXO_CLK 0
576 +#define RPM_PXO_A_CLK 1
577 +#define RPM_CXO_CLK 2
578 +#define RPM_CXO_A_CLK 3
579 +#define RPM_APPS_FABRIC_CLK 4
580 +#define RPM_APPS_FABRIC_A_CLK 5
581 +#define RPM_CFPB_CLK 6
582 +#define RPM_CFPB_A_CLK 7
583 +#define RPM_DAYTONA_FABRIC_CLK 8
584 +#define RPM_DAYTONA_FABRIC_A_CLK 9
585 +#define RPM_EBI1_CLK 10
586 +#define RPM_EBI1_A_CLK 11
587 +#define RPM_NSS_FABRIC_0_CLK 12
588 +#define RPM_NSS_FABRIC_0_A_CLK 13
589 +#define RPM_NSS_FABRIC_1_CLK 14
590 +#define RPM_NSS_FABRIC_1_A_CLK 15
591 +#define RPM_SYS_FABRIC_CLK 16
592 +#define RPM_SYS_FABRIC_A_CLK 17
593 +#define RPM_SFPB_CLK 18
594 +#define RPM_SFPB_A_CLK 19
595 +
596 /* msm8916 */
597 #define RPM_SMD_XO_CLK_SRC 0
598 #define RPM_SMD_XO_A_CLK_SRC 1
Yousong Zhou staging tree