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ixp4xx: Add support for 4.4 kernel, refresh patches
[openwrt/staging/yousong.git] / target / linux / ixp4xx / patches-4.1 / 175-avila_hss_audio_support.patch
1 --- a/sound/soc/Kconfig
2 +++ b/sound/soc/Kconfig
3 @@ -57,6 +57,7 @@ source "sound/soc/tegra/Kconfig"
4 source "sound/soc/txx9/Kconfig"
5 source "sound/soc/ux500/Kconfig"
6 source "sound/soc/xtensa/Kconfig"
7 +source "sound/soc/gw-avila/Kconfig"
8
9 # Supported codecs
10 source "sound/soc/codecs/Kconfig"
11 --- a/sound/soc/Makefile
12 +++ b/sound/soc/Makefile
13 @@ -38,3 +38,4 @@ obj-$(CONFIG_SND_SOC) += tegra/
14 obj-$(CONFIG_SND_SOC) += txx9/
15 obj-$(CONFIG_SND_SOC) += ux500/
16 obj-$(CONFIG_SND_SOC) += xtensa/
17 +obj-$(CONFIG_SND_SOC) += gw-avila/
18 --- /dev/null
19 +++ b/sound/soc/gw-avila/Kconfig
20 @@ -0,0 +1,17 @@
21 +config SND_GW_AVILA_SOC_PCM
22 + tristate
23 +
24 +config SND_GW_AVILA_SOC_HSS
25 + tristate
26 +
27 +config SND_GW_AVILA_SOC
28 + tristate "SoC Audio for the Gateworks AVILA Family"
29 + depends on ARCH_IXP4XX && SND_SOC
30 + select SND_GW_AVILA_SOC_PCM
31 + select SND_GW_AVILA_SOC_HSS
32 + select SND_SOC_TLV320AIC3X
33 + help
34 + Say Y or M if you want to add support for codecs attached to
35 + the Gateworks HSS interface. You will also need
36 + to select the audio interfaces to support below.
37 +
38 --- /dev/null
39 +++ b/sound/soc/gw-avila/Makefile
40 @@ -0,0 +1,8 @@
41 +# Gateworks Avila HSS Platform Support
42 +snd-soc-gw-avila-objs := gw-avila.o ixp4xx_hss.o
43 +snd-soc-gw-avila-pcm-objs := gw-avila-pcm.o
44 +snd-soc-gw-avila-hss-objs := gw-avila-hss.o
45 +
46 +obj-$(CONFIG_SND_GW_AVILA_SOC) += snd-soc-gw-avila.o
47 +obj-$(CONFIG_SND_GW_AVILA_SOC_PCM) += snd-soc-gw-avila-pcm.o
48 +obj-$(CONFIG_SND_GW_AVILA_SOC_HSS) += snd-soc-gw-avila-hss.o
49 --- /dev/null
50 +++ b/sound/soc/gw-avila/gw-avila-hss.c
51 @@ -0,0 +1,103 @@
52 +/*
53 + * gw-avila-hss.c -- HSS Audio Support for Gateworks Avila
54 + *
55 + * Author: Chris Lang <clang@gateworks.com>
56 + *
57 + * This program is free software; you can redistribute it and/or modify
58 + * it under the terms of the GNU General Public License version 2 as
59 + * published by the Free Software Foundation.
60 + */
61 +
62 +#include <linux/init.h>
63 +#include <linux/module.h>
64 +#include <linux/platform_device.h>
65 +#include <linux/interrupt.h>
66 +#include <linux/wait.h>
67 +#include <linux/delay.h>
68 +
69 +#include <sound/core.h>
70 +#include <sound/pcm.h>
71 +#include <sound/ac97_codec.h>
72 +#include <sound/initval.h>
73 +#include <sound/soc.h>
74 +
75 +#include <asm/irq.h>
76 +#include <linux/mutex.h>
77 +#include <linux/gpio.h>
78 +
79 +#include "ixp4xx_hss.h"
80 +#include "gw-avila-hss.h"
81 +
82 +#define gw_avila_hss_suspend NULL
83 +#define gw_avila_hss_resume NULL
84 +
85 +struct snd_soc_dai_driver gw_avila_hss_dai = {
86 + .playback = {
87 + .channels_min = 2,
88 + .channels_max = 2,
89 + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
90 + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
91 + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
92 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
93 + SNDRV_PCM_RATE_KNOT),
94 + .formats = SNDRV_PCM_FMTBIT_S16_LE, },
95 + .capture = {
96 + .channels_min = 2,
97 + .channels_max = 2,
98 + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
99 + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
100 + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
101 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
102 + SNDRV_PCM_RATE_KNOT),
103 + .formats = SNDRV_PCM_FMTBIT_S16_LE, },
104 +};
105 +
106 +static const struct snd_soc_component_driver gw_avila_hss_component = {
107 + .name = "gw_avila_hss",
108 +};
109 +
110 +static int gw_avila_hss_probe(struct platform_device *pdev)
111 +{
112 + int port = (pdev->id < 2) ? 0 : 1;
113 + int channel = (pdev->id % 2);
114 +
115 + hss_handle[pdev->id] = hss_init(port, channel);
116 + if (!hss_handle[pdev->id]) {
117 + return -ENODEV;
118 + }
119 +
120 + return snd_soc_register_component(&pdev->dev, &gw_avila_hss_component,
121 + &gw_avila_hss_dai, 1);
122 +}
123 +
124 +static int gw_avila_hss_remove(struct platform_device *pdev)
125 +{
126 + snd_soc_unregister_component(&pdev->dev);
127 +
128 + return 0;
129 +}
130 +
131 +static struct platform_driver gw_avila_hss_driver = {
132 + .probe = gw_avila_hss_probe,
133 + .remove = gw_avila_hss_remove,
134 + .driver = {
135 + .name = "gw_avila_hss",
136 + .owner = THIS_MODULE,
137 + }
138 +};
139 +
140 +static int __init gw_avila_hss_init(void)
141 +{
142 + return platform_driver_register(&gw_avila_hss_driver);
143 +}
144 +module_init(gw_avila_hss_init);
145 +
146 +static void __exit gw_avila_hss_exit(void)
147 +{
148 + platform_driver_unregister(&gw_avila_hss_driver);
149 +}
150 +module_exit(gw_avila_hss_exit);
151 +
152 +MODULE_AUTHOR("Chris Lang");
153 +MODULE_DESCRIPTION("HSS Audio Driver for Gateworks Avila");
154 +MODULE_LICENSE("GPL");
155 --- /dev/null
156 +++ b/sound/soc/gw-avila/gw-avila-hss.h
157 @@ -0,0 +1,12 @@
158 +/*
159 + * Author: Chris Lang <clang@gateworks.com>
160 + *
161 + * This program is free software; you can redistribute it and/or modify
162 + * it under the terms of the GNU General Public License version 2 as
163 + * published by the Free Software Foundation.
164 + */
165 +
166 +#ifndef _GW_AVILA_HSS_H
167 +#define _GW_AVILA_HSS_H
168 +
169 +#endif
170 --- /dev/null
171 +++ b/sound/soc/gw-avila/gw-avila-pcm.c
172 @@ -0,0 +1,327 @@
173 +/*
174 + * ALSA PCM interface for the TI DAVINCI processor
175 + *
176 + * Author: Chris Lang, <clang@gateworks.com>
177 + * Copyright: (C) 2009 Gateworks Corporation
178 + *
179 + * Based On: davinci-evm.c, Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
180 + *
181 + * This program is free software; you can redistribute it and/or modify
182 + * it under the terms of the GNU General Public License version 2 as
183 + * published by the Free Software Foundation.
184 + */
185 +
186 +#include <linux/module.h>
187 +#include <linux/init.h>
188 +#include <linux/platform_device.h>
189 +#include <linux/slab.h>
190 +#include <linux/dma-mapping.h>
191 +
192 +#include <sound/core.h>
193 +#include <sound/pcm.h>
194 +#include <sound/pcm_params.h>
195 +#include <sound/soc.h>
196 +
197 +#include <asm/dma.h>
198 +
199 +#include "gw-avila-pcm.h"
200 +#include "gw-avila-hss.h"
201 +#include "ixp4xx_hss.h"
202 +
203 +#define GW_AVILA_PCM_DEBUG 0
204 +#if GW_AVILA_PCM_DEBUG
205 +#define DPRINTK(x...) printk(KERN_DEBUG x)
206 +#else
207 +#define DPRINTK(x...)
208 +#endif
209 +
210 +static struct snd_pcm_hardware gw_avila_pcm_hardware = {
211 + .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
212 + SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID),
213 +/* SNDRV_PCM_INFO_PAUSE),*/
214 + .formats = (SNDRV_PCM_FMTBIT_S16_LE),
215 + .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
216 + SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 |
217 + SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000 |
218 + SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
219 + SNDRV_PCM_RATE_KNOT),
220 + .rate_min = 8000,
221 + .rate_max = 8000,
222 + .channels_min = 2,
223 + .channels_max = 2,
224 + .buffer_bytes_max = 64 * 1024, // All of the lines below may need to be changed
225 + .period_bytes_min = 128,
226 + .period_bytes_max = 4 * 1024,
227 + .periods_min = 16,
228 + .periods_max = 32,
229 + .fifo_size = 0,
230 +};
231 +
232 +struct gw_avila_runtime_data {
233 + spinlock_t lock;
234 + int period; /* current DMA period */
235 + int master_lch; /* Master DMA channel */
236 + int slave_lch; /* Slave DMA channel */
237 + struct gw_avila_pcm_dma_params *params; /* DMA params */
238 +};
239 +
240 +static void gw_avila_dma_irq(void *data)
241 +{
242 + struct snd_pcm_substream *substream = data;
243 + snd_pcm_period_elapsed(substream);
244 +}
245 +
246 +static int gw_avila_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
247 +{
248 + struct snd_pcm_runtime *runtime = substream->runtime;
249 + struct hss_device *hdev = runtime->private_data;
250 + int ret = 0;
251 +
252 + switch (cmd) {
253 + case SNDRV_PCM_TRIGGER_START:
254 + case SNDRV_PCM_TRIGGER_RESUME:
255 + case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
256 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
257 + hss_tx_start(hdev);
258 + else
259 + hss_rx_start(hdev);
260 + break;
261 + case SNDRV_PCM_TRIGGER_STOP:
262 + case SNDRV_PCM_TRIGGER_SUSPEND:
263 + case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
264 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
265 + hss_tx_stop(hdev);
266 + else
267 + hss_rx_stop(hdev);
268 + break;
269 + default:
270 + ret = -EINVAL;
271 + break;
272 + }
273 + return ret;
274 +}
275 +
276 +static int gw_avila_pcm_prepare(struct snd_pcm_substream *substream)
277 +{
278 + struct snd_pcm_runtime *runtime = substream->runtime;
279 + struct hss_device *hdev = runtime->private_data;
280 +
281 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
282 + hss_set_tx_callback(hdev, gw_avila_dma_irq, substream);
283 + hss_config_tx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size);
284 + } else {
285 + hss_set_rx_callback(hdev, gw_avila_dma_irq, substream);
286 + hss_config_rx_dma(hdev, runtime->dma_area, runtime->buffer_size, runtime->period_size);
287 + }
288 +
289 + return 0;
290 +}
291 +
292 +static snd_pcm_uframes_t
293 +gw_avila_pcm_pointer(struct snd_pcm_substream *substream)
294 +{
295 + struct snd_pcm_runtime *runtime = substream->runtime;
296 + struct hss_device *hdev = runtime->private_data;
297 +
298 + unsigned int curr = 0;
299 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
300 + curr = hss_curr_offset_tx(hdev);
301 + else
302 + curr = hss_curr_offset_rx(hdev);
303 + return curr;
304 +}
305 +
306 +static int gw_avila_pcm_open(struct snd_pcm_substream *substream)
307 +{
308 + struct snd_pcm_runtime *runtime = substream->runtime;
309 + struct snd_soc_pcm_runtime *rtd = substream->private_data;
310 + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
311 +
312 + snd_soc_set_runtime_hwparams(substream, &gw_avila_pcm_hardware);
313 +
314 + if (hss_handle[cpu_dai->id] != NULL)
315 + runtime->private_data = hss_handle[cpu_dai->id];
316 + else {
317 + pr_err("hss_handle is NULL\n");
318 + return -1;
319 + }
320 +
321 + hss_chan_open(hss_handle[cpu_dai->id]);
322 +
323 + return 0;
324 +}
325 +
326 +static int gw_avila_pcm_close(struct snd_pcm_substream *substream)
327 +{
328 + struct snd_pcm_runtime *runtime = substream->runtime;
329 + struct hss_device *hdev = runtime->private_data;
330 +
331 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
332 + memset(hdev->tx_buf, 0, runtime->buffer_size);
333 + } else
334 + memset(hdev->rx_buf, 0, runtime->buffer_size);
335 +
336 + hss_chan_close(hdev);
337 +
338 + return 0;
339 +}
340 +
341 +static int gw_avila_pcm_hw_params(struct snd_pcm_substream *substream,
342 + struct snd_pcm_hw_params *hw_params)
343 +{
344 + return snd_pcm_lib_malloc_pages(substream,
345 + params_buffer_bytes(hw_params));
346 +}
347 +
348 +static int gw_avila_pcm_hw_free(struct snd_pcm_substream *substream)
349 +{
350 + struct snd_pcm_runtime *runtime = substream->runtime;
351 +
352 + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
353 + memset(runtime->dma_area, 0, runtime->buffer_size);
354 +
355 + return snd_pcm_lib_free_pages(substream);
356 +}
357 +
358 +static int gw_avila_pcm_mmap(struct snd_pcm_substream *substream,
359 + struct vm_area_struct *vma)
360 +{
361 + struct snd_pcm_runtime *runtime = substream->runtime;
362 +
363 + return dma_mmap_writecombine(substream->pcm->card->dev, vma,
364 + runtime->dma_area,
365 + runtime->dma_addr,
366 + runtime->dma_bytes);
367 +}
368 +
369 +struct snd_pcm_ops gw_avila_pcm_ops = {
370 + .open = gw_avila_pcm_open,
371 + .close = gw_avila_pcm_close,
372 + .ioctl = snd_pcm_lib_ioctl,
373 + .hw_params = gw_avila_pcm_hw_params,
374 + .hw_free = gw_avila_pcm_hw_free,
375 + .prepare = gw_avila_pcm_prepare,
376 + .trigger = gw_avila_pcm_trigger,
377 + .pointer = gw_avila_pcm_pointer,
378 + .mmap = gw_avila_pcm_mmap,
379 +};
380 +
381 +static int gw_avila_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
382 +{
383 + struct snd_pcm_substream *substream = pcm->streams[stream].substream;
384 + struct snd_dma_buffer *buf = &substream->dma_buffer;
385 + size_t size = gw_avila_pcm_hardware.buffer_bytes_max;
386 +
387 + buf->dev.type = SNDRV_DMA_TYPE_DEV;
388 + buf->dev.dev = pcm->card->dev;
389 + buf->private_data = NULL;
390 +
391 + buf->area = dma_alloc_coherent(pcm->card->dev, size,
392 + &buf->addr, GFP_KERNEL);
393 +
394 + if (!buf->area) {
395 + return -ENOMEM;
396 + }
397 +
398 + memset(buf->area, 0xff, size);
399 +
400 + DPRINTK("preallocate_dma_buffer: area=%p, addr=%p, size=%d\n",
401 + (void *) buf->area, (void *) buf->addr, size);
402 +
403 + buf->bytes = size;
404 +
405 + return 0;
406 +}
407 +
408 +static void gw_avila_pcm_free(struct snd_pcm *pcm)
409 +{
410 + struct snd_pcm_substream *substream;
411 + struct snd_dma_buffer *buf;
412 + int stream;
413 +
414 + for (stream = 0; stream < 2; stream++) {
415 + substream = pcm->streams[stream].substream;
416 + if (!substream)
417 + continue;
418 +
419 + buf = &substream->dma_buffer;
420 + if (!buf->area)
421 + continue;
422 +
423 + dma_free_coherent(NULL, buf->bytes, buf->area, 0);
424 + buf->area = NULL;
425 + }
426 +}
427 +
428 +static u64 gw_avila_pcm_dmamask = 0xFFFFFFFF;
429 +
430 +static int gw_avila_pcm_new(struct snd_soc_pcm_runtime *rtd)
431 +{
432 + struct snd_card *card = rtd->card->snd_card;
433 + struct snd_pcm *pcm = rtd->pcm;
434 + struct snd_soc_dai *dai = rtd->codec_dai;
435 + int ret;
436 +
437 + if (!card->dev->dma_mask)
438 + card->dev->dma_mask = &gw_avila_pcm_dmamask;
439 + if (!card->dev->coherent_dma_mask)
440 + card->dev->coherent_dma_mask = 0xFFFFFFFF;
441 +
442 + if (dai->driver->playback.channels_min) {
443 + ret = gw_avila_pcm_preallocate_dma_buffer(pcm,
444 + SNDRV_PCM_STREAM_PLAYBACK);
445 + if (ret)
446 + return ret;
447 + }
448 +
449 + if (dai->driver->capture.channels_min) {
450 + ret = gw_avila_pcm_preallocate_dma_buffer(pcm,
451 + SNDRV_PCM_STREAM_CAPTURE);
452 + if (ret)
453 + return ret;
454 + }
455 +
456 + return 0;
457 +}
458 +
459 +struct snd_soc_platform_driver gw_avila_soc_platform = {
460 + .ops = &gw_avila_pcm_ops,
461 + .pcm_new = gw_avila_pcm_new,
462 + .pcm_free = gw_avila_pcm_free,
463 +};
464 +
465 +static int gw_avila_pcm_platform_probe(struct platform_device *pdev)
466 +{
467 + return snd_soc_register_platform(&pdev->dev, &gw_avila_soc_platform);
468 +}
469 +
470 +static int gw_avila_pcm_platform_remove(struct platform_device *pdev)
471 +{
472 + snd_soc_unregister_platform(&pdev->dev);
473 + return 0;
474 +}
475 +
476 +static struct platform_driver gw_avila_pcm_driver = {
477 + .driver = {
478 + .name = "gw_avila-audio",
479 + .owner = THIS_MODULE,
480 + },
481 + .probe = gw_avila_pcm_platform_probe,
482 + .remove = gw_avila_pcm_platform_remove,
483 +};
484 +
485 +static int __init gw_avila_soc_platform_init(void)
486 +{
487 + return platform_driver_register(&gw_avila_pcm_driver);
488 +}
489 +module_init(gw_avila_soc_platform_init);
490 +
491 +static void __exit gw_avila_soc_platform_exit(void)
492 +{
493 + platform_driver_unregister(&gw_avila_pcm_driver);
494 +}
495 +module_exit(gw_avila_soc_platform_exit);
496 +
497 +MODULE_AUTHOR("Chris Lang");
498 +MODULE_DESCRIPTION("Gateworks Avila PCM DMA module");
499 +MODULE_LICENSE("GPL");
500 --- /dev/null
501 +++ b/sound/soc/gw-avila/gw-avila-pcm.h
502 @@ -0,0 +1,32 @@
503 +/*
504 + * ALSA PCM interface for the Gateworks Avila platform
505 + *
506 + * Author: Chris Lang, <clang@gateworks.com>
507 + * Copyright: (C) 2009 Gateworks Corporation
508 + *
509 + * Based On: davinci-evm.c, Author: Vladimir Barinov, <vbarinov@ru.mvista.com>
510 + *
511 + * This program is free software; you can redistribute it and/or modify
512 + * it under the terms of the GNU General Public License version 2 as
513 + * published by the Free Software Foundation.
514 + */
515 +
516 +#ifndef _GW_AVILA_PCM_H
517 +#define _GW_AVILA_PCM_H
518 +
519 +#if 0
520 +struct gw_avila_pcm_dma_params {
521 + char *name; /* stream identifier */
522 + int channel; /* sync dma channel ID */
523 + dma_addr_t dma_addr; /* device physical address for DMA */
524 + unsigned int data_type; /* xfer data type */
525 +};
526 +
527 +struct gw_avila_snd_platform_data {
528 + int tx_dma_ch; // XXX Do we need this?
529 + int rx_dma_ch; // XXX Do we need this
530 +};
531 +extern struct snd_soc_platform gw_avila_soc_platform[];
532 +#endif
533 +
534 +#endif
535 --- /dev/null
536 +++ b/sound/soc/gw-avila/gw-avila.c
537 @@ -0,0 +1,244 @@
538 +/*
539 + * File: sound/soc/gw-avila/gw_avila.c
540 + * Author: Chris Lang <clang@gateworks.com>
541 + *
542 + * Created: Tue June 06 2008
543 + * Description: Board driver for Gateworks Avila
544 + *
545 + * Modified:
546 + * Copyright 2009 Gateworks Corporation
547 + *
548 + * Bugs: What Bugs?
549 + *
550 + * This program is free software; you can redistribute it and/or modify
551 + * it under the terms of the GNU General Public License as published by
552 + * the Free Software Foundation; either version 2 of the License, or
553 + * (at your option) any later version.
554 + *
555 + * This program is distributed in the hope that it will be useful,
556 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
557 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
558 + * GNU General Public License for more details.
559 + *
560 + * You should have received a copy of the GNU General Public License
561 + * along with this program; if not, see the file COPYING, or write
562 + * to the Free Software Foundation, Inc.,
563 + * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
564 + */
565 +
566 +#include <linux/module.h>
567 +#include <linux/moduleparam.h>
568 +#include <linux/device.h>
569 +#include <asm/dma.h>
570 +#include <linux/platform_device.h>
571 +#include <sound/core.h>
572 +#include <sound/pcm.h>
573 +#include <sound/soc.h>
574 +#include <linux/slab.h>
575 +#include <linux/gpio.h>
576 +
577 +#include "ixp4xx_hss.h"
578 +#include "gw-avila-hss.h"
579 +#include "gw-avila-pcm.h"
580 +
581 +#define CODEC_FREQ 33333000
582 +
583 +static int gw_avila_board_startup(struct snd_pcm_substream *substream)
584 +{
585 + pr_debug("%s enter\n", __func__);
586 + return 0;
587 +}
588 +
589 +static int gw_avila_hw_params(struct snd_pcm_substream *substream,
590 + struct snd_pcm_hw_params *params)
591 +{
592 + struct snd_soc_pcm_runtime *rtd = substream->private_data;
593 + struct snd_soc_dai *codec_dai = rtd->codec_dai;
594 + struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
595 +
596 + int ret = 0;
597 +
598 + /* set codec DAI configuration */
599 + if (cpu_dai->id % 2) {
600 + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBS_CFS);
601 + snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 1, 32);
602 + } else {
603 + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF | SND_SOC_DAIFMT_CBM_CFM);
604 + snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, 0, 32);
605 + }
606 +
607 + if (ret < 0)
608 + return ret;
609 +
610 + /* set the codec system clock */
611 + ret = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_FREQ, SND_SOC_CLOCK_OUT);
612 + if (ret < 0)
613 + return ret;
614 +
615 + return 0;
616 +}
617 +
618 +static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
619 + SND_SOC_DAPM_HP("Headphone Jack", NULL),
620 + SND_SOC_DAPM_LINE("Line Out", NULL),
621 + SND_SOC_DAPM_LINE("Line In", NULL),
622 +};
623 +
624 +static const struct snd_soc_dapm_route audio_map[] = {
625 + {"Headphone Jack", NULL, "HPLOUT"},
626 + {"Headphone Jack", NULL, "HPROUT"},
627 +
628 + /* Line Out connected to LLOUT, RLOUT */
629 + {"Line Out", NULL, "LLOUT"},
630 + {"Line Out", NULL, "RLOUT"},
631 +
632 + /* Line In connected to (LINE1L | LINE2L), (LINE1R | LINE2R) */
633 + {"LINE1L", NULL, "Line In"},
634 + {"LINE1R", NULL, "Line In"},
635 +};
636 +
637 +/* Logic for a aic3x as connected on a davinci-evm */
638 +static int avila_aic3x_init(struct snd_soc_pcm_runtime *rtd)
639 +{
640 + struct snd_soc_codec *codec = rtd->codec;
641 + struct snd_soc_dapm_context *dapm = &codec->dapm;
642 +
643 + /* Add davinci-evm specific widgets */
644 + snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
645 + ARRAY_SIZE(aic3x_dapm_widgets));
646 +
647 + /* Set up davinci-evm specific audio path audio_map */
648 + snd_soc_dapm_add_routes(dapm, audio_map, ARRAY_SIZE(audio_map));
649 +
650 + /* not connected */
651 + snd_soc_dapm_disable_pin(dapm, "MONO_LOUT");
652 + //snd_soc_dapm_disable_pin(dapm, "HPLCOM");
653 + //snd_soc_dapm_disable_pin(dapm, "HPRCOM");
654 + snd_soc_dapm_disable_pin(dapm, "MIC3L");
655 + snd_soc_dapm_disable_pin(dapm, "MIC3R");
656 + snd_soc_dapm_disable_pin(dapm, "LINE2L");
657 + snd_soc_dapm_disable_pin(dapm, "LINE2R");
658 +
659 + /* always connected */
660 + snd_soc_dapm_enable_pin(dapm, "Headphone Jack");
661 + snd_soc_dapm_enable_pin(dapm, "Line Out");
662 + snd_soc_dapm_enable_pin(dapm, "Line In");
663 +
664 + snd_soc_dapm_sync(dapm);
665 +
666 + return 0;
667 +}
668 +
669 +static struct snd_soc_ops gw_avila_board_ops = {
670 + .startup = gw_avila_board_startup,
671 + .hw_params = gw_avila_hw_params,
672 +};
673 +
674 +static struct snd_soc_dai_link gw_avila_board_dai[] = {
675 + {
676 + .name = "HSS-0",
677 + .stream_name = "HSS-0",
678 + .cpu_dai_name = "gw_avila_hss.0",
679 + .codec_dai_name = "tlv320aic3x-hifi",
680 + .codec_name = "tlv320aic3x-codec.0-001b",
681 + .platform_name = "gw_avila-audio.0",
682 + .init = avila_aic3x_init,
683 + .ops = &gw_avila_board_ops,
684 + },{
685 + .name = "HSS-1",
686 + .stream_name = "HSS-1",
687 + .cpu_dai_name = "gw_avila_hss.1",
688 + .codec_dai_name = "tlv320aic3x-hifi",
689 + .codec_name = "tlv320aic3x-codec.0-001a",
690 + .platform_name = "gw_avila-audio.1",
691 + .init = avila_aic3x_init,
692 + .ops = &gw_avila_board_ops,
693 + },{
694 + .name = "HSS-2",
695 + .stream_name = "HSS-2",
696 + .cpu_dai_name = "gw_avila_hss.2",
697 + .codec_dai_name = "tlv320aic3x-hifi",
698 + .codec_name = "tlv320aic3x-codec.0-0019",
699 + .platform_name = "gw_avila-audio.2",
700 + .init = avila_aic3x_init,
701 + .ops = &gw_avila_board_ops,
702 + },{
703 + .name = "HSS-3",
704 + .stream_name = "HSS-3",
705 + .cpu_dai_name = "gw_avila_hss.3",
706 + .codec_dai_name = "tlv320aic3x-hifi",
707 + .codec_name = "tlv320aic3x-codec.0-0018",
708 + .platform_name = "gw_avila-audio.3",
709 + .init = avila_aic3x_init,
710 + .ops = &gw_avila_board_ops,
711 + },
712 +};
713 +
714 +static struct snd_soc_card gw_avila_board[] = {
715 + {
716 + .name = "gw_avila-board.0",
717 + .owner = THIS_MODULE,
718 + .dai_link = &gw_avila_board_dai[0],
719 + .num_links = 1,
720 + },{
721 + .name = "gw_avila-board.1",
722 + .owner = THIS_MODULE,
723 + .dai_link = &gw_avila_board_dai[1],
724 + .num_links = 1,
725 + },{
726 + .name = "gw_avila-board.2",
727 + .owner = THIS_MODULE,
728 + .dai_link = &gw_avila_board_dai[2],
729 + .num_links = 1,
730 + },{
731 + .name = "gw_avila-board.3",
732 + .owner = THIS_MODULE,
733 + .dai_link = &gw_avila_board_dai[3],
734 + .num_links = 1,
735 + }
736 +};
737 +
738 +static struct platform_device *gw_avila_board_snd_device[4];
739 +
740 +static int __init gw_avila_board_init(void)
741 +{
742 + int ret;
743 + struct port *port;
744 + int i;
745 +
746 + if ((hss_port[0] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
747 + return -ENOMEM;
748 +
749 + if ((hss_port[1] = kzalloc(sizeof(*port), GFP_KERNEL)) == NULL)
750 + return -ENOMEM;
751 +
752 + for (i = 0; i < 4; i++) {
753 + gw_avila_board_snd_device[i] = platform_device_alloc("soc-audio", i);
754 + if (!gw_avila_board_snd_device[i]) {
755 + return -ENOMEM;
756 + }
757 +
758 + platform_set_drvdata(gw_avila_board_snd_device[i], &gw_avila_board[i]);
759 + ret = platform_device_add(gw_avila_board_snd_device[i]);
760 +
761 + if (ret) {
762 + platform_device_put(gw_avila_board_snd_device[i]);
763 + }
764 + }
765 + return ret;
766 +}
767 +
768 +static void __exit gw_avila_board_exit(void)
769 +{
770 + int i;
771 + for (i = 0; i < 4; i++)
772 + platform_device_unregister(gw_avila_board_snd_device[i]);
773 +}
774 +
775 +module_init(gw_avila_board_init);
776 +module_exit(gw_avila_board_exit);
777 +
778 +/* Module information */
779 +MODULE_AUTHOR("Chris Lang");
780 +MODULE_DESCRIPTION("ALSA SoC HSS Audio gw_avila board");
781 +MODULE_LICENSE("GPL");
782 --- /dev/null
783 +++ b/sound/soc/gw-avila/ixp4xx_hss.c
784 @@ -0,0 +1,902 @@
785 +/*
786 + * Intel IXP4xx HSS (synchronous serial port) driver for Linux
787 + *
788 + * Copyright (C) 2009 Chris Lang <clang@gateworks.com>
789 + *
790 + * This program is free software; you can redistribute it and/or modify it
791 + * under the terms of version 2 of the GNU General Public License
792 + * as published by the Free Software Foundation.
793 + */
794 +
795 +#include <linux/module.h>
796 +#include <linux/bitops.h>
797 +#include <linux/cdev.h>
798 +#include <linux/dma-mapping.h>
799 +#include <linux/dmapool.h>
800 +#include <linux/fs.h>
801 +#include <linux/io.h>
802 +#include <linux/kernel.h>
803 +#include <linux/platform_device.h>
804 +#include <linux/poll.h>
805 +#include <linux/slab.h>
806 +#include <linux/delay.h>
807 +
808 +#include <mach/npe.h>
809 +#include <mach/qmgr.h>
810 +
811 +#include "ixp4xx_hss.h"
812 +
813 +/*****************************************************************************
814 + * global variables
815 + ****************************************************************************/
816 +
817 +void hss_chan_read(unsigned long data);
818 +static char lock_init = 0;
819 +static spinlock_t npe_lock;
820 +static struct npe *npe;
821 +
822 +static const struct {
823 + int tx, txdone, rx, rxfree, chan;
824 +}queue_ids[2] = {{HSS0_PKT_TX0_QUEUE, HSS0_PKT_TXDONE_QUEUE, HSS0_PKT_RX_QUEUE,
825 + HSS0_PKT_RXFREE0_QUEUE, HSS0_CHL_RXTRIG_QUEUE},
826 + {HSS1_PKT_TX0_QUEUE, HSS1_PKT_TXDONE_QUEUE, HSS1_PKT_RX_QUEUE,
827 + HSS1_PKT_RXFREE0_QUEUE, HSS1_CHL_RXTRIG_QUEUE},
828 +};
829 +
830 +struct port *hss_port[2];
831 +struct hss_device *hss_handle[32];
832 +EXPORT_SYMBOL(hss_handle);
833 +
834 +/*****************************************************************************
835 + * utility functions
836 + ****************************************************************************/
837 +
838 +#ifndef __ARMEB__
839 +static inline void memcpy_swab32(u32 *dest, u32 *src, int cnt)
840 +{
841 + int i;
842 + for (i = 0; i < cnt; i++)
843 + dest[i] = swab32(src[i]);
844 +}
845 +#endif
846 +
847 +static inline unsigned int sub_offset(unsigned int a, unsigned int b,
848 + unsigned int modulo)
849 +{
850 + return (modulo /* make sure the result >= 0 */ + a - b) % modulo;
851 +}
852 +
853 +/*****************************************************************************
854 + * HSS access
855 + ****************************************************************************/
856 +
857 +static void hss_config_load(struct port *port)
858 +{
859 + struct msg msg;
860 +
861 + do {
862 + memset(&msg, 0, sizeof(msg));
863 + msg.cmd = PORT_CONFIG_LOAD;
864 + msg.hss_port = port->id;
865 + if (npe_send_message(npe, &msg, "HSS_LOAD_CONFIG"))
866 + break;
867 + if (npe_recv_message(npe, &msg, "HSS_LOAD_CONFIG"))
868 + break;
869 +
870 + /* HSS_LOAD_CONFIG for port #1 returns port_id = #4 */
871 + if (msg.cmd != PORT_CONFIG_LOAD || msg.data32)
872 + break;
873 +
874 + /* HDLC may stop working without this */
875 + npe_recv_message(npe, &msg, "FLUSH_IT");
876 + return;
877 + } while (0);
878 +
879 + printk(KERN_CRIT "HSS-%i: unable to reload HSS configuration\n",
880 + port->id);
881 + BUG();
882 +}
883 +
884 +static void hss_config_set_pcr(struct port *port)
885 +{
886 + struct msg msg;
887 +
888 + do {
889 + memset(&msg, 0, sizeof(msg));
890 + msg.cmd = PORT_CONFIG_WRITE;
891 + msg.hss_port = port->id;
892 + msg.index = HSS_CONFIG_TX_PCR;
893 +#if 0
894 + msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN |
895 + PCR_TX_DATA_ENABLE | PCR_TX_UNASS_HIGH_IMP | PCR_TX_V56K_HIGH_IMP | PCR_TX_FB_HIGH_IMP;
896 +#else
897 + msg.data32 = PCR_FRM_SYNC_RISINGEDGE | PCR_MSB_ENDIAN |
898 + PCR_TX_DATA_ENABLE | PCR_TX_FB_HIGH_IMP | PCR_DCLK_EDGE_RISING;
899 +#endif
900 + if (port->frame_size % 8 == 0)
901 + msg.data32 |= PCR_SOF_NO_FBIT;
902 +
903 + if (npe_send_message(npe, &msg, "HSS_SET_TX_PCR"))
904 + break;
905 +
906 + msg.index = HSS_CONFIG_RX_PCR;
907 + msg.data32 &= ~ (PCR_DCLK_EDGE_RISING | PCR_FCLK_EDGE_RISING | PCR_TX_DATA_ENABLE);
908 +
909 + if (npe_send_message(npe, &msg, "HSS_SET_RX_PCR"))
910 + break;
911 + return;
912 + } while (0);
913 +
914 + printk(KERN_CRIT "HSS-%i: unable to set HSS PCR registers\n", port->id);
915 + BUG();
916 +}
917 +
918 +static void hss_config_set_core(struct port *port)
919 +{
920 + struct msg msg;
921 +
922 + memset(&msg, 0, sizeof(msg));
923 + msg.cmd = PORT_CONFIG_WRITE;
924 + msg.hss_port = port->id;
925 + msg.index = HSS_CONFIG_CORE_CR;
926 +#if 0
927 + msg.data32 = 0 | CCR_LOOPBACK |
928 + (port->id ? CCR_SECOND_HSS : 0);
929 +#else
930 + msg.data32 = 0 |
931 + (port->id ? CCR_SECOND_HSS : 0);
932 +#endif
933 + if (npe_send_message(npe, &msg, "HSS_SET_CORE_CR")) {
934 + printk(KERN_CRIT "HSS-%i: unable to set HSS core control"
935 + " register\n", port->id);
936 + BUG();
937 + }
938 +}
939 +
940 +static void hss_config_set_line(struct port *port)
941 +{
942 + struct msg msg;
943 +
944 + hss_config_set_pcr(port);
945 + hss_config_set_core(port);
946 +
947 + memset(&msg, 0, sizeof(msg));
948 + msg.cmd = PORT_CONFIG_WRITE;
949 + msg.hss_port = port->id;
950 + msg.index = HSS_CONFIG_CLOCK_CR;
951 + msg.data32 = CLK42X_SPEED_8192KHZ /* FIXME */;
952 + if (npe_send_message(npe, &msg, "HSS_SET_CLOCK_CR")) {
953 + printk(KERN_CRIT "HSS-%i: unable to set HSS clock control"
954 + " register\n", port->id);
955 + BUG();
956 + }
957 +}
958 +
959 +static void hss_config_set_rx_frame(struct port *port)
960 +{
961 + struct msg msg;
962 +
963 + memset(&msg, 0, sizeof(msg));
964 + msg.cmd = PORT_CONFIG_WRITE;
965 + msg.hss_port = port->id;
966 + msg.index = HSS_CONFIG_RX_FCR;
967 + msg.data16a = port->frame_sync_offset;
968 + msg.data16b = port->frame_size - 1;
969 + if (npe_send_message(npe, &msg, "HSS_SET_RX_FCR")) {
970 + printk(KERN_CRIT "HSS-%i: unable to set HSS RX frame size"
971 + " and offset\n", port->id);
972 + BUG();
973 + }
974 +}
975 +
976 +static void hss_config_set_frame(struct port *port)
977 +{
978 + struct msg msg;
979 +
980 + memset(&msg, 0, sizeof(msg));
981 + msg.cmd = PORT_CONFIG_WRITE;
982 + msg.hss_port = port->id;
983 + msg.index = HSS_CONFIG_TX_FCR;
984 + msg.data16a = TX_FRAME_SYNC_OFFSET;
985 + msg.data16b = port->frame_size - 1;
986 + if (npe_send_message(npe, &msg, "HSS_SET_TX_FCR")) {
987 + printk(KERN_CRIT "HSS-%i: unable to set HSS TX frame size"
988 + " and offset\n", port->id);
989 + BUG();
990 + }
991 + hss_config_set_rx_frame(port);
992 +}
993 +
994 +static void hss_config_set_lut(struct port *port)
995 +{
996 + struct msg msg;
997 + int chan_count = 32;
998 +
999 + memset(&msg, 0, sizeof(msg));
1000 + msg.cmd = PORT_CONFIG_WRITE;
1001 + msg.hss_port = port->id;
1002 +
1003 + msg.index = HSS_CONFIG_TX_LUT;
1004 + msg.data32 = 0xffffffff;
1005 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1006 + msg.index += 4;
1007 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1008 + msg.data32 = 0x0;
1009 + msg.index += 4;
1010 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1011 + msg.index += 4;
1012 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1013 + msg.index += 4;
1014 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1015 + msg.index += 4;
1016 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1017 + msg.index += 4;
1018 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1019 + msg.index += 4;
1020 + npe_send_message(npe, &msg, "HSS_SET_TX_LUT");
1021 +
1022 + msg.index = HSS_CONFIG_RX_LUT;
1023 + msg.data32 = 0xffffffff;
1024 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1025 + msg.index += 4;
1026 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1027 + msg.data32 = 0x0;
1028 + msg.index += 4;
1029 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1030 + msg.index += 4;
1031 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1032 + msg.index += 4;
1033 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1034 + msg.index += 4;
1035 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1036 + msg.index += 4;
1037 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1038 + msg.index += 4;
1039 + npe_send_message(npe, &msg, "HSS_SET_RX_LUT");
1040 +
1041 + hss_config_set_frame(port);
1042 +
1043 + memset(&msg, 0, sizeof(msg));
1044 + msg.cmd = CHAN_NUM_CHANS_WRITE;
1045 + msg.hss_port = port->id;
1046 + msg.data8a = chan_count;
1047 + if (npe_send_message(npe, &msg, "CHAN_NUM_CHANS_WRITE")) {
1048 + printk(KERN_CRIT "HSS-%i: unable to set HSS channel count\n",
1049 + port->id);
1050 + BUG();
1051 + }
1052 +}
1053 +
1054 +static u32 hss_config_get_status(struct port *port)
1055 +{
1056 + struct msg msg;
1057 +
1058 + do {
1059 + memset(&msg, 0, sizeof(msg));
1060 + msg.cmd = PORT_ERROR_READ;
1061 + msg.hss_port = port->id;
1062 + if (npe_send_message(npe, &msg, "PORT_ERROR_READ"))
1063 + break;
1064 + if (npe_recv_message(npe, &msg, "PORT_ERROR_READ"))
1065 + break;
1066 +
1067 + return msg.data32;
1068 + } while (0);
1069 +
1070 + printk(KERN_CRIT "HSS-%i: unable to read HSS status\n", port->id);
1071 + BUG();
1072 +}
1073 +
1074 +static void hss_config_start_chan(struct port *port)
1075 +{
1076 + struct msg msg;
1077 +
1078 + port->chan_last_tx = 0;
1079 + port->chan_last_rx = 0;
1080 +
1081 + do {
1082 + memset(&msg, 0, sizeof(msg));
1083 + msg.cmd = CHAN_RX_BUF_ADDR_WRITE;
1084 + msg.hss_port = port->id;
1085 + msg.data32 = port->chan_rx_buf_phys;
1086 + if (npe_send_message(npe, &msg, "CHAN_RX_BUF_ADDR_WRITE"))
1087 + break;
1088 +
1089 + memset(&msg, 0, sizeof(msg));
1090 + msg.cmd = CHAN_TX_BUF_ADDR_WRITE;
1091 + msg.hss_port = port->id;
1092 + msg.data32 = port->chan_tx_pointers_phys;
1093 + if (npe_send_message(npe, &msg, "CHAN_TX_BUF_ADDR_WRITE"))
1094 + break;
1095 +
1096 + memset(&msg, 0, sizeof(msg));
1097 + msg.cmd = CHAN_FLOW_ENABLE;
1098 + msg.hss_port = port->id;
1099 + if (npe_send_message(npe, &msg, "CHAN_FLOW_ENABLE"))
1100 + break;
1101 + port->chan_started = 1;
1102 + return;
1103 + } while (0);
1104 +
1105 + printk(KERN_CRIT "HSS-%i: unable to start channelized flow\n",
1106 + port->id);
1107 + BUG();
1108 +}
1109 +
1110 +static void hss_config_stop_chan(struct port *port)
1111 +{
1112 + struct msg msg;
1113 +
1114 + if (!port->chan_started)
1115 + return;
1116 +
1117 + memset(&msg, 0, sizeof(msg));
1118 + msg.cmd = CHAN_FLOW_DISABLE;
1119 + msg.hss_port = port->id;
1120 + if (npe_send_message(npe, &msg, "CHAN_FLOW_DISABLE")) {
1121 + printk(KERN_CRIT "HSS-%i: unable to stop channelized flow\n",
1122 + port->id);
1123 + BUG();
1124 + }
1125 + hss_config_get_status(port); /* make sure it's halted */
1126 + port->chan_started = 0;
1127 +}
1128 +
1129 +static int hss_config_load_firmware(struct port *port)
1130 +{
1131 + struct msg msg;
1132 +
1133 + if (port->initialized)
1134 + return 0;
1135 +
1136 + if (!npe_running(npe)) {
1137 + int err;
1138 + if ((err = npe_load_firmware(npe, "NPE-A-HSS",
1139 + port->dev)))
1140 + return err;
1141 + }
1142 +
1143 + do {
1144 + /* HSS main configuration */
1145 + hss_config_set_line(port);
1146 +
1147 + hss_config_set_frame(port);
1148 +
1149 + /* Channelized operation settings */
1150 + memset(&msg, 0, sizeof(msg));
1151 + msg.cmd = CHAN_TX_BLK_CFG_WRITE;
1152 + msg.hss_port = port->id;
1153 + msg.data8b = (CHAN_TX_LIST_FRAMES & ~7) / 2;
1154 + msg.data8a = msg.data8b / 4;
1155 + msg.data8d = CHAN_TX_LIST_FRAMES - msg.data8b;
1156 + msg.data8c = msg.data8d / 4;
1157 + if (npe_send_message(npe, &msg, "CHAN_TX_BLK_CFG_WRITE"))
1158 + break;
1159 +
1160 + memset(&msg, 0, sizeof(msg));
1161 + msg.cmd = CHAN_RX_BUF_CFG_WRITE;
1162 + msg.hss_port = port->id;
1163 + msg.data8a = CHAN_RX_TRIGGER / 8;
1164 + msg.data8b = CHAN_RX_FRAMES;
1165 + if (npe_send_message(npe, &msg, "CHAN_RX_BUF_CFG_WRITE"))
1166 + break;
1167 +
1168 + memset(&msg, 0, sizeof(msg));
1169 + msg.cmd = CHAN_TX_BUF_SIZE_WRITE;
1170 + msg.hss_port = port->id;
1171 + msg.data8a = CHAN_TX_LISTS;
1172 + if (npe_send_message(npe, &msg, "CHAN_TX_BUF_SIZE_WRITE"))
1173 + break;
1174 +
1175 + port->initialized = 1;
1176 + return 0;
1177 + } while (0);
1178 +
1179 + printk(KERN_CRIT "HSS-%i: unable to start HSS operation\n", port->id);
1180 + BUG();
1181 +}
1182 +
1183 +void hss_chan_irq(void *pdev)
1184 +{
1185 + struct port *port = pdev;
1186 +
1187 + qmgr_disable_irq(queue_ids[port->id].chan);
1188 +
1189 + tasklet_hi_schedule(&port->task);
1190 +}
1191 +
1192 +
1193 +int hss_prepare_chan(struct port *port)
1194 +{
1195 + int err, i, j;
1196 + u32 *temp;
1197 + u32 temp2;
1198 + u8 *temp3;
1199 +
1200 + if (port->initialized)
1201 + return 0;
1202 +
1203 + if ((err = hss_config_load_firmware(port)))
1204 + return err;
1205 +
1206 + if ((err = qmgr_request_queue(queue_ids[port->id].chan,
1207 + CHAN_QUEUE_LEN, 0, 0, "%s:hss", "hss")))
1208 + return err;
1209 +
1210 + port->chan_tx_buf = dma_alloc_coherent(port->dev, chan_tx_buf_len(port), &port->chan_tx_buf_phys, GFP_DMA);
1211 + memset(port->chan_tx_buf, 0, chan_tx_buf_len(port));
1212 +
1213 + port->chan_tx_pointers = dma_alloc_coherent(port->dev, chan_tx_buf_len(port) / CHAN_TX_LIST_FRAMES * 4, &port->chan_tx_pointers_phys, GFP_DMA);
1214 +
1215 + temp3 = port->chan_tx_buf;
1216 + for (i = 0; i < CHAN_TX_LISTS; i++) {
1217 + for (j = 0; j < 8; j++) {
1218 + port->tx_lists[i][j] = temp3;
1219 + temp3 += CHAN_TX_LIST_FRAMES * 4;
1220 + }
1221 + }
1222 +
1223 + temp = port->chan_tx_pointers;
1224 + temp2 = port->chan_tx_buf_phys;
1225 + for (i = 0; i < CHAN_TX_LISTS; i++)
1226 + {
1227 + for (j = 0; j < 32; j++)
1228 + {
1229 + *temp = temp2;
1230 + temp2 += CHAN_TX_LIST_FRAMES;
1231 + temp++;
1232 + }
1233 + }
1234 +
1235 + port->chan_rx_buf = dma_alloc_coherent(port->dev, chan_rx_buf_len(port), &port->chan_rx_buf_phys, GFP_DMA);
1236 +
1237 + for (i = 0; i < 8; i++) {
1238 + temp3 = port->chan_rx_buf + (i * 4 * 128);
1239 + for (j = 0; j < 8; j++) {
1240 + port->rx_frames[i][j] = temp3;
1241 + temp3 += CHAN_RX_TRIGGER;
1242 + }
1243 + }
1244 +
1245 + qmgr_set_irq(queue_ids[port->id].chan, QUEUE_IRQ_SRC_NOT_EMPTY,
1246 + hss_chan_irq, port);
1247 +
1248 + return 0;
1249 +
1250 +}
1251 +
1252 +int hss_tx_start(struct hss_device *hdev)
1253 +{
1254 + unsigned long flags;
1255 + struct port *port = hdev->port;
1256 +
1257 + hdev->tx_loc = 0;
1258 + hdev->tx_frame = 0;
1259 +
1260 + set_bit((1 << hdev->id), &port->chan_tx_bitmap);
1261 +
1262 + if (!port->chan_started)
1263 + {
1264 + qmgr_enable_irq(queue_ids[port->id].chan);
1265 + spin_lock_irqsave(&npe_lock, flags);
1266 + hss_config_start_chan(port);
1267 + spin_unlock_irqrestore(&npe_lock, flags);
1268 + hss_chan_irq(port);
1269 + }
1270 +
1271 + return 0;
1272 +}
1273 +EXPORT_SYMBOL(hss_tx_start);
1274 +
1275 +int hss_rx_start(struct hss_device *hdev)
1276 +{
1277 + unsigned long flags;
1278 + struct port *port = hdev->port;
1279 +
1280 + hdev->rx_loc = 0;
1281 + hdev->rx_frame = 0;
1282 +
1283 + set_bit((1 << hdev->id), &port->chan_rx_bitmap);
1284 +
1285 + if (!port->chan_started)
1286 + {
1287 + qmgr_enable_irq(queue_ids[port->id].chan);
1288 + spin_lock_irqsave(&npe_lock, flags);
1289 + hss_config_start_chan(port);
1290 + spin_unlock_irqrestore(&npe_lock, flags);
1291 + hss_chan_irq(port);
1292 + }
1293 +
1294 + return 0;
1295 +}
1296 +EXPORT_SYMBOL(hss_rx_start);
1297 +
1298 +int hss_tx_stop(struct hss_device *hdev)
1299 +{
1300 + struct port *port = hdev->port;
1301 +
1302 + clear_bit((1 << hdev->id), &port->chan_tx_bitmap);
1303 +
1304 + return 0;
1305 +}
1306 +EXPORT_SYMBOL(hss_tx_stop);
1307 +
1308 +int hss_rx_stop(struct hss_device *hdev)
1309 +{
1310 + struct port *port = hdev->port;
1311 +
1312 + clear_bit((1 << hdev->id), &port->chan_rx_bitmap);
1313 +
1314 + return 0;
1315 +}
1316 +EXPORT_SYMBOL(hss_rx_stop);
1317 +
1318 +int hss_chan_open(struct hss_device *hdev)
1319 +{
1320 + struct port *port = hdev->port;
1321 + int i, err = 0;
1322 +
1323 + if (port->chan_open)
1324 + return 0;
1325 +
1326 + if (port->mode == MODE_HDLC) {
1327 + err = -ENOSYS;
1328 + goto out;
1329 + }
1330 +
1331 + if (port->mode == MODE_G704 && port->channels[0] == hdev->id) {
1332 + err = -EBUSY; /* channel #0 is used for G.704 signaling */
1333 + goto out;
1334 + }
1335 +
1336 + for (i = MAX_CHANNELS; i > port->frame_size / 8; i--)
1337 + if (port->channels[i - 1] == hdev->id) {
1338 + err = -ECHRNG; /* frame too short */
1339 + goto out;
1340 + }
1341 +
1342 + hdev->rx_loc = hdev->tx_loc = 0;
1343 + hdev->rx_frame = hdev->tx_frame = 0;
1344 +
1345 + //clear_bit((1 << hdev->id), &port->chan_rx_bitmap);
1346 + //clear_bit((1 << hdev->id), &port->chan_tx_bitmap);
1347 +
1348 + if (!port->initialized) {
1349 + hss_prepare_chan(port);
1350 +
1351 + hss_config_stop_chan(port);
1352 + hdev->open_count++;
1353 + port->chan_open_count++;
1354 +
1355 + hss_config_set_lut(port);
1356 + hss_config_load(port);
1357 +
1358 + }
1359 + port->chan_open = 1;
1360 +
1361 +out:
1362 + return err;
1363 +}
1364 +EXPORT_SYMBOL(hss_chan_open);
1365 +
1366 +int hss_chan_close(struct hss_device *hdev)
1367 +{
1368 + return 0;
1369 +}
1370 +EXPORT_SYMBOL(hss_chan_close);
1371 +
1372 +void hss_chan_read(unsigned long data)
1373 +{
1374 + struct port *port = (void *)data;
1375 + struct hss_device *hdev;
1376 + u8 *hw_buf, *save_buf;
1377 + u8 *buf;
1378 + u32 v;
1379 + unsigned int tx_list, rx_frame;
1380 + int i, j, channel;
1381 + u8 more_work = 0;
1382 +
1383 +/*
1384 + My Data in the hardware buffer is scattered by channels into 4 trunks
1385 + as follows for rx
1386 +
1387 + channel 0 channel 1 channel 2 channel 3
1388 +Trunk 1 = 0 -> 127 128 -> 255 256 -> 383 384 -> 512
1389 +Trunk 2 = 513 -> 639 640 -> 768 769 -> 895 896 -> 1023
1390 +Trunk 3 = 1024 -> 1151 1152 -> 1207 1208 -> 1407 1408 -> 1535
1391 +Trunk 4 = 1535 -> 1663 1664 -> 1791 1792 -> 1920 1921 -> 2047
1392 +
1393 + I will get CHAN_RX_TRIGGER worth of bytes out of each channel on each trunk
1394 + with each IRQ
1395 +
1396 + For TX Data, it is split into 8 lists with each list containing 16 bytes per
1397 + channel
1398 +
1399 +Trunk 1 = 0 -> 16 17 -> 32 33 -> 48 49 -> 64
1400 +Trunk 2 = 65 -> 80 81 -> 96 97 -> 112 113 -> 128
1401 +Trunk 3 = 129 -> 144 145 -> 160 161 -> 176 177 -> 192
1402 +Trunk 4 = 193 -> 208 209 -> 224 225 -> 240 241 -> 256
1403 +
1404 +*/
1405 +
1406 +
1407 + while ((v = qmgr_get_entry(queue_ids[port->id].chan)))
1408 + {
1409 + tx_list = (v >> 8) & 0xFF;
1410 + rx_frame = v & 0xFF;
1411 +
1412 + if (tx_list == 7)
1413 + tx_list = 0;
1414 + else
1415 + tx_list++;
1416 + for (channel = 0; channel < 8; channel++) {
1417 +
1418 + hdev = port->chan_devices[channel];
1419 + if (!hdev)
1420 + continue;
1421 +
1422 + if (test_bit(1 << channel, &port->chan_tx_bitmap)) {
1423 + buf = (u8 *)hdev->tx_buf + hdev->tx_loc;
1424 +#if 0
1425 + hw_buf = (u8 *)port->chan_tx_buf;
1426 + hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32);
1427 + hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel);
1428 + save_buf = hw_buf;
1429 +#else
1430 + save_buf = port->tx_lists[tx_list][channel];
1431 +#endif
1432 + for (i = 0; i < CHAN_TX_LIST_FRAMES; i++) {
1433 + hw_buf = save_buf + i;
1434 + for (j = 0; j < 4; j++) {
1435 + *hw_buf = *(buf++);
1436 + hw_buf += CHAN_TX_LIST_FRAMES;
1437 + }
1438 +
1439 + hdev->tx_loc += 4;
1440 + hdev->tx_frame++;
1441 + if (hdev->tx_loc >= hdev->tx_buffer_size) {
1442 + hdev->tx_loc = 0;
1443 + buf = (u8 *)hdev->tx_buf;
1444 + }
1445 + }
1446 + } else {
1447 +#if 0
1448 + hw_buf = (u8 *)port->chan_tx_buf;
1449 + hw_buf += (tx_list * CHAN_TX_LIST_FRAMES * 32);
1450 + hw_buf += (4 * CHAN_TX_LIST_FRAMES * channel);
1451 +#else
1452 + hw_buf = port->tx_lists[tx_list][channel];
1453 +#endif
1454 + memset(hw_buf, 0, 64);
1455 + }
1456 +
1457 + if (hdev->tx_frame >= hdev->tx_period_size && test_bit(1 << channel, &port->chan_tx_bitmap))
1458 + {
1459 + hdev->tx_frame %= hdev->tx_period_size;
1460 + if (hdev->tx_callback)
1461 + hdev->tx_callback(hdev->tx_data);
1462 + more_work = 1;
1463 + }
1464 +
1465 + if (test_bit(1 << channel, &port->chan_rx_bitmap)) {
1466 + buf = (u8 *)hdev->rx_buf + hdev->rx_loc;
1467 +#if 0
1468 + hw_buf = (u8 *)port->chan_rx_buf;
1469 + hw_buf += (4 * CHAN_RX_FRAMES * channel);
1470 + hw_buf += rx_frame;
1471 + save_buf = hw_buf;
1472 +#else
1473 + save_buf = port->rx_frames[channel][rx_frame >> 4];
1474 +#endif
1475 + for (i = 0; i < CHAN_RX_TRIGGER; i++) {
1476 + hw_buf = save_buf + i;
1477 + for (j = 0; j < 4; j++) {
1478 + *(buf++) = *hw_buf;
1479 + hw_buf += CHAN_RX_FRAMES;
1480 + }
1481 + hdev->rx_loc += 4;
1482 + hdev->rx_frame++;
1483 + if (hdev->rx_loc >= hdev->rx_buffer_size) {
1484 + hdev->rx_loc = 0;
1485 + buf = (u8 *)hdev->rx_buf;
1486 + }
1487 + }
1488 + }
1489 +
1490 + if (hdev->rx_frame >= hdev->rx_period_size && test_bit(1 << channel, &port->chan_rx_bitmap))
1491 + {
1492 + hdev->rx_frame %= hdev->rx_period_size;
1493 + if (hdev->rx_callback)
1494 + hdev->rx_callback(hdev->rx_data);
1495 + more_work = 1;
1496 + }
1497 + }
1498 +#if 0
1499 + if (more_work)
1500 + {
1501 + tasklet_hi_schedule(&port->task);
1502 + return;
1503 + }
1504 +#endif
1505 + }
1506 +
1507 + qmgr_enable_irq(queue_ids[port->id].chan);
1508 +
1509 + return;
1510 +
1511 +}
1512 +
1513 +struct hss_device *hss_chan_create(struct port *port, unsigned int channel)
1514 +{
1515 + struct hss_device *chan_dev;
1516 + unsigned long flags;
1517 +
1518 + chan_dev = kzalloc(sizeof(struct hss_device), GFP_KERNEL);
1519 +
1520 + spin_lock_irqsave(&npe_lock, flags);
1521 +
1522 + chan_dev->id = channel;
1523 + chan_dev->port = port;
1524 +
1525 + port->channels[channel] = channel;
1526 +
1527 + port->chan_devices[channel] = chan_dev;
1528 +
1529 + spin_unlock_irqrestore(&npe_lock, flags);
1530 +
1531 + return chan_dev;
1532 +}
1533 +
1534 +/*****************************************************************************
1535 + * initialization
1536 + ****************************************************************************/
1537 +
1538 +static struct platform_device gw_avila_hss_device_0 = {
1539 + .name = "ixp4xx_hss",
1540 + .id = 0,
1541 +};
1542 +
1543 +static struct platform_device gw_avila_hss_device_1 = {
1544 + .name = "ixp4xx_hss",
1545 + .id = 1,
1546 +};
1547 +
1548 +static struct platform_device *gw_avila_hss_port_0;
1549 +static struct platform_device *gw_avila_hss_port_1;
1550 +static u64 hss_dmamask = 0xFFFFFFFF;
1551 +
1552 +struct hss_device *hss_init(int id, int channel)
1553 +{
1554 + struct port *port = hss_port[id];
1555 + struct hss_device *hdev;
1556 + int ret;
1557 +
1558 + if (!lock_init)
1559 + {
1560 + spin_lock_init(&npe_lock);
1561 + lock_init = 1;
1562 + npe = npe_request(0);
1563 + }
1564 +
1565 + if (!port->init) {
1566 + if (id == 0) {
1567 + gw_avila_hss_port_0 = platform_device_alloc("hss-port", 0);
1568 +
1569 + platform_set_drvdata(gw_avila_hss_port_0, &gw_avila_hss_device_0);
1570 + port->dev = &gw_avila_hss_port_0->dev;
1571 +
1572 + if (!port->dev->dma_mask)
1573 + port->dev->dma_mask = &hss_dmamask;
1574 + if (!port->dev->coherent_dma_mask)
1575 + port->dev->coherent_dma_mask = 0xFFFFFFFF;
1576 +
1577 + ret = platform_device_add(gw_avila_hss_port_0);
1578 +
1579 + if (ret)
1580 + platform_device_put(gw_avila_hss_port_0);
1581 +
1582 + tasklet_init(&port->task, hss_chan_read, (unsigned long) port);
1583 + }
1584 + else
1585 + {
1586 + gw_avila_hss_port_1 = platform_device_alloc("hss-port", 1);
1587 +
1588 + platform_set_drvdata(gw_avila_hss_port_1, &gw_avila_hss_device_1);
1589 + port->dev = &gw_avila_hss_port_1->dev;
1590 +
1591 + if (!port->dev->dma_mask)
1592 + port->dev->dma_mask = &hss_dmamask;
1593 + if (!port->dev->coherent_dma_mask)
1594 + port->dev->coherent_dma_mask = 0xFFFFFFFF;
1595 +
1596 + ret = platform_device_add(gw_avila_hss_port_1);
1597 +
1598 + if (ret)
1599 + platform_device_put(gw_avila_hss_port_1);
1600 +
1601 + tasklet_init(&port->task, hss_chan_read, (unsigned long) port);
1602 + }
1603 +
1604 + port->init = 1;
1605 + port->id = id;
1606 + port->clock_type = CLOCK_EXT;
1607 + port->clock_rate = 8192000;
1608 + port->frame_size = 256; /* E1 */
1609 + port->mode = MODE_RAW;
1610 + port->next_rx_frame = 0;
1611 + memset(port->channels, CHANNEL_UNUSED, sizeof(port->channels));
1612 + }
1613 +
1614 + hdev = hss_chan_create(port, channel);
1615 +
1616 + return hdev;
1617 +}
1618 +EXPORT_SYMBOL(hss_init);
1619 +
1620 +int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data)
1621 +{
1622 + BUG_ON(tx_callback == NULL);
1623 + hdev->tx_callback = tx_callback;
1624 + hdev->tx_data = tx_data;
1625 +
1626 + return 0;
1627 +}
1628 +EXPORT_SYMBOL(hss_set_tx_callback);
1629 +
1630 +int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data)
1631 +{
1632 + BUG_ON(rx_callback == NULL);
1633 + hdev->rx_callback = rx_callback;
1634 + hdev->rx_data = rx_data;
1635 +
1636 + return 0;
1637 +}
1638 +EXPORT_SYMBOL(hss_set_rx_callback);
1639 +
1640 +int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size)
1641 +{
1642 + /*
1643 + * Period Size and Buffer Size are in Frames which are u32
1644 + * We convert the u32 *buf to u8 in order to make channel reads
1645 + * and rx_loc easier
1646 + */
1647 +
1648 + hdev->rx_buf = (u8 *)buf;
1649 + hdev->rx_buffer_size = buffer_size << 2;
1650 + hdev->rx_period_size = period_size;
1651 +
1652 + return 0;
1653 +}
1654 +EXPORT_SYMBOL(hss_config_rx_dma);
1655 +
1656 +int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size)
1657 +{
1658 + /*
1659 + * Period Size and Buffer Size are in Frames which are u32
1660 + * We convert the u32 *buf to u8 in order to make channel reads
1661 + * and rx_loc easier
1662 + */
1663 +
1664 + hdev->tx_buf = (u8 *)buf;
1665 + hdev->tx_buffer_size = buffer_size << 2;
1666 + hdev->tx_period_size = period_size;
1667 +
1668 + return 0;
1669 +}
1670 +EXPORT_SYMBOL(hss_config_tx_dma);
1671 +
1672 +unsigned long hss_curr_offset_rx(struct hss_device *hdev)
1673 +{
1674 + return hdev->rx_loc >> 2;
1675 +}
1676 +EXPORT_SYMBOL(hss_curr_offset_rx);
1677 +
1678 +unsigned long hss_curr_offset_tx(struct hss_device *hdev)
1679 +{
1680 + return hdev->tx_loc >> 2;
1681 +}
1682 +EXPORT_SYMBOL(hss_curr_offset_tx);
1683 +
1684 +MODULE_AUTHOR("Chris Lang");
1685 +MODULE_DESCRIPTION("Intel IXP4xx HSS Audio driver");
1686 +MODULE_LICENSE("GPL v2");
1687 --- /dev/null
1688 +++ b/sound/soc/gw-avila/ixp4xx_hss.h
1689 @@ -0,0 +1,401 @@
1690 +/*
1691 + *
1692 + *
1693 + * Copyright (C) 2009 Gateworks Corporation
1694 + *
1695 + * This program is free software; you can redistribute it and/or modify it
1696 + * under the terms of version 2 of the GNU General Public License
1697 + * as published by the Free Software Foundation.
1698 + */
1699 +
1700 +#include <linux/types.h>
1701 +#include <linux/bitops.h>
1702 +#include <linux/dma-mapping.h>
1703 +#include <linux/dmapool.h>
1704 +#include <linux/fs.h>
1705 +#include <linux/io.h>
1706 +#include <linux/kernel.h>
1707 +#include <linux/platform_device.h>
1708 +#include <linux/poll.h>
1709 +#include <mach/npe.h>
1710 +#include <mach/qmgr.h>
1711 +#include <linux/interrupt.h>
1712 +
1713 +//#include <linux/hdlc.h> XXX We aren't HDLC
1714 +
1715 +#define DEBUG_QUEUES 0
1716 +#define DEBUG_DESC 0
1717 +#define DEBUG_RX 0
1718 +#define DEBUG_TX 0
1719 +#define DEBUG_PKT_BYTES 0
1720 +#define DEBUG_CLOSE 0
1721 +#define DEBUG_FRAMER 0
1722 +
1723 +#define DRV_NAME "ixp4xx_hss"
1724 +
1725 +#define PKT_EXTRA_FLAGS 0 /* orig 1 */
1726 +#define TX_FRAME_SYNC_OFFSET 0 /* channelized */
1727 +#define PKT_NUM_PIPES 1 /* 1, 2 or 4 */
1728 +#define PKT_PIPE_FIFO_SIZEW 4 /* total 4 dwords per HSS */
1729 +
1730 +#define RX_DESCS 512 /* also length of all RX queues */
1731 +#define TX_DESCS 512 /* also length of all TX queues */
1732 +
1733 +//#define POOL_ALLOC_SIZE (sizeof(struct desc) * (RX_DESCS + TX_DESCS))
1734 +#define RX_SIZE (HDLC_MAX_MRU + 4) /* NPE needs more space */
1735 +#define MAX_CLOSE_WAIT 1000 /* microseconds */
1736 +#define HSS_COUNT 2
1737 +#define MIN_FRAME_SIZE 16 /* bits */
1738 +#define MAX_FRAME_SIZE 257 /* 256 bits + framing bit */
1739 +#define MAX_CHANNELS (MAX_FRAME_SIZE / 8)
1740 +#define MAX_CHAN_DEVICES 32
1741 +#define CHANNEL_HDLC 0xFE
1742 +#define CHANNEL_UNUSED 0xFF
1743 +
1744 +#define NAPI_WEIGHT 16
1745 +#define CHAN_RX_TRIGGER 16 /* 8 RX frames = 1 ms @ E1 */
1746 +#define CHAN_RX_FRAMES 128
1747 +#define CHAN_RX_TRUNKS 1
1748 +#define MAX_CHAN_RX_BAD_SYNC (CHAN_RX_TRIGGER / 2 /* pairs */ - 3)
1749 +
1750 +#define CHAN_TX_LIST_FRAMES CHAN_RX_TRIGGER /* bytes/channel per list, 16 - 48 */
1751 +#define CHAN_TX_LISTS 8
1752 +#define CHAN_TX_TRUNKS CHAN_RX_TRUNKS
1753 +#define CHAN_TX_FRAMES (CHAN_TX_LIST_FRAMES * CHAN_TX_LISTS)
1754 +
1755 +#define CHAN_QUEUE_LEN 32 /* minimum possible */
1756 +
1757 +#define chan_rx_buf_len(port) (port->frame_size / 8 * CHAN_RX_FRAMES * CHAN_RX_TRUNKS)
1758 +#define chan_tx_buf_len(port) (port->frame_size / 8 * CHAN_TX_FRAMES * CHAN_TX_TRUNKS)
1759 +
1760 +/* Queue IDs */
1761 +#define HSS0_CHL_RXTRIG_QUEUE 12 /* orig size = 32 dwords */
1762 +#define HSS0_PKT_RX_QUEUE 13 /* orig size = 32 dwords */
1763 +#define HSS0_PKT_TX0_QUEUE 14 /* orig size = 16 dwords */
1764 +#define HSS0_PKT_TX1_QUEUE 15
1765 +#define HSS0_PKT_TX2_QUEUE 16
1766 +#define HSS0_PKT_TX3_QUEUE 17
1767 +#define HSS0_PKT_RXFREE0_QUEUE 18 /* orig size = 16 dwords */
1768 +#define HSS0_PKT_RXFREE1_QUEUE 19
1769 +#define HSS0_PKT_RXFREE2_QUEUE 20
1770 +#define HSS0_PKT_RXFREE3_QUEUE 21
1771 +#define HSS0_PKT_TXDONE_QUEUE 22 /* orig size = 64 dwords */
1772 +
1773 +#define HSS1_CHL_RXTRIG_QUEUE 10
1774 +#define HSS1_PKT_RX_QUEUE 0
1775 +#define HSS1_PKT_TX0_QUEUE 5
1776 +#define HSS1_PKT_TX1_QUEUE 6
1777 +#define HSS1_PKT_TX2_QUEUE 7
1778 +#define HSS1_PKT_TX3_QUEUE 8
1779 +#define HSS1_PKT_RXFREE0_QUEUE 1
1780 +#define HSS1_PKT_RXFREE1_QUEUE 2
1781 +#define HSS1_PKT_RXFREE2_QUEUE 3
1782 +#define HSS1_PKT_RXFREE3_QUEUE 4
1783 +#define HSS1_PKT_TXDONE_QUEUE 9
1784 +
1785 +#define NPE_PKT_MODE_HDLC 0
1786 +#define NPE_PKT_MODE_RAW 1
1787 +#define NPE_PKT_MODE_56KMODE 2
1788 +#define NPE_PKT_MODE_56KENDIAN_MSB 4
1789 +
1790 +/* PKT_PIPE_HDLC_CFG_WRITE flags */
1791 +#define PKT_HDLC_IDLE_ONES 0x1 /* default = flags */
1792 +#define PKT_HDLC_CRC_32 0x2 /* default = CRC-16 */
1793 +#define PKT_HDLC_MSB_ENDIAN 0x4 /* default = LE */
1794 +
1795 +
1796 +/* hss_config, PCRs */
1797 +/* Frame sync sampling, default = active low */
1798 +#define PCR_FRM_SYNC_ACTIVE_HIGH 0x40000000
1799 +#define PCR_FRM_SYNC_FALLINGEDGE 0x80000000
1800 +#define PCR_FRM_SYNC_RISINGEDGE 0xC0000000
1801 +
1802 +/* Frame sync pin: input (default) or output generated off a given clk edge */
1803 +#define PCR_FRM_SYNC_OUTPUT_FALLING 0x20000000
1804 +#define PCR_FRM_SYNC_OUTPUT_RISING 0x30000000
1805 +
1806 +/* Frame and data clock sampling on edge, default = falling */
1807 +#define PCR_FCLK_EDGE_RISING 0x08000000
1808 +#define PCR_DCLK_EDGE_RISING 0x04000000
1809 +
1810 +/* Clock direction, default = input */
1811 +#define PCR_SYNC_CLK_DIR_OUTPUT 0x02000000
1812 +
1813 +/* Generate/Receive frame pulses, default = enabled */
1814 +#define PCR_FRM_PULSE_DISABLED 0x01000000
1815 +
1816 + /* Data rate is full (default) or half the configured clk speed */
1817 +#define PCR_HALF_CLK_RATE 0x00200000
1818 +
1819 +/* Invert data between NPE and HSS FIFOs? (default = no) */
1820 +#define PCR_DATA_POLARITY_INVERT 0x00100000
1821 +
1822 +/* TX/RX endianness, default = LSB */
1823 +#define PCR_MSB_ENDIAN 0x00080000
1824 +
1825 +/* Normal (default) / open drain mode (TX only) */
1826 +#define PCR_TX_PINS_OPEN_DRAIN 0x00040000
1827 +
1828 +/* No framing bit transmitted and expected on RX? (default = framing bit) */
1829 +#define PCR_SOF_NO_FBIT 0x00020000
1830 +
1831 +/* Drive data pins? */
1832 +#define PCR_TX_DATA_ENABLE 0x00010000
1833 +
1834 +/* Voice 56k type: drive the data pins low (default), high, high Z */
1835 +#define PCR_TX_V56K_HIGH 0x00002000
1836 +#define PCR_TX_V56K_HIGH_IMP 0x00004000
1837 +
1838 +/* Unassigned type: drive the data pins low (default), high, high Z */
1839 +#define PCR_TX_UNASS_HIGH 0x00000800
1840 +#define PCR_TX_UNASS_HIGH_IMP 0x00001000
1841 +
1842 +/* T1 @ 1.544MHz only: Fbit dictated in FIFO (default) or high Z */
1843 +#define PCR_TX_FB_HIGH_IMP 0x00000400
1844 +
1845 +/* 56k data endiannes - which bit unused: high (default) or low */
1846 +#define PCR_TX_56KE_BIT_0_UNUSED 0x00000200
1847 +
1848 +/* 56k data transmission type: 32/8 bit data (default) or 56K data */
1849 +#define PCR_TX_56KS_56K_DATA 0x00000100
1850 +
1851 +/* hss_config, cCR */
1852 +/* Number of packetized clients, default = 1 */
1853 +#define CCR_NPE_HFIFO_2_HDLC 0x04000000
1854 +#define CCR_NPE_HFIFO_3_OR_4HDLC 0x08000000
1855 +
1856 +/* default = no loopback */
1857 +#define CCR_LOOPBACK 0x02000000
1858 +
1859 +/* HSS number, default = 0 (first) */
1860 +#define CCR_SECOND_HSS 0x01000000
1861 +
1862 +
1863 +/* hss_config, clkCR: main:10, num:10, denom:12 */
1864 +#define CLK42X_SPEED_EXP ((0x3FF << 22) | ( 2 << 12) | 15) /*65 KHz*/
1865 +
1866 +#define CLK42X_SPEED_512KHZ (( 130 << 22) | ( 2 << 12) | 15)
1867 +#define CLK42X_SPEED_1536KHZ (( 43 << 22) | ( 18 << 12) | 47)
1868 +#define CLK42X_SPEED_1544KHZ (( 43 << 22) | ( 33 << 12) | 192)
1869 +#define CLK42X_SPEED_2048KHZ (( 32 << 22) | ( 34 << 12) | 63)
1870 +#define CLK42X_SPEED_4096KHZ (( 16 << 22) | ( 34 << 12) | 127)
1871 +#define CLK42X_SPEED_8192KHZ (( 8 << 22) | ( 34 << 12) | 255)
1872 +
1873 +#define CLK46X_SPEED_512KHZ (( 130 << 22) | ( 24 << 12) | 127)
1874 +#define CLK46X_SPEED_1536KHZ (( 43 << 22) | (152 << 12) | 383)
1875 +#define CLK46X_SPEED_1544KHZ (( 43 << 22) | ( 66 << 12) | 385)
1876 +#define CLK46X_SPEED_2048KHZ (( 32 << 22) | (280 << 12) | 511)
1877 +#define CLK46X_SPEED_4096KHZ (( 16 << 22) | (280 << 12) | 1023)
1878 +#define CLK46X_SPEED_8192KHZ (( 8 << 22) | (280 << 12) | 2047)
1879 +
1880 +
1881 +/* hss_config, LUT entries */
1882 +#define TDMMAP_UNASSIGNED 0
1883 +#define TDMMAP_HDLC 1 /* HDLC - packetized */
1884 +#define TDMMAP_VOICE56K 2 /* Voice56K - 7-bit channelized */
1885 +#define TDMMAP_VOICE64K 3 /* Voice64K - 8-bit channelized */
1886 +
1887 +/* offsets into HSS config */
1888 +#define HSS_CONFIG_TX_PCR 0x00 /* port configuration registers */
1889 +#define HSS_CONFIG_RX_PCR 0x04
1890 +#define HSS_CONFIG_CORE_CR 0x08 /* loopback control, HSS# */
1891 +#define HSS_CONFIG_CLOCK_CR 0x0C /* clock generator control */
1892 +#define HSS_CONFIG_TX_FCR 0x10 /* frame configuration registers */
1893 +#define HSS_CONFIG_RX_FCR 0x14
1894 +#define HSS_CONFIG_TX_LUT 0x18 /* channel look-up tables */
1895 +#define HSS_CONFIG_RX_LUT 0x38
1896 +
1897 +
1898 +/* NPE command codes */
1899 +/* writes the ConfigWord value to the location specified by offset */
1900 +#define PORT_CONFIG_WRITE 0x40
1901 +
1902 +/* triggers the NPE to load the contents of the configuration table */
1903 +#define PORT_CONFIG_LOAD 0x41
1904 +
1905 +/* triggers the NPE to return an HssErrorReadResponse message */
1906 +#define PORT_ERROR_READ 0x42
1907 +
1908 +/* reset NPE internal status and enable the HssChannelized operation */
1909 +#define CHAN_FLOW_ENABLE 0x43
1910 +#define CHAN_FLOW_DISABLE 0x44
1911 +#define CHAN_IDLE_PATTERN_WRITE 0x45
1912 +#define CHAN_NUM_CHANS_WRITE 0x46
1913 +#define CHAN_RX_BUF_ADDR_WRITE 0x47
1914 +#define CHAN_RX_BUF_CFG_WRITE 0x48
1915 +#define CHAN_TX_BLK_CFG_WRITE 0x49
1916 +#define CHAN_TX_BUF_ADDR_WRITE 0x4A
1917 +#define CHAN_TX_BUF_SIZE_WRITE 0x4B
1918 +#define CHAN_TSLOTSWITCH_ENABLE 0x4C
1919 +#define CHAN_TSLOTSWITCH_DISABLE 0x4D
1920 +
1921 +/* downloads the gainWord value for a timeslot switching channel associated
1922 + with bypassNum */
1923 +#define CHAN_TSLOTSWITCH_GCT_DOWNLOAD 0x4E
1924 +
1925 +/* triggers the NPE to reset internal status and enable the HssPacketized
1926 + operation for the flow specified by pPipe */
1927 +#define PKT_PIPE_FLOW_ENABLE 0x50
1928 +#define PKT_PIPE_FLOW_DISABLE 0x51
1929 +#define PKT_NUM_PIPES_WRITE 0x52
1930 +#define PKT_PIPE_FIFO_SIZEW_WRITE 0x53
1931 +#define PKT_PIPE_HDLC_CFG_WRITE 0x54
1932 +#define PKT_PIPE_IDLE_PATTERN_WRITE 0x55
1933 +#define PKT_PIPE_RX_SIZE_WRITE 0x56
1934 +#define PKT_PIPE_MODE_WRITE 0x57
1935 +
1936 +/* HDLC packet status values - desc->status */
1937 +#define ERR_SHUTDOWN 1 /* stop or shutdown occurrance */
1938 +#define ERR_HDLC_ALIGN 2 /* HDLC alignment error */
1939 +#define ERR_HDLC_FCS 3 /* HDLC Frame Check Sum error */
1940 +#define ERR_RXFREE_Q_EMPTY 4 /* RX-free queue became empty while receiving
1941 + this packet (if buf_len < pkt_len) */
1942 +#define ERR_HDLC_TOO_LONG 5 /* HDLC frame size too long */
1943 +#define ERR_HDLC_ABORT 6 /* abort sequence received */
1944 +#define ERR_DISCONNECTING 7 /* disconnect is in progress */
1945 +
1946 +#define CLOCK_EXT 0
1947 +#define CLOCK_INT 1
1948 +
1949 +enum mode {MODE_HDLC = 0, MODE_RAW, MODE_G704};
1950 +enum rx_tx_bit {
1951 + TX_BIT = 0,
1952 + RX_BIT = 1
1953 +};
1954 +enum chan_bit {
1955 + CHAN_0 = (1 << 0),
1956 + CHAN_1 = (1 << 1),
1957 + CHAN_2 = (1 << 2),
1958 + CHAN_3 = (1 << 3),
1959 + CHAN_4 = (1 << 4),
1960 + CHAN_5 = (1 << 5),
1961 + CHAN_6 = (1 << 6),
1962 + CHAN_7 = (1 << 7),
1963 + CHAN_8 = (1 << 8),
1964 + CHAN_9 = (1 << 9),
1965 + CHAN_10 = (1 << 10),
1966 + CHAN_11 = (1 << 11),
1967 + CHAN_12 = (1 << 12),
1968 + CHAN_13 = (1 << 13),
1969 + CHAN_14 = (1 << 14),
1970 + CHAN_15 = (1 << 15)
1971 +};
1972 +
1973 +enum alignment { NOT_ALIGNED = 0, EVEN_FIRST, ODD_FIRST };
1974 +
1975 +#ifdef __ARMEB__
1976 +typedef struct sk_buff buffer_t;
1977 +#define free_buffer dev_kfree_skb
1978 +#define free_buffer_irq dev_kfree_skb_irq
1979 +#else
1980 +typedef void buffer_t;
1981 +#define free_buffer kfree
1982 +#define free_buffer_irq kfree
1983 +#endif
1984 +
1985 +struct hss_device {
1986 + struct port *port;
1987 + unsigned int open_count, excl_open;
1988 + unsigned long tx_loc, rx_loc; /* bytes */
1989 + unsigned long tx_frame, rx_frame; /* Frames */
1990 + u8 id, chan_count;
1991 + u8 log_channels[MAX_CHANNELS];
1992 +
1993 + u8 *rx_buf;
1994 + u8 *tx_buf;
1995 +
1996 + size_t rx_buffer_size;
1997 + size_t rx_period_size;
1998 + size_t tx_buffer_size;
1999 + size_t tx_period_size;
2000 +
2001 + void (*rx_callback)(void *data);
2002 + void *rx_data;
2003 + void (*tx_callback)(void *data);
2004 + void *tx_data;
2005 + void *private_data;
2006 +};
2007 +
2008 +extern struct hss_device *hss_handle[32];
2009 +extern struct port *hss_port[2];
2010 +
2011 +struct port {
2012 + unsigned char init;
2013 +
2014 + struct device *dev;
2015 +
2016 + struct tasklet_struct task;
2017 + unsigned int id;
2018 + unsigned long chan_rx_bitmap;
2019 + unsigned long chan_tx_bitmap;
2020 + unsigned char chan_open;
2021 +
2022 + /* the following fields must be protected by npe_lock */
2023 + enum mode mode;
2024 + unsigned int clock_type, clock_rate, loopback;
2025 + unsigned int frame_size, frame_sync_offset;
2026 + unsigned int next_rx_frame;
2027 +
2028 + struct hss_device *chan_devices[MAX_CHAN_DEVICES];
2029 + u32 chan_tx_buf_phys, chan_rx_buf_phys;
2030 + u32 chan_tx_pointers_phys;
2031 + u32 *chan_tx_pointers;
2032 + u8 *chan_rx_buf;
2033 + u8 *chan_tx_buf;
2034 + u8 *tx_lists[CHAN_TX_LISTS][8];
2035 + u8 *rx_frames[8][CHAN_TX_LISTS];
2036 + unsigned int chan_open_count, hdlc_open;
2037 + unsigned int chan_started, initialized, just_set_offset;
2038 + unsigned int chan_last_rx, chan_last_tx;
2039 +
2040 + /* assigned channels, may be invalid with given frame length or mode */
2041 + u8 channels[MAX_CHANNELS];
2042 + int msg_count;
2043 +};
2044 +
2045 +/* NPE message structure */
2046 +struct msg {
2047 +#ifdef __ARMEB__
2048 + u8 cmd, unused, hss_port, index;
2049 + union {
2050 + struct { u8 data8a, data8b, data8c, data8d; };
2051 + struct { u16 data16a, data16b; };
2052 + struct { u32 data32; };
2053 + };
2054 +#else
2055 + u8 index, hss_port, unused, cmd;
2056 + union {
2057 + struct { u8 data8d, data8c, data8b, data8a; };
2058 + struct { u16 data16b, data16a; };
2059 + struct { u32 data32; };
2060 + };
2061 +#endif
2062 +};
2063 +
2064 +#define rx_desc_phys(port, n) ((port)->desc_tab_phys + \
2065 + (n) * sizeof(struct desc))
2066 +#define rx_desc_ptr(port, n) (&(port)->desc_tab[n])
2067 +
2068 +#define tx_desc_phys(port, n) ((port)->desc_tab_phys + \
2069 + ((n) + RX_DESCS) * sizeof(struct desc))
2070 +#define tx_desc_ptr(port, n) (&(port)->desc_tab[(n) + RX_DESCS])
2071 +
2072 +int hss_prepare_chan(struct port *port);
2073 +void hss_chan_stop(struct port *port);
2074 +
2075 +struct hss_device *hss_init(int id, int channel);
2076 +int hss_chan_open(struct hss_device *hdev);
2077 +int hss_chan_close(struct hss_device *hdev);
2078 +
2079 +int hss_set_tx_callback(struct hss_device *hdev, void (*tx_callback)(void *), void *tx_data);
2080 +int hss_set_rx_callback(struct hss_device *hdev, void (*rx_callback)(void *), void *rx_data);
2081 +int hss_tx_start(struct hss_device *hdev);
2082 +int hss_tx_stop(struct hss_device *hdev);
2083 +int hss_rx_start(struct hss_device *hdev);
2084 +int hss_rx_stop(struct hss_device *hdev);
2085 +
2086 +int hss_config_rx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size);
2087 +int hss_config_tx_dma(struct hss_device *hdev, void *buf, size_t buffer_size, size_t period_size);
2088 +unsigned long hss_curr_offset_rx(struct hss_device *hdev);
2089 +unsigned long hss_curr_offset_tx(struct hss_device *hdev);
2090 +
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