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[openwrt/staging/yousong.git] / target / linux / mediatek / patches-4.4 / 0009-clk-mediatek-Add-MT2701-clock-support.patch
1 From a4c507d052390b42d7e8c59241e3c336796f730f Mon Sep 17 00:00:00 2001
2 From: Shunli Wang <shunli.wang@mediatek.com>
3 Date: Tue, 5 Jan 2016 14:30:20 +0800
4 Subject: [PATCH 009/102] clk: mediatek: Add MT2701 clock support
5
6 Add MT2701 clock support, include topckgen, apmixedsys,
7 infracfg, pericfg and subsystem clocks.
8
9 Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
10 Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
11 ---
12 drivers/clk/mediatek/Kconfig | 8 +
13 drivers/clk/mediatek/Makefile | 1 +
14 drivers/clk/mediatek/clk-gate.c | 56 ++
15 drivers/clk/mediatek/clk-gate.h | 2 +
16 drivers/clk/mediatek/clk-mt2701.c | 1210 +++++++++++++++++++++++++++++++++++++
17 drivers/clk/mediatek/clk-mtk.c | 25 +
18 drivers/clk/mediatek/clk-mtk.h | 35 +-
19 7 files changed, 1334 insertions(+), 3 deletions(-)
20 create mode 100644 drivers/clk/mediatek/clk-mt2701.c
21
22 --- a/drivers/clk/mediatek/Kconfig
23 +++ b/drivers/clk/mediatek/Kconfig
24 @@ -6,6 +6,14 @@ config COMMON_CLK_MEDIATEK
25 ---help---
26 Mediatek SoCs' clock support.
27
28 +config COMMON_CLK_MT2701
29 + bool "Clock driver for Mediatek MT2701 and MT7623"
30 + depends on COMMON_CLK
31 + select COMMON_CLK_MEDIATEK
32 + default ARCH_MEDIATEK
33 + ---help---
34 + This driver supports Mediatek MT2701 and MT7623 clocks.
35 +
36 config COMMON_CLK_MT8135
37 bool "Clock driver for Mediatek MT8135"
38 depends on COMMON_CLK
39 --- a/drivers/clk/mediatek/Makefile
40 +++ b/drivers/clk/mediatek/Makefile
41 @@ -1,4 +1,5 @@
42 obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o
43 obj-$(CONFIG_RESET_CONTROLLER) += reset.o
44 +obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o
45 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
46 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
47 --- a/drivers/clk/mediatek/clk-gate.c
48 +++ b/drivers/clk/mediatek/clk-gate.c
49 @@ -61,6 +61,26 @@ static void mtk_cg_clr_bit(struct clk_hw
50 regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
51 }
52
53 +static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
54 +{
55 + struct mtk_clk_gate *cg = to_clk_gate(hw);
56 + u32 val;
57 +
58 + regmap_read(cg->regmap, cg->sta_ofs, &val);
59 + val |= BIT(cg->bit);
60 + regmap_write(cg->regmap, cg->sta_ofs, val);
61 +}
62 +
63 +static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
64 +{
65 + struct mtk_clk_gate *cg = to_clk_gate(hw);
66 + u32 val;
67 +
68 + regmap_read(cg->regmap, cg->sta_ofs, &val);
69 + val &= ~(BIT(cg->bit));
70 + regmap_write(cg->regmap, cg->sta_ofs, val);
71 +}
72 +
73 static int mtk_cg_enable(struct clk_hw *hw)
74 {
75 mtk_cg_clr_bit(hw);
76 @@ -85,6 +105,30 @@ static void mtk_cg_disable_inv(struct cl
77 mtk_cg_clr_bit(hw);
78 }
79
80 +static int mtk_cg_enable_no_setclr(struct clk_hw *hw)
81 +{
82 + mtk_cg_clr_bit_no_setclr(hw);
83 +
84 + return 0;
85 +}
86 +
87 +static void mtk_cg_disable_no_setclr(struct clk_hw *hw)
88 +{
89 + mtk_cg_set_bit_no_setclr(hw);
90 +}
91 +
92 +static int mtk_cg_enable_inv_no_setclr(struct clk_hw *hw)
93 +{
94 + mtk_cg_set_bit_no_setclr(hw);
95 +
96 + return 0;
97 +}
98 +
99 +static void mtk_cg_disable_inv_no_setclr(struct clk_hw *hw)
100 +{
101 + mtk_cg_clr_bit_no_setclr(hw);
102 +}
103 +
104 const struct clk_ops mtk_clk_gate_ops_setclr = {
105 .is_enabled = mtk_cg_bit_is_cleared,
106 .enable = mtk_cg_enable,
107 @@ -97,6 +141,18 @@ const struct clk_ops mtk_clk_gate_ops_se
108 .disable = mtk_cg_disable_inv,
109 };
110
111 +const struct clk_ops mtk_clk_gate_ops_no_setclr = {
112 + .is_enabled = mtk_cg_bit_is_cleared,
113 + .enable = mtk_cg_enable_no_setclr,
114 + .disable = mtk_cg_disable_no_setclr,
115 +};
116 +
117 +const struct clk_ops mtk_clk_gate_ops_no_setclr_inv = {
118 + .is_enabled = mtk_cg_bit_is_set,
119 + .enable = mtk_cg_enable_inv_no_setclr,
120 + .disable = mtk_cg_disable_inv_no_setclr,
121 +};
122 +
123 struct clk * __init mtk_clk_register_gate(
124 const char *name,
125 const char *parent_name,
126 --- a/drivers/clk/mediatek/clk-gate.h
127 +++ b/drivers/clk/mediatek/clk-gate.h
128 @@ -36,6 +36,8 @@ static inline struct mtk_clk_gate *to_cl
129
130 extern const struct clk_ops mtk_clk_gate_ops_setclr;
131 extern const struct clk_ops mtk_clk_gate_ops_setclr_inv;
132 +extern const struct clk_ops mtk_clk_gate_ops_no_setclr;
133 +extern const struct clk_ops mtk_clk_gate_ops_no_setclr_inv;
134
135 struct clk *mtk_clk_register_gate(
136 const char *name,
137 --- /dev/null
138 +++ b/drivers/clk/mediatek/clk-mt2701.c
139 @@ -0,0 +1,1210 @@
140 +/*
141 + * Copyright (c) 2014 MediaTek Inc.
142 + * Author: Shunli Wang <shunli.wang@mediatek.com>
143 + *
144 + * This program is free software; you can redistribute it and/or modify
145 + * it under the terms of the GNU General Public License version 2 as
146 + * published by the Free Software Foundation.
147 + *
148 + * This program is distributed in the hope that it will be useful,
149 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
150 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
151 + * GNU General Public License for more details.
152 + */
153 +
154 +#include <linux/clk.h>
155 +#include <linux/of.h>
156 +#include <linux/of_address.h>
157 +
158 +#include "clk-mtk.h"
159 +#include "clk-gate.h"
160 +
161 +#include <dt-bindings/clock/mt2701-clk.h>
162 +
163 +static DEFINE_SPINLOCK(lock);
164 +
165 +static const struct mtk_fixed_clk top_fixed_clks[] __initconst = {
166 + FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m", 108 * MHZ),
167 + FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m", 400 * MHZ),
168 + FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m", 295750000),
169 + FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m", 340 * MHZ),
170 + FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m", 340 * MHZ),
171 + FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m", 340 * MHZ),
172 + FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m", 300 * MHZ),
173 + FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m", 27 * MHZ),
174 + FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m", 416 * MHZ),
175 +};
176 +
177 +static const struct mtk_fixed_factor top_fixed_divs[] __initconst = {
178 + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
179 + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
180 + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
181 + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
182 + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
183 + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
184 + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
185 + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
186 + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
187 + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
188 + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
189 + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
190 + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
191 + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
192 + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
193 + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
194 +
195 + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
196 + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
197 + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
198 + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
199 + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
200 + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
201 + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
202 + FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
203 + FACTOR(CLK_TOP_USB_PHY48M, "USB_PHY48M_CK", "univpll", 1, 26),
204 + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
205 + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
206 + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
207 + FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
208 + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
209 + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
210 + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
211 + FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
212 + FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
213 + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
214 + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
215 + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
216 +
217 + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
218 + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
219 + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
220 + FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
221 +
222 + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
223 + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
224 +
225 + FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
226 + FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
227 + FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
228 +
229 + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
230 + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
231 + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
232 +
233 + FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
234 + FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
235 + FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
236 +
237 + FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
238 + FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
239 + FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
240 +
241 + FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
242 + FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
243 + FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
244 +
245 + FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
246 +
247 + FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
248 + FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
249 + FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
250 + FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
251 + FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
252 +
253 + FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
254 + FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
255 + FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
256 + FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
257 + FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
258 + FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
259 + FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
260 + FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
261 +};
262 +
263 +static const char * const axi_parents[] __initconst = {
264 + "clk26m",
265 + "syspll1_d2",
266 + "syspll_d5",
267 + "syspll1_d4",
268 + "univpll_d5",
269 + "univpll2_d2",
270 + "mmpll_d2",
271 + "dmpll_d2"
272 +};
273 +
274 +static const char * const mem_parents[] __initconst = {
275 + "clk26m",
276 + "dmpll_ck"
277 +};
278 +
279 +static const char * const ddrphycfg_parents[] __initconst = {
280 + "clk26m",
281 + "syspll1_d8"
282 +};
283 +
284 +static const char * const mm_parents[] __initconst = {
285 + "clk26m",
286 + "vencpll_ck",
287 + "syspll1_d2",
288 + "syspll1_d4",
289 + "univpll_d5",
290 + "univpll1_d2",
291 + "univpll2_d2",
292 + "dmpll_ck"
293 +};
294 +
295 +static const char * const pwm_parents[] __initconst = {
296 + "clk26m",
297 + "univpll2_d4",
298 + "univpll3_d2",
299 + "univpll1_d4",
300 +};
301 +
302 +static const char * const vdec_parents[] __initconst = {
303 + "clk26m",
304 + "vdecpll_ck",
305 + "syspll_d5",
306 + "syspll1_d4",
307 + "univpll_d5",
308 + "univpll2_d2",
309 + "vencpll_ck",
310 + "msdcpll_d2",
311 + "mmpll_d2"
312 +};
313 +
314 +static const char * const mfg_parents[] __initconst = {
315 + "clk26m",
316 + "mmpll_ck",
317 + "dmpll_x2_ck",
318 + "msdcpll_ck",
319 + "clk26m",
320 + "syspll_d3",
321 + "univpll_d3",
322 + "univpll1_d2"
323 +};
324 +
325 +static const char * const camtg_parents[] __initconst = {
326 + "clk26m",
327 + "univpll_d26",
328 + "univpll2_d2",
329 + "syspll3_d2",
330 + "syspll3_d4",
331 + "msdcpll_d2",
332 + "mmpll_d2"
333 +};
334 +
335 +static const char * const uart_parents[] __initconst = {
336 + "clk26m",
337 + "univpll2_d8"
338 +};
339 +
340 +static const char * const spi_parents[] __initconst = {
341 + "clk26m",
342 + "syspll3_d2",
343 + "syspll4_d2",
344 + "univpll2_d4",
345 + "univpll1_d8"
346 +};
347 +
348 +static const char * const usb20_parents[] __initconst = {
349 + "clk26m",
350 + "univpll1_d8",
351 + "univpll3_d4"
352 +};
353 +
354 +static const char * const msdc30_parents[] __initconst = {
355 + "clk26m",
356 + "msdcpll_d2",
357 + "syspll2_d2",
358 + "syspll1_d4",
359 + "univpll1_d4",
360 + "univpll2_d4"
361 +};
362 +
363 +static const char * const audio_parents[] __initconst = {
364 + "clk26m",
365 + "syspll1_d16"
366 +};
367 +
368 +static const char * const aud_intbus_parents[] __initconst = {
369 + "clk26m",
370 + "syspll1_d4",
371 + "syspll3_d2",
372 + "syspll4_d2",
373 + "univpll3_d2",
374 + "univpll2_d4"
375 +};
376 +
377 +static const char * const pmicspi_parents[] __initconst = {
378 + "clk26m",
379 + "syspll1_d8",
380 + "syspll2_d4",
381 + "syspll4_d2",
382 + "syspll3_d4",
383 + "syspll2_d8",
384 + "syspll1_d16",
385 + "univpll3_d4",
386 + "univpll_d26",
387 + "dmpll_d2",
388 + "dmpll_d4"
389 +};
390 +
391 +static const char * const scp_parents[] __initconst = {
392 + "clk26m",
393 + "syspll1_d8",
394 + "dmpll_d2",
395 + "dmpll_d4"
396 +};
397 +
398 +static const char * const dpi0_parents[] __initconst = {
399 + "clk26m",
400 + "mipipll",
401 + "mipipll_d2",
402 + "mipipll_d4",
403 + "clk26m",
404 + "tvdpll_ck",
405 + "tvdpll_d2",
406 + "tvdpll_d4"
407 +};
408 +
409 +static const char * const dpi1_parents[] __initconst = {
410 + "clk26m",
411 + "tvdpll_ck",
412 + "tvdpll_d2",
413 + "tvdpll_d4"
414 +};
415 +
416 +static const char * const tve_parents[] __initconst = {
417 + "clk26m",
418 + "mipipll",
419 + "mipipll_d2",
420 + "mipipll_d4",
421 + "clk26m",
422 + "tvdpll_ck",
423 + "tvdpll_d2",
424 + "tvdpll_d4"
425 +};
426 +
427 +static const char * const hdmi_parents[] __initconst = {
428 + "clk26m",
429 + "hdmipll_ck",
430 + "hdmipll_d2",
431 + "hdmipll_d3"
432 +};
433 +
434 +static const char * const apll_parents[] __initconst = {
435 + "clk26m",
436 + "audpll",
437 + "audpll_d4",
438 + "audpll_d8",
439 + "audpll_d16",
440 + "audpll_d24",
441 + "clk26m",
442 + "clk26m"
443 +};
444 +
445 +static const char * const rtc_parents[] __initconst = {
446 + "32k_internal",
447 + "32k_external",
448 + "clk26m",
449 + "univpll3_d8"
450 +};
451 +
452 +static const char * const nfi2x_parents[] __initconst = {
453 + "clk26m",
454 + "syspll2_d2",
455 + "syspll_d7",
456 + "univpll3_d2",
457 + "syspll2_d4",
458 + "univpll3_d4",
459 + "syspll4_d4",
460 + "clk26m"
461 +};
462 +
463 +static const char * const emmc_hclk_parents[] __initconst = {
464 + "clk26m",
465 + "syspll1_d2",
466 + "syspll1_d4",
467 + "syspll2_d2"
468 +};
469 +
470 +static const char * const flash_parents[] __initconst = {
471 + "clk26m_d8",
472 + "clk26m",
473 + "syspll2_d8",
474 + "syspll3_d4",
475 + "univpll3_d4",
476 + "syspll4_d2",
477 + "syspll2_d4",
478 + "univpll2_d4"
479 +};
480 +
481 +static const char * const di_parents[] __initconst = {
482 + "clk26m",
483 + "tvd2pll_ck",
484 + "tvd2pll_d2",
485 + "clk26m"
486 +};
487 +
488 +static const char * const nr_osd_parents[] __initconst = {
489 + "clk26m",
490 + "vencpll_ck",
491 + "syspll1_d2",
492 + "syspll1_d4",
493 + "univpll_d5",
494 + "univpll1_d2",
495 + "univpll2_d2",
496 + "dmpll_ck"
497 +};
498 +
499 +static const char * const hdmirx_bist_parents[] __initconst = {
500 + "clk26m",
501 + "syspll_d3",
502 + "clk26m",
503 + "syspll1_d16",
504 + "syspll4_d2",
505 + "syspll1_d4",
506 + "vencpll_ck",
507 + "clk26m"
508 +};
509 +
510 +static const char * const intdir_parents[] __initconst = {
511 + "clk26m",
512 + "mmpll_ck",
513 + "syspll_d2",
514 + "univpll_d2"
515 +};
516 +
517 +static const char * const asm_parents[] __initconst = {
518 + "clk26m",
519 + "univpll2_d4",
520 + "univpll2_d2",
521 + "syspll_d5"
522 +};
523 +
524 +static const char * const ms_card_parents[] __initconst = {
525 + "clk26m",
526 + "univpll3_d8",
527 + "syspll4_d4"
528 +};
529 +
530 +static const char * const ethif_parents[] __initconst = {
531 + "clk26m",
532 + "syspll1_d2",
533 + "syspll_d5",
534 + "syspll1_d4",
535 + "univpll_d5",
536 + "univpll1_d2",
537 + "dmpll_ck",
538 + "dmpll_d2"
539 +};
540 +
541 +static const char * const hdmirx_parents[] __initconst = {
542 + "clk26m",
543 + "univpll_d52"
544 +};
545 +
546 +static const char * const cmsys_parents[] __initconst = {
547 + "clk26m",
548 + "syspll1_d2",
549 + "univpll1_d2",
550 + "univpll_d5",
551 + "syspll_d5",
552 + "syspll2_d2",
553 + "syspll1_d4",
554 + "syspll3_d2",
555 + "syspll2_d4",
556 + "syspll1_d8",
557 + "clk26m",
558 + "clk26m",
559 + "clk26m",
560 + "clk26m",
561 + "clk26m"
562 +};
563 +
564 +static const char * const clk_8bdac_parents[] __initconst = {
565 + "clkrtc_int",
566 + "8bdac_ck_pre",
567 + "clk26m",
568 + "clk26m"
569 +};
570 +
571 +static const char * const aud2dvd_parents[] __initconst = {
572 + "a1sys_hp_ck",
573 + "a2sys_hp_ck"
574 +};
575 +
576 +static const char * const padmclk_parents[] __initconst = {
577 + "clk26m",
578 + "univpll_d26",
579 + "univpll_d52",
580 + "univpll_d108",
581 + "univpll2_d8",
582 + "univpll2_d16",
583 + "univpll2_d32"
584 +};
585 +
586 +static const char * const aud_mux_parents[] __initconst = {
587 + "clk26m",
588 + "aud1pll_98m_ck",
589 + "aud2pll_90m_ck",
590 + "hadds2pll_98m",
591 + "audio_ext1_ck",
592 + "audio_ext2_ck"
593 +};
594 +
595 +static const char * const aud_src_parents[] __initconst = {
596 + "aud_mux1_sel",
597 + "aud_mux2_sel"
598 +};
599 +
600 +static const char * const cpu_parents[] __initconst = {
601 + "clk26m",
602 + "armpll",
603 + "mainpll",
604 + "mmpll"
605 +};
606 +
607 +static const struct mtk_composite top_muxes[] __initconst = {
608 + MUX_GATE(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
609 + 0x0040, 0, 3, INVALID_MUX_GATE_BIT),
610 + MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1, 15),
611 + MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel", ddrphycfg_parents, 0x0040, 16, 1, 23),
612 + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 3, 31),
613 +
614 + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents, 0x0050, 0, 2, 7),
615 + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents, 0x0050, 8, 4, 15),
616 + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents, 0x0050, 16, 3, 23),
617 + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents, 0x0050, 24, 3, 31),
618 + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 0, 1, 7),
619 +
620 + MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents, 0x0060, 8, 3, 15),
621 + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents, 0x0060, 16, 2, 23),
622 + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents, 0x0060, 24, 3, 31),
623 +
624 + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0070, 0, 3, 7),
625 + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0070, 8, 3, 15),
626 + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents, 0x0070, 16, 1, 23),
627 + MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents, 0x0070, 24, 3, 31),
628 +
629 + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents, 0x0080, 0, 4, 7),
630 + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0080, 8, 2, 15),
631 + MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x0080, 16, 3, 23),
632 + MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents, 0x0080, 24, 2, 31),
633 +
634 + MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents, 0x0090, 0, 3, 7),
635 + MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents, 0x0090, 8, 2, 15),
636 + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents, 0x0090, 16, 3, 23),
637 +
638 + MUX_GATE(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents, 0x00A0, 0, 2, 7),
639 + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents, 0x00A0, 8, 3, 15),
640 + MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents, 0x00A0, 24, 2, 31),
641 +
642 + MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents, 0x00B0, 0, 3, 7),
643 + MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents, 0x00B0, 8, 2, 15),
644 + MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents, 0x00B0, 16, 3, 23),
645 + MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents, 0x00B0, 24, 3, 31),
646 +
647 + MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel", hdmirx_bist_parents, 0x00C0, 0, 3, 7),
648 + MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents, 0x00C0, 8, 2, 15),
649 + MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents, 0x00C0, 16, 2, 23),
650 + MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents, 0x00C0, 24, 3, 31),
651 +
652 + MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents, 0x00D0, 0, 2, 7),
653 + MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents, 0x00D0, 16, 2, 23),
654 + MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents, 0x00D0, 24, 3, 31),
655 +
656 + MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents, 0x00E0, 0, 1, 7),
657 + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents, 0x00E0, 8, 3, 15),
658 + MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents, 0x00E0, 16, 4, 23),
659 +
660 + MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents, 0x00E0, 24, 3, 31),
661 + MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents, 0x00F0, 0, 3, 7),
662 + MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents, 0x00F0, 8, 2, 15),
663 + MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents, 0x00F0, 16, 1, 23),
664 +
665 + MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents, 0x0100, 0, 3),
666 +
667 + MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents, 0x012c, 0, 3),
668 + MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents, 0x012c, 3, 3),
669 + MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents, 0x012c, 6, 3),
670 + MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents, 0x012c, 15, 1, 23),
671 + MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents, 0x012c, 16, 1, 24),
672 + MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents, 0x012c, 17, 1, 25),
673 + MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents, 0x012c, 18, 1, 26),
674 + MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents, 0x012c, 19, 1, 27),
675 + MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents, 0x012c, 20, 1, 28),
676 +};
677 +
678 +static const struct mtk_clk_divider top_adj_divs[] __initconst = {
679 + DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext_ck1", 0x0120, 0, 8),
680 + DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext_ck2", 0x0120, 8, 8),
681 + DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel", 0x0120, 16, 8),
682 + DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel", 0x0120, 24, 8),
683 + DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel", 0x0124, 0, 8),
684 + DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel", 0x0124, 8, 8),
685 + DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel", 0x0124, 16, 8),
686 + DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel", 0x0124, 24, 8),
687 + DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel", 0x0128, 0, 8),
688 + DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel", 0x0128, 8, 8),
689 +};
690 +
691 +static const struct mtk_gate_regs top_aud_cg_regs __initconst = {
692 + .sta_ofs = 0x012C,
693 +};
694 +
695 +#define GATE_TOP_AUD(_id, _name, _parent, _shift) { \
696 + .id = _id, \
697 + .name = _name, \
698 + .parent_name = _parent, \
699 + .regs = &top_aud_cg_regs, \
700 + .shift = _shift, \
701 + .ops = &mtk_clk_gate_ops_no_setclr, \
702 + }
703 +
704 +static const struct mtk_gate top_clks[] __initconst = {
705 + GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div", 21),
706 + GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div", 22),
707 + GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div", 23),
708 + GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div", 24),
709 + GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div", 25),
710 + GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div", 26),
711 + GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div", 27),
712 + GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div", 28),
713 +};
714 +
715 +static void __init mtk_topckgen_init(struct device_node *node)
716 +{
717 + struct clk_onecell_data *clk_data;
718 + void __iomem *base;
719 + int r;
720 +
721 + base = of_iomap(node, 0);
722 + if (!base) {
723 + pr_err("%s(): ioremap failed\n", __func__);
724 + return;
725 + }
726 +
727 + clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
728 +
729 + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
730 + clk_data);
731 +
732 + mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
733 + clk_data);
734 +
735 + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
736 + base, &lock, clk_data);
737 +
738 + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
739 + base, &lock, clk_data);
740 +
741 + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
742 + clk_data);
743 +
744 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
745 + if (r)
746 + pr_err("%s(): could not register clock provider: %d\n",
747 + __func__, r);
748 +}
749 +CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt2701-topckgen", mtk_topckgen_init);
750 +
751 +static const struct mtk_gate_regs infra_cg_regs __initconst = {
752 + .set_ofs = 0x0040,
753 + .clr_ofs = 0x0044,
754 + .sta_ofs = 0x0048,
755 +};
756 +
757 +#define GATE_ICG(_id, _name, _parent, _shift) { \
758 + .id = _id, \
759 + .name = _name, \
760 + .parent_name = _parent, \
761 + .regs = &infra_cg_regs, \
762 + .shift = _shift, \
763 + .ops = &mtk_clk_gate_ops_setclr, \
764 + }
765 +
766 +static const struct mtk_gate infra_clks[] __initconst = {
767 + GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
768 + GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
769 + GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
770 + GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2_294m_ck", 4),
771 + GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk_null", 5),
772 + GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
773 + GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
774 + GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
775 + GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
776 + GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
777 + GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
778 + GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
779 + GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
780 + GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
781 + GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
782 + GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
783 + GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
784 + GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
785 +};
786 +
787 +static const struct mtk_fixed_factor infra_fixed_divs[] __initconst = {
788 + FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
789 +};
790 +
791 +static void __init mtk_infrasys_init(struct device_node *node)
792 +{
793 + struct clk_onecell_data *clk_data;
794 + int r;
795 +
796 + clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
797 +
798 + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
799 + clk_data);
800 + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
801 + clk_data);
802 +
803 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
804 + if (r)
805 + pr_err("%s(): could not register clock provider: %d\n",
806 + __func__, r);
807 +}
808 +CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt2701-infracfg", mtk_infrasys_init);
809 +
810 +static const struct mtk_gate_regs peri0_cg_regs __initconst = {
811 + .set_ofs = 0x0008,
812 + .clr_ofs = 0x0010,
813 + .sta_ofs = 0x0018,
814 +};
815 +
816 +static const struct mtk_gate_regs peri1_cg_regs __initconst = {
817 + .set_ofs = 0x000c,
818 + .clr_ofs = 0x0014,
819 + .sta_ofs = 0x001c,
820 +};
821 +
822 +#define GATE_PERI0(_id, _name, _parent, _shift) { \
823 + .id = _id, \
824 + .name = _name, \
825 + .parent_name = _parent, \
826 + .regs = &peri0_cg_regs, \
827 + .shift = _shift, \
828 + .ops = &mtk_clk_gate_ops_setclr, \
829 + }
830 +
831 +#define GATE_PERI1(_id, _name, _parent, _shift) { \
832 + .id = _id, \
833 + .name = _name, \
834 + .parent_name = _parent, \
835 + .regs = &peri1_cg_regs, \
836 + .shift = _shift, \
837 + .ops = &mtk_clk_gate_ops_setclr, \
838 + }
839 +
840 +static const struct mtk_gate peri_clks[] __initconst = {
841 + GATE_PERI1(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
842 + GATE_PERI1(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
843 + GATE_PERI1(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
844 + GATE_PERI1(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
845 + GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
846 + GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
847 + GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
848 + GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
849 + GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
850 + GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
851 + GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
852 + GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
853 + GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
854 + GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
855 + GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
856 + GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
857 + GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
858 + GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
859 + GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
860 + GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
861 + GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
862 + GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
863 + GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
864 + GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
865 + GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
866 + GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
867 + GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
868 + GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
869 + GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
870 + GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
871 + GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
872 + GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
873 +
874 + GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card", 11),
875 + GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
876 + GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
877 + GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
878 + GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
879 + GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
880 + GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
881 + GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi_sel", 4),
882 + GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi_sel", 3),
883 + GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
884 + GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
885 + GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
886 +};
887 +
888 +static const char * const uart_ck_sel_parents[] __initconst = {
889 + "clk26m",
890 + "uart_sel",
891 +};
892 +
893 +static const struct mtk_composite peri_muxs[] __initconst = {
894 + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents, 0x40c, 0, 1),
895 + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents, 0x40c, 1, 1),
896 + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents, 0x40c, 2, 1),
897 + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents, 0x40c, 3, 1),
898 +};
899 +
900 +static void __init mtk_pericfg_init(struct device_node *node)
901 +{
902 + struct clk_onecell_data *clk_data;
903 + void __iomem *base;
904 + int r;
905 +
906 + base = of_iomap(node, 0);
907 + if (!base) {
908 + pr_err("%s(): ioremap failed\n", __func__);
909 + return;
910 + }
911 +
912 + clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
913 +
914 + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
915 + clk_data);
916 +
917 + mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
918 + &lock, clk_data);
919 +
920 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
921 + if (r)
922 + pr_err("%s(): could not register clock provider: %d\n",
923 + __func__, r);
924 +}
925 +CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt2701-pericfg", mtk_pericfg_init);
926 +
927 +static const struct mtk_gate_regs disp0_cg_regs __initconst = {
928 + .set_ofs = 0x0104,
929 + .clr_ofs = 0x0108,
930 + .sta_ofs = 0x0100,
931 +};
932 +
933 +static const struct mtk_gate_regs disp1_cg_regs __initconst = {
934 + .set_ofs = 0x0114,
935 + .clr_ofs = 0x0118,
936 + .sta_ofs = 0x0110,
937 +};
938 +
939 +#define GATE_DISP0(_id, _name, _parent, _shift) { \
940 + .id = _id, \
941 + .name = _name, \
942 + .parent_name = _parent, \
943 + .regs = &disp0_cg_regs, \
944 + .shift = _shift, \
945 + .ops = &mtk_clk_gate_ops_setclr, \
946 + }
947 +
948 +#define GATE_DISP1(_id, _name, _parent, _shift) { \
949 + .id = _id, \
950 + .name = _name, \
951 + .parent_name = _parent, \
952 + .regs = &disp1_cg_regs, \
953 + .shift = _shift, \
954 + .ops = &mtk_clk_gate_ops_setclr, \
955 + }
956 +
957 +static const struct mtk_gate mm_clks[] __initconst = {
958 + GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
959 + GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
960 + GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),
961 + GATE_DISP0(CLK_MM_MUTEX, "mm_mutex", "mm_sel", 3),
962 + GATE_DISP0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 4),
963 + GATE_DISP0(CLK_MM_DISP_BLS, "mm_disp_bls", "mm_sel", 5),
964 + GATE_DISP0(CLK_MM_DISP_WDMA, "mm_disp_wdma", "mm_sel", 6),
965 + GATE_DISP0(CLK_MM_DISP_RDMA, "mm_disp_rdma", "mm_sel", 7),
966 + GATE_DISP0(CLK_MM_DISP_OVL, "mm_disp_ovl", "mm_sel", 8),
967 + GATE_DISP0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),
968 + GATE_DISP0(CLK_MM_MDP_WROT, "mm_mdp_wrot", "mm_sel", 10),
969 + GATE_DISP0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
970 + GATE_DISP0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 12),
971 + GATE_DISP0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 13),
972 + GATE_DISP0(CLK_MM_MDP_RDMA, "mm_mdp_rdma", "mm_sel", 14),
973 + GATE_DISP0(CLK_MM_MDP_BLS_26M, "mm_mdp_bls_26m", "clk26m", 15),
974 + GATE_DISP0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 16),
975 + GATE_DISP0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 17),
976 + GATE_DISP0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 18),
977 + GATE_DISP0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
978 + GATE_DISP0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 20),
979 + GATE_DISP1(CLK_MM_DSI_ENGINE, "mm_dsi_eng", "mm_sel", 0),
980 + GATE_DISP1(CLK_MM_DSI_DIG, "mm_dsi_dig", "dsio_lntc_dsiclk", 1),
981 + GATE_DISP1(CLK_MM_DPI_DIGL, "mm_dpi_digl", "dpi0_sel", 2),
982 + GATE_DISP1(CLK_MM_DPI_ENGINE, "mm_dpi_eng", "mm_sel", 3),
983 + GATE_DISP1(CLK_MM_DPI1_DIGL, "mm_dpi1_digl", "dpi1_sel", 4),
984 + GATE_DISP1(CLK_MM_DPI1_ENGINE, "mm_dpi1_eng", "mm_sel", 5),
985 + GATE_DISP1(CLK_MM_TVE_OUTPUT, "mm_tve_output", "tve_sel", 6),
986 + GATE_DISP1(CLK_MM_TVE_INPUT, "mm_tve_input", "dpi0_sel", 7),
987 + GATE_DISP1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi1_sel", 8),
988 + GATE_DISP1(CLK_MM_HDMI_PLL, "mm_hdmi_pll", "hdmi_sel", 9),
989 + GATE_DISP1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll_sel", 10),
990 + GATE_DISP1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll_sel", 11),
991 + GATE_DISP1(CLK_MM_TVE_FMM, "mm_tve_fmm", "mm_sel", 14),
992 +};
993 +
994 +static void __init mtk_mmsys_init(struct device_node *node)
995 +{
996 + struct clk_onecell_data *clk_data;
997 + int r;
998 +
999 + clk_data = mtk_alloc_clk_data(CLK_MM_NR);
1000 +
1001 + mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
1002 + clk_data);
1003 +
1004 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1005 + if (r)
1006 + pr_err("%s(): could not register clock provider: %d\n",
1007 + __func__, r);
1008 +}
1009 +CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt2701-mmsys", mtk_mmsys_init);
1010 +
1011 +static const struct mtk_gate_regs img_cg_regs __initconst = {
1012 + .set_ofs = 0x0004,
1013 + .clr_ofs = 0x0008,
1014 + .sta_ofs = 0x0000,
1015 +};
1016 +
1017 +#define GATE_IMG(_id, _name, _parent, _shift) { \
1018 + .id = _id, \
1019 + .name = _name, \
1020 + .parent_name = _parent, \
1021 + .regs = &img_cg_regs, \
1022 + .shift = _shift, \
1023 + .ops = &mtk_clk_gate_ops_setclr, \
1024 + }
1025 +
1026 +static const struct mtk_gate img_clks[] __initconst = {
1027 + GATE_IMG(CLK_IMG_SMI_COMM, "img_smi_comm", "mm_sel", 0),
1028 + GATE_IMG(CLK_IMG_RESZ, "img_resz", "mm_sel", 1),
1029 + GATE_IMG(CLK_IMG_JPGDEC, "img_jpgdec", "mm_sel", 5),
1030 + GATE_IMG(CLK_IMG_VENC_LT, "img_venc_lt", "mm_sel", 8),
1031 + GATE_IMG(CLK_IMG_VENC, "img_venc", "mm_sel", 9),
1032 +};
1033 +
1034 +static void __init mtk_imgsys_init(struct device_node *node)
1035 +{
1036 + struct clk_onecell_data *clk_data;
1037 + int r;
1038 +
1039 + clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
1040 +
1041 + mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
1042 + clk_data);
1043 +
1044 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1045 + if (r)
1046 + pr_err("%s(): could not register clock provider: %d\n",
1047 + __func__, r);
1048 +}
1049 +CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt2701-imgsys", mtk_imgsys_init);
1050 +
1051 +static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
1052 + .set_ofs = 0x0000,
1053 + .clr_ofs = 0x0004,
1054 + .sta_ofs = 0x0000,
1055 +};
1056 +
1057 +static const struct mtk_gate_regs vdec1_cg_regs __initconst = {
1058 + .set_ofs = 0x0008,
1059 + .clr_ofs = 0x000c,
1060 + .sta_ofs = 0x0008,
1061 +};
1062 +
1063 +#define GATE_VDEC0(_id, _name, _parent, _shift) { \
1064 + .id = _id, \
1065 + .name = _name, \
1066 + .parent_name = _parent, \
1067 + .regs = &vdec0_cg_regs, \
1068 + .shift = _shift, \
1069 + .ops = &mtk_clk_gate_ops_setclr_inv, \
1070 + }
1071 +
1072 +#define GATE_VDEC1(_id, _name, _parent, _shift) { \
1073 + .id = _id, \
1074 + .name = _name, \
1075 + .parent_name = _parent, \
1076 + .regs = &vdec1_cg_regs, \
1077 + .shift = _shift, \
1078 + .ops = &mtk_clk_gate_ops_setclr_inv, \
1079 + }
1080 +
1081 +static const struct mtk_gate vdec_clks[] __initconst = {
1082 + GATE_VDEC0(CLK_VDEC_CKGEN, "vdec_cken", "vdec_sel", 0),
1083 + GATE_VDEC1(CLK_VDEC_LARB, "vdec_larb_cken", "mm_sel", 0),
1084 +};
1085 +
1086 +static void __init mtk_vdecsys_init(struct device_node *node)
1087 +{
1088 + struct clk_onecell_data *clk_data;
1089 + int r;
1090 +
1091 + clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
1092 +
1093 + mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
1094 + clk_data);
1095 +
1096 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1097 + if (r)
1098 + pr_err("%s(): could not register clock provider: %d\n",
1099 + __func__, r);
1100 +}
1101 +CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt2701-vdecsys", mtk_vdecsys_init);
1102 +
1103 +static const struct mtk_gate_regs hif_cg_regs __initconst = {
1104 + .sta_ofs = 0x0008,
1105 +};
1106 +
1107 +#define GATE_HIF(_id, _name, _parent, _shift) { \
1108 + .id = _id, \
1109 + .name = _name, \
1110 + .parent_name = _parent, \
1111 + .regs = &hif_cg_regs, \
1112 + .shift = _shift, \
1113 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1114 + }
1115 +
1116 +static const struct mtk_gate hif_clks[] __initconst = {
1117 + GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
1118 + GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
1119 + GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
1120 + GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
1121 + GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
1122 +};
1123 +
1124 +static void __init mtk_hifsys_init(struct device_node *node)
1125 +{
1126 + struct clk_onecell_data *clk_data;
1127 + int r;
1128 +
1129 + clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
1130 +
1131 + mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
1132 + clk_data);
1133 +
1134 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1135 + if (r)
1136 + pr_err("%s(): could not register clock provider: %d\n",
1137 + __func__, r);
1138 +}
1139 +CLK_OF_DECLARE(mtk_hifsys, "mediatek,mt2701-hifsys", mtk_hifsys_init);
1140 +
1141 +static const struct mtk_gate_regs eth_cg_regs __initconst = {
1142 + .sta_ofs = 0x0030,
1143 +};
1144 +
1145 +#define GATE_eth(_id, _name, _parent, _shift) { \
1146 + .id = _id, \
1147 + .name = _name, \
1148 + .parent_name = _parent, \
1149 + .regs = &eth_cg_regs, \
1150 + .shift = _shift, \
1151 + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
1152 + }
1153 +
1154 +static const struct mtk_gate eth_clks[] __initconst = {
1155 + GATE_HIF(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
1156 + GATE_HIF(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
1157 + GATE_HIF(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
1158 + GATE_HIF(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
1159 + GATE_HIF(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
1160 + GATE_HIF(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
1161 + GATE_HIF(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
1162 + GATE_HIF(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
1163 +};
1164 +
1165 +static void __init mtk_ethsys_init(struct device_node *node)
1166 +{
1167 + struct clk_onecell_data *clk_data;
1168 + int r;
1169 +
1170 + clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
1171 +
1172 + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
1173 + clk_data);
1174 +
1175 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1176 + if (r)
1177 + pr_err("%s(): could not register clock provider: %d\n",
1178 + __func__, r);
1179 +}
1180 +CLK_OF_DECLARE(mtk_ethsys, "mediatek,mt2701-ethsys", mtk_ethsys_init);
1181 +
1182 +static const struct mtk_gate_regs bdp0_cg_regs __initconst = {
1183 + .set_ofs = 0x0104,
1184 + .clr_ofs = 0x0108,
1185 + .sta_ofs = 0x0100,
1186 +};
1187 +
1188 +static const struct mtk_gate_regs bdp1_cg_regs __initconst = {
1189 + .set_ofs = 0x0114,
1190 + .clr_ofs = 0x0118,
1191 + .sta_ofs = 0x0110,
1192 +};
1193 +
1194 +#define GATE_BDP0(_id, _name, _parent, _shift) { \
1195 + .id = _id, \
1196 + .name = _name, \
1197 + .parent_name = _parent, \
1198 + .regs = &bdp0_cg_regs, \
1199 + .shift = _shift, \
1200 + .ops = &mtk_clk_gate_ops_setclr_inv, \
1201 + }
1202 +
1203 +#define GATE_BDP1(_id, _name, _parent, _shift) { \
1204 + .id = _id, \
1205 + .name = _name, \
1206 + .parent_name = _parent, \
1207 + .regs = &bdp1_cg_regs, \
1208 + .shift = _shift, \
1209 + .ops = &mtk_clk_gate_ops_setclr_inv, \
1210 + }
1211 +
1212 +static const struct mtk_gate bdp_clks[] __initconst = {
1213 + GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
1214 + GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
1215 + GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
1216 + GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
1217 + GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
1218 + GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
1219 + GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
1220 + GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi_sel", 7),
1221 + GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
1222 + GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
1223 + GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
1224 + GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
1225 + GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
1226 + GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
1227 + GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
1228 + GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
1229 + GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
1230 + GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
1231 + GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
1232 + GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
1233 + GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
1234 + GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
1235 + GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
1236 + GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
1237 + GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
1238 + GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
1239 + GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
1240 + GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
1241 + GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
1242 + GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
1243 + GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
1244 + GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
1245 + GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
1246 + GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
1247 + GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
1248 + GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
1249 + GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
1250 + GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
1251 + GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
1252 + GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
1253 + GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
1254 + GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
1255 + GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
1256 + GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
1257 + GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
1258 + GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
1259 + GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
1260 + GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
1261 + GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_mon", 16),
1262 +};
1263 +
1264 +static void __init mtk_bdpsys_init(struct device_node *node)
1265 +{
1266 + struct clk_onecell_data *clk_data;
1267 + int r;
1268 +
1269 + clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
1270 +
1271 + mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
1272 + clk_data);
1273 +
1274 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1275 + if (r)
1276 + pr_err("%s(): could not register clock provider: %d\n",
1277 + __func__, r);
1278 +}
1279 +CLK_OF_DECLARE(mtk_bdpsys, "mediatek,mt2701-bdpsys", mtk_bdpsys_init);
1280 +
1281 +#define MT8590_PLL_FMAX (2000 * MHZ)
1282 +#define CON0_MT8590_RST_BAR BIT(27)
1283 +
1284 +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
1285 + _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
1286 + .id = _id, \
1287 + .name = _name, \
1288 + .reg = _reg, \
1289 + .pwr_reg = _pwr_reg, \
1290 + .en_mask = _en_mask, \
1291 + .flags = _flags, \
1292 + .rst_bar_mask = CON0_MT8590_RST_BAR, \
1293 + .fmax = MT8590_PLL_FMAX, \
1294 + .pcwbits = _pcwbits, \
1295 + .pd_reg = _pd_reg, \
1296 + .pd_shift = _pd_shift, \
1297 + .tuner_reg = _tuner_reg, \
1298 + .pcw_reg = _pcw_reg, \
1299 + .pcw_shift = _pcw_shift, \
1300 + }
1301 +
1302 +static const struct mtk_pll_data apmixed_plls[] = {
1303 + PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000001, 0,
1304 + 21, 0x204, 24, 0x0, 0x204, 0),
1305 + PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000001,
1306 + HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
1307 + PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000001,
1308 + HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
1309 + PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0x00000001, 0,
1310 + 21, 0x230, 4, 0x0, 0x234, 0),
1311 + PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
1312 + 21, 0x240, 4, 0x0, 0x244, 0),
1313 + PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
1314 + 21, 0x250, 4, 0x0, 0x254, 0),
1315 + PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
1316 + 31, 0x270, 4, 0x0, 0x274, 0),
1317 + PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
1318 + 31, 0x280, 4, 0x0, 0x284, 0),
1319 + PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
1320 + 31, 0x290, 4, 0x0, 0x294, 0),
1321 + PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
1322 + 31, 0x2a0, 4, 0x0, 0x2a4, 0),
1323 + PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
1324 + 31, 0x2b0, 4, 0x0, 0x2b4, 0),
1325 + PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
1326 + 31, 0x2c0, 4, 0x0, 0x2c4, 0),
1327 + PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
1328 + 21, 0x2d0, 4, 0x0, 0x2d4, 0),
1329 +};
1330 +
1331 +static void __init mtk_apmixedsys_init(struct device_node *node)
1332 +{
1333 + struct clk_onecell_data *clk_data;
1334 + int r;
1335 +
1336 + clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
1337 + if (!clk_data)
1338 + return;
1339 +
1340 + mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
1341 + clk_data);
1342 +
1343 + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1344 + if (r)
1345 + pr_err("%s(): could not register clock provider: %d\n",
1346 + __func__, r);
1347 +}
1348 +CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt2701-apmixedsys",
1349 + mtk_apmixedsys_init);
1350 --- a/drivers/clk/mediatek/clk-mtk.c
1351 +++ b/drivers/clk/mediatek/clk-mtk.c
1352 @@ -242,3 +242,28 @@ void __init mtk_clk_register_composites(
1353 clk_data->clks[mc->id] = clk;
1354 }
1355 }
1356 +
1357 +void __init mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
1358 + int num, void __iomem *base, spinlock_t *lock,
1359 + struct clk_onecell_data *clk_data)
1360 +{
1361 + struct clk *clk;
1362 + int i;
1363 +
1364 + for (i = 0; i < num; i++) {
1365 + const struct mtk_clk_divider *mcd = &mcds[i];
1366 +
1367 + clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
1368 + mcd->flags, base + mcd->div_reg, mcd->div_shift,
1369 + mcd->div_width, mcd->clk_divider_flags, lock);
1370 +
1371 + if (IS_ERR(clk)) {
1372 + pr_err("Failed to register clk %s: %ld\n",
1373 + mcd->name, PTR_ERR(clk));
1374 + continue;
1375 + }
1376 +
1377 + if (clk_data)
1378 + clk_data->clks[mcd->id] = clk;
1379 + }
1380 +}
1381 --- a/drivers/clk/mediatek/clk-mtk.h
1382 +++ b/drivers/clk/mediatek/clk-mtk.h
1383 @@ -110,7 +110,8 @@ struct mtk_composite {
1384 .flags = CLK_SET_RATE_PARENT, \
1385 }
1386
1387 -#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
1388 +#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
1389 + _div_width, _div_shift) { \
1390 .id = _id, \
1391 .parent = _parent, \
1392 .name = _name, \
1393 @@ -145,8 +146,36 @@ struct mtk_gate {
1394 const struct clk_ops *ops;
1395 };
1396
1397 -int mtk_clk_register_gates(struct device_node *node, const struct mtk_gate *clks,
1398 - int num, struct clk_onecell_data *clk_data);
1399 +int mtk_clk_register_gates(struct device_node *node,
1400 + const struct mtk_gate *clks, int num,
1401 + struct clk_onecell_data *clk_data);
1402 +
1403 +struct mtk_clk_divider {
1404 + int id;
1405 + const char *name;
1406 + const char *parent_name;
1407 + unsigned long flags;
1408 +
1409 + uint32_t div_reg;
1410 + unsigned char div_shift;
1411 + unsigned char div_width;
1412 + unsigned char clk_divider_flags;
1413 + const struct clk_div_table *clk_div_table;
1414 +};
1415 +
1416 +#define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \
1417 + .id = _id, \
1418 + .name = _name, \
1419 + .parent_name = _parent, \
1420 + .flags = CLK_SET_RATE_PARENT, \
1421 + .div_reg = _reg, \
1422 + .div_shift = _shift, \
1423 + .div_width = _width, \
1424 +}
1425 +
1426 +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
1427 + int num, void __iomem *base, spinlock_t *lock,
1428 + struct clk_onecell_data *clk_data);
1429
1430 struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
1431
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