target/linux/mediatek/patches-4.9/0024-dt-bindings-add-MediaTek-PCIe-binding-documentation.patch

   1 From 05be818061b9f2a0fa5ad0cde6881917ff14a2f2 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 6 Jan 2016 21:55:10 +0100
   4 Subject: [PATCH 024/102] dt-bindings: add MediaTek PCIe binding documentation
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  .../devicetree/bindings/pci/mediatek-pcie.txt      |  140 ++++++++++++++++++++
   9  1 file changed, 140 insertions(+)
  10  create mode 100644 Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  11
  12 --- /dev/null
  13 +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.txt
  14 @@ -0,0 +1,140 @@
  15 +Mediatek PCIe controller
  16 +
  17 +Required properties:
  18 +- compatible: Should be one of:
  19 +       - "mediatek,mt2701-pcie"
  20 +       - "mediatek,mt7623-pcie"
  21 +- device_type: Must be "pci"
  22 +- reg: A list of physical base address and length for each set of controller
  23 +  registers. A list of register ranges to use. Must contain an
  24 +    entry for each entry in the reg-names property.
  25 +- reg-names: Must include the following entries:
  26 +  "pcie": PCIe registers
  27 +  "pcie phy0": PCIe PHY0 registers
  28 +  "pcie phy1": PCIe PHY0 registers
  29 +  "pcie phy2": PCIe PHY0 registers
  30 +- interrupts: A list of interrupt outputs of the controller. Must contain an
  31 +  entry for each entry in the interrupt-names property.
  32 +- interrupt-names: Must include the following entries:
  33 +  "pcie0": The interrupt that is asserted for port0
  34 +  "pcie1": The interrupt that is asserted for port1
  35 +  "pcie2": The interrupt that is asserted for port2
  36 +- bus-range: Range of bus numbers associated with this controller
  37 +- #address-cells: Address representation for root ports (must be 3)
  38 +- #size-cells: Size representation for root ports (must be 2)
  39 +- ranges: Describes the translation of addresses for root ports and standard
  40 +  PCI regions. The entries must be 6 cells each.
  41 +  Please refer to the standard PCI bus binding document for a more detailed
  42 +  explanation.
  43 +- #interrupt-cells: Size representation for interrupts (must be 1)
  44 +- clocks: Must contain an entry for each entry in clock-names.
  45 +  See ../clocks/clock-bindings.txt for details.
  46 +- clock-names: Must include the following entries:
  47 +  - pcie0
  48 +  - pcie1
  49 +  - pcie2
  50 +- resets: Must contain an entry for each entry in reset-names.
  51 +  See ../reset/reset.txt for details.
  52 +- reset-names: Must include the following entries:
  53 +  - pcie0
  54 +  - pcie1
  55 +  - pcie2
  56 +- mediatek,hifsys: Must contain a phandle to the HIFSYS syscon range.
  57 +Root ports are defined as subnodes of the PCIe controller node.
  58 +
  59 +Required properties:
  60 +- device_type: Must be "pci"
  61 +- assigned-addresses: Address and size of the port configuration registers
  62 +- reg: PCI bus address of the root port
  63 +- #address-cells: Must be 3
  64 +- #size-cells: Must be 2
  65 +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
  66 +  property is sufficient.
  67 +
  68 +Example:
  69 +
  70 +SoC DTSI:
  71 +
  72 +       hifsys: clock-controller@1a000000 {
  73 +               compatible = "mediatek,mt7623-hifsys",
  74 +                            "mediatek,mt2701-hifsys",
  75 +                            "syscon";
  76 +               reg = <0 0x1a000000 0 0x1000>;
  77 +               #clock-cells = <1>;
  78 +               #reset-cells = <1>;
  79 +       };
  80 +
  81 +       pcie-controller@1a140000 {
  82 +               compatible = "mediatek,mt7623-pcie";
  83 +               device_type = "pci";
  84 +               reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
  85 +                     <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
  86 +                     <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
  87 +                     <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
  88 +               reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
  89 +               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
  90 +                            <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
  91 +                            <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
  92 +               interrupt-names = "pcie0", "pcie1", "pcie2";
  93 +               clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
  94 +               clock-names = "pcie";
  95 +               power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
  96 +               resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
  97 +                        <&hifsys MT2701_HIFSYS_PCIE1_RST>,
  98 +                        <&hifsys MT2701_HIFSYS_PCIE2_RST>;
  99 +               reset-names = "pcie0", "pice1", "pcie2";
 100 +
 101 +               bus-range = <0x00 0xff>;
 102 +               #address-cells = <3>;
 103 +               #size-cells = <2>;
 104 +
 105 +                mediatek,hifsys = <&hifsys>;
 106 +
 107 +               ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
 108 +                         0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
 109 +
 110 +               status = "disabled";
 111 +
 112 +               pcie@1,0 {
 113 +                       device_type = "pci";
 114 +                       reg = <0x0800 0 0 0 0>;
 115 +
 116 +                       #address-cells = <3>;
 117 +                       #size-cells = <2>;
 118 +                       ranges;
 119 +
 120 +                       status = "disabled";
 121 +               };
 122 +
 123 +               pcie@2,0{
 124 +                       device_type = "pci";
 125 +                       reg = <0x1000 0 0 0 0>;
 126 +
 127 +                       #address-cells = <3>;
 128 +                       #size-cells = <2>;
 129 +                       ranges;
 130 +
 131 +                       status = "disabled";
 132 +               };
 133 +
 134 +               pcie@3,0{
 135 +                       device_type = "pci";
 136 +                       reg = <0x1800 0 0 0 0>;
 137 +
 138 +                       #address-cells = <3>;
 139 +                       #size-cells = <2>;
 140 +                       ranges;
 141 +
 142 +                       status = "disabled";
 143 +               };
 144 +       };
 145 +
 146 +Board DTS:
 147 +
 148 +       pcie-controller {
 149 +               status = "okay";
 150 +
 151 +               pci@1,0 {
 152 +                       status = "okay";
 153 +               };
 154 +       };